1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Kevin Tian <kevin.tian@intel.com> 25 * Eddie Dong <eddie.dong@intel.com> 26 * Zhiyuan Lv <zhiyuan.lv@intel.com> 27 * 28 * Contributors: 29 * Min He <min.he@intel.com> 30 * Tina Zhang <tina.zhang@intel.com> 31 * Pei Zhang <pei.zhang@intel.com> 32 * Niu Bing <bing.niu@intel.com> 33 * Ping Gao <ping.a.gao@intel.com> 34 * Zhi Wang <zhi.a.wang@intel.com> 35 * 36 37 */ 38 39 #include "i915_drv.h" 40 #include "gvt.h" 41 #include "i915_pvinfo.h" 42 43 /* XXX FIXME i915 has changed PP_XXX definition */ 44 #define PCH_PP_STATUS _MMIO(0xc7200) 45 #define PCH_PP_CONTROL _MMIO(0xc7204) 46 #define PCH_PP_ON_DELAYS _MMIO(0xc7208) 47 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c) 48 #define PCH_PP_DIVISOR _MMIO(0xc7210) 49 50 unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt) 51 { 52 if (IS_BROADWELL(gvt->dev_priv)) 53 return D_BDW; 54 else if (IS_SKYLAKE(gvt->dev_priv)) 55 return D_SKL; 56 else if (IS_KABYLAKE(gvt->dev_priv)) 57 return D_KBL; 58 59 return 0; 60 } 61 62 bool intel_gvt_match_device(struct intel_gvt *gvt, 63 unsigned long device) 64 { 65 return intel_gvt_get_device_type(gvt) & device; 66 } 67 68 static void read_vreg(struct intel_vgpu *vgpu, unsigned int offset, 69 void *p_data, unsigned int bytes) 70 { 71 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); 72 } 73 74 static void write_vreg(struct intel_vgpu *vgpu, unsigned int offset, 75 void *p_data, unsigned int bytes) 76 { 77 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes); 78 } 79 80 static struct intel_gvt_mmio_info *find_mmio_info(struct intel_gvt *gvt, 81 unsigned int offset) 82 { 83 struct intel_gvt_mmio_info *e; 84 85 hash_for_each_possible(gvt->mmio.mmio_info_table, e, node, offset) { 86 if (e->offset == offset) 87 return e; 88 } 89 return NULL; 90 } 91 92 static int new_mmio_info(struct intel_gvt *gvt, 93 u32 offset, u8 flags, u32 size, 94 u32 addr_mask, u32 ro_mask, u32 device, 95 gvt_mmio_func read, gvt_mmio_func write) 96 { 97 struct intel_gvt_mmio_info *info, *p; 98 u32 start, end, i; 99 100 if (!intel_gvt_match_device(gvt, device)) 101 return 0; 102 103 if (WARN_ON(!IS_ALIGNED(offset, 4))) 104 return -EINVAL; 105 106 start = offset; 107 end = offset + size; 108 109 for (i = start; i < end; i += 4) { 110 info = kzalloc(sizeof(*info), GFP_KERNEL); 111 if (!info) 112 return -ENOMEM; 113 114 info->offset = i; 115 p = find_mmio_info(gvt, info->offset); 116 if (p) { 117 WARN(1, "dup mmio definition offset %x\n", 118 info->offset); 119 kfree(info); 120 121 /* We return -EEXIST here to make GVT-g load fail. 122 * So duplicated MMIO can be found as soon as 123 * possible. 124 */ 125 return -EEXIST; 126 } 127 128 info->ro_mask = ro_mask; 129 info->device = device; 130 info->read = read ? read : intel_vgpu_default_mmio_read; 131 info->write = write ? write : intel_vgpu_default_mmio_write; 132 gvt->mmio.mmio_attribute[info->offset / 4] = flags; 133 INIT_HLIST_NODE(&info->node); 134 hash_add(gvt->mmio.mmio_info_table, &info->node, info->offset); 135 gvt->mmio.num_tracked_mmio++; 136 } 137 return 0; 138 } 139 140 static int render_mmio_to_ring_id(struct intel_gvt *gvt, unsigned int reg) 141 { 142 enum intel_engine_id id; 143 struct intel_engine_cs *engine; 144 145 reg &= ~GENMASK(11, 0); 146 for_each_engine(engine, gvt->dev_priv, id) { 147 if (engine->mmio_base == reg) 148 return id; 149 } 150 return -1; 151 } 152 153 #define offset_to_fence_num(offset) \ 154 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3) 155 156 #define fence_num_to_offset(num) \ 157 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) 158 159 160 static void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason) 161 { 162 switch (reason) { 163 case GVT_FAILSAFE_UNSUPPORTED_GUEST: 164 pr_err("Detected your guest driver doesn't support GVT-g.\n"); 165 break; 166 case GVT_FAILSAFE_INSUFFICIENT_RESOURCE: 167 pr_err("Graphics resource is not enough for the guest\n"); 168 default: 169 break; 170 } 171 pr_err("Now vgpu %d will enter failsafe mode.\n", vgpu->id); 172 vgpu->failsafe = true; 173 } 174 175 static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu, 176 unsigned int fence_num, void *p_data, unsigned int bytes) 177 { 178 if (fence_num >= vgpu_fence_sz(vgpu)) { 179 180 /* When guest access oob fence regs without access 181 * pv_info first, we treat guest not supporting GVT, 182 * and we will let vgpu enter failsafe mode. 183 */ 184 if (!vgpu->pv_notified) 185 enter_failsafe_mode(vgpu, 186 GVT_FAILSAFE_UNSUPPORTED_GUEST); 187 188 if (!vgpu->mmio.disable_warn_untrack) { 189 gvt_vgpu_err("found oob fence register access\n"); 190 gvt_vgpu_err("total fence %d, access fence %d\n", 191 vgpu_fence_sz(vgpu), fence_num); 192 } 193 memset(p_data, 0, bytes); 194 return -EINVAL; 195 } 196 return 0; 197 } 198 199 static int fence_mmio_read(struct intel_vgpu *vgpu, unsigned int off, 200 void *p_data, unsigned int bytes) 201 { 202 int ret; 203 204 ret = sanitize_fence_mmio_access(vgpu, offset_to_fence_num(off), 205 p_data, bytes); 206 if (ret) 207 return ret; 208 read_vreg(vgpu, off, p_data, bytes); 209 return 0; 210 } 211 212 static int fence_mmio_write(struct intel_vgpu *vgpu, unsigned int off, 213 void *p_data, unsigned int bytes) 214 { 215 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 216 unsigned int fence_num = offset_to_fence_num(off); 217 int ret; 218 219 ret = sanitize_fence_mmio_access(vgpu, fence_num, p_data, bytes); 220 if (ret) 221 return ret; 222 write_vreg(vgpu, off, p_data, bytes); 223 224 mmio_hw_access_pre(dev_priv); 225 intel_vgpu_write_fence(vgpu, fence_num, 226 vgpu_vreg64(vgpu, fence_num_to_offset(fence_num))); 227 mmio_hw_access_post(dev_priv); 228 return 0; 229 } 230 231 #define CALC_MODE_MASK_REG(old, new) \ 232 (((new) & GENMASK(31, 16)) \ 233 | ((((old) & GENMASK(15, 0)) & ~((new) >> 16)) \ 234 | ((new) & ((new) >> 16)))) 235 236 static int mul_force_wake_write(struct intel_vgpu *vgpu, 237 unsigned int offset, void *p_data, unsigned int bytes) 238 { 239 u32 old, new; 240 uint32_t ack_reg_offset; 241 242 old = vgpu_vreg(vgpu, offset); 243 new = CALC_MODE_MASK_REG(old, *(u32 *)p_data); 244 245 if (IS_SKYLAKE(vgpu->gvt->dev_priv) 246 || IS_KABYLAKE(vgpu->gvt->dev_priv)) { 247 switch (offset) { 248 case FORCEWAKE_RENDER_GEN9_REG: 249 ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG; 250 break; 251 case FORCEWAKE_BLITTER_GEN9_REG: 252 ack_reg_offset = FORCEWAKE_ACK_BLITTER_GEN9_REG; 253 break; 254 case FORCEWAKE_MEDIA_GEN9_REG: 255 ack_reg_offset = FORCEWAKE_ACK_MEDIA_GEN9_REG; 256 break; 257 default: 258 /*should not hit here*/ 259 gvt_vgpu_err("invalid forcewake offset 0x%x\n", offset); 260 return -EINVAL; 261 } 262 } else { 263 ack_reg_offset = FORCEWAKE_ACK_HSW_REG; 264 } 265 266 vgpu_vreg(vgpu, offset) = new; 267 vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0)); 268 return 0; 269 } 270 271 static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 272 void *p_data, unsigned int bytes) 273 { 274 unsigned int engine_mask = 0; 275 u32 data; 276 277 write_vreg(vgpu, offset, p_data, bytes); 278 data = vgpu_vreg(vgpu, offset); 279 280 if (data & GEN6_GRDOM_FULL) { 281 gvt_dbg_mmio("vgpu%d: request full GPU reset\n", vgpu->id); 282 engine_mask = ALL_ENGINES; 283 } else { 284 if (data & GEN6_GRDOM_RENDER) { 285 gvt_dbg_mmio("vgpu%d: request RCS reset\n", vgpu->id); 286 engine_mask |= (1 << RCS); 287 } 288 if (data & GEN6_GRDOM_MEDIA) { 289 gvt_dbg_mmio("vgpu%d: request VCS reset\n", vgpu->id); 290 engine_mask |= (1 << VCS); 291 } 292 if (data & GEN6_GRDOM_BLT) { 293 gvt_dbg_mmio("vgpu%d: request BCS Reset\n", vgpu->id); 294 engine_mask |= (1 << BCS); 295 } 296 if (data & GEN6_GRDOM_VECS) { 297 gvt_dbg_mmio("vgpu%d: request VECS Reset\n", vgpu->id); 298 engine_mask |= (1 << VECS); 299 } 300 if (data & GEN8_GRDOM_MEDIA2) { 301 gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id); 302 if (HAS_BSD2(vgpu->gvt->dev_priv)) 303 engine_mask |= (1 << VCS2); 304 } 305 } 306 307 intel_gvt_reset_vgpu_locked(vgpu, false, engine_mask); 308 309 /* sw will wait for the device to ack the reset request */ 310 vgpu_vreg(vgpu, offset) = 0; 311 312 return 0; 313 } 314 315 static int gmbus_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 316 void *p_data, unsigned int bytes) 317 { 318 return intel_gvt_i2c_handle_gmbus_read(vgpu, offset, p_data, bytes); 319 } 320 321 static int gmbus_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 322 void *p_data, unsigned int bytes) 323 { 324 return intel_gvt_i2c_handle_gmbus_write(vgpu, offset, p_data, bytes); 325 } 326 327 static int pch_pp_control_mmio_write(struct intel_vgpu *vgpu, 328 unsigned int offset, void *p_data, unsigned int bytes) 329 { 330 write_vreg(vgpu, offset, p_data, bytes); 331 332 if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) { 333 vgpu_vreg(vgpu, PCH_PP_STATUS) |= PP_ON; 334 vgpu_vreg(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE; 335 vgpu_vreg(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN; 336 vgpu_vreg(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE; 337 338 } else 339 vgpu_vreg(vgpu, PCH_PP_STATUS) &= 340 ~(PP_ON | PP_SEQUENCE_POWER_DOWN 341 | PP_CYCLE_DELAY_ACTIVE); 342 return 0; 343 } 344 345 static int transconf_mmio_write(struct intel_vgpu *vgpu, 346 unsigned int offset, void *p_data, unsigned int bytes) 347 { 348 write_vreg(vgpu, offset, p_data, bytes); 349 350 if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE) 351 vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE; 352 else 353 vgpu_vreg(vgpu, offset) &= ~TRANS_STATE_ENABLE; 354 return 0; 355 } 356 357 static int lcpll_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 358 void *p_data, unsigned int bytes) 359 { 360 write_vreg(vgpu, offset, p_data, bytes); 361 362 if (vgpu_vreg(vgpu, offset) & LCPLL_PLL_DISABLE) 363 vgpu_vreg(vgpu, offset) &= ~LCPLL_PLL_LOCK; 364 else 365 vgpu_vreg(vgpu, offset) |= LCPLL_PLL_LOCK; 366 367 if (vgpu_vreg(vgpu, offset) & LCPLL_CD_SOURCE_FCLK) 368 vgpu_vreg(vgpu, offset) |= LCPLL_CD_SOURCE_FCLK_DONE; 369 else 370 vgpu_vreg(vgpu, offset) &= ~LCPLL_CD_SOURCE_FCLK_DONE; 371 372 return 0; 373 } 374 375 static int dpy_reg_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 376 void *p_data, unsigned int bytes) 377 { 378 switch (offset) { 379 case 0xe651c: 380 case 0xe661c: 381 case 0xe671c: 382 case 0xe681c: 383 vgpu_vreg(vgpu, offset) = 1 << 17; 384 break; 385 case 0xe6c04: 386 vgpu_vreg(vgpu, offset) = 0x3; 387 break; 388 case 0xe6e1c: 389 vgpu_vreg(vgpu, offset) = 0x2f << 16; 390 break; 391 default: 392 return -EINVAL; 393 } 394 395 read_vreg(vgpu, offset, p_data, bytes); 396 return 0; 397 } 398 399 static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 400 void *p_data, unsigned int bytes) 401 { 402 u32 data; 403 404 write_vreg(vgpu, offset, p_data, bytes); 405 data = vgpu_vreg(vgpu, offset); 406 407 if (data & PIPECONF_ENABLE) 408 vgpu_vreg(vgpu, offset) |= I965_PIPECONF_ACTIVE; 409 else 410 vgpu_vreg(vgpu, offset) &= ~I965_PIPECONF_ACTIVE; 411 intel_gvt_check_vblank_emulation(vgpu->gvt); 412 return 0; 413 } 414 415 /* ascendingly sorted */ 416 static i915_reg_t force_nonpriv_white_list[] = { 417 GEN9_CS_DEBUG_MODE1, //_MMIO(0x20ec) 418 GEN9_CTX_PREEMPT_REG,//_MMIO(0x2248) 419 GEN8_CS_CHICKEN1,//_MMIO(0x2580) 420 _MMIO(0x2690), 421 _MMIO(0x2694), 422 _MMIO(0x2698), 423 _MMIO(0x4de0), 424 _MMIO(0x4de4), 425 _MMIO(0x4dfc), 426 GEN7_COMMON_SLICE_CHICKEN1,//_MMIO(0x7010) 427 _MMIO(0x7014), 428 HDC_CHICKEN0,//_MMIO(0x7300) 429 GEN8_HDC_CHICKEN1,//_MMIO(0x7304) 430 _MMIO(0x7700), 431 _MMIO(0x7704), 432 _MMIO(0x7708), 433 _MMIO(0x770c), 434 _MMIO(0xb110), 435 GEN8_L3SQCREG4,//_MMIO(0xb118) 436 _MMIO(0xe100), 437 _MMIO(0xe18c), 438 _MMIO(0xe48c), 439 _MMIO(0xe5f4), 440 }; 441 442 /* a simple bsearch */ 443 static inline bool in_whitelist(unsigned int reg) 444 { 445 int left = 0, right = ARRAY_SIZE(force_nonpriv_white_list); 446 i915_reg_t *array = force_nonpriv_white_list; 447 448 while (left < right) { 449 int mid = (left + right)/2; 450 451 if (reg > array[mid].reg) 452 left = mid + 1; 453 else if (reg < array[mid].reg) 454 right = mid; 455 else 456 return true; 457 } 458 return false; 459 } 460 461 static int force_nonpriv_write(struct intel_vgpu *vgpu, 462 unsigned int offset, void *p_data, unsigned int bytes) 463 { 464 u32 reg_nonpriv = *(u32 *)p_data; 465 int ret = -EINVAL; 466 467 if ((bytes != 4) || ((offset & (bytes - 1)) != 0)) { 468 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV offset %x(%dB)\n", 469 vgpu->id, offset, bytes); 470 return ret; 471 } 472 473 if (in_whitelist(reg_nonpriv)) { 474 ret = intel_vgpu_default_mmio_write(vgpu, offset, p_data, 475 bytes); 476 } else { 477 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x\n", 478 vgpu->id, reg_nonpriv); 479 } 480 return ret; 481 } 482 483 static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 484 void *p_data, unsigned int bytes) 485 { 486 write_vreg(vgpu, offset, p_data, bytes); 487 488 if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) { 489 vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE; 490 } else { 491 vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE; 492 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E))) 493 vgpu_vreg(vgpu, DP_TP_STATUS(PORT_E)) 494 &= ~DP_TP_STATUS_AUTOTRAIN_DONE; 495 } 496 return 0; 497 } 498 499 static int fdi_rx_iir_mmio_write(struct intel_vgpu *vgpu, 500 unsigned int offset, void *p_data, unsigned int bytes) 501 { 502 vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data; 503 return 0; 504 } 505 506 #define FDI_LINK_TRAIN_PATTERN1 0 507 #define FDI_LINK_TRAIN_PATTERN2 1 508 509 static int fdi_auto_training_started(struct intel_vgpu *vgpu) 510 { 511 u32 ddi_buf_ctl = vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_E)); 512 u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL); 513 u32 tx_ctl = vgpu_vreg(vgpu, DP_TP_CTL(PORT_E)); 514 515 if ((ddi_buf_ctl & DDI_BUF_CTL_ENABLE) && 516 (rx_ctl & FDI_RX_ENABLE) && 517 (rx_ctl & FDI_AUTO_TRAINING) && 518 (tx_ctl & DP_TP_CTL_ENABLE) && 519 (tx_ctl & DP_TP_CTL_FDI_AUTOTRAIN)) 520 return 1; 521 else 522 return 0; 523 } 524 525 static int check_fdi_rx_train_status(struct intel_vgpu *vgpu, 526 enum pipe pipe, unsigned int train_pattern) 527 { 528 i915_reg_t fdi_rx_imr, fdi_tx_ctl, fdi_rx_ctl; 529 unsigned int fdi_rx_check_bits, fdi_tx_check_bits; 530 unsigned int fdi_rx_train_bits, fdi_tx_train_bits; 531 unsigned int fdi_iir_check_bits; 532 533 fdi_rx_imr = FDI_RX_IMR(pipe); 534 fdi_tx_ctl = FDI_TX_CTL(pipe); 535 fdi_rx_ctl = FDI_RX_CTL(pipe); 536 537 if (train_pattern == FDI_LINK_TRAIN_PATTERN1) { 538 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_1_CPT; 539 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_1; 540 fdi_iir_check_bits = FDI_RX_BIT_LOCK; 541 } else if (train_pattern == FDI_LINK_TRAIN_PATTERN2) { 542 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_2_CPT; 543 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_2; 544 fdi_iir_check_bits = FDI_RX_SYMBOL_LOCK; 545 } else { 546 gvt_vgpu_err("Invalid train pattern %d\n", train_pattern); 547 return -EINVAL; 548 } 549 550 fdi_rx_check_bits = FDI_RX_ENABLE | fdi_rx_train_bits; 551 fdi_tx_check_bits = FDI_TX_ENABLE | fdi_tx_train_bits; 552 553 /* If imr bit has been masked */ 554 if (vgpu_vreg(vgpu, fdi_rx_imr) & fdi_iir_check_bits) 555 return 0; 556 557 if (((vgpu_vreg(vgpu, fdi_tx_ctl) & fdi_tx_check_bits) 558 == fdi_tx_check_bits) 559 && ((vgpu_vreg(vgpu, fdi_rx_ctl) & fdi_rx_check_bits) 560 == fdi_rx_check_bits)) 561 return 1; 562 else 563 return 0; 564 } 565 566 #define INVALID_INDEX (~0U) 567 568 static unsigned int calc_index(unsigned int offset, unsigned int start, 569 unsigned int next, unsigned int end, i915_reg_t i915_end) 570 { 571 unsigned int range = next - start; 572 573 if (!end) 574 end = i915_mmio_reg_offset(i915_end); 575 if (offset < start || offset > end) 576 return INVALID_INDEX; 577 offset -= start; 578 return offset / range; 579 } 580 581 #define FDI_RX_CTL_TO_PIPE(offset) \ 582 calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, 0, FDI_RX_CTL(PIPE_C)) 583 584 #define FDI_TX_CTL_TO_PIPE(offset) \ 585 calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, 0, FDI_TX_CTL(PIPE_C)) 586 587 #define FDI_RX_IMR_TO_PIPE(offset) \ 588 calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, 0, FDI_RX_IMR(PIPE_C)) 589 590 static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu, 591 unsigned int offset, void *p_data, unsigned int bytes) 592 { 593 i915_reg_t fdi_rx_iir; 594 unsigned int index; 595 int ret; 596 597 if (FDI_RX_CTL_TO_PIPE(offset) != INVALID_INDEX) 598 index = FDI_RX_CTL_TO_PIPE(offset); 599 else if (FDI_TX_CTL_TO_PIPE(offset) != INVALID_INDEX) 600 index = FDI_TX_CTL_TO_PIPE(offset); 601 else if (FDI_RX_IMR_TO_PIPE(offset) != INVALID_INDEX) 602 index = FDI_RX_IMR_TO_PIPE(offset); 603 else { 604 gvt_vgpu_err("Unsupport registers %x\n", offset); 605 return -EINVAL; 606 } 607 608 write_vreg(vgpu, offset, p_data, bytes); 609 610 fdi_rx_iir = FDI_RX_IIR(index); 611 612 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN1); 613 if (ret < 0) 614 return ret; 615 if (ret) 616 vgpu_vreg(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK; 617 618 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN2); 619 if (ret < 0) 620 return ret; 621 if (ret) 622 vgpu_vreg(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK; 623 624 if (offset == _FDI_RXA_CTL) 625 if (fdi_auto_training_started(vgpu)) 626 vgpu_vreg(vgpu, DP_TP_STATUS(PORT_E)) |= 627 DP_TP_STATUS_AUTOTRAIN_DONE; 628 return 0; 629 } 630 631 #define DP_TP_CTL_TO_PORT(offset) \ 632 calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, 0, DP_TP_CTL(PORT_E)) 633 634 static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 635 void *p_data, unsigned int bytes) 636 { 637 i915_reg_t status_reg; 638 unsigned int index; 639 u32 data; 640 641 write_vreg(vgpu, offset, p_data, bytes); 642 643 index = DP_TP_CTL_TO_PORT(offset); 644 data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8; 645 if (data == 0x2) { 646 status_reg = DP_TP_STATUS(index); 647 vgpu_vreg(vgpu, status_reg) |= (1 << 25); 648 } 649 return 0; 650 } 651 652 static int dp_tp_status_mmio_write(struct intel_vgpu *vgpu, 653 unsigned int offset, void *p_data, unsigned int bytes) 654 { 655 u32 reg_val; 656 u32 sticky_mask; 657 658 reg_val = *((u32 *)p_data); 659 sticky_mask = GENMASK(27, 26) | (1 << 24); 660 661 vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) | 662 (vgpu_vreg(vgpu, offset) & sticky_mask); 663 vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask); 664 return 0; 665 } 666 667 static int pch_adpa_mmio_write(struct intel_vgpu *vgpu, 668 unsigned int offset, void *p_data, unsigned int bytes) 669 { 670 u32 data; 671 672 write_vreg(vgpu, offset, p_data, bytes); 673 data = vgpu_vreg(vgpu, offset); 674 675 if (data & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) 676 vgpu_vreg(vgpu, offset) &= ~ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 677 return 0; 678 } 679 680 static int south_chicken2_mmio_write(struct intel_vgpu *vgpu, 681 unsigned int offset, void *p_data, unsigned int bytes) 682 { 683 u32 data; 684 685 write_vreg(vgpu, offset, p_data, bytes); 686 data = vgpu_vreg(vgpu, offset); 687 688 if (data & FDI_MPHY_IOSFSB_RESET_CTL) 689 vgpu_vreg(vgpu, offset) |= FDI_MPHY_IOSFSB_RESET_STATUS; 690 else 691 vgpu_vreg(vgpu, offset) &= ~FDI_MPHY_IOSFSB_RESET_STATUS; 692 return 0; 693 } 694 695 #define DSPSURF_TO_PIPE(offset) \ 696 calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C)) 697 698 static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 699 void *p_data, unsigned int bytes) 700 { 701 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 702 unsigned int index = DSPSURF_TO_PIPE(offset); 703 i915_reg_t surflive_reg = DSPSURFLIVE(index); 704 int flip_event[] = { 705 [PIPE_A] = PRIMARY_A_FLIP_DONE, 706 [PIPE_B] = PRIMARY_B_FLIP_DONE, 707 [PIPE_C] = PRIMARY_C_FLIP_DONE, 708 }; 709 710 write_vreg(vgpu, offset, p_data, bytes); 711 vgpu_vreg(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset); 712 713 set_bit(flip_event[index], vgpu->irq.flip_done_event[index]); 714 return 0; 715 } 716 717 #define SPRSURF_TO_PIPE(offset) \ 718 calc_index(offset, _SPRA_SURF, _SPRB_SURF, 0, SPRSURF(PIPE_C)) 719 720 static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 721 void *p_data, unsigned int bytes) 722 { 723 unsigned int index = SPRSURF_TO_PIPE(offset); 724 i915_reg_t surflive_reg = SPRSURFLIVE(index); 725 int flip_event[] = { 726 [PIPE_A] = SPRITE_A_FLIP_DONE, 727 [PIPE_B] = SPRITE_B_FLIP_DONE, 728 [PIPE_C] = SPRITE_C_FLIP_DONE, 729 }; 730 731 write_vreg(vgpu, offset, p_data, bytes); 732 vgpu_vreg(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset); 733 734 set_bit(flip_event[index], vgpu->irq.flip_done_event[index]); 735 return 0; 736 } 737 738 static int trigger_aux_channel_interrupt(struct intel_vgpu *vgpu, 739 unsigned int reg) 740 { 741 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 742 enum intel_gvt_event_type event; 743 744 if (reg == _DPA_AUX_CH_CTL) 745 event = AUX_CHANNEL_A; 746 else if (reg == _PCH_DPB_AUX_CH_CTL || reg == _DPB_AUX_CH_CTL) 747 event = AUX_CHANNEL_B; 748 else if (reg == _PCH_DPC_AUX_CH_CTL || reg == _DPC_AUX_CH_CTL) 749 event = AUX_CHANNEL_C; 750 else if (reg == _PCH_DPD_AUX_CH_CTL || reg == _DPD_AUX_CH_CTL) 751 event = AUX_CHANNEL_D; 752 else { 753 WARN_ON(true); 754 return -EINVAL; 755 } 756 757 intel_vgpu_trigger_virtual_event(vgpu, event); 758 return 0; 759 } 760 761 static int dp_aux_ch_ctl_trans_done(struct intel_vgpu *vgpu, u32 value, 762 unsigned int reg, int len, bool data_valid) 763 { 764 /* mark transaction done */ 765 value |= DP_AUX_CH_CTL_DONE; 766 value &= ~DP_AUX_CH_CTL_SEND_BUSY; 767 value &= ~DP_AUX_CH_CTL_RECEIVE_ERROR; 768 769 if (data_valid) 770 value &= ~DP_AUX_CH_CTL_TIME_OUT_ERROR; 771 else 772 value |= DP_AUX_CH_CTL_TIME_OUT_ERROR; 773 774 /* message size */ 775 value &= ~(0xf << 20); 776 value |= (len << 20); 777 vgpu_vreg(vgpu, reg) = value; 778 779 if (value & DP_AUX_CH_CTL_INTERRUPT) 780 return trigger_aux_channel_interrupt(vgpu, reg); 781 return 0; 782 } 783 784 static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd, 785 uint8_t t) 786 { 787 if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == DPCD_TRAINING_PATTERN_1) { 788 /* training pattern 1 for CR */ 789 /* set LANE0_CR_DONE, LANE1_CR_DONE */ 790 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_CR_DONE; 791 /* set LANE2_CR_DONE, LANE3_CR_DONE */ 792 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_CR_DONE; 793 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == 794 DPCD_TRAINING_PATTERN_2) { 795 /* training pattern 2 for EQ */ 796 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane0_1 */ 797 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_EQ_DONE; 798 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_SYMBOL_LOCKED; 799 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane2_3 */ 800 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_EQ_DONE; 801 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_SYMBOL_LOCKED; 802 /* set INTERLANE_ALIGN_DONE */ 803 dpcd->data[DPCD_LANE_ALIGN_STATUS_UPDATED] |= 804 DPCD_INTERLANE_ALIGN_DONE; 805 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == 806 DPCD_LINK_TRAINING_DISABLED) { 807 /* finish link training */ 808 /* set sink status as synchronized */ 809 dpcd->data[DPCD_SINK_STATUS] = DPCD_SINK_IN_SYNC; 810 } 811 } 812 813 #define _REG_HSW_DP_AUX_CH_CTL(dp) \ 814 ((dp) ? (_PCH_DPB_AUX_CH_CTL + ((dp)-1)*0x100) : 0x64010) 815 816 #define _REG_SKL_DP_AUX_CH_CTL(dp) (0x64010 + (dp) * 0x100) 817 818 #define OFFSET_TO_DP_AUX_PORT(offset) (((offset) & 0xF00) >> 8) 819 820 #define dpy_is_valid_port(port) \ 821 (((port) >= PORT_A) && ((port) < I915_MAX_PORTS)) 822 823 static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu, 824 unsigned int offset, void *p_data, unsigned int bytes) 825 { 826 struct intel_vgpu_display *display = &vgpu->display; 827 int msg, addr, ctrl, op, len; 828 int port_index = OFFSET_TO_DP_AUX_PORT(offset); 829 struct intel_vgpu_dpcd_data *dpcd = NULL; 830 struct intel_vgpu_port *port = NULL; 831 u32 data; 832 833 if (!dpy_is_valid_port(port_index)) { 834 gvt_vgpu_err("Unsupported DP port access!\n"); 835 return 0; 836 } 837 838 write_vreg(vgpu, offset, p_data, bytes); 839 data = vgpu_vreg(vgpu, offset); 840 841 if ((IS_SKYLAKE(vgpu->gvt->dev_priv) 842 || IS_KABYLAKE(vgpu->gvt->dev_priv)) 843 && offset != _REG_SKL_DP_AUX_CH_CTL(port_index)) { 844 /* SKL DPB/C/D aux ctl register changed */ 845 return 0; 846 } else if (IS_BROADWELL(vgpu->gvt->dev_priv) && 847 offset != _REG_HSW_DP_AUX_CH_CTL(port_index)) { 848 /* write to the data registers */ 849 return 0; 850 } 851 852 if (!(data & DP_AUX_CH_CTL_SEND_BUSY)) { 853 /* just want to clear the sticky bits */ 854 vgpu_vreg(vgpu, offset) = 0; 855 return 0; 856 } 857 858 port = &display->ports[port_index]; 859 dpcd = port->dpcd; 860 861 /* read out message from DATA1 register */ 862 msg = vgpu_vreg(vgpu, offset + 4); 863 addr = (msg >> 8) & 0xffff; 864 ctrl = (msg >> 24) & 0xff; 865 len = msg & 0xff; 866 op = ctrl >> 4; 867 868 if (op == GVT_AUX_NATIVE_WRITE) { 869 int t; 870 uint8_t buf[16]; 871 872 if ((addr + len + 1) >= DPCD_SIZE) { 873 /* 874 * Write request exceeds what we supported, 875 * DCPD spec: When a Source Device is writing a DPCD 876 * address not supported by the Sink Device, the Sink 877 * Device shall reply with AUX NACK and “M” equal to 878 * zero. 879 */ 880 881 /* NAK the write */ 882 vgpu_vreg(vgpu, offset + 4) = AUX_NATIVE_REPLY_NAK; 883 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 2, true); 884 return 0; 885 } 886 887 /* 888 * Write request format: (command + address) occupies 889 * 3 bytes, followed by (len + 1) bytes of data. 890 */ 891 if (WARN_ON((len + 4) > AUX_BURST_SIZE)) 892 return -EINVAL; 893 894 /* unpack data from vreg to buf */ 895 for (t = 0; t < 4; t++) { 896 u32 r = vgpu_vreg(vgpu, offset + 8 + t * 4); 897 898 buf[t * 4] = (r >> 24) & 0xff; 899 buf[t * 4 + 1] = (r >> 16) & 0xff; 900 buf[t * 4 + 2] = (r >> 8) & 0xff; 901 buf[t * 4 + 3] = r & 0xff; 902 } 903 904 /* write to virtual DPCD */ 905 if (dpcd && dpcd->data_valid) { 906 for (t = 0; t <= len; t++) { 907 int p = addr + t; 908 909 dpcd->data[p] = buf[t]; 910 /* check for link training */ 911 if (p == DPCD_TRAINING_PATTERN_SET) 912 dp_aux_ch_ctl_link_training(dpcd, 913 buf[t]); 914 } 915 } 916 917 /* ACK the write */ 918 vgpu_vreg(vgpu, offset + 4) = 0; 919 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 1, 920 dpcd && dpcd->data_valid); 921 return 0; 922 } 923 924 if (op == GVT_AUX_NATIVE_READ) { 925 int idx, i, ret = 0; 926 927 if ((addr + len + 1) >= DPCD_SIZE) { 928 /* 929 * read request exceeds what we supported 930 * DPCD spec: A Sink Device receiving a Native AUX CH 931 * read request for an unsupported DPCD address must 932 * reply with an AUX ACK and read data set equal to 933 * zero instead of replying with AUX NACK. 934 */ 935 936 /* ACK the READ*/ 937 vgpu_vreg(vgpu, offset + 4) = 0; 938 vgpu_vreg(vgpu, offset + 8) = 0; 939 vgpu_vreg(vgpu, offset + 12) = 0; 940 vgpu_vreg(vgpu, offset + 16) = 0; 941 vgpu_vreg(vgpu, offset + 20) = 0; 942 943 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2, 944 true); 945 return 0; 946 } 947 948 for (idx = 1; idx <= 5; idx++) { 949 /* clear the data registers */ 950 vgpu_vreg(vgpu, offset + 4 * idx) = 0; 951 } 952 953 /* 954 * Read reply format: ACK (1 byte) plus (len + 1) bytes of data. 955 */ 956 if (WARN_ON((len + 2) > AUX_BURST_SIZE)) 957 return -EINVAL; 958 959 /* read from virtual DPCD to vreg */ 960 /* first 4 bytes: [ACK][addr][addr+1][addr+2] */ 961 if (dpcd && dpcd->data_valid) { 962 for (i = 1; i <= (len + 1); i++) { 963 int t; 964 965 t = dpcd->data[addr + i - 1]; 966 t <<= (24 - 8 * (i % 4)); 967 ret |= t; 968 969 if ((i % 4 == 3) || (i == (len + 1))) { 970 vgpu_vreg(vgpu, offset + 971 (i / 4 + 1) * 4) = ret; 972 ret = 0; 973 } 974 } 975 } 976 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2, 977 dpcd && dpcd->data_valid); 978 return 0; 979 } 980 981 /* i2c transaction starts */ 982 intel_gvt_i2c_handle_aux_ch_write(vgpu, port_index, offset, p_data); 983 984 if (data & DP_AUX_CH_CTL_INTERRUPT) 985 trigger_aux_channel_interrupt(vgpu, offset); 986 return 0; 987 } 988 989 static int mbctl_write(struct intel_vgpu *vgpu, unsigned int offset, 990 void *p_data, unsigned int bytes) 991 { 992 *(u32 *)p_data &= (~GEN6_MBCTL_ENABLE_BOOT_FETCH); 993 write_vreg(vgpu, offset, p_data, bytes); 994 return 0; 995 } 996 997 static int vga_control_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 998 void *p_data, unsigned int bytes) 999 { 1000 bool vga_disable; 1001 1002 write_vreg(vgpu, offset, p_data, bytes); 1003 vga_disable = vgpu_vreg(vgpu, offset) & VGA_DISP_DISABLE; 1004 1005 gvt_dbg_core("vgpu%d: %s VGA mode\n", vgpu->id, 1006 vga_disable ? "Disable" : "Enable"); 1007 return 0; 1008 } 1009 1010 static u32 read_virtual_sbi_register(struct intel_vgpu *vgpu, 1011 unsigned int sbi_offset) 1012 { 1013 struct intel_vgpu_display *display = &vgpu->display; 1014 int num = display->sbi.number; 1015 int i; 1016 1017 for (i = 0; i < num; ++i) 1018 if (display->sbi.registers[i].offset == sbi_offset) 1019 break; 1020 1021 if (i == num) 1022 return 0; 1023 1024 return display->sbi.registers[i].value; 1025 } 1026 1027 static void write_virtual_sbi_register(struct intel_vgpu *vgpu, 1028 unsigned int offset, u32 value) 1029 { 1030 struct intel_vgpu_display *display = &vgpu->display; 1031 int num = display->sbi.number; 1032 int i; 1033 1034 for (i = 0; i < num; ++i) { 1035 if (display->sbi.registers[i].offset == offset) 1036 break; 1037 } 1038 1039 if (i == num) { 1040 if (num == SBI_REG_MAX) { 1041 gvt_vgpu_err("SBI caching meets maximum limits\n"); 1042 return; 1043 } 1044 display->sbi.number++; 1045 } 1046 1047 display->sbi.registers[i].offset = offset; 1048 display->sbi.registers[i].value = value; 1049 } 1050 1051 static int sbi_data_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 1052 void *p_data, unsigned int bytes) 1053 { 1054 if (((vgpu_vreg(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> 1055 SBI_OPCODE_SHIFT) == SBI_CMD_CRRD) { 1056 unsigned int sbi_offset = (vgpu_vreg(vgpu, SBI_ADDR) & 1057 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; 1058 vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu, 1059 sbi_offset); 1060 } 1061 read_vreg(vgpu, offset, p_data, bytes); 1062 return 0; 1063 } 1064 1065 static int sbi_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1066 void *p_data, unsigned int bytes) 1067 { 1068 u32 data; 1069 1070 write_vreg(vgpu, offset, p_data, bytes); 1071 data = vgpu_vreg(vgpu, offset); 1072 1073 data &= ~(SBI_STAT_MASK << SBI_STAT_SHIFT); 1074 data |= SBI_READY; 1075 1076 data &= ~(SBI_RESPONSE_MASK << SBI_RESPONSE_SHIFT); 1077 data |= SBI_RESPONSE_SUCCESS; 1078 1079 vgpu_vreg(vgpu, offset) = data; 1080 1081 if (((vgpu_vreg(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> 1082 SBI_OPCODE_SHIFT) == SBI_CMD_CRWR) { 1083 unsigned int sbi_offset = (vgpu_vreg(vgpu, SBI_ADDR) & 1084 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; 1085 1086 write_virtual_sbi_register(vgpu, sbi_offset, 1087 vgpu_vreg(vgpu, SBI_DATA)); 1088 } 1089 return 0; 1090 } 1091 1092 #define _vgtif_reg(x) \ 1093 (VGT_PVINFO_PAGE + offsetof(struct vgt_if, x)) 1094 1095 static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 1096 void *p_data, unsigned int bytes) 1097 { 1098 bool invalid_read = false; 1099 1100 read_vreg(vgpu, offset, p_data, bytes); 1101 1102 switch (offset) { 1103 case _vgtif_reg(magic) ... _vgtif_reg(vgt_id): 1104 if (offset + bytes > _vgtif_reg(vgt_id) + 4) 1105 invalid_read = true; 1106 break; 1107 case _vgtif_reg(avail_rs.mappable_gmadr.base) ... 1108 _vgtif_reg(avail_rs.fence_num): 1109 if (offset + bytes > 1110 _vgtif_reg(avail_rs.fence_num) + 4) 1111 invalid_read = true; 1112 break; 1113 case 0x78010: /* vgt_caps */ 1114 case 0x7881c: 1115 break; 1116 default: 1117 invalid_read = true; 1118 break; 1119 } 1120 if (invalid_read) 1121 gvt_vgpu_err("invalid pvinfo read: [%x:%x] = %x\n", 1122 offset, bytes, *(u32 *)p_data); 1123 vgpu->pv_notified = true; 1124 return 0; 1125 } 1126 1127 static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification) 1128 { 1129 int ret = 0; 1130 1131 switch (notification) { 1132 case VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE: 1133 ret = intel_vgpu_g2v_create_ppgtt_mm(vgpu, 3); 1134 break; 1135 case VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY: 1136 ret = intel_vgpu_g2v_destroy_ppgtt_mm(vgpu, 3); 1137 break; 1138 case VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE: 1139 ret = intel_vgpu_g2v_create_ppgtt_mm(vgpu, 4); 1140 break; 1141 case VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY: 1142 ret = intel_vgpu_g2v_destroy_ppgtt_mm(vgpu, 4); 1143 break; 1144 case VGT_G2V_EXECLIST_CONTEXT_CREATE: 1145 case VGT_G2V_EXECLIST_CONTEXT_DESTROY: 1146 case 1: /* Remove this in guest driver. */ 1147 break; 1148 default: 1149 gvt_vgpu_err("Invalid PV notification %d\n", notification); 1150 } 1151 return ret; 1152 } 1153 1154 static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready) 1155 { 1156 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1157 struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj; 1158 char *env[3] = {NULL, NULL, NULL}; 1159 char vmid_str[20]; 1160 char display_ready_str[20]; 1161 1162 snprintf(display_ready_str, 20, "GVT_DISPLAY_READY=%d", ready); 1163 env[0] = display_ready_str; 1164 1165 snprintf(vmid_str, 20, "VMID=%d", vgpu->id); 1166 env[1] = vmid_str; 1167 1168 return kobject_uevent_env(kobj, KOBJ_ADD, env); 1169 } 1170 1171 static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1172 void *p_data, unsigned int bytes) 1173 { 1174 u32 data; 1175 int ret; 1176 1177 write_vreg(vgpu, offset, p_data, bytes); 1178 data = vgpu_vreg(vgpu, offset); 1179 1180 switch (offset) { 1181 case _vgtif_reg(display_ready): 1182 send_display_ready_uevent(vgpu, data ? 1 : 0); 1183 break; 1184 case _vgtif_reg(g2v_notify): 1185 ret = handle_g2v_notification(vgpu, data); 1186 break; 1187 /* add xhot and yhot to handled list to avoid error log */ 1188 case 0x78830: 1189 case 0x78834: 1190 case _vgtif_reg(pdp[0].lo): 1191 case _vgtif_reg(pdp[0].hi): 1192 case _vgtif_reg(pdp[1].lo): 1193 case _vgtif_reg(pdp[1].hi): 1194 case _vgtif_reg(pdp[2].lo): 1195 case _vgtif_reg(pdp[2].hi): 1196 case _vgtif_reg(pdp[3].lo): 1197 case _vgtif_reg(pdp[3].hi): 1198 case _vgtif_reg(execlist_context_descriptor_lo): 1199 case _vgtif_reg(execlist_context_descriptor_hi): 1200 break; 1201 case _vgtif_reg(rsv5[0])..._vgtif_reg(rsv5[3]): 1202 enter_failsafe_mode(vgpu, GVT_FAILSAFE_INSUFFICIENT_RESOURCE); 1203 break; 1204 default: 1205 gvt_vgpu_err("invalid pvinfo write offset %x bytes %x data %x\n", 1206 offset, bytes, data); 1207 break; 1208 } 1209 return 0; 1210 } 1211 1212 static int pf_write(struct intel_vgpu *vgpu, 1213 unsigned int offset, void *p_data, unsigned int bytes) 1214 { 1215 u32 val = *(u32 *)p_data; 1216 1217 if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL || 1218 offset == _PS_1B_CTRL || offset == _PS_2B_CTRL || 1219 offset == _PS_1C_CTRL) && (val & PS_PLANE_SEL_MASK) != 0) { 1220 WARN_ONCE(true, "VM(%d): guest is trying to scaling a plane\n", 1221 vgpu->id); 1222 return 0; 1223 } 1224 1225 return intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes); 1226 } 1227 1228 static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu, 1229 unsigned int offset, void *p_data, unsigned int bytes) 1230 { 1231 write_vreg(vgpu, offset, p_data, bytes); 1232 1233 if (vgpu_vreg(vgpu, offset) & HSW_PWR_WELL_CTL_REQ(HSW_DISP_PW_GLOBAL)) 1234 vgpu_vreg(vgpu, offset) |= 1235 HSW_PWR_WELL_CTL_STATE(HSW_DISP_PW_GLOBAL); 1236 else 1237 vgpu_vreg(vgpu, offset) &= 1238 ~HSW_PWR_WELL_CTL_STATE(HSW_DISP_PW_GLOBAL); 1239 return 0; 1240 } 1241 1242 static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu, 1243 unsigned int offset, void *p_data, unsigned int bytes) 1244 { 1245 write_vreg(vgpu, offset, p_data, bytes); 1246 1247 if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM) 1248 vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM; 1249 return 0; 1250 } 1251 1252 static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset, 1253 void *p_data, unsigned int bytes) 1254 { 1255 u32 mode; 1256 1257 write_vreg(vgpu, offset, p_data, bytes); 1258 mode = vgpu_vreg(vgpu, offset); 1259 1260 if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) { 1261 WARN_ONCE(1, "VM(%d): iGVT-g doesn't support GuC\n", 1262 vgpu->id); 1263 return 0; 1264 } 1265 1266 return 0; 1267 } 1268 1269 static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset, 1270 void *p_data, unsigned int bytes) 1271 { 1272 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1273 u32 trtte = *(u32 *)p_data; 1274 1275 if ((trtte & 1) && (trtte & (1 << 1)) == 0) { 1276 WARN(1, "VM(%d): Use physical address for TRTT!\n", 1277 vgpu->id); 1278 return -EINVAL; 1279 } 1280 write_vreg(vgpu, offset, p_data, bytes); 1281 /* TRTTE is not per-context */ 1282 1283 mmio_hw_access_pre(dev_priv); 1284 I915_WRITE(_MMIO(offset), vgpu_vreg(vgpu, offset)); 1285 mmio_hw_access_post(dev_priv); 1286 1287 return 0; 1288 } 1289 1290 static int gen9_trtt_chicken_write(struct intel_vgpu *vgpu, unsigned int offset, 1291 void *p_data, unsigned int bytes) 1292 { 1293 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1294 u32 val = *(u32 *)p_data; 1295 1296 if (val & 1) { 1297 /* unblock hw logic */ 1298 mmio_hw_access_pre(dev_priv); 1299 I915_WRITE(_MMIO(offset), val); 1300 mmio_hw_access_post(dev_priv); 1301 } 1302 write_vreg(vgpu, offset, p_data, bytes); 1303 return 0; 1304 } 1305 1306 static int dpll_status_read(struct intel_vgpu *vgpu, unsigned int offset, 1307 void *p_data, unsigned int bytes) 1308 { 1309 u32 v = 0; 1310 1311 if (vgpu_vreg(vgpu, 0x46010) & (1 << 31)) 1312 v |= (1 << 0); 1313 1314 if (vgpu_vreg(vgpu, 0x46014) & (1 << 31)) 1315 v |= (1 << 8); 1316 1317 if (vgpu_vreg(vgpu, 0x46040) & (1 << 31)) 1318 v |= (1 << 16); 1319 1320 if (vgpu_vreg(vgpu, 0x46060) & (1 << 31)) 1321 v |= (1 << 24); 1322 1323 vgpu_vreg(vgpu, offset) = v; 1324 1325 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1326 } 1327 1328 static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset, 1329 void *p_data, unsigned int bytes) 1330 { 1331 u32 value = *(u32 *)p_data; 1332 u32 cmd = value & 0xff; 1333 u32 *data0 = &vgpu_vreg(vgpu, GEN6_PCODE_DATA); 1334 1335 switch (cmd) { 1336 case GEN9_PCODE_READ_MEM_LATENCY: 1337 if (IS_SKYLAKE(vgpu->gvt->dev_priv) 1338 || IS_KABYLAKE(vgpu->gvt->dev_priv)) { 1339 /** 1340 * "Read memory latency" command on gen9. 1341 * Below memory latency values are read 1342 * from skylake platform. 1343 */ 1344 if (!*data0) 1345 *data0 = 0x1e1a1100; 1346 else 1347 *data0 = 0x61514b3d; 1348 } 1349 break; 1350 case SKL_PCODE_CDCLK_CONTROL: 1351 if (IS_SKYLAKE(vgpu->gvt->dev_priv) 1352 || IS_KABYLAKE(vgpu->gvt->dev_priv)) 1353 *data0 = SKL_CDCLK_READY_FOR_CHANGE; 1354 break; 1355 case GEN6_PCODE_READ_RC6VIDS: 1356 *data0 |= 0x1; 1357 break; 1358 } 1359 1360 gvt_dbg_core("VM(%d) write %x to mailbox, return data0 %x\n", 1361 vgpu->id, value, *data0); 1362 /** 1363 * PCODE_READY clear means ready for pcode read/write, 1364 * PCODE_ERROR_MASK clear means no error happened. In GVT-g we 1365 * always emulate as pcode read/write success and ready for access 1366 * anytime, since we don't touch real physical registers here. 1367 */ 1368 value &= ~(GEN6_PCODE_READY | GEN6_PCODE_ERROR_MASK); 1369 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes); 1370 } 1371 1372 static int skl_power_well_ctl_write(struct intel_vgpu *vgpu, 1373 unsigned int offset, void *p_data, unsigned int bytes) 1374 { 1375 u32 v = *(u32 *)p_data; 1376 1377 v &= (1 << 31) | (1 << 29) | (1 << 9) | 1378 (1 << 7) | (1 << 5) | (1 << 3) | (1 << 1); 1379 v |= (v >> 1); 1380 1381 return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes); 1382 } 1383 1384 static int skl_misc_ctl_write(struct intel_vgpu *vgpu, unsigned int offset, 1385 void *p_data, unsigned int bytes) 1386 { 1387 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1388 u32 v = *(u32 *)p_data; 1389 1390 if (!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv)) 1391 return intel_vgpu_default_mmio_write(vgpu, 1392 offset, p_data, bytes); 1393 1394 switch (offset) { 1395 case 0x4ddc: 1396 /* bypass WaCompressedResourceSamplerPbeMediaNewHashMode */ 1397 vgpu_vreg(vgpu, offset) = v & ~(1 << 31); 1398 break; 1399 case 0x42080: 1400 /* bypass WaCompressedResourceDisplayNewHashMode */ 1401 vgpu_vreg(vgpu, offset) = v & ~(1 << 15); 1402 break; 1403 case 0xe194: 1404 /* bypass WaCompressedResourceSamplerPbeMediaNewHashMode */ 1405 vgpu_vreg(vgpu, offset) = v & ~(1 << 8); 1406 break; 1407 case 0x7014: 1408 /* bypass WaCompressedResourceSamplerPbeMediaNewHashMode */ 1409 vgpu_vreg(vgpu, offset) = v & ~(1 << 13); 1410 break; 1411 default: 1412 return -EINVAL; 1413 } 1414 1415 return 0; 1416 } 1417 1418 static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset, 1419 void *p_data, unsigned int bytes) 1420 { 1421 u32 v = *(u32 *)p_data; 1422 1423 /* other bits are MBZ. */ 1424 v &= (1 << 31) | (1 << 30); 1425 v & (1 << 31) ? (v |= (1 << 30)) : (v &= ~(1 << 30)); 1426 1427 vgpu_vreg(vgpu, offset) = v; 1428 1429 return 0; 1430 } 1431 1432 static int ring_timestamp_mmio_read(struct intel_vgpu *vgpu, 1433 unsigned int offset, void *p_data, unsigned int bytes) 1434 { 1435 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1436 1437 mmio_hw_access_pre(dev_priv); 1438 vgpu_vreg(vgpu, offset) = I915_READ(_MMIO(offset)); 1439 mmio_hw_access_post(dev_priv); 1440 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1441 } 1442 1443 static int instdone_mmio_read(struct intel_vgpu *vgpu, 1444 unsigned int offset, void *p_data, unsigned int bytes) 1445 { 1446 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1447 1448 mmio_hw_access_pre(dev_priv); 1449 vgpu_vreg(vgpu, offset) = I915_READ(_MMIO(offset)); 1450 mmio_hw_access_post(dev_priv); 1451 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1452 } 1453 1454 static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1455 void *p_data, unsigned int bytes) 1456 { 1457 int ring_id = render_mmio_to_ring_id(vgpu->gvt, offset); 1458 struct intel_vgpu_execlist *execlist; 1459 u32 data = *(u32 *)p_data; 1460 int ret = 0; 1461 1462 if (WARN_ON(ring_id < 0 || ring_id > I915_NUM_ENGINES - 1)) 1463 return -EINVAL; 1464 1465 execlist = &vgpu->execlist[ring_id]; 1466 1467 execlist->elsp_dwords.data[execlist->elsp_dwords.index] = data; 1468 if (execlist->elsp_dwords.index == 3) { 1469 ret = intel_vgpu_submit_execlist(vgpu, ring_id); 1470 if(ret) 1471 gvt_vgpu_err("fail submit workload on ring %d\n", 1472 ring_id); 1473 } 1474 1475 ++execlist->elsp_dwords.index; 1476 execlist->elsp_dwords.index &= 0x3; 1477 return ret; 1478 } 1479 1480 static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1481 void *p_data, unsigned int bytes) 1482 { 1483 u32 data = *(u32 *)p_data; 1484 int ring_id = render_mmio_to_ring_id(vgpu->gvt, offset); 1485 bool enable_execlist; 1486 1487 write_vreg(vgpu, offset, p_data, bytes); 1488 1489 /* when PPGTT mode enabled, we will check if guest has called 1490 * pvinfo, if not, we will treat this guest as non-gvtg-aware 1491 * guest, and stop emulating its cfg space, mmio, gtt, etc. 1492 */ 1493 if (((data & _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)) || 1494 (data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE))) 1495 && !vgpu->pv_notified) { 1496 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); 1497 return 0; 1498 } 1499 if ((data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)) 1500 || (data & _MASKED_BIT_DISABLE(GFX_RUN_LIST_ENABLE))) { 1501 enable_execlist = !!(data & GFX_RUN_LIST_ENABLE); 1502 1503 gvt_dbg_core("EXECLIST %s on ring %d\n", 1504 (enable_execlist ? "enabling" : "disabling"), 1505 ring_id); 1506 1507 if (enable_execlist) 1508 intel_vgpu_start_schedule(vgpu); 1509 } 1510 return 0; 1511 } 1512 1513 static int gvt_reg_tlb_control_handler(struct intel_vgpu *vgpu, 1514 unsigned int offset, void *p_data, unsigned int bytes) 1515 { 1516 unsigned int id = 0; 1517 1518 write_vreg(vgpu, offset, p_data, bytes); 1519 vgpu_vreg(vgpu, offset) = 0; 1520 1521 switch (offset) { 1522 case 0x4260: 1523 id = RCS; 1524 break; 1525 case 0x4264: 1526 id = VCS; 1527 break; 1528 case 0x4268: 1529 id = VCS2; 1530 break; 1531 case 0x426c: 1532 id = BCS; 1533 break; 1534 case 0x4270: 1535 id = VECS; 1536 break; 1537 default: 1538 return -EINVAL; 1539 } 1540 set_bit(id, (void *)vgpu->tlb_handle_pending); 1541 1542 return 0; 1543 } 1544 1545 static int ring_reset_ctl_write(struct intel_vgpu *vgpu, 1546 unsigned int offset, void *p_data, unsigned int bytes) 1547 { 1548 u32 data; 1549 1550 write_vreg(vgpu, offset, p_data, bytes); 1551 data = vgpu_vreg(vgpu, offset); 1552 1553 if (data & _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET)) 1554 data |= RESET_CTL_READY_TO_RESET; 1555 else if (data & _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET)) 1556 data &= ~RESET_CTL_READY_TO_RESET; 1557 1558 vgpu_vreg(vgpu, offset) = data; 1559 return 0; 1560 } 1561 1562 #define MMIO_F(reg, s, f, am, rm, d, r, w) do { \ 1563 ret = new_mmio_info(gvt, INTEL_GVT_MMIO_OFFSET(reg), \ 1564 f, s, am, rm, d, r, w); \ 1565 if (ret) \ 1566 return ret; \ 1567 } while (0) 1568 1569 #define MMIO_D(reg, d) \ 1570 MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL) 1571 1572 #define MMIO_DH(reg, d, r, w) \ 1573 MMIO_F(reg, 4, 0, 0, 0, d, r, w) 1574 1575 #define MMIO_DFH(reg, d, f, r, w) \ 1576 MMIO_F(reg, 4, f, 0, 0, d, r, w) 1577 1578 #define MMIO_GM(reg, d, r, w) \ 1579 MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w) 1580 1581 #define MMIO_GM_RDR(reg, d, r, w) \ 1582 MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w) 1583 1584 #define MMIO_RO(reg, d, f, rm, r, w) \ 1585 MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w) 1586 1587 #define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \ 1588 MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \ 1589 MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \ 1590 MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \ 1591 MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \ 1592 } while (0) 1593 1594 #define MMIO_RING_D(prefix, d) \ 1595 MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL) 1596 1597 #define MMIO_RING_DFH(prefix, d, f, r, w) \ 1598 MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w) 1599 1600 #define MMIO_RING_GM(prefix, d, r, w) \ 1601 MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w) 1602 1603 #define MMIO_RING_GM_RDR(prefix, d, r, w) \ 1604 MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w) 1605 1606 #define MMIO_RING_RO(prefix, d, f, rm, r, w) \ 1607 MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w) 1608 1609 static int init_generic_mmio_info(struct intel_gvt *gvt) 1610 { 1611 struct drm_i915_private *dev_priv = gvt->dev_priv; 1612 int ret; 1613 1614 MMIO_RING_DFH(RING_IMR, D_ALL, F_CMD_ACCESS, NULL, 1615 intel_vgpu_reg_imr_handler); 1616 1617 MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler); 1618 MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler); 1619 MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler); 1620 MMIO_D(SDEISR, D_ALL); 1621 1622 MMIO_RING_DFH(RING_HWSTAM, D_ALL, F_CMD_ACCESS, NULL, NULL); 1623 1624 MMIO_GM_RDR(RENDER_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1625 MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1626 MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1627 MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1628 1629 #define RING_REG(base) (base + 0x28) 1630 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL); 1631 #undef RING_REG 1632 1633 #define RING_REG(base) (base + 0x134) 1634 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL); 1635 #undef RING_REG 1636 1637 #define RING_REG(base) (base + 0x6c) 1638 MMIO_RING_DFH(RING_REG, D_ALL, 0, instdone_mmio_read, NULL); 1639 MMIO_DH(RING_REG(GEN8_BSD2_RING_BASE), D_ALL, instdone_mmio_read, NULL); 1640 #undef RING_REG 1641 MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, instdone_mmio_read, NULL); 1642 1643 MMIO_GM_RDR(0x2148, D_ALL, NULL, NULL); 1644 MMIO_GM_RDR(CCID, D_ALL, NULL, NULL); 1645 MMIO_GM_RDR(0x12198, D_ALL, NULL, NULL); 1646 MMIO_D(GEN7_CXT_SIZE, D_ALL); 1647 1648 MMIO_RING_DFH(RING_TAIL, D_ALL, F_CMD_ACCESS, NULL, NULL); 1649 MMIO_RING_DFH(RING_HEAD, D_ALL, F_CMD_ACCESS, NULL, NULL); 1650 MMIO_RING_DFH(RING_CTL, D_ALL, F_CMD_ACCESS, NULL, NULL); 1651 MMIO_RING_DFH(RING_ACTHD, D_ALL, F_CMD_ACCESS, NULL, NULL); 1652 MMIO_RING_GM_RDR(RING_START, D_ALL, NULL, NULL); 1653 1654 /* RING MODE */ 1655 #define RING_REG(base) (base + 0x29c) 1656 MMIO_RING_DFH(RING_REG, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, 1657 ring_mode_mmio_write); 1658 #undef RING_REG 1659 1660 MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 1661 NULL, NULL); 1662 MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 1663 NULL, NULL); 1664 MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS, 1665 ring_timestamp_mmio_read, NULL); 1666 MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS, 1667 ring_timestamp_mmio_read, NULL); 1668 1669 MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1670 MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 1671 NULL, NULL); 1672 MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1673 MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1674 MMIO_DFH(0x2124, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1675 1676 MMIO_DFH(0x20dc, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1677 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1678 MMIO_DFH(0x2088, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1679 MMIO_DFH(0x20e4, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1680 MMIO_DFH(0x2470, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1681 MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL); 1682 MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 1683 NULL, NULL); 1684 MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, 1685 skl_misc_ctl_write); 1686 MMIO_DFH(0x9030, D_ALL, F_CMD_ACCESS, NULL, NULL); 1687 MMIO_DFH(0x20a0, D_ALL, F_CMD_ACCESS, NULL, NULL); 1688 MMIO_DFH(0x2420, D_ALL, F_CMD_ACCESS, NULL, NULL); 1689 MMIO_DFH(0x2430, D_ALL, F_CMD_ACCESS, NULL, NULL); 1690 MMIO_DFH(0x2434, D_ALL, F_CMD_ACCESS, NULL, NULL); 1691 MMIO_DFH(0x2438, D_ALL, F_CMD_ACCESS, NULL, NULL); 1692 MMIO_DFH(0x243c, D_ALL, F_CMD_ACCESS, NULL, NULL); 1693 MMIO_DFH(0x7018, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1694 MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1695 MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1696 1697 /* display */ 1698 MMIO_F(0x60220, 0x20, 0, 0, 0, D_ALL, NULL, NULL); 1699 MMIO_D(0x602a0, D_ALL); 1700 1701 MMIO_D(0x65050, D_ALL); 1702 MMIO_D(0x650b4, D_ALL); 1703 1704 MMIO_D(0xc4040, D_ALL); 1705 MMIO_D(DERRMR, D_ALL); 1706 1707 MMIO_D(PIPEDSL(PIPE_A), D_ALL); 1708 MMIO_D(PIPEDSL(PIPE_B), D_ALL); 1709 MMIO_D(PIPEDSL(PIPE_C), D_ALL); 1710 MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL); 1711 1712 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write); 1713 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write); 1714 MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write); 1715 MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write); 1716 1717 MMIO_D(PIPESTAT(PIPE_A), D_ALL); 1718 MMIO_D(PIPESTAT(PIPE_B), D_ALL); 1719 MMIO_D(PIPESTAT(PIPE_C), D_ALL); 1720 MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL); 1721 1722 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL); 1723 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL); 1724 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL); 1725 MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL); 1726 1727 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL); 1728 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL); 1729 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL); 1730 MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL); 1731 1732 MMIO_D(CURCNTR(PIPE_A), D_ALL); 1733 MMIO_D(CURCNTR(PIPE_B), D_ALL); 1734 MMIO_D(CURCNTR(PIPE_C), D_ALL); 1735 1736 MMIO_D(CURPOS(PIPE_A), D_ALL); 1737 MMIO_D(CURPOS(PIPE_B), D_ALL); 1738 MMIO_D(CURPOS(PIPE_C), D_ALL); 1739 1740 MMIO_D(CURBASE(PIPE_A), D_ALL); 1741 MMIO_D(CURBASE(PIPE_B), D_ALL); 1742 MMIO_D(CURBASE(PIPE_C), D_ALL); 1743 1744 MMIO_D(0x700ac, D_ALL); 1745 MMIO_D(0x710ac, D_ALL); 1746 MMIO_D(0x720ac, D_ALL); 1747 1748 MMIO_D(0x70090, D_ALL); 1749 MMIO_D(0x70094, D_ALL); 1750 MMIO_D(0x70098, D_ALL); 1751 MMIO_D(0x7009c, D_ALL); 1752 1753 MMIO_D(DSPCNTR(PIPE_A), D_ALL); 1754 MMIO_D(DSPADDR(PIPE_A), D_ALL); 1755 MMIO_D(DSPSTRIDE(PIPE_A), D_ALL); 1756 MMIO_D(DSPPOS(PIPE_A), D_ALL); 1757 MMIO_D(DSPSIZE(PIPE_A), D_ALL); 1758 MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write); 1759 MMIO_D(DSPOFFSET(PIPE_A), D_ALL); 1760 MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL); 1761 1762 MMIO_D(DSPCNTR(PIPE_B), D_ALL); 1763 MMIO_D(DSPADDR(PIPE_B), D_ALL); 1764 MMIO_D(DSPSTRIDE(PIPE_B), D_ALL); 1765 MMIO_D(DSPPOS(PIPE_B), D_ALL); 1766 MMIO_D(DSPSIZE(PIPE_B), D_ALL); 1767 MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write); 1768 MMIO_D(DSPOFFSET(PIPE_B), D_ALL); 1769 MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL); 1770 1771 MMIO_D(DSPCNTR(PIPE_C), D_ALL); 1772 MMIO_D(DSPADDR(PIPE_C), D_ALL); 1773 MMIO_D(DSPSTRIDE(PIPE_C), D_ALL); 1774 MMIO_D(DSPPOS(PIPE_C), D_ALL); 1775 MMIO_D(DSPSIZE(PIPE_C), D_ALL); 1776 MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write); 1777 MMIO_D(DSPOFFSET(PIPE_C), D_ALL); 1778 MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL); 1779 1780 MMIO_D(SPRCTL(PIPE_A), D_ALL); 1781 MMIO_D(SPRLINOFF(PIPE_A), D_ALL); 1782 MMIO_D(SPRSTRIDE(PIPE_A), D_ALL); 1783 MMIO_D(SPRPOS(PIPE_A), D_ALL); 1784 MMIO_D(SPRSIZE(PIPE_A), D_ALL); 1785 MMIO_D(SPRKEYVAL(PIPE_A), D_ALL); 1786 MMIO_D(SPRKEYMSK(PIPE_A), D_ALL); 1787 MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write); 1788 MMIO_D(SPRKEYMAX(PIPE_A), D_ALL); 1789 MMIO_D(SPROFFSET(PIPE_A), D_ALL); 1790 MMIO_D(SPRSCALE(PIPE_A), D_ALL); 1791 MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL); 1792 1793 MMIO_D(SPRCTL(PIPE_B), D_ALL); 1794 MMIO_D(SPRLINOFF(PIPE_B), D_ALL); 1795 MMIO_D(SPRSTRIDE(PIPE_B), D_ALL); 1796 MMIO_D(SPRPOS(PIPE_B), D_ALL); 1797 MMIO_D(SPRSIZE(PIPE_B), D_ALL); 1798 MMIO_D(SPRKEYVAL(PIPE_B), D_ALL); 1799 MMIO_D(SPRKEYMSK(PIPE_B), D_ALL); 1800 MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write); 1801 MMIO_D(SPRKEYMAX(PIPE_B), D_ALL); 1802 MMIO_D(SPROFFSET(PIPE_B), D_ALL); 1803 MMIO_D(SPRSCALE(PIPE_B), D_ALL); 1804 MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL); 1805 1806 MMIO_D(SPRCTL(PIPE_C), D_ALL); 1807 MMIO_D(SPRLINOFF(PIPE_C), D_ALL); 1808 MMIO_D(SPRSTRIDE(PIPE_C), D_ALL); 1809 MMIO_D(SPRPOS(PIPE_C), D_ALL); 1810 MMIO_D(SPRSIZE(PIPE_C), D_ALL); 1811 MMIO_D(SPRKEYVAL(PIPE_C), D_ALL); 1812 MMIO_D(SPRKEYMSK(PIPE_C), D_ALL); 1813 MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write); 1814 MMIO_D(SPRKEYMAX(PIPE_C), D_ALL); 1815 MMIO_D(SPROFFSET(PIPE_C), D_ALL); 1816 MMIO_D(SPRSCALE(PIPE_C), D_ALL); 1817 MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL); 1818 1819 MMIO_D(HTOTAL(TRANSCODER_A), D_ALL); 1820 MMIO_D(HBLANK(TRANSCODER_A), D_ALL); 1821 MMIO_D(HSYNC(TRANSCODER_A), D_ALL); 1822 MMIO_D(VTOTAL(TRANSCODER_A), D_ALL); 1823 MMIO_D(VBLANK(TRANSCODER_A), D_ALL); 1824 MMIO_D(VSYNC(TRANSCODER_A), D_ALL); 1825 MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL); 1826 MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL); 1827 MMIO_D(PIPESRC(TRANSCODER_A), D_ALL); 1828 1829 MMIO_D(HTOTAL(TRANSCODER_B), D_ALL); 1830 MMIO_D(HBLANK(TRANSCODER_B), D_ALL); 1831 MMIO_D(HSYNC(TRANSCODER_B), D_ALL); 1832 MMIO_D(VTOTAL(TRANSCODER_B), D_ALL); 1833 MMIO_D(VBLANK(TRANSCODER_B), D_ALL); 1834 MMIO_D(VSYNC(TRANSCODER_B), D_ALL); 1835 MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL); 1836 MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL); 1837 MMIO_D(PIPESRC(TRANSCODER_B), D_ALL); 1838 1839 MMIO_D(HTOTAL(TRANSCODER_C), D_ALL); 1840 MMIO_D(HBLANK(TRANSCODER_C), D_ALL); 1841 MMIO_D(HSYNC(TRANSCODER_C), D_ALL); 1842 MMIO_D(VTOTAL(TRANSCODER_C), D_ALL); 1843 MMIO_D(VBLANK(TRANSCODER_C), D_ALL); 1844 MMIO_D(VSYNC(TRANSCODER_C), D_ALL); 1845 MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL); 1846 MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL); 1847 MMIO_D(PIPESRC(TRANSCODER_C), D_ALL); 1848 1849 MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL); 1850 MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL); 1851 MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL); 1852 MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL); 1853 MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL); 1854 MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL); 1855 MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL); 1856 MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL); 1857 1858 MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL); 1859 MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL); 1860 MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL); 1861 MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL); 1862 MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL); 1863 MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL); 1864 MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL); 1865 MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL); 1866 1867 MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL); 1868 MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL); 1869 MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL); 1870 MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL); 1871 MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL); 1872 MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL); 1873 MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL); 1874 MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL); 1875 1876 MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL); 1877 MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL); 1878 MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL); 1879 MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL); 1880 MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL); 1881 MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL); 1882 MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL); 1883 MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL); 1884 1885 MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL); 1886 MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL); 1887 MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL); 1888 MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL); 1889 MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL); 1890 MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL); 1891 MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL); 1892 MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL); 1893 1894 MMIO_D(PF_CTL(PIPE_A), D_ALL); 1895 MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL); 1896 MMIO_D(PF_WIN_POS(PIPE_A), D_ALL); 1897 MMIO_D(PF_VSCALE(PIPE_A), D_ALL); 1898 MMIO_D(PF_HSCALE(PIPE_A), D_ALL); 1899 1900 MMIO_D(PF_CTL(PIPE_B), D_ALL); 1901 MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL); 1902 MMIO_D(PF_WIN_POS(PIPE_B), D_ALL); 1903 MMIO_D(PF_VSCALE(PIPE_B), D_ALL); 1904 MMIO_D(PF_HSCALE(PIPE_B), D_ALL); 1905 1906 MMIO_D(PF_CTL(PIPE_C), D_ALL); 1907 MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL); 1908 MMIO_D(PF_WIN_POS(PIPE_C), D_ALL); 1909 MMIO_D(PF_VSCALE(PIPE_C), D_ALL); 1910 MMIO_D(PF_HSCALE(PIPE_C), D_ALL); 1911 1912 MMIO_D(WM0_PIPEA_ILK, D_ALL); 1913 MMIO_D(WM0_PIPEB_ILK, D_ALL); 1914 MMIO_D(WM0_PIPEC_IVB, D_ALL); 1915 MMIO_D(WM1_LP_ILK, D_ALL); 1916 MMIO_D(WM2_LP_ILK, D_ALL); 1917 MMIO_D(WM3_LP_ILK, D_ALL); 1918 MMIO_D(WM1S_LP_ILK, D_ALL); 1919 MMIO_D(WM2S_LP_IVB, D_ALL); 1920 MMIO_D(WM3S_LP_IVB, D_ALL); 1921 1922 MMIO_D(BLC_PWM_CPU_CTL2, D_ALL); 1923 MMIO_D(BLC_PWM_CPU_CTL, D_ALL); 1924 MMIO_D(BLC_PWM_PCH_CTL1, D_ALL); 1925 MMIO_D(BLC_PWM_PCH_CTL2, D_ALL); 1926 1927 MMIO_D(0x48268, D_ALL); 1928 1929 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read, 1930 gmbus_mmio_write); 1931 MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL); 1932 MMIO_F(0xe4f00, 0x28, 0, 0, 0, D_ALL, NULL, NULL); 1933 1934 MMIO_F(_PCH_DPB_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 1935 dp_aux_ch_ctl_mmio_write); 1936 MMIO_F(_PCH_DPC_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 1937 dp_aux_ch_ctl_mmio_write); 1938 MMIO_F(_PCH_DPD_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 1939 dp_aux_ch_ctl_mmio_write); 1940 1941 MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write); 1942 1943 MMIO_DH(_PCH_TRANSACONF, D_ALL, NULL, transconf_mmio_write); 1944 MMIO_DH(_PCH_TRANSBCONF, D_ALL, NULL, transconf_mmio_write); 1945 1946 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write); 1947 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write); 1948 MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write); 1949 MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); 1950 MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); 1951 MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); 1952 MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); 1953 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); 1954 MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); 1955 1956 MMIO_D(_PCH_TRANS_HTOTAL_A, D_ALL); 1957 MMIO_D(_PCH_TRANS_HBLANK_A, D_ALL); 1958 MMIO_D(_PCH_TRANS_HSYNC_A, D_ALL); 1959 MMIO_D(_PCH_TRANS_VTOTAL_A, D_ALL); 1960 MMIO_D(_PCH_TRANS_VBLANK_A, D_ALL); 1961 MMIO_D(_PCH_TRANS_VSYNC_A, D_ALL); 1962 MMIO_D(_PCH_TRANS_VSYNCSHIFT_A, D_ALL); 1963 1964 MMIO_D(_PCH_TRANS_HTOTAL_B, D_ALL); 1965 MMIO_D(_PCH_TRANS_HBLANK_B, D_ALL); 1966 MMIO_D(_PCH_TRANS_HSYNC_B, D_ALL); 1967 MMIO_D(_PCH_TRANS_VTOTAL_B, D_ALL); 1968 MMIO_D(_PCH_TRANS_VBLANK_B, D_ALL); 1969 MMIO_D(_PCH_TRANS_VSYNC_B, D_ALL); 1970 MMIO_D(_PCH_TRANS_VSYNCSHIFT_B, D_ALL); 1971 1972 MMIO_D(_PCH_TRANSA_DATA_M1, D_ALL); 1973 MMIO_D(_PCH_TRANSA_DATA_N1, D_ALL); 1974 MMIO_D(_PCH_TRANSA_DATA_M2, D_ALL); 1975 MMIO_D(_PCH_TRANSA_DATA_N2, D_ALL); 1976 MMIO_D(_PCH_TRANSA_LINK_M1, D_ALL); 1977 MMIO_D(_PCH_TRANSA_LINK_N1, D_ALL); 1978 MMIO_D(_PCH_TRANSA_LINK_M2, D_ALL); 1979 MMIO_D(_PCH_TRANSA_LINK_N2, D_ALL); 1980 1981 MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL); 1982 MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL); 1983 MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL); 1984 1985 MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL); 1986 MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL); 1987 MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL); 1988 1989 MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL); 1990 MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL); 1991 MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL); 1992 1993 MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL); 1994 MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL); 1995 MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL); 1996 1997 MMIO_D(_FDI_RXA_MISC, D_ALL); 1998 MMIO_D(_FDI_RXB_MISC, D_ALL); 1999 MMIO_D(_FDI_RXA_TUSIZE1, D_ALL); 2000 MMIO_D(_FDI_RXA_TUSIZE2, D_ALL); 2001 MMIO_D(_FDI_RXB_TUSIZE1, D_ALL); 2002 MMIO_D(_FDI_RXB_TUSIZE2, D_ALL); 2003 2004 MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write); 2005 MMIO_D(PCH_PP_DIVISOR, D_ALL); 2006 MMIO_D(PCH_PP_STATUS, D_ALL); 2007 MMIO_D(PCH_LVDS, D_ALL); 2008 MMIO_D(_PCH_DPLL_A, D_ALL); 2009 MMIO_D(_PCH_DPLL_B, D_ALL); 2010 MMIO_D(_PCH_FPA0, D_ALL); 2011 MMIO_D(_PCH_FPA1, D_ALL); 2012 MMIO_D(_PCH_FPB0, D_ALL); 2013 MMIO_D(_PCH_FPB1, D_ALL); 2014 MMIO_D(PCH_DREF_CONTROL, D_ALL); 2015 MMIO_D(PCH_RAWCLK_FREQ, D_ALL); 2016 MMIO_D(PCH_DPLL_SEL, D_ALL); 2017 2018 MMIO_D(0x61208, D_ALL); 2019 MMIO_D(0x6120c, D_ALL); 2020 MMIO_D(PCH_PP_ON_DELAYS, D_ALL); 2021 MMIO_D(PCH_PP_OFF_DELAYS, D_ALL); 2022 2023 MMIO_DH(0xe651c, D_ALL, dpy_reg_mmio_read, NULL); 2024 MMIO_DH(0xe661c, D_ALL, dpy_reg_mmio_read, NULL); 2025 MMIO_DH(0xe671c, D_ALL, dpy_reg_mmio_read, NULL); 2026 MMIO_DH(0xe681c, D_ALL, dpy_reg_mmio_read, NULL); 2027 MMIO_DH(0xe6c04, D_ALL, dpy_reg_mmio_read, NULL); 2028 MMIO_DH(0xe6e1c, D_ALL, dpy_reg_mmio_read, NULL); 2029 2030 MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0, 2031 PORTA_HOTPLUG_STATUS_MASK 2032 | PORTB_HOTPLUG_STATUS_MASK 2033 | PORTC_HOTPLUG_STATUS_MASK 2034 | PORTD_HOTPLUG_STATUS_MASK, 2035 NULL, NULL); 2036 2037 MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write); 2038 MMIO_D(FUSE_STRAP, D_ALL); 2039 MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL); 2040 2041 MMIO_D(DISP_ARB_CTL, D_ALL); 2042 MMIO_D(DISP_ARB_CTL2, D_ALL); 2043 2044 MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL); 2045 MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL); 2046 MMIO_D(ILK_DSPCLK_GATE_D, D_ALL); 2047 2048 MMIO_D(SOUTH_CHICKEN1, D_ALL); 2049 MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write); 2050 MMIO_D(_TRANSA_CHICKEN1, D_ALL); 2051 MMIO_D(_TRANSB_CHICKEN1, D_ALL); 2052 MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL); 2053 MMIO_D(_TRANSA_CHICKEN2, D_ALL); 2054 MMIO_D(_TRANSB_CHICKEN2, D_ALL); 2055 2056 MMIO_D(ILK_DPFC_CB_BASE, D_ALL); 2057 MMIO_D(ILK_DPFC_CONTROL, D_ALL); 2058 MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL); 2059 MMIO_D(ILK_DPFC_STATUS, D_ALL); 2060 MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL); 2061 MMIO_D(ILK_DPFC_CHICKEN, D_ALL); 2062 MMIO_D(ILK_FBC_RT_BASE, D_ALL); 2063 2064 MMIO_D(IPS_CTL, D_ALL); 2065 2066 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL); 2067 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL); 2068 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL); 2069 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL); 2070 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL); 2071 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL); 2072 MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL); 2073 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL); 2074 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL); 2075 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL); 2076 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL); 2077 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL); 2078 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL); 2079 2080 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL); 2081 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL); 2082 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL); 2083 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL); 2084 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL); 2085 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL); 2086 MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL); 2087 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL); 2088 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL); 2089 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL); 2090 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL); 2091 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL); 2092 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL); 2093 2094 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL); 2095 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL); 2096 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL); 2097 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL); 2098 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL); 2099 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL); 2100 MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL); 2101 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL); 2102 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL); 2103 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL); 2104 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL); 2105 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL); 2106 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL); 2107 2108 MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL); 2109 MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL); 2110 MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 2111 2112 MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL); 2113 MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL); 2114 MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 2115 2116 MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL); 2117 MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL); 2118 MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 2119 2120 MMIO_D(0x60110, D_ALL); 2121 MMIO_D(0x61110, D_ALL); 2122 MMIO_F(0x70400, 0x40, 0, 0, 0, D_ALL, NULL, NULL); 2123 MMIO_F(0x71400, 0x40, 0, 0, 0, D_ALL, NULL, NULL); 2124 MMIO_F(0x72400, 0x40, 0, 0, 0, D_ALL, NULL, NULL); 2125 MMIO_F(0x70440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2126 MMIO_F(0x71440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2127 MMIO_F(0x72440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2128 MMIO_F(0x7044c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2129 MMIO_F(0x7144c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2130 MMIO_F(0x7244c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2131 2132 MMIO_D(PIPE_WM_LINETIME(PIPE_A), D_ALL); 2133 MMIO_D(PIPE_WM_LINETIME(PIPE_B), D_ALL); 2134 MMIO_D(PIPE_WM_LINETIME(PIPE_C), D_ALL); 2135 MMIO_D(SPLL_CTL, D_ALL); 2136 MMIO_D(_WRPLL_CTL1, D_ALL); 2137 MMIO_D(_WRPLL_CTL2, D_ALL); 2138 MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL); 2139 MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL); 2140 MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL); 2141 MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL); 2142 MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL); 2143 MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL); 2144 MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL); 2145 MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL); 2146 2147 MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL); 2148 MMIO_D(0x46508, D_ALL); 2149 2150 MMIO_D(0x49080, D_ALL); 2151 MMIO_D(0x49180, D_ALL); 2152 MMIO_D(0x49280, D_ALL); 2153 2154 MMIO_F(0x49090, 0x14, 0, 0, 0, D_ALL, NULL, NULL); 2155 MMIO_F(0x49190, 0x14, 0, 0, 0, D_ALL, NULL, NULL); 2156 MMIO_F(0x49290, 0x14, 0, 0, 0, D_ALL, NULL, NULL); 2157 2158 MMIO_D(GAMMA_MODE(PIPE_A), D_ALL); 2159 MMIO_D(GAMMA_MODE(PIPE_B), D_ALL); 2160 MMIO_D(GAMMA_MODE(PIPE_C), D_ALL); 2161 2162 MMIO_D(PIPE_MULT(PIPE_A), D_ALL); 2163 MMIO_D(PIPE_MULT(PIPE_B), D_ALL); 2164 MMIO_D(PIPE_MULT(PIPE_C), D_ALL); 2165 2166 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL); 2167 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL); 2168 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL); 2169 2170 MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL); 2171 MMIO_D(SBI_ADDR, D_ALL); 2172 MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL); 2173 MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write); 2174 MMIO_D(PIXCLK_GATE, D_ALL); 2175 2176 MMIO_F(_DPA_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_ALL, NULL, 2177 dp_aux_ch_ctl_mmio_write); 2178 2179 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2180 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2181 MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2182 MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2183 MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2184 2185 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write); 2186 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write); 2187 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write); 2188 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write); 2189 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write); 2190 2191 MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write); 2192 MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write); 2193 MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write); 2194 MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write); 2195 MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL); 2196 2197 MMIO_F(_DDI_BUF_TRANS_A, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2198 MMIO_F(0x64e60, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2199 MMIO_F(0x64eC0, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2200 MMIO_F(0x64f20, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2201 MMIO_F(0x64f80, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2202 2203 MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL); 2204 MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL); 2205 2206 MMIO_DH(_TRANS_DDI_FUNC_CTL_A, D_ALL, NULL, NULL); 2207 MMIO_DH(_TRANS_DDI_FUNC_CTL_B, D_ALL, NULL, NULL); 2208 MMIO_DH(_TRANS_DDI_FUNC_CTL_C, D_ALL, NULL, NULL); 2209 MMIO_DH(_TRANS_DDI_FUNC_CTL_EDP, D_ALL, NULL, NULL); 2210 2211 MMIO_D(_TRANSA_MSA_MISC, D_ALL); 2212 MMIO_D(_TRANSB_MSA_MISC, D_ALL); 2213 MMIO_D(_TRANSC_MSA_MISC, D_ALL); 2214 MMIO_D(_TRANS_EDP_MSA_MISC, D_ALL); 2215 2216 MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL); 2217 MMIO_D(FORCEWAKE_ACK, D_ALL); 2218 MMIO_D(GEN6_GT_CORE_STATUS, D_ALL); 2219 MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL); 2220 MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL); 2221 MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL); 2222 MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write); 2223 MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL); 2224 MMIO_D(ECOBUS, D_ALL); 2225 MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL); 2226 MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL); 2227 MMIO_D(GEN6_RPNSWREQ, D_ALL); 2228 MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL); 2229 MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL); 2230 MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL); 2231 MMIO_D(GEN6_RPSTAT1, D_ALL); 2232 MMIO_D(GEN6_RP_CONTROL, D_ALL); 2233 MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL); 2234 MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL); 2235 MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL); 2236 MMIO_D(GEN6_RP_CUR_UP, D_ALL); 2237 MMIO_D(GEN6_RP_PREV_UP, D_ALL); 2238 MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL); 2239 MMIO_D(GEN6_RP_CUR_DOWN, D_ALL); 2240 MMIO_D(GEN6_RP_PREV_DOWN, D_ALL); 2241 MMIO_D(GEN6_RP_UP_EI, D_ALL); 2242 MMIO_D(GEN6_RP_DOWN_EI, D_ALL); 2243 MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL); 2244 MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL); 2245 MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL); 2246 MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL); 2247 MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL); 2248 MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL); 2249 MMIO_D(GEN6_RC_SLEEP, D_ALL); 2250 MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL); 2251 MMIO_D(GEN6_RC6_THRESHOLD, D_ALL); 2252 MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL); 2253 MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL); 2254 MMIO_D(GEN6_PMINTRMSK, D_ALL); 2255 /* 2256 * Use an arbitrary power well controlled by the PWR_WELL_CTL 2257 * register. 2258 */ 2259 MMIO_DH(HSW_PWR_WELL_CTL_BIOS(HSW_DISP_PW_GLOBAL), D_BDW, NULL, 2260 power_well_ctl_mmio_write); 2261 MMIO_DH(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL), D_BDW, NULL, 2262 power_well_ctl_mmio_write); 2263 MMIO_DH(HSW_PWR_WELL_CTL_KVMR, D_BDW, NULL, power_well_ctl_mmio_write); 2264 MMIO_DH(HSW_PWR_WELL_CTL_DEBUG(HSW_DISP_PW_GLOBAL), D_BDW, NULL, 2265 power_well_ctl_mmio_write); 2266 MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write); 2267 MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write); 2268 2269 MMIO_D(RSTDBYCTL, D_ALL); 2270 2271 MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write); 2272 MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write); 2273 MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write); 2274 2275 MMIO_D(TILECTL, D_ALL); 2276 2277 MMIO_D(GEN6_UCGCTL1, D_ALL); 2278 MMIO_D(GEN6_UCGCTL2, D_ALL); 2279 2280 MMIO_F(0x4f000, 0x90, 0, 0, 0, D_ALL, NULL, NULL); 2281 2282 MMIO_D(GEN6_PCODE_DATA, D_ALL); 2283 MMIO_D(0x13812c, D_ALL); 2284 MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL); 2285 MMIO_D(HSW_EDRAM_CAP, D_ALL); 2286 MMIO_D(HSW_IDICR, D_ALL); 2287 MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL); 2288 2289 MMIO_D(0x3c, D_ALL); 2290 MMIO_D(0x860, D_ALL); 2291 MMIO_D(ECOSKPD, D_ALL); 2292 MMIO_D(0x121d0, D_ALL); 2293 MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL); 2294 MMIO_D(0x41d0, D_ALL); 2295 MMIO_D(GAC_ECO_BITS, D_ALL); 2296 MMIO_D(0x6200, D_ALL); 2297 MMIO_D(0x6204, D_ALL); 2298 MMIO_D(0x6208, D_ALL); 2299 MMIO_D(0x7118, D_ALL); 2300 MMIO_D(0x7180, D_ALL); 2301 MMIO_D(0x7408, D_ALL); 2302 MMIO_D(0x7c00, D_ALL); 2303 MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write); 2304 MMIO_D(0x911c, D_ALL); 2305 MMIO_D(0x9120, D_ALL); 2306 MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL); 2307 2308 MMIO_D(GAB_CTL, D_ALL); 2309 MMIO_D(0x48800, D_ALL); 2310 MMIO_D(0xce044, D_ALL); 2311 MMIO_D(0xe6500, D_ALL); 2312 MMIO_D(0xe6504, D_ALL); 2313 MMIO_D(0xe6600, D_ALL); 2314 MMIO_D(0xe6604, D_ALL); 2315 MMIO_D(0xe6700, D_ALL); 2316 MMIO_D(0xe6704, D_ALL); 2317 MMIO_D(0xe6800, D_ALL); 2318 MMIO_D(0xe6804, D_ALL); 2319 MMIO_D(PCH_GMBUS4, D_ALL); 2320 MMIO_D(PCH_GMBUS5, D_ALL); 2321 2322 MMIO_D(0x902c, D_ALL); 2323 MMIO_D(0xec008, D_ALL); 2324 MMIO_D(0xec00c, D_ALL); 2325 MMIO_D(0xec008 + 0x18, D_ALL); 2326 MMIO_D(0xec00c + 0x18, D_ALL); 2327 MMIO_D(0xec008 + 0x18 * 2, D_ALL); 2328 MMIO_D(0xec00c + 0x18 * 2, D_ALL); 2329 MMIO_D(0xec008 + 0x18 * 3, D_ALL); 2330 MMIO_D(0xec00c + 0x18 * 3, D_ALL); 2331 MMIO_D(0xec408, D_ALL); 2332 MMIO_D(0xec40c, D_ALL); 2333 MMIO_D(0xec408 + 0x18, D_ALL); 2334 MMIO_D(0xec40c + 0x18, D_ALL); 2335 MMIO_D(0xec408 + 0x18 * 2, D_ALL); 2336 MMIO_D(0xec40c + 0x18 * 2, D_ALL); 2337 MMIO_D(0xec408 + 0x18 * 3, D_ALL); 2338 MMIO_D(0xec40c + 0x18 * 3, D_ALL); 2339 MMIO_D(0xfc810, D_ALL); 2340 MMIO_D(0xfc81c, D_ALL); 2341 MMIO_D(0xfc828, D_ALL); 2342 MMIO_D(0xfc834, D_ALL); 2343 MMIO_D(0xfcc00, D_ALL); 2344 MMIO_D(0xfcc0c, D_ALL); 2345 MMIO_D(0xfcc18, D_ALL); 2346 MMIO_D(0xfcc24, D_ALL); 2347 MMIO_D(0xfd000, D_ALL); 2348 MMIO_D(0xfd00c, D_ALL); 2349 MMIO_D(0xfd018, D_ALL); 2350 MMIO_D(0xfd024, D_ALL); 2351 MMIO_D(0xfd034, D_ALL); 2352 2353 MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write); 2354 MMIO_D(0x2054, D_ALL); 2355 MMIO_D(0x12054, D_ALL); 2356 MMIO_D(0x22054, D_ALL); 2357 MMIO_D(0x1a054, D_ALL); 2358 2359 MMIO_D(0x44070, D_ALL); 2360 MMIO_DFH(0x215c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2361 MMIO_DFH(0x2178, D_ALL, F_CMD_ACCESS, NULL, NULL); 2362 MMIO_DFH(0x217c, D_ALL, F_CMD_ACCESS, NULL, NULL); 2363 MMIO_DFH(0x12178, D_ALL, F_CMD_ACCESS, NULL, NULL); 2364 MMIO_DFH(0x1217c, D_ALL, F_CMD_ACCESS, NULL, NULL); 2365 2366 MMIO_F(0x2290, 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL); 2367 MMIO_D(0x2b00, D_BDW_PLUS); 2368 MMIO_D(0x2360, D_BDW_PLUS); 2369 MMIO_F(0x5200, 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2370 MMIO_F(0x5240, 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2371 MMIO_F(0x5280, 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2372 2373 MMIO_DFH(0x1c17c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2374 MMIO_DFH(0x1c178, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2375 MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL); 2376 2377 MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2378 MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2379 MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2380 MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2381 MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2382 MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2383 MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2384 MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2385 MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2386 MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2387 MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2388 MMIO_DH(0x4260, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2389 MMIO_DH(0x4264, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2390 MMIO_DH(0x4268, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2391 MMIO_DH(0x426c, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2392 MMIO_DH(0x4270, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2393 MMIO_DFH(0x4094, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2394 2395 MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2396 MMIO_RING_GM_RDR(RING_BBADDR, D_ALL, NULL, NULL); 2397 MMIO_DFH(0x2220, D_ALL, F_CMD_ACCESS, NULL, NULL); 2398 MMIO_DFH(0x12220, D_ALL, F_CMD_ACCESS, NULL, NULL); 2399 MMIO_DFH(0x22220, D_ALL, F_CMD_ACCESS, NULL, NULL); 2400 MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL); 2401 MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL); 2402 MMIO_DFH(0x22178, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2403 MMIO_DFH(0x1a178, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2404 MMIO_DFH(0x1a17c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2405 MMIO_DFH(0x2217c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2406 return 0; 2407 } 2408 2409 static int init_broadwell_mmio_info(struct intel_gvt *gvt) 2410 { 2411 struct drm_i915_private *dev_priv = gvt->dev_priv; 2412 int ret; 2413 2414 MMIO_DFH(RING_IMR(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS, NULL, 2415 intel_vgpu_reg_imr_handler); 2416 2417 MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2418 MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2419 MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2420 MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS); 2421 2422 MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2423 MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2424 MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2425 MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS); 2426 2427 MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2428 MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2429 MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2430 MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS); 2431 2432 MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2433 MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2434 MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2435 MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS); 2436 2437 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL, 2438 intel_vgpu_reg_imr_handler); 2439 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL, 2440 intel_vgpu_reg_ier_handler); 2441 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL, 2442 intel_vgpu_reg_iir_handler); 2443 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS); 2444 2445 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL, 2446 intel_vgpu_reg_imr_handler); 2447 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL, 2448 intel_vgpu_reg_ier_handler); 2449 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL, 2450 intel_vgpu_reg_iir_handler); 2451 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS); 2452 2453 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL, 2454 intel_vgpu_reg_imr_handler); 2455 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL, 2456 intel_vgpu_reg_ier_handler); 2457 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL, 2458 intel_vgpu_reg_iir_handler); 2459 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS); 2460 2461 MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2462 MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2463 MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2464 MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS); 2465 2466 MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2467 MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2468 MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2469 MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS); 2470 2471 MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2472 MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2473 MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2474 MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS); 2475 2476 MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL, 2477 intel_vgpu_reg_master_irq_handler); 2478 2479 MMIO_DFH(RING_HWSTAM(GEN8_BSD2_RING_BASE), D_BDW_PLUS, 2480 F_CMD_ACCESS, NULL, NULL); 2481 MMIO_DFH(0x1c134, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2482 2483 MMIO_DFH(RING_TAIL(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS, 2484 NULL, NULL); 2485 MMIO_DFH(RING_HEAD(GEN8_BSD2_RING_BASE), D_BDW_PLUS, 2486 F_CMD_ACCESS, NULL, NULL); 2487 MMIO_GM_RDR(RING_START(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, NULL); 2488 MMIO_DFH(RING_CTL(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS, 2489 NULL, NULL); 2490 MMIO_DFH(RING_ACTHD(GEN8_BSD2_RING_BASE), D_BDW_PLUS, 2491 F_CMD_ACCESS, NULL, NULL); 2492 MMIO_DFH(RING_ACTHD_UDW(GEN8_BSD2_RING_BASE), D_BDW_PLUS, 2493 F_CMD_ACCESS, NULL, NULL); 2494 MMIO_DFH(0x1c29c, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, 2495 ring_mode_mmio_write); 2496 MMIO_DFH(RING_MI_MODE(GEN8_BSD2_RING_BASE), D_BDW_PLUS, 2497 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2498 MMIO_DFH(RING_INSTPM(GEN8_BSD2_RING_BASE), D_BDW_PLUS, 2499 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2500 MMIO_DFH(RING_TIMESTAMP(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS, 2501 ring_timestamp_mmio_read, NULL); 2502 2503 MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2504 2505 #define RING_REG(base) (base + 0xd0) 2506 MMIO_RING_F(RING_REG, 4, F_RO, 0, 2507 ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL, 2508 ring_reset_ctl_write); 2509 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 4, F_RO, 0, 2510 ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL, 2511 ring_reset_ctl_write); 2512 #undef RING_REG 2513 2514 #define RING_REG(base) (base + 0x230) 2515 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write); 2516 MMIO_DH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, elsp_mmio_write); 2517 #undef RING_REG 2518 2519 #define RING_REG(base) (base + 0x234) 2520 MMIO_RING_F(RING_REG, 8, F_RO | F_CMD_ACCESS, 0, ~0, D_BDW_PLUS, 2521 NULL, NULL); 2522 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 4, F_RO | F_CMD_ACCESS, 0, 2523 ~0LL, D_BDW_PLUS, NULL, NULL); 2524 #undef RING_REG 2525 2526 #define RING_REG(base) (base + 0x244) 2527 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2528 MMIO_DFH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS, 2529 NULL, NULL); 2530 #undef RING_REG 2531 2532 #define RING_REG(base) (base + 0x370) 2533 MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL); 2534 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 48, F_RO, 0, ~0, D_BDW_PLUS, 2535 NULL, NULL); 2536 #undef RING_REG 2537 2538 #define RING_REG(base) (base + 0x3a0) 2539 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2540 MMIO_DFH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2541 #undef RING_REG 2542 2543 MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS); 2544 MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS); 2545 MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS); 2546 MMIO_D(0x1c1d0, D_BDW_PLUS); 2547 MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS); 2548 MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS); 2549 MMIO_D(0x1c054, D_BDW_PLUS); 2550 2551 MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write); 2552 2553 MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS); 2554 MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS); 2555 2556 MMIO_D(GAMTARBMODE, D_BDW_PLUS); 2557 2558 #define RING_REG(base) (base + 0x270) 2559 MMIO_RING_F(RING_REG, 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL); 2560 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL); 2561 #undef RING_REG 2562 2563 MMIO_RING_GM_RDR(RING_HWS_PGA, D_BDW_PLUS, NULL, NULL); 2564 MMIO_GM_RDR(RING_HWS_PGA(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, NULL); 2565 2566 MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2567 2568 MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS); 2569 MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS); 2570 MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS); 2571 2572 MMIO_D(WM_MISC, D_BDW); 2573 MMIO_D(BDW_EDP_PSR_BASE, D_BDW); 2574 2575 MMIO_D(0x66c00, D_BDW_PLUS); 2576 MMIO_D(0x66c04, D_BDW_PLUS); 2577 2578 MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS); 2579 2580 MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS); 2581 MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS); 2582 MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS); 2583 2584 MMIO_D(0xfdc, D_BDW_PLUS); 2585 MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2586 NULL, NULL); 2587 MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2588 NULL, NULL); 2589 MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2590 2591 MMIO_DFH(0xb1f0, D_BDW, F_CMD_ACCESS, NULL, NULL); 2592 MMIO_DFH(0xb1c0, D_BDW, F_CMD_ACCESS, NULL, NULL); 2593 MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2594 MMIO_DFH(0xb100, D_BDW, F_CMD_ACCESS, NULL, NULL); 2595 MMIO_DFH(0xb10c, D_BDW, F_CMD_ACCESS, NULL, NULL); 2596 MMIO_D(0xb110, D_BDW); 2597 2598 MMIO_F(0x24d0, 48, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, 2599 NULL, force_nonpriv_write); 2600 2601 MMIO_D(0x44484, D_BDW_PLUS); 2602 MMIO_D(0x4448c, D_BDW_PLUS); 2603 2604 MMIO_DFH(0x83a4, D_BDW, F_CMD_ACCESS, NULL, NULL); 2605 MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS); 2606 2607 MMIO_DFH(0x8430, D_BDW, F_CMD_ACCESS, NULL, NULL); 2608 2609 MMIO_D(0x110000, D_BDW_PLUS); 2610 2611 MMIO_D(0x48400, D_BDW_PLUS); 2612 2613 MMIO_D(0x6e570, D_BDW_PLUS); 2614 MMIO_D(0x65f10, D_BDW_PLUS); 2615 2616 MMIO_DFH(0xe194, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, 2617 skl_misc_ctl_write); 2618 MMIO_DFH(0xe188, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2619 MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2620 MMIO_DFH(0x2580, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2621 2622 MMIO_DFH(0x2248, D_BDW, F_CMD_ACCESS, NULL, NULL); 2623 2624 MMIO_DFH(0xe220, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2625 MMIO_DFH(0xe230, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2626 MMIO_DFH(0xe240, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2627 MMIO_DFH(0xe260, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2628 MMIO_DFH(0xe270, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2629 MMIO_DFH(0xe280, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2630 MMIO_DFH(0xe2a0, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2631 MMIO_DFH(0xe2b0, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2632 MMIO_DFH(0xe2c0, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2633 return 0; 2634 } 2635 2636 static int init_skl_mmio_info(struct intel_gvt *gvt) 2637 { 2638 struct drm_i915_private *dev_priv = gvt->dev_priv; 2639 int ret; 2640 2641 MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2642 MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL); 2643 MMIO_DH(FORCEWAKE_BLITTER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2644 MMIO_DH(FORCEWAKE_ACK_BLITTER_GEN9, D_SKL_PLUS, NULL, NULL); 2645 MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2646 MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL); 2647 2648 MMIO_F(_DPB_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 2649 dp_aux_ch_ctl_mmio_write); 2650 MMIO_F(_DPC_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 2651 dp_aux_ch_ctl_mmio_write); 2652 MMIO_F(_DPD_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 2653 dp_aux_ch_ctl_mmio_write); 2654 2655 /* 2656 * Use an arbitrary power well controlled by the PWR_WELL_CTL 2657 * register. 2658 */ 2659 MMIO_D(HSW_PWR_WELL_CTL_BIOS(SKL_DISP_PW_MISC_IO), D_SKL_PLUS); 2660 MMIO_DH(HSW_PWR_WELL_CTL_DRIVER(SKL_DISP_PW_MISC_IO), D_SKL_PLUS, NULL, 2661 skl_power_well_ctl_write); 2662 2663 MMIO_D(0xa210, D_SKL_PLUS); 2664 MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS); 2665 MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS); 2666 MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2667 MMIO_DH(0x4ddc, D_SKL_PLUS, NULL, skl_misc_ctl_write); 2668 MMIO_DH(0x42080, D_SKL_PLUS, NULL, skl_misc_ctl_write); 2669 MMIO_D(0x45504, D_SKL_PLUS); 2670 MMIO_D(0x45520, D_SKL_PLUS); 2671 MMIO_D(0x46000, D_SKL_PLUS); 2672 MMIO_DH(0x46010, D_SKL | D_KBL, NULL, skl_lcpll_write); 2673 MMIO_DH(0x46014, D_SKL | D_KBL, NULL, skl_lcpll_write); 2674 MMIO_D(0x6C040, D_SKL | D_KBL); 2675 MMIO_D(0x6C048, D_SKL | D_KBL); 2676 MMIO_D(0x6C050, D_SKL | D_KBL); 2677 MMIO_D(0x6C044, D_SKL | D_KBL); 2678 MMIO_D(0x6C04C, D_SKL | D_KBL); 2679 MMIO_D(0x6C054, D_SKL | D_KBL); 2680 MMIO_D(0x6c058, D_SKL | D_KBL); 2681 MMIO_D(0x6c05c, D_SKL | D_KBL); 2682 MMIO_DH(0X6c060, D_SKL | D_KBL, dpll_status_read, NULL); 2683 2684 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); 2685 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); 2686 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); 2687 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); 2688 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); 2689 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); 2690 2691 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); 2692 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); 2693 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); 2694 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); 2695 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); 2696 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); 2697 2698 MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); 2699 MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); 2700 MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); 2701 MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); 2702 MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); 2703 MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); 2704 2705 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 2706 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 2707 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 2708 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); 2709 2710 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 2711 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 2712 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 2713 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); 2714 2715 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 2716 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 2717 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2718 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); 2719 2720 MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL); 2721 MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL); 2722 MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL); 2723 2724 MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2725 MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2726 MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2727 2728 MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2729 MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2730 MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2731 2732 MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2733 MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2734 MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2735 2736 MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2737 MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2738 MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2739 2740 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 2741 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 2742 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 2743 2744 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 2745 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 2746 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 2747 2748 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 2749 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 2750 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2751 2752 MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL); 2753 MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL); 2754 MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL); 2755 2756 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 2757 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 2758 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 2759 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); 2760 2761 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 2762 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 2763 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 2764 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); 2765 2766 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 2767 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 2768 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2769 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); 2770 2771 MMIO_DH(_REG_701C0(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 2772 MMIO_DH(_REG_701C0(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 2773 MMIO_DH(_REG_701C0(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); 2774 MMIO_DH(_REG_701C0(PIPE_A, 4), D_SKL_PLUS, NULL, NULL); 2775 2776 MMIO_DH(_REG_701C0(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 2777 MMIO_DH(_REG_701C0(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 2778 MMIO_DH(_REG_701C0(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); 2779 MMIO_DH(_REG_701C0(PIPE_B, 4), D_SKL_PLUS, NULL, NULL); 2780 2781 MMIO_DH(_REG_701C0(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 2782 MMIO_DH(_REG_701C0(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2783 MMIO_DH(_REG_701C0(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); 2784 MMIO_DH(_REG_701C0(PIPE_C, 4), D_SKL_PLUS, NULL, NULL); 2785 2786 MMIO_DH(_REG_701C4(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 2787 MMIO_DH(_REG_701C4(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 2788 MMIO_DH(_REG_701C4(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); 2789 MMIO_DH(_REG_701C4(PIPE_A, 4), D_SKL_PLUS, NULL, NULL); 2790 2791 MMIO_DH(_REG_701C4(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 2792 MMIO_DH(_REG_701C4(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 2793 MMIO_DH(_REG_701C4(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); 2794 MMIO_DH(_REG_701C4(PIPE_B, 4), D_SKL_PLUS, NULL, NULL); 2795 2796 MMIO_DH(_REG_701C4(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 2797 MMIO_DH(_REG_701C4(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2798 MMIO_DH(_REG_701C4(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); 2799 MMIO_DH(_REG_701C4(PIPE_C, 4), D_SKL_PLUS, NULL, NULL); 2800 2801 MMIO_D(0x70380, D_SKL_PLUS); 2802 MMIO_D(0x71380, D_SKL_PLUS); 2803 MMIO_D(0x72380, D_SKL_PLUS); 2804 MMIO_D(0x7039c, D_SKL_PLUS); 2805 2806 MMIO_D(0x8f074, D_SKL | D_KBL); 2807 MMIO_D(0x8f004, D_SKL | D_KBL); 2808 MMIO_D(0x8f034, D_SKL | D_KBL); 2809 2810 MMIO_D(0xb11c, D_SKL | D_KBL); 2811 2812 MMIO_D(0x51000, D_SKL | D_KBL); 2813 MMIO_D(0x6c00c, D_SKL_PLUS); 2814 2815 MMIO_F(0xc800, 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL | D_KBL, NULL, NULL); 2816 MMIO_F(0xb020, 0x80, F_CMD_ACCESS, 0, 0, D_SKL | D_KBL, NULL, NULL); 2817 2818 MMIO_D(0xd08, D_SKL_PLUS); 2819 MMIO_DFH(0x20e0, D_SKL_PLUS, F_MODE_MASK, NULL, NULL); 2820 MMIO_DFH(0x20ec, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2821 2822 /* TRTT */ 2823 MMIO_DFH(0x4de0, D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL); 2824 MMIO_DFH(0x4de4, D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL); 2825 MMIO_DFH(0x4de8, D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL); 2826 MMIO_DFH(0x4dec, D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL); 2827 MMIO_DFH(0x4df0, D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL); 2828 MMIO_DFH(0x4df4, D_SKL | D_KBL, F_CMD_ACCESS, NULL, gen9_trtte_write); 2829 MMIO_DH(0x4dfc, D_SKL | D_KBL, NULL, gen9_trtt_chicken_write); 2830 2831 MMIO_D(0x45008, D_SKL | D_KBL); 2832 2833 MMIO_D(0x46430, D_SKL | D_KBL); 2834 2835 MMIO_D(0x46520, D_SKL | D_KBL); 2836 2837 MMIO_D(0xc403c, D_SKL | D_KBL); 2838 MMIO_D(0xb004, D_SKL_PLUS); 2839 MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write); 2840 2841 MMIO_D(0x65900, D_SKL_PLUS); 2842 MMIO_D(0x1082c0, D_SKL | D_KBL); 2843 MMIO_D(0x4068, D_SKL | D_KBL); 2844 MMIO_D(0x67054, D_SKL | D_KBL); 2845 MMIO_D(0x6e560, D_SKL | D_KBL); 2846 MMIO_D(0x6e554, D_SKL | D_KBL); 2847 MMIO_D(0x2b20, D_SKL | D_KBL); 2848 MMIO_D(0x65f00, D_SKL | D_KBL); 2849 MMIO_D(0x65f08, D_SKL | D_KBL); 2850 MMIO_D(0x320f0, D_SKL | D_KBL); 2851 2852 MMIO_DFH(_REG_VCS2_EXCC, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2853 MMIO_D(0x70034, D_SKL_PLUS); 2854 MMIO_D(0x71034, D_SKL_PLUS); 2855 MMIO_D(0x72034, D_SKL_PLUS); 2856 2857 MMIO_D(_PLANE_KEYVAL_1(PIPE_A), D_SKL_PLUS); 2858 MMIO_D(_PLANE_KEYVAL_1(PIPE_B), D_SKL_PLUS); 2859 MMIO_D(_PLANE_KEYVAL_1(PIPE_C), D_SKL_PLUS); 2860 MMIO_D(_PLANE_KEYMSK_1(PIPE_A), D_SKL_PLUS); 2861 MMIO_D(_PLANE_KEYMSK_1(PIPE_B), D_SKL_PLUS); 2862 MMIO_D(_PLANE_KEYMSK_1(PIPE_C), D_SKL_PLUS); 2863 2864 MMIO_D(0x44500, D_SKL_PLUS); 2865 MMIO_DFH(GEN9_CSFE_CHICKEN1_RCS, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2866 MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL | D_KBL, F_MODE_MASK | F_CMD_ACCESS, 2867 NULL, NULL); 2868 2869 MMIO_D(0x4ab8, D_KBL); 2870 MMIO_D(0x2248, D_SKL_PLUS | D_KBL); 2871 2872 return 0; 2873 } 2874 2875 static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt, 2876 unsigned int offset) 2877 { 2878 unsigned long device = intel_gvt_get_device_type(gvt); 2879 struct gvt_mmio_block *block = gvt->mmio.mmio_block; 2880 int num = gvt->mmio.num_mmio_block; 2881 int i; 2882 2883 for (i = 0; i < num; i++, block++) { 2884 if (!(device & block->device)) 2885 continue; 2886 if (offset >= INTEL_GVT_MMIO_OFFSET(block->offset) && 2887 offset < INTEL_GVT_MMIO_OFFSET(block->offset) + block->size) 2888 return block; 2889 } 2890 return NULL; 2891 } 2892 2893 /** 2894 * intel_gvt_clean_mmio_info - clean up MMIO information table for GVT device 2895 * @gvt: GVT device 2896 * 2897 * This function is called at the driver unloading stage, to clean up the MMIO 2898 * information table of GVT device 2899 * 2900 */ 2901 void intel_gvt_clean_mmio_info(struct intel_gvt *gvt) 2902 { 2903 struct hlist_node *tmp; 2904 struct intel_gvt_mmio_info *e; 2905 int i; 2906 2907 hash_for_each_safe(gvt->mmio.mmio_info_table, i, tmp, e, node) 2908 kfree(e); 2909 2910 vfree(gvt->mmio.mmio_attribute); 2911 gvt->mmio.mmio_attribute = NULL; 2912 } 2913 2914 /* Special MMIO blocks. */ 2915 static struct gvt_mmio_block mmio_blocks[] = { 2916 {D_SKL_PLUS, _MMIO(CSR_MMIO_START_RANGE), 0x3000, NULL, NULL}, 2917 {D_ALL, _MMIO(MCHBAR_MIRROR_BASE_SNB), 0x40000, NULL, NULL}, 2918 {D_ALL, _MMIO(VGT_PVINFO_PAGE), VGT_PVINFO_SIZE, 2919 pvinfo_mmio_read, pvinfo_mmio_write}, 2920 {D_ALL, LGC_PALETTE(PIPE_A, 0), 1024, NULL, NULL}, 2921 {D_ALL, LGC_PALETTE(PIPE_B, 0), 1024, NULL, NULL}, 2922 {D_ALL, LGC_PALETTE(PIPE_C, 0), 1024, NULL, NULL}, 2923 }; 2924 2925 /** 2926 * intel_gvt_setup_mmio_info - setup MMIO information table for GVT device 2927 * @gvt: GVT device 2928 * 2929 * This function is called at the initialization stage, to setup the MMIO 2930 * information table for GVT device 2931 * 2932 * Returns: 2933 * zero on success, negative if failed. 2934 */ 2935 int intel_gvt_setup_mmio_info(struct intel_gvt *gvt) 2936 { 2937 struct intel_gvt_device_info *info = &gvt->device_info; 2938 struct drm_i915_private *dev_priv = gvt->dev_priv; 2939 int size = info->mmio_size / 4 * sizeof(*gvt->mmio.mmio_attribute); 2940 int ret; 2941 2942 gvt->mmio.mmio_attribute = vzalloc(size); 2943 if (!gvt->mmio.mmio_attribute) 2944 return -ENOMEM; 2945 2946 ret = init_generic_mmio_info(gvt); 2947 if (ret) 2948 goto err; 2949 2950 if (IS_BROADWELL(dev_priv)) { 2951 ret = init_broadwell_mmio_info(gvt); 2952 if (ret) 2953 goto err; 2954 } else if (IS_SKYLAKE(dev_priv) 2955 || IS_KABYLAKE(dev_priv)) { 2956 ret = init_broadwell_mmio_info(gvt); 2957 if (ret) 2958 goto err; 2959 ret = init_skl_mmio_info(gvt); 2960 if (ret) 2961 goto err; 2962 } 2963 2964 gvt->mmio.mmio_block = mmio_blocks; 2965 gvt->mmio.num_mmio_block = ARRAY_SIZE(mmio_blocks); 2966 2967 gvt_dbg_mmio("traced %u virtual mmio registers\n", 2968 gvt->mmio.num_tracked_mmio); 2969 return 0; 2970 err: 2971 intel_gvt_clean_mmio_info(gvt); 2972 return ret; 2973 } 2974 2975 2976 /** 2977 * intel_vgpu_default_mmio_read - default MMIO read handler 2978 * @vgpu: a vGPU 2979 * @offset: access offset 2980 * @p_data: data return buffer 2981 * @bytes: access data length 2982 * 2983 * Returns: 2984 * Zero on success, negative error code if failed. 2985 */ 2986 int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 2987 void *p_data, unsigned int bytes) 2988 { 2989 read_vreg(vgpu, offset, p_data, bytes); 2990 return 0; 2991 } 2992 2993 /** 2994 * intel_t_default_mmio_write - default MMIO write handler 2995 * @vgpu: a vGPU 2996 * @offset: access offset 2997 * @p_data: write data buffer 2998 * @bytes: access data length 2999 * 3000 * Returns: 3001 * Zero on success, negative error code if failed. 3002 */ 3003 int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 3004 void *p_data, unsigned int bytes) 3005 { 3006 write_vreg(vgpu, offset, p_data, bytes); 3007 return 0; 3008 } 3009 3010 /** 3011 * intel_gvt_in_force_nonpriv_whitelist - if a mmio is in whitelist to be 3012 * force-nopriv register 3013 * 3014 * @gvt: a GVT device 3015 * @offset: register offset 3016 * 3017 * Returns: 3018 * True if the register is in force-nonpriv whitelist; 3019 * False if outside; 3020 */ 3021 bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt, 3022 unsigned int offset) 3023 { 3024 return in_whitelist(offset); 3025 } 3026 3027 /** 3028 * intel_vgpu_mmio_reg_rw - emulate tracked mmio registers 3029 * @vgpu: a vGPU 3030 * @offset: register offset 3031 * @pdata: data buffer 3032 * @bytes: data length 3033 * 3034 * Returns: 3035 * Zero on success, negative error code if failed. 3036 */ 3037 int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset, 3038 void *pdata, unsigned int bytes, bool is_read) 3039 { 3040 struct intel_gvt *gvt = vgpu->gvt; 3041 struct intel_gvt_mmio_info *mmio_info; 3042 struct gvt_mmio_block *mmio_block; 3043 gvt_mmio_func func; 3044 int ret; 3045 3046 if (WARN_ON(bytes > 8)) 3047 return -EINVAL; 3048 3049 /* 3050 * Handle special MMIO blocks. 3051 */ 3052 mmio_block = find_mmio_block(gvt, offset); 3053 if (mmio_block) { 3054 func = is_read ? mmio_block->read : mmio_block->write; 3055 if (func) 3056 return func(vgpu, offset, pdata, bytes); 3057 goto default_rw; 3058 } 3059 3060 /* 3061 * Normal tracked MMIOs. 3062 */ 3063 mmio_info = find_mmio_info(gvt, offset); 3064 if (!mmio_info) { 3065 if (!vgpu->mmio.disable_warn_untrack) 3066 gvt_vgpu_err("untracked MMIO %08x len %d\n", 3067 offset, bytes); 3068 goto default_rw; 3069 } 3070 3071 if (is_read) 3072 return mmio_info->read(vgpu, offset, pdata, bytes); 3073 else { 3074 u64 ro_mask = mmio_info->ro_mask; 3075 u32 old_vreg = 0, old_sreg = 0; 3076 u64 data = 0; 3077 3078 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) { 3079 old_vreg = vgpu_vreg(vgpu, offset); 3080 old_sreg = vgpu_sreg(vgpu, offset); 3081 } 3082 3083 if (likely(!ro_mask)) 3084 ret = mmio_info->write(vgpu, offset, pdata, bytes); 3085 else if (!~ro_mask) { 3086 gvt_vgpu_err("try to write RO reg %x\n", offset); 3087 return 0; 3088 } else { 3089 /* keep the RO bits in the virtual register */ 3090 memcpy(&data, pdata, bytes); 3091 data &= ~ro_mask; 3092 data |= vgpu_vreg(vgpu, offset) & ro_mask; 3093 ret = mmio_info->write(vgpu, offset, &data, bytes); 3094 } 3095 3096 /* higher 16bits of mode ctl regs are mask bits for change */ 3097 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) { 3098 u32 mask = vgpu_vreg(vgpu, offset) >> 16; 3099 3100 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask) 3101 | (vgpu_vreg(vgpu, offset) & mask); 3102 vgpu_sreg(vgpu, offset) = (old_sreg & ~mask) 3103 | (vgpu_sreg(vgpu, offset) & mask); 3104 } 3105 } 3106 3107 return ret; 3108 3109 default_rw: 3110 return is_read ? 3111 intel_vgpu_default_mmio_read(vgpu, offset, pdata, bytes) : 3112 intel_vgpu_default_mmio_write(vgpu, offset, pdata, bytes); 3113 } 3114