1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Kevin Tian <kevin.tian@intel.com> 25 * Eddie Dong <eddie.dong@intel.com> 26 * Zhiyuan Lv <zhiyuan.lv@intel.com> 27 * 28 * Contributors: 29 * Min He <min.he@intel.com> 30 * Tina Zhang <tina.zhang@intel.com> 31 * Pei Zhang <pei.zhang@intel.com> 32 * Niu Bing <bing.niu@intel.com> 33 * Ping Gao <ping.a.gao@intel.com> 34 * Zhi Wang <zhi.a.wang@intel.com> 35 * 36 37 */ 38 39 #include "i915_drv.h" 40 #include "gvt.h" 41 #include "i915_pvinfo.h" 42 #include "display/intel_display_types.h" 43 44 /* XXX FIXME i915 has changed PP_XXX definition */ 45 #define PCH_PP_STATUS _MMIO(0xc7200) 46 #define PCH_PP_CONTROL _MMIO(0xc7204) 47 #define PCH_PP_ON_DELAYS _MMIO(0xc7208) 48 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c) 49 #define PCH_PP_DIVISOR _MMIO(0xc7210) 50 51 unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt) 52 { 53 struct drm_i915_private *i915 = gvt->gt->i915; 54 55 if (IS_BROADWELL(i915)) 56 return D_BDW; 57 else if (IS_SKYLAKE(i915)) 58 return D_SKL; 59 else if (IS_KABYLAKE(i915)) 60 return D_KBL; 61 else if (IS_BROXTON(i915)) 62 return D_BXT; 63 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) 64 return D_CFL; 65 66 return 0; 67 } 68 69 bool intel_gvt_match_device(struct intel_gvt *gvt, 70 unsigned long device) 71 { 72 return intel_gvt_get_device_type(gvt) & device; 73 } 74 75 static void read_vreg(struct intel_vgpu *vgpu, unsigned int offset, 76 void *p_data, unsigned int bytes) 77 { 78 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); 79 } 80 81 static void write_vreg(struct intel_vgpu *vgpu, unsigned int offset, 82 void *p_data, unsigned int bytes) 83 { 84 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes); 85 } 86 87 struct intel_gvt_mmio_info *intel_gvt_find_mmio_info(struct intel_gvt *gvt, 88 unsigned int offset) 89 { 90 struct intel_gvt_mmio_info *e; 91 92 hash_for_each_possible(gvt->mmio.mmio_info_table, e, node, offset) { 93 if (e->offset == offset) 94 return e; 95 } 96 return NULL; 97 } 98 99 static int new_mmio_info(struct intel_gvt *gvt, 100 u32 offset, u16 flags, u32 size, 101 u32 addr_mask, u32 ro_mask, u32 device, 102 gvt_mmio_func read, gvt_mmio_func write) 103 { 104 struct intel_gvt_mmio_info *info, *p; 105 u32 start, end, i; 106 107 if (!intel_gvt_match_device(gvt, device)) 108 return 0; 109 110 if (WARN_ON(!IS_ALIGNED(offset, 4))) 111 return -EINVAL; 112 113 start = offset; 114 end = offset + size; 115 116 for (i = start; i < end; i += 4) { 117 info = kzalloc(sizeof(*info), GFP_KERNEL); 118 if (!info) 119 return -ENOMEM; 120 121 info->offset = i; 122 p = intel_gvt_find_mmio_info(gvt, info->offset); 123 if (p) { 124 WARN(1, "dup mmio definition offset %x\n", 125 info->offset); 126 kfree(info); 127 128 /* We return -EEXIST here to make GVT-g load fail. 129 * So duplicated MMIO can be found as soon as 130 * possible. 131 */ 132 return -EEXIST; 133 } 134 135 info->ro_mask = ro_mask; 136 info->device = device; 137 info->read = read ? read : intel_vgpu_default_mmio_read; 138 info->write = write ? write : intel_vgpu_default_mmio_write; 139 gvt->mmio.mmio_attribute[info->offset / 4] = flags; 140 INIT_HLIST_NODE(&info->node); 141 hash_add(gvt->mmio.mmio_info_table, &info->node, info->offset); 142 gvt->mmio.num_tracked_mmio++; 143 } 144 return 0; 145 } 146 147 /** 148 * intel_gvt_render_mmio_to_engine - convert a mmio offset into the engine 149 * @gvt: a GVT device 150 * @offset: register offset 151 * 152 * Returns: 153 * The engine containing the offset within its mmio page. 154 */ 155 const struct intel_engine_cs * 156 intel_gvt_render_mmio_to_engine(struct intel_gvt *gvt, unsigned int offset) 157 { 158 struct intel_engine_cs *engine; 159 enum intel_engine_id id; 160 161 offset &= ~GENMASK(11, 0); 162 for_each_engine(engine, gvt->gt, id) 163 if (engine->mmio_base == offset) 164 return engine; 165 166 return NULL; 167 } 168 169 #define offset_to_fence_num(offset) \ 170 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3) 171 172 #define fence_num_to_offset(num) \ 173 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) 174 175 176 void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason) 177 { 178 switch (reason) { 179 case GVT_FAILSAFE_UNSUPPORTED_GUEST: 180 pr_err("Detected your guest driver doesn't support GVT-g.\n"); 181 break; 182 case GVT_FAILSAFE_INSUFFICIENT_RESOURCE: 183 pr_err("Graphics resource is not enough for the guest\n"); 184 break; 185 case GVT_FAILSAFE_GUEST_ERR: 186 pr_err("GVT Internal error for the guest\n"); 187 break; 188 default: 189 break; 190 } 191 pr_err("Now vgpu %d will enter failsafe mode.\n", vgpu->id); 192 vgpu->failsafe = true; 193 } 194 195 static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu, 196 unsigned int fence_num, void *p_data, unsigned int bytes) 197 { 198 unsigned int max_fence = vgpu_fence_sz(vgpu); 199 200 if (fence_num >= max_fence) { 201 gvt_vgpu_err("access oob fence reg %d/%d\n", 202 fence_num, max_fence); 203 204 /* When guest access oob fence regs without access 205 * pv_info first, we treat guest not supporting GVT, 206 * and we will let vgpu enter failsafe mode. 207 */ 208 if (!vgpu->pv_notified) 209 enter_failsafe_mode(vgpu, 210 GVT_FAILSAFE_UNSUPPORTED_GUEST); 211 212 memset(p_data, 0, bytes); 213 return -EINVAL; 214 } 215 return 0; 216 } 217 218 static int gamw_echo_dev_rw_ia_write(struct intel_vgpu *vgpu, 219 unsigned int offset, void *p_data, unsigned int bytes) 220 { 221 u32 ips = (*(u32 *)p_data) & GAMW_ECO_ENABLE_64K_IPS_FIELD; 222 223 if (GRAPHICS_VER(vgpu->gvt->gt->i915) <= 10) { 224 if (ips == GAMW_ECO_ENABLE_64K_IPS_FIELD) 225 gvt_dbg_core("vgpu%d: ips enabled\n", vgpu->id); 226 else if (!ips) 227 gvt_dbg_core("vgpu%d: ips disabled\n", vgpu->id); 228 else { 229 /* All engines must be enabled together for vGPU, 230 * since we don't know which engine the ppgtt will 231 * bind to when shadowing. 232 */ 233 gvt_vgpu_err("Unsupported IPS setting %x, cannot enable 64K gtt.\n", 234 ips); 235 return -EINVAL; 236 } 237 } 238 239 write_vreg(vgpu, offset, p_data, bytes); 240 return 0; 241 } 242 243 static int fence_mmio_read(struct intel_vgpu *vgpu, unsigned int off, 244 void *p_data, unsigned int bytes) 245 { 246 int ret; 247 248 ret = sanitize_fence_mmio_access(vgpu, offset_to_fence_num(off), 249 p_data, bytes); 250 if (ret) 251 return ret; 252 read_vreg(vgpu, off, p_data, bytes); 253 return 0; 254 } 255 256 static int fence_mmio_write(struct intel_vgpu *vgpu, unsigned int off, 257 void *p_data, unsigned int bytes) 258 { 259 struct intel_gvt *gvt = vgpu->gvt; 260 unsigned int fence_num = offset_to_fence_num(off); 261 int ret; 262 263 ret = sanitize_fence_mmio_access(vgpu, fence_num, p_data, bytes); 264 if (ret) 265 return ret; 266 write_vreg(vgpu, off, p_data, bytes); 267 268 mmio_hw_access_pre(gvt->gt); 269 intel_vgpu_write_fence(vgpu, fence_num, 270 vgpu_vreg64(vgpu, fence_num_to_offset(fence_num))); 271 mmio_hw_access_post(gvt->gt); 272 return 0; 273 } 274 275 #define CALC_MODE_MASK_REG(old, new) \ 276 (((new) & GENMASK(31, 16)) \ 277 | ((((old) & GENMASK(15, 0)) & ~((new) >> 16)) \ 278 | ((new) & ((new) >> 16)))) 279 280 static int mul_force_wake_write(struct intel_vgpu *vgpu, 281 unsigned int offset, void *p_data, unsigned int bytes) 282 { 283 u32 old, new; 284 u32 ack_reg_offset; 285 286 old = vgpu_vreg(vgpu, offset); 287 new = CALC_MODE_MASK_REG(old, *(u32 *)p_data); 288 289 if (GRAPHICS_VER(vgpu->gvt->gt->i915) >= 9) { 290 switch (offset) { 291 case FORCEWAKE_RENDER_GEN9_REG: 292 ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG; 293 break; 294 case FORCEWAKE_GT_GEN9_REG: 295 ack_reg_offset = FORCEWAKE_ACK_GT_GEN9_REG; 296 break; 297 case FORCEWAKE_MEDIA_GEN9_REG: 298 ack_reg_offset = FORCEWAKE_ACK_MEDIA_GEN9_REG; 299 break; 300 default: 301 /*should not hit here*/ 302 gvt_vgpu_err("invalid forcewake offset 0x%x\n", offset); 303 return -EINVAL; 304 } 305 } else { 306 ack_reg_offset = FORCEWAKE_ACK_HSW_REG; 307 } 308 309 vgpu_vreg(vgpu, offset) = new; 310 vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0)); 311 return 0; 312 } 313 314 static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 315 void *p_data, unsigned int bytes) 316 { 317 intel_engine_mask_t engine_mask = 0; 318 u32 data; 319 320 write_vreg(vgpu, offset, p_data, bytes); 321 data = vgpu_vreg(vgpu, offset); 322 323 if (data & GEN6_GRDOM_FULL) { 324 gvt_dbg_mmio("vgpu%d: request full GPU reset\n", vgpu->id); 325 engine_mask = ALL_ENGINES; 326 } else { 327 if (data & GEN6_GRDOM_RENDER) { 328 gvt_dbg_mmio("vgpu%d: request RCS reset\n", vgpu->id); 329 engine_mask |= BIT(RCS0); 330 } 331 if (data & GEN6_GRDOM_MEDIA) { 332 gvt_dbg_mmio("vgpu%d: request VCS reset\n", vgpu->id); 333 engine_mask |= BIT(VCS0); 334 } 335 if (data & GEN6_GRDOM_BLT) { 336 gvt_dbg_mmio("vgpu%d: request BCS Reset\n", vgpu->id); 337 engine_mask |= BIT(BCS0); 338 } 339 if (data & GEN6_GRDOM_VECS) { 340 gvt_dbg_mmio("vgpu%d: request VECS Reset\n", vgpu->id); 341 engine_mask |= BIT(VECS0); 342 } 343 if (data & GEN8_GRDOM_MEDIA2) { 344 gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id); 345 engine_mask |= BIT(VCS1); 346 } 347 if (data & GEN9_GRDOM_GUC) { 348 gvt_dbg_mmio("vgpu%d: request GUC Reset\n", vgpu->id); 349 vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET; 350 } 351 engine_mask &= vgpu->gvt->gt->info.engine_mask; 352 } 353 354 /* vgpu_lock already hold by emulate mmio r/w */ 355 intel_gvt_reset_vgpu_locked(vgpu, false, engine_mask); 356 357 /* sw will wait for the device to ack the reset request */ 358 vgpu_vreg(vgpu, offset) = 0; 359 360 return 0; 361 } 362 363 static int gmbus_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 364 void *p_data, unsigned int bytes) 365 { 366 return intel_gvt_i2c_handle_gmbus_read(vgpu, offset, p_data, bytes); 367 } 368 369 static int gmbus_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 370 void *p_data, unsigned int bytes) 371 { 372 return intel_gvt_i2c_handle_gmbus_write(vgpu, offset, p_data, bytes); 373 } 374 375 static int pch_pp_control_mmio_write(struct intel_vgpu *vgpu, 376 unsigned int offset, void *p_data, unsigned int bytes) 377 { 378 write_vreg(vgpu, offset, p_data, bytes); 379 380 if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) { 381 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_ON; 382 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE; 383 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN; 384 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE; 385 386 } else 387 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= 388 ~(PP_ON | PP_SEQUENCE_POWER_DOWN 389 | PP_CYCLE_DELAY_ACTIVE); 390 return 0; 391 } 392 393 static int transconf_mmio_write(struct intel_vgpu *vgpu, 394 unsigned int offset, void *p_data, unsigned int bytes) 395 { 396 write_vreg(vgpu, offset, p_data, bytes); 397 398 if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE) 399 vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE; 400 else 401 vgpu_vreg(vgpu, offset) &= ~TRANS_STATE_ENABLE; 402 return 0; 403 } 404 405 static int lcpll_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 406 void *p_data, unsigned int bytes) 407 { 408 write_vreg(vgpu, offset, p_data, bytes); 409 410 if (vgpu_vreg(vgpu, offset) & LCPLL_PLL_DISABLE) 411 vgpu_vreg(vgpu, offset) &= ~LCPLL_PLL_LOCK; 412 else 413 vgpu_vreg(vgpu, offset) |= LCPLL_PLL_LOCK; 414 415 if (vgpu_vreg(vgpu, offset) & LCPLL_CD_SOURCE_FCLK) 416 vgpu_vreg(vgpu, offset) |= LCPLL_CD_SOURCE_FCLK_DONE; 417 else 418 vgpu_vreg(vgpu, offset) &= ~LCPLL_CD_SOURCE_FCLK_DONE; 419 420 return 0; 421 } 422 423 static int dpy_reg_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 424 void *p_data, unsigned int bytes) 425 { 426 switch (offset) { 427 case 0xe651c: 428 case 0xe661c: 429 case 0xe671c: 430 case 0xe681c: 431 vgpu_vreg(vgpu, offset) = 1 << 17; 432 break; 433 case 0xe6c04: 434 vgpu_vreg(vgpu, offset) = 0x3; 435 break; 436 case 0xe6e1c: 437 vgpu_vreg(vgpu, offset) = 0x2f << 16; 438 break; 439 default: 440 return -EINVAL; 441 } 442 443 read_vreg(vgpu, offset, p_data, bytes); 444 return 0; 445 } 446 447 /* 448 * Only PIPE_A is enabled in current vGPU display and PIPE_A is tied to 449 * TRANSCODER_A in HW. DDI/PORT could be PORT_x depends on 450 * setup_virtual_dp_monitor(). 451 * emulate_monitor_status_change() set up PLL for PORT_x as the initial enabled 452 * DPLL. Later guest driver may setup a different DPLLx when setting mode. 453 * So the correct sequence to find DP stream clock is: 454 * Check TRANS_DDI_FUNC_CTL on TRANSCODER_A to get PORT_x. 455 * Check correct PLLx for PORT_x to get PLL frequency and DP bitrate. 456 * Then Refresh rate then can be calculated based on follow equations: 457 * Pixel clock = h_total * v_total * refresh_rate 458 * stream clock = Pixel clock 459 * ls_clk = DP bitrate 460 * Link M/N = strm_clk / ls_clk 461 */ 462 463 static u32 bdw_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port) 464 { 465 u32 dp_br = 0; 466 u32 ddi_pll_sel = vgpu_vreg_t(vgpu, PORT_CLK_SEL(port)); 467 468 switch (ddi_pll_sel) { 469 case PORT_CLK_SEL_LCPLL_2700: 470 dp_br = 270000 * 2; 471 break; 472 case PORT_CLK_SEL_LCPLL_1350: 473 dp_br = 135000 * 2; 474 break; 475 case PORT_CLK_SEL_LCPLL_810: 476 dp_br = 81000 * 2; 477 break; 478 case PORT_CLK_SEL_SPLL: 479 { 480 switch (vgpu_vreg_t(vgpu, SPLL_CTL) & SPLL_FREQ_MASK) { 481 case SPLL_FREQ_810MHz: 482 dp_br = 81000 * 2; 483 break; 484 case SPLL_FREQ_1350MHz: 485 dp_br = 135000 * 2; 486 break; 487 case SPLL_FREQ_2700MHz: 488 dp_br = 270000 * 2; 489 break; 490 default: 491 gvt_dbg_dpy("vgpu-%d PORT_%c can't get freq from SPLL 0x%08x\n", 492 vgpu->id, port_name(port), vgpu_vreg_t(vgpu, SPLL_CTL)); 493 break; 494 } 495 break; 496 } 497 case PORT_CLK_SEL_WRPLL1: 498 case PORT_CLK_SEL_WRPLL2: 499 { 500 u32 wrpll_ctl; 501 int refclk, n, p, r; 502 503 if (ddi_pll_sel == PORT_CLK_SEL_WRPLL1) 504 wrpll_ctl = vgpu_vreg_t(vgpu, WRPLL_CTL(DPLL_ID_WRPLL1)); 505 else 506 wrpll_ctl = vgpu_vreg_t(vgpu, WRPLL_CTL(DPLL_ID_WRPLL2)); 507 508 switch (wrpll_ctl & WRPLL_REF_MASK) { 509 case WRPLL_REF_PCH_SSC: 510 refclk = vgpu->gvt->gt->i915->dpll.ref_clks.ssc; 511 break; 512 case WRPLL_REF_LCPLL: 513 refclk = 2700000; 514 break; 515 default: 516 gvt_dbg_dpy("vgpu-%d PORT_%c WRPLL can't get refclk 0x%08x\n", 517 vgpu->id, port_name(port), wrpll_ctl); 518 goto out; 519 } 520 521 r = wrpll_ctl & WRPLL_DIVIDER_REF_MASK; 522 p = (wrpll_ctl & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT; 523 n = (wrpll_ctl & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT; 524 525 dp_br = (refclk * n / 10) / (p * r) * 2; 526 break; 527 } 528 default: 529 gvt_dbg_dpy("vgpu-%d PORT_%c has invalid clock select 0x%08x\n", 530 vgpu->id, port_name(port), vgpu_vreg_t(vgpu, PORT_CLK_SEL(port))); 531 break; 532 } 533 534 out: 535 return dp_br; 536 } 537 538 static u32 bxt_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port) 539 { 540 u32 dp_br = 0; 541 int refclk = vgpu->gvt->gt->i915->dpll.ref_clks.nssc; 542 enum dpio_phy phy = DPIO_PHY0; 543 enum dpio_channel ch = DPIO_CH0; 544 struct dpll clock = {0}; 545 u32 temp; 546 547 /* Port to PHY mapping is fixed, see bxt_ddi_phy_info{} */ 548 switch (port) { 549 case PORT_A: 550 phy = DPIO_PHY1; 551 ch = DPIO_CH0; 552 break; 553 case PORT_B: 554 phy = DPIO_PHY0; 555 ch = DPIO_CH0; 556 break; 557 case PORT_C: 558 phy = DPIO_PHY0; 559 ch = DPIO_CH1; 560 break; 561 default: 562 gvt_dbg_dpy("vgpu-%d no PHY for PORT_%c\n", vgpu->id, port_name(port)); 563 goto out; 564 } 565 566 temp = vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(port)); 567 if (!(temp & PORT_PLL_ENABLE) || !(temp & PORT_PLL_LOCK)) { 568 gvt_dbg_dpy("vgpu-%d PORT_%c PLL_ENABLE 0x%08x isn't enabled or locked\n", 569 vgpu->id, port_name(port), temp); 570 goto out; 571 } 572 573 clock.m1 = 2; 574 clock.m2 = (vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 0)) & PORT_PLL_M2_MASK) << 22; 575 if (vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 3)) & PORT_PLL_M2_FRAC_ENABLE) 576 clock.m2 |= vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 2)) & PORT_PLL_M2_FRAC_MASK; 577 clock.n = (vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 1)) & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT; 578 clock.p1 = (vgpu_vreg_t(vgpu, BXT_PORT_PLL_EBB_0(phy, ch)) & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT; 579 clock.p2 = (vgpu_vreg_t(vgpu, BXT_PORT_PLL_EBB_0(phy, ch)) & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT; 580 clock.m = clock.m1 * clock.m2; 581 clock.p = clock.p1 * clock.p2; 582 583 if (clock.n == 0 || clock.p == 0) { 584 gvt_dbg_dpy("vgpu-%d PORT_%c PLL has invalid divider\n", vgpu->id, port_name(port)); 585 goto out; 586 } 587 588 clock.vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock.m), clock.n << 22); 589 clock.dot = DIV_ROUND_CLOSEST(clock.vco, clock.p); 590 591 dp_br = clock.dot / 5; 592 593 out: 594 return dp_br; 595 } 596 597 static u32 skl_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port) 598 { 599 u32 dp_br = 0; 600 enum intel_dpll_id dpll_id = DPLL_ID_SKL_DPLL0; 601 602 /* Find the enabled DPLL for the DDI/PORT */ 603 if (!(vgpu_vreg_t(vgpu, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)) && 604 (vgpu_vreg_t(vgpu, DPLL_CTRL2) & DPLL_CTRL2_DDI_SEL_OVERRIDE(port))) { 605 dpll_id += (vgpu_vreg_t(vgpu, DPLL_CTRL2) & 606 DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> 607 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); 608 } else { 609 gvt_dbg_dpy("vgpu-%d DPLL for PORT_%c isn't turned on\n", 610 vgpu->id, port_name(port)); 611 return dp_br; 612 } 613 614 /* Find PLL output frequency from correct DPLL, and get bir rate */ 615 switch ((vgpu_vreg_t(vgpu, DPLL_CTRL1) & 616 DPLL_CTRL1_LINK_RATE_MASK(dpll_id)) >> 617 DPLL_CTRL1_LINK_RATE_SHIFT(dpll_id)) { 618 case DPLL_CTRL1_LINK_RATE_810: 619 dp_br = 81000 * 2; 620 break; 621 case DPLL_CTRL1_LINK_RATE_1080: 622 dp_br = 108000 * 2; 623 break; 624 case DPLL_CTRL1_LINK_RATE_1350: 625 dp_br = 135000 * 2; 626 break; 627 case DPLL_CTRL1_LINK_RATE_1620: 628 dp_br = 162000 * 2; 629 break; 630 case DPLL_CTRL1_LINK_RATE_2160: 631 dp_br = 216000 * 2; 632 break; 633 case DPLL_CTRL1_LINK_RATE_2700: 634 dp_br = 270000 * 2; 635 break; 636 default: 637 dp_br = 0; 638 gvt_dbg_dpy("vgpu-%d PORT_%c fail to get DPLL-%d freq\n", 639 vgpu->id, port_name(port), dpll_id); 640 } 641 642 return dp_br; 643 } 644 645 static void vgpu_update_refresh_rate(struct intel_vgpu *vgpu) 646 { 647 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 648 enum port port; 649 u32 dp_br, link_m, link_n, htotal, vtotal; 650 651 /* Find DDI/PORT assigned to TRANSCODER_A, expect B or D */ 652 port = (vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) & 653 TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; 654 if (port != PORT_B && port != PORT_D) { 655 gvt_dbg_dpy("vgpu-%d unsupported PORT_%c\n", vgpu->id, port_name(port)); 656 return; 657 } 658 659 /* Calculate DP bitrate from PLL */ 660 if (IS_BROADWELL(dev_priv)) 661 dp_br = bdw_vgpu_get_dp_bitrate(vgpu, port); 662 else if (IS_BROXTON(dev_priv)) 663 dp_br = bxt_vgpu_get_dp_bitrate(vgpu, port); 664 else 665 dp_br = skl_vgpu_get_dp_bitrate(vgpu, port); 666 667 /* Get DP link symbol clock M/N */ 668 link_m = vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)); 669 link_n = vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)); 670 671 /* Get H/V total from transcoder timing */ 672 htotal = (vgpu_vreg_t(vgpu, HTOTAL(TRANSCODER_A)) >> TRANS_HTOTAL_SHIFT); 673 vtotal = (vgpu_vreg_t(vgpu, VTOTAL(TRANSCODER_A)) >> TRANS_VTOTAL_SHIFT); 674 675 if (dp_br && link_n && htotal && vtotal) { 676 u64 pixel_clk = 0; 677 u32 new_rate = 0; 678 u32 *old_rate = &(intel_vgpu_port(vgpu, vgpu->display.port_num)->vrefresh_k); 679 680 /* Calcuate pixel clock by (ls_clk * M / N) */ 681 pixel_clk = div_u64(mul_u32_u32(link_m, dp_br), link_n); 682 pixel_clk *= MSEC_PER_SEC; 683 684 /* Calcuate refresh rate by (pixel_clk / (h_total * v_total)) */ 685 new_rate = DIV64_U64_ROUND_CLOSEST(mul_u64_u32_shr(pixel_clk, MSEC_PER_SEC, 0), mul_u32_u32(htotal + 1, vtotal + 1)); 686 687 if (*old_rate != new_rate) 688 *old_rate = new_rate; 689 690 gvt_dbg_dpy("vgpu-%d PIPE_%c refresh rate updated to %d\n", 691 vgpu->id, pipe_name(PIPE_A), new_rate); 692 } 693 } 694 695 static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 696 void *p_data, unsigned int bytes) 697 { 698 u32 data; 699 700 write_vreg(vgpu, offset, p_data, bytes); 701 data = vgpu_vreg(vgpu, offset); 702 703 if (data & PIPECONF_ENABLE) { 704 vgpu_vreg(vgpu, offset) |= I965_PIPECONF_ACTIVE; 705 vgpu_update_refresh_rate(vgpu); 706 vgpu_update_vblank_emulation(vgpu, true); 707 } else { 708 vgpu_vreg(vgpu, offset) &= ~I965_PIPECONF_ACTIVE; 709 vgpu_update_vblank_emulation(vgpu, false); 710 } 711 return 0; 712 } 713 714 /* sorted in ascending order */ 715 static i915_reg_t force_nonpriv_white_list[] = { 716 _MMIO(0xd80), 717 GEN9_CS_DEBUG_MODE1, //_MMIO(0x20ec) 718 GEN9_CTX_PREEMPT_REG,//_MMIO(0x2248) 719 CL_PRIMITIVES_COUNT, //_MMIO(0x2340) 720 PS_INVOCATION_COUNT, //_MMIO(0x2348) 721 PS_DEPTH_COUNT, //_MMIO(0x2350) 722 GEN8_CS_CHICKEN1,//_MMIO(0x2580) 723 _MMIO(0x2690), 724 _MMIO(0x2694), 725 _MMIO(0x2698), 726 _MMIO(0x2754), 727 _MMIO(0x28a0), 728 _MMIO(0x4de0), 729 _MMIO(0x4de4), 730 _MMIO(0x4dfc), 731 GEN7_COMMON_SLICE_CHICKEN1,//_MMIO(0x7010) 732 _MMIO(0x7014), 733 HDC_CHICKEN0,//_MMIO(0x7300) 734 GEN8_HDC_CHICKEN1,//_MMIO(0x7304) 735 _MMIO(0x7700), 736 _MMIO(0x7704), 737 _MMIO(0x7708), 738 _MMIO(0x770c), 739 _MMIO(0x83a8), 740 _MMIO(0xb110), 741 GEN8_L3SQCREG4,//_MMIO(0xb118) 742 _MMIO(0xe100), 743 _MMIO(0xe18c), 744 _MMIO(0xe48c), 745 _MMIO(0xe5f4), 746 _MMIO(0x64844), 747 }; 748 749 /* a simple bsearch */ 750 static inline bool in_whitelist(u32 reg) 751 { 752 int left = 0, right = ARRAY_SIZE(force_nonpriv_white_list); 753 i915_reg_t *array = force_nonpriv_white_list; 754 755 while (left < right) { 756 int mid = (left + right)/2; 757 758 if (reg > array[mid].reg) 759 left = mid + 1; 760 else if (reg < array[mid].reg) 761 right = mid; 762 else 763 return true; 764 } 765 return false; 766 } 767 768 static int force_nonpriv_write(struct intel_vgpu *vgpu, 769 unsigned int offset, void *p_data, unsigned int bytes) 770 { 771 u32 reg_nonpriv = (*(u32 *)p_data) & REG_GENMASK(25, 2); 772 const struct intel_engine_cs *engine = 773 intel_gvt_render_mmio_to_engine(vgpu->gvt, offset); 774 775 if (bytes != 4 || !IS_ALIGNED(offset, bytes) || !engine) { 776 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV offset %x(%dB)\n", 777 vgpu->id, offset, bytes); 778 return -EINVAL; 779 } 780 781 if (!in_whitelist(reg_nonpriv) && 782 reg_nonpriv != i915_mmio_reg_offset(RING_NOPID(engine->mmio_base))) { 783 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x at offset %x\n", 784 vgpu->id, reg_nonpriv, offset); 785 } else 786 intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes); 787 788 return 0; 789 } 790 791 static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 792 void *p_data, unsigned int bytes) 793 { 794 write_vreg(vgpu, offset, p_data, bytes); 795 796 if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) { 797 vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE; 798 } else { 799 vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE; 800 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E))) 801 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) 802 &= ~DP_TP_STATUS_AUTOTRAIN_DONE; 803 } 804 return 0; 805 } 806 807 static int fdi_rx_iir_mmio_write(struct intel_vgpu *vgpu, 808 unsigned int offset, void *p_data, unsigned int bytes) 809 { 810 vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data; 811 return 0; 812 } 813 814 #define FDI_LINK_TRAIN_PATTERN1 0 815 #define FDI_LINK_TRAIN_PATTERN2 1 816 817 static int fdi_auto_training_started(struct intel_vgpu *vgpu) 818 { 819 u32 ddi_buf_ctl = vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_E)); 820 u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL); 821 u32 tx_ctl = vgpu_vreg_t(vgpu, DP_TP_CTL(PORT_E)); 822 823 if ((ddi_buf_ctl & DDI_BUF_CTL_ENABLE) && 824 (rx_ctl & FDI_RX_ENABLE) && 825 (rx_ctl & FDI_AUTO_TRAINING) && 826 (tx_ctl & DP_TP_CTL_ENABLE) && 827 (tx_ctl & DP_TP_CTL_FDI_AUTOTRAIN)) 828 return 1; 829 else 830 return 0; 831 } 832 833 static int check_fdi_rx_train_status(struct intel_vgpu *vgpu, 834 enum pipe pipe, unsigned int train_pattern) 835 { 836 i915_reg_t fdi_rx_imr, fdi_tx_ctl, fdi_rx_ctl; 837 unsigned int fdi_rx_check_bits, fdi_tx_check_bits; 838 unsigned int fdi_rx_train_bits, fdi_tx_train_bits; 839 unsigned int fdi_iir_check_bits; 840 841 fdi_rx_imr = FDI_RX_IMR(pipe); 842 fdi_tx_ctl = FDI_TX_CTL(pipe); 843 fdi_rx_ctl = FDI_RX_CTL(pipe); 844 845 if (train_pattern == FDI_LINK_TRAIN_PATTERN1) { 846 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_1_CPT; 847 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_1; 848 fdi_iir_check_bits = FDI_RX_BIT_LOCK; 849 } else if (train_pattern == FDI_LINK_TRAIN_PATTERN2) { 850 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_2_CPT; 851 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_2; 852 fdi_iir_check_bits = FDI_RX_SYMBOL_LOCK; 853 } else { 854 gvt_vgpu_err("Invalid train pattern %d\n", train_pattern); 855 return -EINVAL; 856 } 857 858 fdi_rx_check_bits = FDI_RX_ENABLE | fdi_rx_train_bits; 859 fdi_tx_check_bits = FDI_TX_ENABLE | fdi_tx_train_bits; 860 861 /* If imr bit has been masked */ 862 if (vgpu_vreg_t(vgpu, fdi_rx_imr) & fdi_iir_check_bits) 863 return 0; 864 865 if (((vgpu_vreg_t(vgpu, fdi_tx_ctl) & fdi_tx_check_bits) 866 == fdi_tx_check_bits) 867 && ((vgpu_vreg_t(vgpu, fdi_rx_ctl) & fdi_rx_check_bits) 868 == fdi_rx_check_bits)) 869 return 1; 870 else 871 return 0; 872 } 873 874 #define INVALID_INDEX (~0U) 875 876 static unsigned int calc_index(unsigned int offset, unsigned int start, 877 unsigned int next, unsigned int end, i915_reg_t i915_end) 878 { 879 unsigned int range = next - start; 880 881 if (!end) 882 end = i915_mmio_reg_offset(i915_end); 883 if (offset < start || offset > end) 884 return INVALID_INDEX; 885 offset -= start; 886 return offset / range; 887 } 888 889 #define FDI_RX_CTL_TO_PIPE(offset) \ 890 calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, 0, FDI_RX_CTL(PIPE_C)) 891 892 #define FDI_TX_CTL_TO_PIPE(offset) \ 893 calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, 0, FDI_TX_CTL(PIPE_C)) 894 895 #define FDI_RX_IMR_TO_PIPE(offset) \ 896 calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, 0, FDI_RX_IMR(PIPE_C)) 897 898 static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu, 899 unsigned int offset, void *p_data, unsigned int bytes) 900 { 901 i915_reg_t fdi_rx_iir; 902 unsigned int index; 903 int ret; 904 905 if (FDI_RX_CTL_TO_PIPE(offset) != INVALID_INDEX) 906 index = FDI_RX_CTL_TO_PIPE(offset); 907 else if (FDI_TX_CTL_TO_PIPE(offset) != INVALID_INDEX) 908 index = FDI_TX_CTL_TO_PIPE(offset); 909 else if (FDI_RX_IMR_TO_PIPE(offset) != INVALID_INDEX) 910 index = FDI_RX_IMR_TO_PIPE(offset); 911 else { 912 gvt_vgpu_err("Unsupport registers %x\n", offset); 913 return -EINVAL; 914 } 915 916 write_vreg(vgpu, offset, p_data, bytes); 917 918 fdi_rx_iir = FDI_RX_IIR(index); 919 920 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN1); 921 if (ret < 0) 922 return ret; 923 if (ret) 924 vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK; 925 926 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN2); 927 if (ret < 0) 928 return ret; 929 if (ret) 930 vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK; 931 932 if (offset == _FDI_RXA_CTL) 933 if (fdi_auto_training_started(vgpu)) 934 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) |= 935 DP_TP_STATUS_AUTOTRAIN_DONE; 936 return 0; 937 } 938 939 #define DP_TP_CTL_TO_PORT(offset) \ 940 calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, 0, DP_TP_CTL(PORT_E)) 941 942 static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 943 void *p_data, unsigned int bytes) 944 { 945 i915_reg_t status_reg; 946 unsigned int index; 947 u32 data; 948 949 write_vreg(vgpu, offset, p_data, bytes); 950 951 index = DP_TP_CTL_TO_PORT(offset); 952 data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8; 953 if (data == 0x2) { 954 status_reg = DP_TP_STATUS(index); 955 vgpu_vreg_t(vgpu, status_reg) |= (1 << 25); 956 } 957 return 0; 958 } 959 960 static int dp_tp_status_mmio_write(struct intel_vgpu *vgpu, 961 unsigned int offset, void *p_data, unsigned int bytes) 962 { 963 u32 reg_val; 964 u32 sticky_mask; 965 966 reg_val = *((u32 *)p_data); 967 sticky_mask = GENMASK(27, 26) | (1 << 24); 968 969 vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) | 970 (vgpu_vreg(vgpu, offset) & sticky_mask); 971 vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask); 972 return 0; 973 } 974 975 static int pch_adpa_mmio_write(struct intel_vgpu *vgpu, 976 unsigned int offset, void *p_data, unsigned int bytes) 977 { 978 u32 data; 979 980 write_vreg(vgpu, offset, p_data, bytes); 981 data = vgpu_vreg(vgpu, offset); 982 983 if (data & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) 984 vgpu_vreg(vgpu, offset) &= ~ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 985 return 0; 986 } 987 988 static int south_chicken2_mmio_write(struct intel_vgpu *vgpu, 989 unsigned int offset, void *p_data, unsigned int bytes) 990 { 991 u32 data; 992 993 write_vreg(vgpu, offset, p_data, bytes); 994 data = vgpu_vreg(vgpu, offset); 995 996 if (data & FDI_MPHY_IOSFSB_RESET_CTL) 997 vgpu_vreg(vgpu, offset) |= FDI_MPHY_IOSFSB_RESET_STATUS; 998 else 999 vgpu_vreg(vgpu, offset) &= ~FDI_MPHY_IOSFSB_RESET_STATUS; 1000 return 0; 1001 } 1002 1003 #define DSPSURF_TO_PIPE(offset) \ 1004 calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C)) 1005 1006 static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1007 void *p_data, unsigned int bytes) 1008 { 1009 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 1010 u32 pipe = DSPSURF_TO_PIPE(offset); 1011 int event = SKL_FLIP_EVENT(pipe, PLANE_PRIMARY); 1012 1013 write_vreg(vgpu, offset, p_data, bytes); 1014 vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); 1015 1016 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++; 1017 1018 if (vgpu_vreg_t(vgpu, DSPCNTR(pipe)) & PLANE_CTL_ASYNC_FLIP) 1019 intel_vgpu_trigger_virtual_event(vgpu, event); 1020 else 1021 set_bit(event, vgpu->irq.flip_done_event[pipe]); 1022 1023 return 0; 1024 } 1025 1026 #define SPRSURF_TO_PIPE(offset) \ 1027 calc_index(offset, _SPRA_SURF, _SPRB_SURF, 0, SPRSURF(PIPE_C)) 1028 1029 static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1030 void *p_data, unsigned int bytes) 1031 { 1032 u32 pipe = SPRSURF_TO_PIPE(offset); 1033 int event = SKL_FLIP_EVENT(pipe, PLANE_SPRITE0); 1034 1035 write_vreg(vgpu, offset, p_data, bytes); 1036 vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); 1037 1038 if (vgpu_vreg_t(vgpu, SPRCTL(pipe)) & PLANE_CTL_ASYNC_FLIP) 1039 intel_vgpu_trigger_virtual_event(vgpu, event); 1040 else 1041 set_bit(event, vgpu->irq.flip_done_event[pipe]); 1042 1043 return 0; 1044 } 1045 1046 static int reg50080_mmio_write(struct intel_vgpu *vgpu, 1047 unsigned int offset, void *p_data, 1048 unsigned int bytes) 1049 { 1050 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 1051 enum pipe pipe = REG_50080_TO_PIPE(offset); 1052 enum plane_id plane = REG_50080_TO_PLANE(offset); 1053 int event = SKL_FLIP_EVENT(pipe, plane); 1054 1055 write_vreg(vgpu, offset, p_data, bytes); 1056 if (plane == PLANE_PRIMARY) { 1057 vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); 1058 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++; 1059 } else { 1060 vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); 1061 } 1062 1063 if ((vgpu_vreg(vgpu, offset) & REG50080_FLIP_TYPE_MASK) == REG50080_FLIP_TYPE_ASYNC) 1064 intel_vgpu_trigger_virtual_event(vgpu, event); 1065 else 1066 set_bit(event, vgpu->irq.flip_done_event[pipe]); 1067 1068 return 0; 1069 } 1070 1071 static int trigger_aux_channel_interrupt(struct intel_vgpu *vgpu, 1072 unsigned int reg) 1073 { 1074 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 1075 enum intel_gvt_event_type event; 1076 1077 if (reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_A))) 1078 event = AUX_CHANNEL_A; 1079 else if (reg == _PCH_DPB_AUX_CH_CTL || 1080 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_B))) 1081 event = AUX_CHANNEL_B; 1082 else if (reg == _PCH_DPC_AUX_CH_CTL || 1083 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_C))) 1084 event = AUX_CHANNEL_C; 1085 else if (reg == _PCH_DPD_AUX_CH_CTL || 1086 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_D))) 1087 event = AUX_CHANNEL_D; 1088 else { 1089 drm_WARN_ON(&dev_priv->drm, true); 1090 return -EINVAL; 1091 } 1092 1093 intel_vgpu_trigger_virtual_event(vgpu, event); 1094 return 0; 1095 } 1096 1097 static int dp_aux_ch_ctl_trans_done(struct intel_vgpu *vgpu, u32 value, 1098 unsigned int reg, int len, bool data_valid) 1099 { 1100 /* mark transaction done */ 1101 value |= DP_AUX_CH_CTL_DONE; 1102 value &= ~DP_AUX_CH_CTL_SEND_BUSY; 1103 value &= ~DP_AUX_CH_CTL_RECEIVE_ERROR; 1104 1105 if (data_valid) 1106 value &= ~DP_AUX_CH_CTL_TIME_OUT_ERROR; 1107 else 1108 value |= DP_AUX_CH_CTL_TIME_OUT_ERROR; 1109 1110 /* message size */ 1111 value &= ~(0xf << 20); 1112 value |= (len << 20); 1113 vgpu_vreg(vgpu, reg) = value; 1114 1115 if (value & DP_AUX_CH_CTL_INTERRUPT) 1116 return trigger_aux_channel_interrupt(vgpu, reg); 1117 return 0; 1118 } 1119 1120 static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd, 1121 u8 t) 1122 { 1123 if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == DPCD_TRAINING_PATTERN_1) { 1124 /* training pattern 1 for CR */ 1125 /* set LANE0_CR_DONE, LANE1_CR_DONE */ 1126 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_CR_DONE; 1127 /* set LANE2_CR_DONE, LANE3_CR_DONE */ 1128 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_CR_DONE; 1129 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == 1130 DPCD_TRAINING_PATTERN_2) { 1131 /* training pattern 2 for EQ */ 1132 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane0_1 */ 1133 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_EQ_DONE; 1134 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_SYMBOL_LOCKED; 1135 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane2_3 */ 1136 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_EQ_DONE; 1137 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_SYMBOL_LOCKED; 1138 /* set INTERLANE_ALIGN_DONE */ 1139 dpcd->data[DPCD_LANE_ALIGN_STATUS_UPDATED] |= 1140 DPCD_INTERLANE_ALIGN_DONE; 1141 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == 1142 DPCD_LINK_TRAINING_DISABLED) { 1143 /* finish link training */ 1144 /* set sink status as synchronized */ 1145 dpcd->data[DPCD_SINK_STATUS] = DPCD_SINK_IN_SYNC; 1146 } 1147 } 1148 1149 #define _REG_HSW_DP_AUX_CH_CTL(dp) \ 1150 ((dp) ? (_PCH_DPB_AUX_CH_CTL + ((dp)-1)*0x100) : 0x64010) 1151 1152 #define _REG_SKL_DP_AUX_CH_CTL(dp) (0x64010 + (dp) * 0x100) 1153 1154 #define OFFSET_TO_DP_AUX_PORT(offset) (((offset) & 0xF00) >> 8) 1155 1156 #define dpy_is_valid_port(port) \ 1157 (((port) >= PORT_A) && ((port) < I915_MAX_PORTS)) 1158 1159 static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu, 1160 unsigned int offset, void *p_data, unsigned int bytes) 1161 { 1162 struct intel_vgpu_display *display = &vgpu->display; 1163 int msg, addr, ctrl, op, len; 1164 int port_index = OFFSET_TO_DP_AUX_PORT(offset); 1165 struct intel_vgpu_dpcd_data *dpcd = NULL; 1166 struct intel_vgpu_port *port = NULL; 1167 u32 data; 1168 1169 if (!dpy_is_valid_port(port_index)) { 1170 gvt_vgpu_err("Unsupported DP port access!\n"); 1171 return 0; 1172 } 1173 1174 write_vreg(vgpu, offset, p_data, bytes); 1175 data = vgpu_vreg(vgpu, offset); 1176 1177 if ((GRAPHICS_VER(vgpu->gvt->gt->i915) >= 9) 1178 && offset != _REG_SKL_DP_AUX_CH_CTL(port_index)) { 1179 /* SKL DPB/C/D aux ctl register changed */ 1180 return 0; 1181 } else if (IS_BROADWELL(vgpu->gvt->gt->i915) && 1182 offset != _REG_HSW_DP_AUX_CH_CTL(port_index)) { 1183 /* write to the data registers */ 1184 return 0; 1185 } 1186 1187 if (!(data & DP_AUX_CH_CTL_SEND_BUSY)) { 1188 /* just want to clear the sticky bits */ 1189 vgpu_vreg(vgpu, offset) = 0; 1190 return 0; 1191 } 1192 1193 port = &display->ports[port_index]; 1194 dpcd = port->dpcd; 1195 1196 /* read out message from DATA1 register */ 1197 msg = vgpu_vreg(vgpu, offset + 4); 1198 addr = (msg >> 8) & 0xffff; 1199 ctrl = (msg >> 24) & 0xff; 1200 len = msg & 0xff; 1201 op = ctrl >> 4; 1202 1203 if (op == GVT_AUX_NATIVE_WRITE) { 1204 int t; 1205 u8 buf[16]; 1206 1207 if ((addr + len + 1) >= DPCD_SIZE) { 1208 /* 1209 * Write request exceeds what we supported, 1210 * DCPD spec: When a Source Device is writing a DPCD 1211 * address not supported by the Sink Device, the Sink 1212 * Device shall reply with AUX NACK and “M” equal to 1213 * zero. 1214 */ 1215 1216 /* NAK the write */ 1217 vgpu_vreg(vgpu, offset + 4) = AUX_NATIVE_REPLY_NAK; 1218 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 2, true); 1219 return 0; 1220 } 1221 1222 /* 1223 * Write request format: Headr (command + address + size) occupies 1224 * 4 bytes, followed by (len + 1) bytes of data. See details at 1225 * intel_dp_aux_transfer(). 1226 */ 1227 if ((len + 1 + 4) > AUX_BURST_SIZE) { 1228 gvt_vgpu_err("dp_aux_header: len %d is too large\n", len); 1229 return -EINVAL; 1230 } 1231 1232 /* unpack data from vreg to buf */ 1233 for (t = 0; t < 4; t++) { 1234 u32 r = vgpu_vreg(vgpu, offset + 8 + t * 4); 1235 1236 buf[t * 4] = (r >> 24) & 0xff; 1237 buf[t * 4 + 1] = (r >> 16) & 0xff; 1238 buf[t * 4 + 2] = (r >> 8) & 0xff; 1239 buf[t * 4 + 3] = r & 0xff; 1240 } 1241 1242 /* write to virtual DPCD */ 1243 if (dpcd && dpcd->data_valid) { 1244 for (t = 0; t <= len; t++) { 1245 int p = addr + t; 1246 1247 dpcd->data[p] = buf[t]; 1248 /* check for link training */ 1249 if (p == DPCD_TRAINING_PATTERN_SET) 1250 dp_aux_ch_ctl_link_training(dpcd, 1251 buf[t]); 1252 } 1253 } 1254 1255 /* ACK the write */ 1256 vgpu_vreg(vgpu, offset + 4) = 0; 1257 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 1, 1258 dpcd && dpcd->data_valid); 1259 return 0; 1260 } 1261 1262 if (op == GVT_AUX_NATIVE_READ) { 1263 int idx, i, ret = 0; 1264 1265 if ((addr + len + 1) >= DPCD_SIZE) { 1266 /* 1267 * read request exceeds what we supported 1268 * DPCD spec: A Sink Device receiving a Native AUX CH 1269 * read request for an unsupported DPCD address must 1270 * reply with an AUX ACK and read data set equal to 1271 * zero instead of replying with AUX NACK. 1272 */ 1273 1274 /* ACK the READ*/ 1275 vgpu_vreg(vgpu, offset + 4) = 0; 1276 vgpu_vreg(vgpu, offset + 8) = 0; 1277 vgpu_vreg(vgpu, offset + 12) = 0; 1278 vgpu_vreg(vgpu, offset + 16) = 0; 1279 vgpu_vreg(vgpu, offset + 20) = 0; 1280 1281 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2, 1282 true); 1283 return 0; 1284 } 1285 1286 for (idx = 1; idx <= 5; idx++) { 1287 /* clear the data registers */ 1288 vgpu_vreg(vgpu, offset + 4 * idx) = 0; 1289 } 1290 1291 /* 1292 * Read reply format: ACK (1 byte) plus (len + 1) bytes of data. 1293 */ 1294 if ((len + 2) > AUX_BURST_SIZE) { 1295 gvt_vgpu_err("dp_aux_header: len %d is too large\n", len); 1296 return -EINVAL; 1297 } 1298 1299 /* read from virtual DPCD to vreg */ 1300 /* first 4 bytes: [ACK][addr][addr+1][addr+2] */ 1301 if (dpcd && dpcd->data_valid) { 1302 for (i = 1; i <= (len + 1); i++) { 1303 int t; 1304 1305 t = dpcd->data[addr + i - 1]; 1306 t <<= (24 - 8 * (i % 4)); 1307 ret |= t; 1308 1309 if ((i % 4 == 3) || (i == (len + 1))) { 1310 vgpu_vreg(vgpu, offset + 1311 (i / 4 + 1) * 4) = ret; 1312 ret = 0; 1313 } 1314 } 1315 } 1316 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2, 1317 dpcd && dpcd->data_valid); 1318 return 0; 1319 } 1320 1321 /* i2c transaction starts */ 1322 intel_gvt_i2c_handle_aux_ch_write(vgpu, port_index, offset, p_data); 1323 1324 if (data & DP_AUX_CH_CTL_INTERRUPT) 1325 trigger_aux_channel_interrupt(vgpu, offset); 1326 return 0; 1327 } 1328 1329 static int mbctl_write(struct intel_vgpu *vgpu, unsigned int offset, 1330 void *p_data, unsigned int bytes) 1331 { 1332 *(u32 *)p_data &= (~GEN6_MBCTL_ENABLE_BOOT_FETCH); 1333 write_vreg(vgpu, offset, p_data, bytes); 1334 return 0; 1335 } 1336 1337 static int vga_control_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1338 void *p_data, unsigned int bytes) 1339 { 1340 bool vga_disable; 1341 1342 write_vreg(vgpu, offset, p_data, bytes); 1343 vga_disable = vgpu_vreg(vgpu, offset) & VGA_DISP_DISABLE; 1344 1345 gvt_dbg_core("vgpu%d: %s VGA mode\n", vgpu->id, 1346 vga_disable ? "Disable" : "Enable"); 1347 return 0; 1348 } 1349 1350 static u32 read_virtual_sbi_register(struct intel_vgpu *vgpu, 1351 unsigned int sbi_offset) 1352 { 1353 struct intel_vgpu_display *display = &vgpu->display; 1354 int num = display->sbi.number; 1355 int i; 1356 1357 for (i = 0; i < num; ++i) 1358 if (display->sbi.registers[i].offset == sbi_offset) 1359 break; 1360 1361 if (i == num) 1362 return 0; 1363 1364 return display->sbi.registers[i].value; 1365 } 1366 1367 static void write_virtual_sbi_register(struct intel_vgpu *vgpu, 1368 unsigned int offset, u32 value) 1369 { 1370 struct intel_vgpu_display *display = &vgpu->display; 1371 int num = display->sbi.number; 1372 int i; 1373 1374 for (i = 0; i < num; ++i) { 1375 if (display->sbi.registers[i].offset == offset) 1376 break; 1377 } 1378 1379 if (i == num) { 1380 if (num == SBI_REG_MAX) { 1381 gvt_vgpu_err("SBI caching meets maximum limits\n"); 1382 return; 1383 } 1384 display->sbi.number++; 1385 } 1386 1387 display->sbi.registers[i].offset = offset; 1388 display->sbi.registers[i].value = value; 1389 } 1390 1391 static int sbi_data_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 1392 void *p_data, unsigned int bytes) 1393 { 1394 if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> 1395 SBI_OPCODE_SHIFT) == SBI_CMD_CRRD) { 1396 unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) & 1397 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; 1398 vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu, 1399 sbi_offset); 1400 } 1401 read_vreg(vgpu, offset, p_data, bytes); 1402 return 0; 1403 } 1404 1405 static int sbi_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1406 void *p_data, unsigned int bytes) 1407 { 1408 u32 data; 1409 1410 write_vreg(vgpu, offset, p_data, bytes); 1411 data = vgpu_vreg(vgpu, offset); 1412 1413 data &= ~(SBI_STAT_MASK << SBI_STAT_SHIFT); 1414 data |= SBI_READY; 1415 1416 data &= ~(SBI_RESPONSE_MASK << SBI_RESPONSE_SHIFT); 1417 data |= SBI_RESPONSE_SUCCESS; 1418 1419 vgpu_vreg(vgpu, offset) = data; 1420 1421 if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> 1422 SBI_OPCODE_SHIFT) == SBI_CMD_CRWR) { 1423 unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) & 1424 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; 1425 1426 write_virtual_sbi_register(vgpu, sbi_offset, 1427 vgpu_vreg_t(vgpu, SBI_DATA)); 1428 } 1429 return 0; 1430 } 1431 1432 #define _vgtif_reg(x) \ 1433 (VGT_PVINFO_PAGE + offsetof(struct vgt_if, x)) 1434 1435 static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 1436 void *p_data, unsigned int bytes) 1437 { 1438 bool invalid_read = false; 1439 1440 read_vreg(vgpu, offset, p_data, bytes); 1441 1442 switch (offset) { 1443 case _vgtif_reg(magic) ... _vgtif_reg(vgt_id): 1444 if (offset + bytes > _vgtif_reg(vgt_id) + 4) 1445 invalid_read = true; 1446 break; 1447 case _vgtif_reg(avail_rs.mappable_gmadr.base) ... 1448 _vgtif_reg(avail_rs.fence_num): 1449 if (offset + bytes > 1450 _vgtif_reg(avail_rs.fence_num) + 4) 1451 invalid_read = true; 1452 break; 1453 case 0x78010: /* vgt_caps */ 1454 case 0x7881c: 1455 break; 1456 default: 1457 invalid_read = true; 1458 break; 1459 } 1460 if (invalid_read) 1461 gvt_vgpu_err("invalid pvinfo read: [%x:%x] = %x\n", 1462 offset, bytes, *(u32 *)p_data); 1463 vgpu->pv_notified = true; 1464 return 0; 1465 } 1466 1467 static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification) 1468 { 1469 enum intel_gvt_gtt_type root_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY; 1470 struct intel_vgpu_mm *mm; 1471 u64 *pdps; 1472 1473 pdps = (u64 *)&vgpu_vreg64_t(vgpu, vgtif_reg(pdp[0])); 1474 1475 switch (notification) { 1476 case VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE: 1477 root_entry_type = GTT_TYPE_PPGTT_ROOT_L3_ENTRY; 1478 fallthrough; 1479 case VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE: 1480 mm = intel_vgpu_get_ppgtt_mm(vgpu, root_entry_type, pdps); 1481 return PTR_ERR_OR_ZERO(mm); 1482 case VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY: 1483 case VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY: 1484 return intel_vgpu_put_ppgtt_mm(vgpu, pdps); 1485 case VGT_G2V_EXECLIST_CONTEXT_CREATE: 1486 case VGT_G2V_EXECLIST_CONTEXT_DESTROY: 1487 case 1: /* Remove this in guest driver. */ 1488 break; 1489 default: 1490 gvt_vgpu_err("Invalid PV notification %d\n", notification); 1491 } 1492 return 0; 1493 } 1494 1495 static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready) 1496 { 1497 struct kobject *kobj = &vgpu->gvt->gt->i915->drm.primary->kdev->kobj; 1498 char *env[3] = {NULL, NULL, NULL}; 1499 char vmid_str[20]; 1500 char display_ready_str[20]; 1501 1502 snprintf(display_ready_str, 20, "GVT_DISPLAY_READY=%d", ready); 1503 env[0] = display_ready_str; 1504 1505 snprintf(vmid_str, 20, "VMID=%d", vgpu->id); 1506 env[1] = vmid_str; 1507 1508 return kobject_uevent_env(kobj, KOBJ_ADD, env); 1509 } 1510 1511 static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1512 void *p_data, unsigned int bytes) 1513 { 1514 u32 data = *(u32 *)p_data; 1515 bool invalid_write = false; 1516 1517 switch (offset) { 1518 case _vgtif_reg(display_ready): 1519 send_display_ready_uevent(vgpu, data ? 1 : 0); 1520 break; 1521 case _vgtif_reg(g2v_notify): 1522 handle_g2v_notification(vgpu, data); 1523 break; 1524 /* add xhot and yhot to handled list to avoid error log */ 1525 case _vgtif_reg(cursor_x_hot): 1526 case _vgtif_reg(cursor_y_hot): 1527 case _vgtif_reg(pdp[0].lo): 1528 case _vgtif_reg(pdp[0].hi): 1529 case _vgtif_reg(pdp[1].lo): 1530 case _vgtif_reg(pdp[1].hi): 1531 case _vgtif_reg(pdp[2].lo): 1532 case _vgtif_reg(pdp[2].hi): 1533 case _vgtif_reg(pdp[3].lo): 1534 case _vgtif_reg(pdp[3].hi): 1535 case _vgtif_reg(execlist_context_descriptor_lo): 1536 case _vgtif_reg(execlist_context_descriptor_hi): 1537 break; 1538 case _vgtif_reg(rsv5[0])..._vgtif_reg(rsv5[3]): 1539 invalid_write = true; 1540 enter_failsafe_mode(vgpu, GVT_FAILSAFE_INSUFFICIENT_RESOURCE); 1541 break; 1542 default: 1543 invalid_write = true; 1544 gvt_vgpu_err("invalid pvinfo write offset %x bytes %x data %x\n", 1545 offset, bytes, data); 1546 break; 1547 } 1548 1549 if (!invalid_write) 1550 write_vreg(vgpu, offset, p_data, bytes); 1551 1552 return 0; 1553 } 1554 1555 static int pf_write(struct intel_vgpu *vgpu, 1556 unsigned int offset, void *p_data, unsigned int bytes) 1557 { 1558 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 1559 u32 val = *(u32 *)p_data; 1560 1561 if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL || 1562 offset == _PS_1B_CTRL || offset == _PS_2B_CTRL || 1563 offset == _PS_1C_CTRL) && (val & PS_PLANE_SEL_MASK) != 0) { 1564 drm_WARN_ONCE(&i915->drm, true, 1565 "VM(%d): guest is trying to scaling a plane\n", 1566 vgpu->id); 1567 return 0; 1568 } 1569 1570 return intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes); 1571 } 1572 1573 static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu, 1574 unsigned int offset, void *p_data, unsigned int bytes) 1575 { 1576 write_vreg(vgpu, offset, p_data, bytes); 1577 1578 if (vgpu_vreg(vgpu, offset) & 1579 HSW_PWR_WELL_CTL_REQ(HSW_PW_CTL_IDX_GLOBAL)) 1580 vgpu_vreg(vgpu, offset) |= 1581 HSW_PWR_WELL_CTL_STATE(HSW_PW_CTL_IDX_GLOBAL); 1582 else 1583 vgpu_vreg(vgpu, offset) &= 1584 ~HSW_PWR_WELL_CTL_STATE(HSW_PW_CTL_IDX_GLOBAL); 1585 return 0; 1586 } 1587 1588 static int gen9_dbuf_ctl_mmio_write(struct intel_vgpu *vgpu, 1589 unsigned int offset, void *p_data, unsigned int bytes) 1590 { 1591 write_vreg(vgpu, offset, p_data, bytes); 1592 1593 if (vgpu_vreg(vgpu, offset) & DBUF_POWER_REQUEST) 1594 vgpu_vreg(vgpu, offset) |= DBUF_POWER_STATE; 1595 else 1596 vgpu_vreg(vgpu, offset) &= ~DBUF_POWER_STATE; 1597 1598 return 0; 1599 } 1600 1601 static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu, 1602 unsigned int offset, void *p_data, unsigned int bytes) 1603 { 1604 write_vreg(vgpu, offset, p_data, bytes); 1605 1606 if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM) 1607 vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM; 1608 return 0; 1609 } 1610 1611 static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset, 1612 void *p_data, unsigned int bytes) 1613 { 1614 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 1615 u32 mode; 1616 1617 write_vreg(vgpu, offset, p_data, bytes); 1618 mode = vgpu_vreg(vgpu, offset); 1619 1620 if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) { 1621 drm_WARN_ONCE(&i915->drm, 1, 1622 "VM(%d): iGVT-g doesn't support GuC\n", 1623 vgpu->id); 1624 return 0; 1625 } 1626 1627 return 0; 1628 } 1629 1630 static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset, 1631 void *p_data, unsigned int bytes) 1632 { 1633 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 1634 u32 trtte = *(u32 *)p_data; 1635 1636 if ((trtte & 1) && (trtte & (1 << 1)) == 0) { 1637 drm_WARN(&i915->drm, 1, 1638 "VM(%d): Use physical address for TRTT!\n", 1639 vgpu->id); 1640 return -EINVAL; 1641 } 1642 write_vreg(vgpu, offset, p_data, bytes); 1643 1644 return 0; 1645 } 1646 1647 static int gen9_trtt_chicken_write(struct intel_vgpu *vgpu, unsigned int offset, 1648 void *p_data, unsigned int bytes) 1649 { 1650 write_vreg(vgpu, offset, p_data, bytes); 1651 return 0; 1652 } 1653 1654 static int dpll_status_read(struct intel_vgpu *vgpu, unsigned int offset, 1655 void *p_data, unsigned int bytes) 1656 { 1657 u32 v = 0; 1658 1659 if (vgpu_vreg(vgpu, 0x46010) & (1 << 31)) 1660 v |= (1 << 0); 1661 1662 if (vgpu_vreg(vgpu, 0x46014) & (1 << 31)) 1663 v |= (1 << 8); 1664 1665 if (vgpu_vreg(vgpu, 0x46040) & (1 << 31)) 1666 v |= (1 << 16); 1667 1668 if (vgpu_vreg(vgpu, 0x46060) & (1 << 31)) 1669 v |= (1 << 24); 1670 1671 vgpu_vreg(vgpu, offset) = v; 1672 1673 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1674 } 1675 1676 static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset, 1677 void *p_data, unsigned int bytes) 1678 { 1679 u32 value = *(u32 *)p_data; 1680 u32 cmd = value & 0xff; 1681 u32 *data0 = &vgpu_vreg_t(vgpu, GEN6_PCODE_DATA); 1682 1683 switch (cmd) { 1684 case GEN9_PCODE_READ_MEM_LATENCY: 1685 if (IS_SKYLAKE(vgpu->gvt->gt->i915) || 1686 IS_KABYLAKE(vgpu->gvt->gt->i915) || 1687 IS_COFFEELAKE(vgpu->gvt->gt->i915) || 1688 IS_COMETLAKE(vgpu->gvt->gt->i915)) { 1689 /** 1690 * "Read memory latency" command on gen9. 1691 * Below memory latency values are read 1692 * from skylake platform. 1693 */ 1694 if (!*data0) 1695 *data0 = 0x1e1a1100; 1696 else 1697 *data0 = 0x61514b3d; 1698 } else if (IS_BROXTON(vgpu->gvt->gt->i915)) { 1699 /** 1700 * "Read memory latency" command on gen9. 1701 * Below memory latency values are read 1702 * from Broxton MRB. 1703 */ 1704 if (!*data0) 1705 *data0 = 0x16080707; 1706 else 1707 *data0 = 0x16161616; 1708 } 1709 break; 1710 case SKL_PCODE_CDCLK_CONTROL: 1711 if (IS_SKYLAKE(vgpu->gvt->gt->i915) || 1712 IS_KABYLAKE(vgpu->gvt->gt->i915) || 1713 IS_COFFEELAKE(vgpu->gvt->gt->i915) || 1714 IS_COMETLAKE(vgpu->gvt->gt->i915)) 1715 *data0 = SKL_CDCLK_READY_FOR_CHANGE; 1716 break; 1717 case GEN6_PCODE_READ_RC6VIDS: 1718 *data0 |= 0x1; 1719 break; 1720 } 1721 1722 gvt_dbg_core("VM(%d) write %x to mailbox, return data0 %x\n", 1723 vgpu->id, value, *data0); 1724 /** 1725 * PCODE_READY clear means ready for pcode read/write, 1726 * PCODE_ERROR_MASK clear means no error happened. In GVT-g we 1727 * always emulate as pcode read/write success and ready for access 1728 * anytime, since we don't touch real physical registers here. 1729 */ 1730 value &= ~(GEN6_PCODE_READY | GEN6_PCODE_ERROR_MASK); 1731 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes); 1732 } 1733 1734 static int hws_pga_write(struct intel_vgpu *vgpu, unsigned int offset, 1735 void *p_data, unsigned int bytes) 1736 { 1737 u32 value = *(u32 *)p_data; 1738 const struct intel_engine_cs *engine = 1739 intel_gvt_render_mmio_to_engine(vgpu->gvt, offset); 1740 1741 if (value != 0 && 1742 !intel_gvt_ggtt_validate_range(vgpu, value, I915_GTT_PAGE_SIZE)) { 1743 gvt_vgpu_err("write invalid HWSP address, reg:0x%x, value:0x%x\n", 1744 offset, value); 1745 return -EINVAL; 1746 } 1747 1748 /* 1749 * Need to emulate all the HWSP register write to ensure host can 1750 * update the VM CSB status correctly. Here listed registers can 1751 * support BDW, SKL or other platforms with same HWSP registers. 1752 */ 1753 if (unlikely(!engine)) { 1754 gvt_vgpu_err("access unknown hardware status page register:0x%x\n", 1755 offset); 1756 return -EINVAL; 1757 } 1758 vgpu->hws_pga[engine->id] = value; 1759 gvt_dbg_mmio("VM(%d) write: 0x%x to HWSP: 0x%x\n", 1760 vgpu->id, value, offset); 1761 1762 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes); 1763 } 1764 1765 static int skl_power_well_ctl_write(struct intel_vgpu *vgpu, 1766 unsigned int offset, void *p_data, unsigned int bytes) 1767 { 1768 u32 v = *(u32 *)p_data; 1769 1770 if (IS_BROXTON(vgpu->gvt->gt->i915)) 1771 v &= (1 << 31) | (1 << 29); 1772 else 1773 v &= (1 << 31) | (1 << 29) | (1 << 9) | 1774 (1 << 7) | (1 << 5) | (1 << 3) | (1 << 1); 1775 v |= (v >> 1); 1776 1777 return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes); 1778 } 1779 1780 static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset, 1781 void *p_data, unsigned int bytes) 1782 { 1783 u32 v = *(u32 *)p_data; 1784 1785 /* other bits are MBZ. */ 1786 v &= (1 << 31) | (1 << 30); 1787 v & (1 << 31) ? (v |= (1 << 30)) : (v &= ~(1 << 30)); 1788 1789 vgpu_vreg(vgpu, offset) = v; 1790 1791 return 0; 1792 } 1793 1794 static int bxt_de_pll_enable_write(struct intel_vgpu *vgpu, 1795 unsigned int offset, void *p_data, unsigned int bytes) 1796 { 1797 u32 v = *(u32 *)p_data; 1798 1799 if (v & BXT_DE_PLL_PLL_ENABLE) 1800 v |= BXT_DE_PLL_LOCK; 1801 1802 vgpu_vreg(vgpu, offset) = v; 1803 1804 return 0; 1805 } 1806 1807 static int bxt_port_pll_enable_write(struct intel_vgpu *vgpu, 1808 unsigned int offset, void *p_data, unsigned int bytes) 1809 { 1810 u32 v = *(u32 *)p_data; 1811 1812 if (v & PORT_PLL_ENABLE) 1813 v |= PORT_PLL_LOCK; 1814 1815 vgpu_vreg(vgpu, offset) = v; 1816 1817 return 0; 1818 } 1819 1820 static int bxt_phy_ctl_family_write(struct intel_vgpu *vgpu, 1821 unsigned int offset, void *p_data, unsigned int bytes) 1822 { 1823 u32 v = *(u32 *)p_data; 1824 u32 data = v & COMMON_RESET_DIS ? BXT_PHY_LANE_ENABLED : 0; 1825 1826 switch (offset) { 1827 case _PHY_CTL_FAMILY_EDP: 1828 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_A) = data; 1829 break; 1830 case _PHY_CTL_FAMILY_DDI: 1831 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_B) = data; 1832 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_C) = data; 1833 break; 1834 } 1835 1836 vgpu_vreg(vgpu, offset) = v; 1837 1838 return 0; 1839 } 1840 1841 static int bxt_port_tx_dw3_read(struct intel_vgpu *vgpu, 1842 unsigned int offset, void *p_data, unsigned int bytes) 1843 { 1844 u32 v = vgpu_vreg(vgpu, offset); 1845 1846 v &= ~UNIQUE_TRANGE_EN_METHOD; 1847 1848 vgpu_vreg(vgpu, offset) = v; 1849 1850 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1851 } 1852 1853 static int bxt_pcs_dw12_grp_write(struct intel_vgpu *vgpu, 1854 unsigned int offset, void *p_data, unsigned int bytes) 1855 { 1856 u32 v = *(u32 *)p_data; 1857 1858 if (offset == _PORT_PCS_DW12_GRP_A || offset == _PORT_PCS_DW12_GRP_B) { 1859 vgpu_vreg(vgpu, offset - 0x600) = v; 1860 vgpu_vreg(vgpu, offset - 0x800) = v; 1861 } else { 1862 vgpu_vreg(vgpu, offset - 0x400) = v; 1863 vgpu_vreg(vgpu, offset - 0x600) = v; 1864 } 1865 1866 vgpu_vreg(vgpu, offset) = v; 1867 1868 return 0; 1869 } 1870 1871 static int bxt_gt_disp_pwron_write(struct intel_vgpu *vgpu, 1872 unsigned int offset, void *p_data, unsigned int bytes) 1873 { 1874 u32 v = *(u32 *)p_data; 1875 1876 if (v & BIT(0)) { 1877 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &= 1878 ~PHY_RESERVED; 1879 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |= 1880 PHY_POWER_GOOD; 1881 } 1882 1883 if (v & BIT(1)) { 1884 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &= 1885 ~PHY_RESERVED; 1886 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |= 1887 PHY_POWER_GOOD; 1888 } 1889 1890 1891 vgpu_vreg(vgpu, offset) = v; 1892 1893 return 0; 1894 } 1895 1896 static int edp_psr_imr_iir_write(struct intel_vgpu *vgpu, 1897 unsigned int offset, void *p_data, unsigned int bytes) 1898 { 1899 vgpu_vreg(vgpu, offset) = 0; 1900 return 0; 1901 } 1902 1903 /* 1904 * FixMe: 1905 * If guest fills non-priv batch buffer on ApolloLake/Broxton as Mesa i965 did: 1906 * 717e7539124d (i965: Use a WC map and memcpy for the batch instead of pwrite.) 1907 * Due to the missing flush of bb filled by VM vCPU, host GPU hangs on executing 1908 * these MI_BATCH_BUFFER. 1909 * Temporarily workaround this by setting SNOOP bit for PAT3 used by PPGTT 1910 * PML4 PTE: PAT(0) PCD(1) PWT(1). 1911 * The performance is still expected to be low, will need further improvement. 1912 */ 1913 static int bxt_ppat_low_write(struct intel_vgpu *vgpu, unsigned int offset, 1914 void *p_data, unsigned int bytes) 1915 { 1916 u64 pat = 1917 GEN8_PPAT(0, CHV_PPAT_SNOOP) | 1918 GEN8_PPAT(1, 0) | 1919 GEN8_PPAT(2, 0) | 1920 GEN8_PPAT(3, CHV_PPAT_SNOOP) | 1921 GEN8_PPAT(4, CHV_PPAT_SNOOP) | 1922 GEN8_PPAT(5, CHV_PPAT_SNOOP) | 1923 GEN8_PPAT(6, CHV_PPAT_SNOOP) | 1924 GEN8_PPAT(7, CHV_PPAT_SNOOP); 1925 1926 vgpu_vreg(vgpu, offset) = lower_32_bits(pat); 1927 1928 return 0; 1929 } 1930 1931 static int guc_status_read(struct intel_vgpu *vgpu, 1932 unsigned int offset, void *p_data, 1933 unsigned int bytes) 1934 { 1935 /* keep MIA_IN_RESET before clearing */ 1936 read_vreg(vgpu, offset, p_data, bytes); 1937 vgpu_vreg(vgpu, offset) &= ~GS_MIA_IN_RESET; 1938 return 0; 1939 } 1940 1941 static int mmio_read_from_hw(struct intel_vgpu *vgpu, 1942 unsigned int offset, void *p_data, unsigned int bytes) 1943 { 1944 struct intel_gvt *gvt = vgpu->gvt; 1945 const struct intel_engine_cs *engine = 1946 intel_gvt_render_mmio_to_engine(gvt, offset); 1947 1948 /** 1949 * Read HW reg in following case 1950 * a. the offset isn't a ring mmio 1951 * b. the offset's ring is running on hw. 1952 * c. the offset is ring time stamp mmio 1953 */ 1954 1955 if (!engine || 1956 vgpu == gvt->scheduler.engine_owner[engine->id] || 1957 offset == i915_mmio_reg_offset(RING_TIMESTAMP(engine->mmio_base)) || 1958 offset == i915_mmio_reg_offset(RING_TIMESTAMP_UDW(engine->mmio_base))) { 1959 mmio_hw_access_pre(gvt->gt); 1960 vgpu_vreg(vgpu, offset) = 1961 intel_uncore_read(gvt->gt->uncore, _MMIO(offset)); 1962 mmio_hw_access_post(gvt->gt); 1963 } 1964 1965 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1966 } 1967 1968 static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1969 void *p_data, unsigned int bytes) 1970 { 1971 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 1972 const struct intel_engine_cs *engine = intel_gvt_render_mmio_to_engine(vgpu->gvt, offset); 1973 struct intel_vgpu_execlist *execlist; 1974 u32 data = *(u32 *)p_data; 1975 int ret = 0; 1976 1977 if (drm_WARN_ON(&i915->drm, !engine)) 1978 return -EINVAL; 1979 1980 /* 1981 * Due to d3_entered is used to indicate skipping PPGTT invalidation on 1982 * vGPU reset, it's set on D0->D3 on PCI config write, and cleared after 1983 * vGPU reset if in resuming. 1984 * In S0ix exit, the device power state also transite from D3 to D0 as 1985 * S3 resume, but no vGPU reset (triggered by QEMU devic model). After 1986 * S0ix exit, all engines continue to work. However the d3_entered 1987 * remains set which will break next vGPU reset logic (miss the expected 1988 * PPGTT invalidation). 1989 * Engines can only work in D0. Thus the 1st elsp write gives GVT a 1990 * chance to clear d3_entered. 1991 */ 1992 if (vgpu->d3_entered) 1993 vgpu->d3_entered = false; 1994 1995 execlist = &vgpu->submission.execlist[engine->id]; 1996 1997 execlist->elsp_dwords.data[3 - execlist->elsp_dwords.index] = data; 1998 if (execlist->elsp_dwords.index == 3) { 1999 ret = intel_vgpu_submit_execlist(vgpu, engine); 2000 if(ret) 2001 gvt_vgpu_err("fail submit workload on ring %s\n", 2002 engine->name); 2003 } 2004 2005 ++execlist->elsp_dwords.index; 2006 execlist->elsp_dwords.index &= 0x3; 2007 return ret; 2008 } 2009 2010 static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 2011 void *p_data, unsigned int bytes) 2012 { 2013 u32 data = *(u32 *)p_data; 2014 const struct intel_engine_cs *engine = 2015 intel_gvt_render_mmio_to_engine(vgpu->gvt, offset); 2016 bool enable_execlist; 2017 int ret; 2018 2019 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(1); 2020 if (IS_COFFEELAKE(vgpu->gvt->gt->i915) || 2021 IS_COMETLAKE(vgpu->gvt->gt->i915)) 2022 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(2); 2023 write_vreg(vgpu, offset, p_data, bytes); 2024 2025 if (IS_MASKED_BITS_ENABLED(data, 1)) { 2026 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); 2027 return 0; 2028 } 2029 2030 if ((IS_COFFEELAKE(vgpu->gvt->gt->i915) || 2031 IS_COMETLAKE(vgpu->gvt->gt->i915)) && 2032 IS_MASKED_BITS_ENABLED(data, 2)) { 2033 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); 2034 return 0; 2035 } 2036 2037 /* when PPGTT mode enabled, we will check if guest has called 2038 * pvinfo, if not, we will treat this guest as non-gvtg-aware 2039 * guest, and stop emulating its cfg space, mmio, gtt, etc. 2040 */ 2041 if ((IS_MASKED_BITS_ENABLED(data, GFX_PPGTT_ENABLE) || 2042 IS_MASKED_BITS_ENABLED(data, GFX_RUN_LIST_ENABLE)) && 2043 !vgpu->pv_notified) { 2044 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); 2045 return 0; 2046 } 2047 if (IS_MASKED_BITS_ENABLED(data, GFX_RUN_LIST_ENABLE) || 2048 IS_MASKED_BITS_DISABLED(data, GFX_RUN_LIST_ENABLE)) { 2049 enable_execlist = !!(data & GFX_RUN_LIST_ENABLE); 2050 2051 gvt_dbg_core("EXECLIST %s on ring %s\n", 2052 (enable_execlist ? "enabling" : "disabling"), 2053 engine->name); 2054 2055 if (!enable_execlist) 2056 return 0; 2057 2058 ret = intel_vgpu_select_submission_ops(vgpu, 2059 engine->mask, 2060 INTEL_VGPU_EXECLIST_SUBMISSION); 2061 if (ret) 2062 return ret; 2063 2064 intel_vgpu_start_schedule(vgpu); 2065 } 2066 return 0; 2067 } 2068 2069 static int gvt_reg_tlb_control_handler(struct intel_vgpu *vgpu, 2070 unsigned int offset, void *p_data, unsigned int bytes) 2071 { 2072 unsigned int id = 0; 2073 2074 write_vreg(vgpu, offset, p_data, bytes); 2075 vgpu_vreg(vgpu, offset) = 0; 2076 2077 switch (offset) { 2078 case 0x4260: 2079 id = RCS0; 2080 break; 2081 case 0x4264: 2082 id = VCS0; 2083 break; 2084 case 0x4268: 2085 id = VCS1; 2086 break; 2087 case 0x426c: 2088 id = BCS0; 2089 break; 2090 case 0x4270: 2091 id = VECS0; 2092 break; 2093 default: 2094 return -EINVAL; 2095 } 2096 set_bit(id, (void *)vgpu->submission.tlb_handle_pending); 2097 2098 return 0; 2099 } 2100 2101 static int ring_reset_ctl_write(struct intel_vgpu *vgpu, 2102 unsigned int offset, void *p_data, unsigned int bytes) 2103 { 2104 u32 data; 2105 2106 write_vreg(vgpu, offset, p_data, bytes); 2107 data = vgpu_vreg(vgpu, offset); 2108 2109 if (IS_MASKED_BITS_ENABLED(data, RESET_CTL_REQUEST_RESET)) 2110 data |= RESET_CTL_READY_TO_RESET; 2111 else if (data & _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET)) 2112 data &= ~RESET_CTL_READY_TO_RESET; 2113 2114 vgpu_vreg(vgpu, offset) = data; 2115 return 0; 2116 } 2117 2118 static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu, 2119 unsigned int offset, void *p_data, 2120 unsigned int bytes) 2121 { 2122 u32 data = *(u32 *)p_data; 2123 2124 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(0x18); 2125 write_vreg(vgpu, offset, p_data, bytes); 2126 2127 if (IS_MASKED_BITS_ENABLED(data, 0x10) || 2128 IS_MASKED_BITS_ENABLED(data, 0x8)) 2129 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); 2130 2131 return 0; 2132 } 2133 2134 #define MMIO_F(reg, s, f, am, rm, d, r, w) do { \ 2135 ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \ 2136 f, s, am, rm, d, r, w); \ 2137 if (ret) \ 2138 return ret; \ 2139 } while (0) 2140 2141 #define MMIO_D(reg, d) \ 2142 MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL) 2143 2144 #define MMIO_DH(reg, d, r, w) \ 2145 MMIO_F(reg, 4, 0, 0, 0, d, r, w) 2146 2147 #define MMIO_DFH(reg, d, f, r, w) \ 2148 MMIO_F(reg, 4, f, 0, 0, d, r, w) 2149 2150 #define MMIO_GM(reg, d, r, w) \ 2151 MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w) 2152 2153 #define MMIO_GM_RDR(reg, d, r, w) \ 2154 MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w) 2155 2156 #define MMIO_RO(reg, d, f, rm, r, w) \ 2157 MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w) 2158 2159 #define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \ 2160 MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \ 2161 MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \ 2162 MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \ 2163 MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \ 2164 if (HAS_ENGINE(gvt->gt, VCS1)) \ 2165 MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \ 2166 } while (0) 2167 2168 #define MMIO_RING_D(prefix, d) \ 2169 MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL) 2170 2171 #define MMIO_RING_DFH(prefix, d, f, r, w) \ 2172 MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w) 2173 2174 #define MMIO_RING_GM(prefix, d, r, w) \ 2175 MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w) 2176 2177 #define MMIO_RING_GM_RDR(prefix, d, r, w) \ 2178 MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w) 2179 2180 #define MMIO_RING_RO(prefix, d, f, rm, r, w) \ 2181 MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w) 2182 2183 static int init_generic_mmio_info(struct intel_gvt *gvt) 2184 { 2185 struct drm_i915_private *dev_priv = gvt->gt->i915; 2186 int ret; 2187 2188 MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL, 2189 intel_vgpu_reg_imr_handler); 2190 2191 MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler); 2192 MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler); 2193 MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler); 2194 MMIO_D(SDEISR, D_ALL); 2195 2196 MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL); 2197 2198 2199 MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL, 2200 gamw_echo_dev_rw_ia_write); 2201 2202 MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL); 2203 MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL); 2204 MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL); 2205 2206 #define RING_REG(base) _MMIO((base) + 0x28) 2207 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL); 2208 #undef RING_REG 2209 2210 #define RING_REG(base) _MMIO((base) + 0x134) 2211 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL); 2212 #undef RING_REG 2213 2214 #define RING_REG(base) _MMIO((base) + 0x6c) 2215 MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL); 2216 #undef RING_REG 2217 MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL); 2218 2219 MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL); 2220 MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL); 2221 MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL); 2222 MMIO_D(GEN7_CXT_SIZE, D_ALL); 2223 2224 MMIO_RING_DFH(RING_TAIL, D_ALL, 0, NULL, NULL); 2225 MMIO_RING_DFH(RING_HEAD, D_ALL, 0, NULL, NULL); 2226 MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL); 2227 MMIO_RING_DFH(RING_ACTHD, D_ALL, 0, mmio_read_from_hw, NULL); 2228 MMIO_RING_GM(RING_START, D_ALL, NULL, NULL); 2229 2230 /* RING MODE */ 2231 #define RING_REG(base) _MMIO((base) + 0x29c) 2232 MMIO_RING_DFH(RING_REG, D_ALL, 2233 F_MODE_MASK | F_CMD_ACCESS | F_CMD_WRITE_PATCH, NULL, 2234 ring_mode_mmio_write); 2235 #undef RING_REG 2236 2237 MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 2238 NULL, NULL); 2239 MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 2240 NULL, NULL); 2241 MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS, 2242 mmio_read_from_hw, NULL); 2243 MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS, 2244 mmio_read_from_hw, NULL); 2245 2246 MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2247 MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 2248 NULL, NULL); 2249 MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2250 MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2251 MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2252 2253 MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2254 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2255 MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2256 MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL, 2257 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2258 MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2259 MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL); 2260 MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 2261 NULL, NULL); 2262 MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 2263 NULL, NULL); 2264 MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL); 2265 MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL); 2266 MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL); 2267 MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL); 2268 MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL); 2269 MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL); 2270 MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL); 2271 MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2272 MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2273 MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2274 2275 /* display */ 2276 MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL); 2277 MMIO_D(_MMIO(0x602a0), D_ALL); 2278 2279 MMIO_D(_MMIO(0x65050), D_ALL); 2280 MMIO_D(_MMIO(0x650b4), D_ALL); 2281 2282 MMIO_D(_MMIO(0xc4040), D_ALL); 2283 MMIO_D(DERRMR, D_ALL); 2284 2285 MMIO_D(PIPEDSL(PIPE_A), D_ALL); 2286 MMIO_D(PIPEDSL(PIPE_B), D_ALL); 2287 MMIO_D(PIPEDSL(PIPE_C), D_ALL); 2288 MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL); 2289 2290 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write); 2291 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write); 2292 MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write); 2293 MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write); 2294 2295 MMIO_D(PIPESTAT(PIPE_A), D_ALL); 2296 MMIO_D(PIPESTAT(PIPE_B), D_ALL); 2297 MMIO_D(PIPESTAT(PIPE_C), D_ALL); 2298 MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL); 2299 2300 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL); 2301 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL); 2302 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL); 2303 MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL); 2304 2305 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL); 2306 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL); 2307 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL); 2308 MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL); 2309 2310 MMIO_D(CURCNTR(PIPE_A), D_ALL); 2311 MMIO_D(CURCNTR(PIPE_B), D_ALL); 2312 MMIO_D(CURCNTR(PIPE_C), D_ALL); 2313 2314 MMIO_D(CURPOS(PIPE_A), D_ALL); 2315 MMIO_D(CURPOS(PIPE_B), D_ALL); 2316 MMIO_D(CURPOS(PIPE_C), D_ALL); 2317 2318 MMIO_D(CURBASE(PIPE_A), D_ALL); 2319 MMIO_D(CURBASE(PIPE_B), D_ALL); 2320 MMIO_D(CURBASE(PIPE_C), D_ALL); 2321 2322 MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL); 2323 MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL); 2324 MMIO_D(CUR_FBC_CTL(PIPE_C), D_ALL); 2325 2326 MMIO_D(_MMIO(0x700ac), D_ALL); 2327 MMIO_D(_MMIO(0x710ac), D_ALL); 2328 MMIO_D(_MMIO(0x720ac), D_ALL); 2329 2330 MMIO_D(_MMIO(0x70090), D_ALL); 2331 MMIO_D(_MMIO(0x70094), D_ALL); 2332 MMIO_D(_MMIO(0x70098), D_ALL); 2333 MMIO_D(_MMIO(0x7009c), D_ALL); 2334 2335 MMIO_D(DSPCNTR(PIPE_A), D_ALL); 2336 MMIO_D(DSPADDR(PIPE_A), D_ALL); 2337 MMIO_D(DSPSTRIDE(PIPE_A), D_ALL); 2338 MMIO_D(DSPPOS(PIPE_A), D_ALL); 2339 MMIO_D(DSPSIZE(PIPE_A), D_ALL); 2340 MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write); 2341 MMIO_D(DSPOFFSET(PIPE_A), D_ALL); 2342 MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL); 2343 MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL, 2344 reg50080_mmio_write); 2345 2346 MMIO_D(DSPCNTR(PIPE_B), D_ALL); 2347 MMIO_D(DSPADDR(PIPE_B), D_ALL); 2348 MMIO_D(DSPSTRIDE(PIPE_B), D_ALL); 2349 MMIO_D(DSPPOS(PIPE_B), D_ALL); 2350 MMIO_D(DSPSIZE(PIPE_B), D_ALL); 2351 MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write); 2352 MMIO_D(DSPOFFSET(PIPE_B), D_ALL); 2353 MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL); 2354 MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL, 2355 reg50080_mmio_write); 2356 2357 MMIO_D(DSPCNTR(PIPE_C), D_ALL); 2358 MMIO_D(DSPADDR(PIPE_C), D_ALL); 2359 MMIO_D(DSPSTRIDE(PIPE_C), D_ALL); 2360 MMIO_D(DSPPOS(PIPE_C), D_ALL); 2361 MMIO_D(DSPSIZE(PIPE_C), D_ALL); 2362 MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write); 2363 MMIO_D(DSPOFFSET(PIPE_C), D_ALL); 2364 MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL); 2365 MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL, 2366 reg50080_mmio_write); 2367 2368 MMIO_D(SPRCTL(PIPE_A), D_ALL); 2369 MMIO_D(SPRLINOFF(PIPE_A), D_ALL); 2370 MMIO_D(SPRSTRIDE(PIPE_A), D_ALL); 2371 MMIO_D(SPRPOS(PIPE_A), D_ALL); 2372 MMIO_D(SPRSIZE(PIPE_A), D_ALL); 2373 MMIO_D(SPRKEYVAL(PIPE_A), D_ALL); 2374 MMIO_D(SPRKEYMSK(PIPE_A), D_ALL); 2375 MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write); 2376 MMIO_D(SPRKEYMAX(PIPE_A), D_ALL); 2377 MMIO_D(SPROFFSET(PIPE_A), D_ALL); 2378 MMIO_D(SPRSCALE(PIPE_A), D_ALL); 2379 MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL); 2380 MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL, 2381 reg50080_mmio_write); 2382 2383 MMIO_D(SPRCTL(PIPE_B), D_ALL); 2384 MMIO_D(SPRLINOFF(PIPE_B), D_ALL); 2385 MMIO_D(SPRSTRIDE(PIPE_B), D_ALL); 2386 MMIO_D(SPRPOS(PIPE_B), D_ALL); 2387 MMIO_D(SPRSIZE(PIPE_B), D_ALL); 2388 MMIO_D(SPRKEYVAL(PIPE_B), D_ALL); 2389 MMIO_D(SPRKEYMSK(PIPE_B), D_ALL); 2390 MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write); 2391 MMIO_D(SPRKEYMAX(PIPE_B), D_ALL); 2392 MMIO_D(SPROFFSET(PIPE_B), D_ALL); 2393 MMIO_D(SPRSCALE(PIPE_B), D_ALL); 2394 MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL); 2395 MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL, 2396 reg50080_mmio_write); 2397 2398 MMIO_D(SPRCTL(PIPE_C), D_ALL); 2399 MMIO_D(SPRLINOFF(PIPE_C), D_ALL); 2400 MMIO_D(SPRSTRIDE(PIPE_C), D_ALL); 2401 MMIO_D(SPRPOS(PIPE_C), D_ALL); 2402 MMIO_D(SPRSIZE(PIPE_C), D_ALL); 2403 MMIO_D(SPRKEYVAL(PIPE_C), D_ALL); 2404 MMIO_D(SPRKEYMSK(PIPE_C), D_ALL); 2405 MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write); 2406 MMIO_D(SPRKEYMAX(PIPE_C), D_ALL); 2407 MMIO_D(SPROFFSET(PIPE_C), D_ALL); 2408 MMIO_D(SPRSCALE(PIPE_C), D_ALL); 2409 MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL); 2410 MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL, 2411 reg50080_mmio_write); 2412 2413 MMIO_D(HTOTAL(TRANSCODER_A), D_ALL); 2414 MMIO_D(HBLANK(TRANSCODER_A), D_ALL); 2415 MMIO_D(HSYNC(TRANSCODER_A), D_ALL); 2416 MMIO_D(VTOTAL(TRANSCODER_A), D_ALL); 2417 MMIO_D(VBLANK(TRANSCODER_A), D_ALL); 2418 MMIO_D(VSYNC(TRANSCODER_A), D_ALL); 2419 MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL); 2420 MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL); 2421 MMIO_D(PIPESRC(TRANSCODER_A), D_ALL); 2422 2423 MMIO_D(HTOTAL(TRANSCODER_B), D_ALL); 2424 MMIO_D(HBLANK(TRANSCODER_B), D_ALL); 2425 MMIO_D(HSYNC(TRANSCODER_B), D_ALL); 2426 MMIO_D(VTOTAL(TRANSCODER_B), D_ALL); 2427 MMIO_D(VBLANK(TRANSCODER_B), D_ALL); 2428 MMIO_D(VSYNC(TRANSCODER_B), D_ALL); 2429 MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL); 2430 MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL); 2431 MMIO_D(PIPESRC(TRANSCODER_B), D_ALL); 2432 2433 MMIO_D(HTOTAL(TRANSCODER_C), D_ALL); 2434 MMIO_D(HBLANK(TRANSCODER_C), D_ALL); 2435 MMIO_D(HSYNC(TRANSCODER_C), D_ALL); 2436 MMIO_D(VTOTAL(TRANSCODER_C), D_ALL); 2437 MMIO_D(VBLANK(TRANSCODER_C), D_ALL); 2438 MMIO_D(VSYNC(TRANSCODER_C), D_ALL); 2439 MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL); 2440 MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL); 2441 MMIO_D(PIPESRC(TRANSCODER_C), D_ALL); 2442 2443 MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL); 2444 MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL); 2445 MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL); 2446 MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL); 2447 MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL); 2448 MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL); 2449 MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL); 2450 MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL); 2451 2452 MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL); 2453 MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL); 2454 MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL); 2455 MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL); 2456 MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL); 2457 MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL); 2458 MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL); 2459 MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL); 2460 2461 MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL); 2462 MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL); 2463 MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL); 2464 MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL); 2465 MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL); 2466 MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL); 2467 MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL); 2468 MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL); 2469 2470 MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL); 2471 MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL); 2472 MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL); 2473 MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL); 2474 MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL); 2475 MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL); 2476 MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL); 2477 MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL); 2478 2479 MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL); 2480 MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL); 2481 MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL); 2482 MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL); 2483 MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL); 2484 MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL); 2485 MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL); 2486 MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL); 2487 2488 MMIO_D(PF_CTL(PIPE_A), D_ALL); 2489 MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL); 2490 MMIO_D(PF_WIN_POS(PIPE_A), D_ALL); 2491 MMIO_D(PF_VSCALE(PIPE_A), D_ALL); 2492 MMIO_D(PF_HSCALE(PIPE_A), D_ALL); 2493 2494 MMIO_D(PF_CTL(PIPE_B), D_ALL); 2495 MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL); 2496 MMIO_D(PF_WIN_POS(PIPE_B), D_ALL); 2497 MMIO_D(PF_VSCALE(PIPE_B), D_ALL); 2498 MMIO_D(PF_HSCALE(PIPE_B), D_ALL); 2499 2500 MMIO_D(PF_CTL(PIPE_C), D_ALL); 2501 MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL); 2502 MMIO_D(PF_WIN_POS(PIPE_C), D_ALL); 2503 MMIO_D(PF_VSCALE(PIPE_C), D_ALL); 2504 MMIO_D(PF_HSCALE(PIPE_C), D_ALL); 2505 2506 MMIO_D(WM0_PIPE_ILK(PIPE_A), D_ALL); 2507 MMIO_D(WM0_PIPE_ILK(PIPE_B), D_ALL); 2508 MMIO_D(WM0_PIPE_ILK(PIPE_C), D_ALL); 2509 MMIO_D(WM1_LP_ILK, D_ALL); 2510 MMIO_D(WM2_LP_ILK, D_ALL); 2511 MMIO_D(WM3_LP_ILK, D_ALL); 2512 MMIO_D(WM1S_LP_ILK, D_ALL); 2513 MMIO_D(WM2S_LP_IVB, D_ALL); 2514 MMIO_D(WM3S_LP_IVB, D_ALL); 2515 2516 MMIO_D(BLC_PWM_CPU_CTL2, D_ALL); 2517 MMIO_D(BLC_PWM_CPU_CTL, D_ALL); 2518 MMIO_D(BLC_PWM_PCH_CTL1, D_ALL); 2519 MMIO_D(BLC_PWM_PCH_CTL2, D_ALL); 2520 2521 MMIO_D(_MMIO(0x48268), D_ALL); 2522 2523 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read, 2524 gmbus_mmio_write); 2525 MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL); 2526 MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL); 2527 2528 MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 2529 dp_aux_ch_ctl_mmio_write); 2530 MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 2531 dp_aux_ch_ctl_mmio_write); 2532 MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 2533 dp_aux_ch_ctl_mmio_write); 2534 2535 MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write); 2536 2537 MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write); 2538 MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write); 2539 2540 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write); 2541 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write); 2542 MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write); 2543 MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); 2544 MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); 2545 MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); 2546 MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); 2547 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); 2548 MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); 2549 2550 MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A), D_ALL); 2551 MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A), D_ALL); 2552 MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A), D_ALL); 2553 MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A), D_ALL); 2554 MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A), D_ALL); 2555 MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A), D_ALL); 2556 MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A), D_ALL); 2557 2558 MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B), D_ALL); 2559 MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B), D_ALL); 2560 MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B), D_ALL); 2561 MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B), D_ALL); 2562 MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B), D_ALL); 2563 MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B), D_ALL); 2564 MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B), D_ALL); 2565 2566 MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1), D_ALL); 2567 MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1), D_ALL); 2568 MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2), D_ALL); 2569 MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2), D_ALL); 2570 MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1), D_ALL); 2571 MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1), D_ALL); 2572 MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2), D_ALL); 2573 MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2), D_ALL); 2574 2575 MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL); 2576 MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL); 2577 MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL); 2578 2579 MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL); 2580 MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL); 2581 MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL); 2582 2583 MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL); 2584 MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL); 2585 MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL); 2586 2587 MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL); 2588 MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL); 2589 MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL); 2590 2591 MMIO_D(_MMIO(_FDI_RXA_MISC), D_ALL); 2592 MMIO_D(_MMIO(_FDI_RXB_MISC), D_ALL); 2593 MMIO_D(_MMIO(_FDI_RXA_TUSIZE1), D_ALL); 2594 MMIO_D(_MMIO(_FDI_RXA_TUSIZE2), D_ALL); 2595 MMIO_D(_MMIO(_FDI_RXB_TUSIZE1), D_ALL); 2596 MMIO_D(_MMIO(_FDI_RXB_TUSIZE2), D_ALL); 2597 2598 MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write); 2599 MMIO_D(PCH_PP_DIVISOR, D_ALL); 2600 MMIO_D(PCH_PP_STATUS, D_ALL); 2601 MMIO_D(PCH_LVDS, D_ALL); 2602 MMIO_D(_MMIO(_PCH_DPLL_A), D_ALL); 2603 MMIO_D(_MMIO(_PCH_DPLL_B), D_ALL); 2604 MMIO_D(_MMIO(_PCH_FPA0), D_ALL); 2605 MMIO_D(_MMIO(_PCH_FPA1), D_ALL); 2606 MMIO_D(_MMIO(_PCH_FPB0), D_ALL); 2607 MMIO_D(_MMIO(_PCH_FPB1), D_ALL); 2608 MMIO_D(PCH_DREF_CONTROL, D_ALL); 2609 MMIO_D(PCH_RAWCLK_FREQ, D_ALL); 2610 MMIO_D(PCH_DPLL_SEL, D_ALL); 2611 2612 MMIO_D(_MMIO(0x61208), D_ALL); 2613 MMIO_D(_MMIO(0x6120c), D_ALL); 2614 MMIO_D(PCH_PP_ON_DELAYS, D_ALL); 2615 MMIO_D(PCH_PP_OFF_DELAYS, D_ALL); 2616 2617 MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL); 2618 MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL); 2619 MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL); 2620 MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL); 2621 MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL); 2622 MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL); 2623 2624 MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0, 2625 PORTA_HOTPLUG_STATUS_MASK 2626 | PORTB_HOTPLUG_STATUS_MASK 2627 | PORTC_HOTPLUG_STATUS_MASK 2628 | PORTD_HOTPLUG_STATUS_MASK, 2629 NULL, NULL); 2630 2631 MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write); 2632 MMIO_D(FUSE_STRAP, D_ALL); 2633 MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL); 2634 2635 MMIO_D(DISP_ARB_CTL, D_ALL); 2636 MMIO_D(DISP_ARB_CTL2, D_ALL); 2637 2638 MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL); 2639 MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL); 2640 MMIO_D(ILK_DSPCLK_GATE_D, D_ALL); 2641 2642 MMIO_D(SOUTH_CHICKEN1, D_ALL); 2643 MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write); 2644 MMIO_D(_MMIO(_TRANSA_CHICKEN1), D_ALL); 2645 MMIO_D(_MMIO(_TRANSB_CHICKEN1), D_ALL); 2646 MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL); 2647 MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL); 2648 MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL); 2649 2650 MMIO_D(ILK_DPFC_CB_BASE, D_ALL); 2651 MMIO_D(ILK_DPFC_CONTROL, D_ALL); 2652 MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL); 2653 MMIO_D(ILK_DPFC_STATUS, D_ALL); 2654 MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL); 2655 MMIO_D(ILK_DPFC_CHICKEN, D_ALL); 2656 MMIO_D(ILK_FBC_RT_BASE, D_ALL); 2657 2658 MMIO_D(IPS_CTL, D_ALL); 2659 2660 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL); 2661 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL); 2662 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL); 2663 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL); 2664 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL); 2665 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL); 2666 MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL); 2667 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL); 2668 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL); 2669 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL); 2670 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL); 2671 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL); 2672 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL); 2673 2674 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL); 2675 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL); 2676 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL); 2677 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL); 2678 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL); 2679 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL); 2680 MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL); 2681 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL); 2682 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL); 2683 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL); 2684 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL); 2685 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL); 2686 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL); 2687 2688 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL); 2689 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL); 2690 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL); 2691 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL); 2692 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL); 2693 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL); 2694 MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL); 2695 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL); 2696 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL); 2697 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL); 2698 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL); 2699 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL); 2700 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL); 2701 2702 MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL); 2703 MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL); 2704 MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 2705 2706 MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL); 2707 MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL); 2708 MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 2709 2710 MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL); 2711 MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL); 2712 MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 2713 2714 MMIO_D(_MMIO(0x60110), D_ALL); 2715 MMIO_D(_MMIO(0x61110), D_ALL); 2716 MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL); 2717 MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL); 2718 MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL); 2719 MMIO_F(_MMIO(0x70440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2720 MMIO_F(_MMIO(0x71440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2721 MMIO_F(_MMIO(0x72440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2722 MMIO_F(_MMIO(0x7044c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2723 MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2724 MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2725 2726 MMIO_D(WM_LINETIME(PIPE_A), D_ALL); 2727 MMIO_D(WM_LINETIME(PIPE_B), D_ALL); 2728 MMIO_D(WM_LINETIME(PIPE_C), D_ALL); 2729 MMIO_D(SPLL_CTL, D_ALL); 2730 MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL); 2731 MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL); 2732 MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL); 2733 MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL); 2734 MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL); 2735 MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL); 2736 MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL); 2737 MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL); 2738 MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL); 2739 MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL); 2740 2741 MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL); 2742 MMIO_D(_MMIO(0x46508), D_ALL); 2743 2744 MMIO_D(_MMIO(0x49080), D_ALL); 2745 MMIO_D(_MMIO(0x49180), D_ALL); 2746 MMIO_D(_MMIO(0x49280), D_ALL); 2747 2748 MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL); 2749 MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL); 2750 MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL); 2751 2752 MMIO_D(GAMMA_MODE(PIPE_A), D_ALL); 2753 MMIO_D(GAMMA_MODE(PIPE_B), D_ALL); 2754 MMIO_D(GAMMA_MODE(PIPE_C), D_ALL); 2755 2756 MMIO_D(PIPE_MULT(PIPE_A), D_ALL); 2757 MMIO_D(PIPE_MULT(PIPE_B), D_ALL); 2758 MMIO_D(PIPE_MULT(PIPE_C), D_ALL); 2759 2760 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL); 2761 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL); 2762 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL); 2763 2764 MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL); 2765 MMIO_D(SBI_ADDR, D_ALL); 2766 MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL); 2767 MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write); 2768 MMIO_D(PIXCLK_GATE, D_ALL); 2769 2770 MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL, 2771 dp_aux_ch_ctl_mmio_write); 2772 2773 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2774 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2775 MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2776 MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2777 MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2778 2779 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write); 2780 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write); 2781 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write); 2782 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write); 2783 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write); 2784 2785 MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write); 2786 MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write); 2787 MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write); 2788 MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write); 2789 MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL); 2790 2791 MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2792 MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2793 MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2794 MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2795 MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2796 2797 MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL); 2798 MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL); 2799 MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A), D_ALL); 2800 2801 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL); 2802 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL); 2803 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL); 2804 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL); 2805 2806 MMIO_D(_MMIO(_TRANSA_MSA_MISC), D_ALL); 2807 MMIO_D(_MMIO(_TRANSB_MSA_MISC), D_ALL); 2808 MMIO_D(_MMIO(_TRANSC_MSA_MISC), D_ALL); 2809 MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC), D_ALL); 2810 2811 MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL); 2812 MMIO_D(FORCEWAKE_ACK, D_ALL); 2813 MMIO_D(GEN6_GT_CORE_STATUS, D_ALL); 2814 MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL); 2815 MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL); 2816 MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL); 2817 MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write); 2818 MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL); 2819 MMIO_D(ECOBUS, D_ALL); 2820 MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL); 2821 MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL); 2822 MMIO_D(GEN6_RPNSWREQ, D_ALL); 2823 MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL); 2824 MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL); 2825 MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL); 2826 MMIO_D(GEN6_RPSTAT1, D_ALL); 2827 MMIO_D(GEN6_RP_CONTROL, D_ALL); 2828 MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL); 2829 MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL); 2830 MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL); 2831 MMIO_D(GEN6_RP_CUR_UP, D_ALL); 2832 MMIO_D(GEN6_RP_PREV_UP, D_ALL); 2833 MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL); 2834 MMIO_D(GEN6_RP_CUR_DOWN, D_ALL); 2835 MMIO_D(GEN6_RP_PREV_DOWN, D_ALL); 2836 MMIO_D(GEN6_RP_UP_EI, D_ALL); 2837 MMIO_D(GEN6_RP_DOWN_EI, D_ALL); 2838 MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL); 2839 MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL); 2840 MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL); 2841 MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL); 2842 MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL); 2843 MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL); 2844 MMIO_D(GEN6_RC_SLEEP, D_ALL); 2845 MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL); 2846 MMIO_D(GEN6_RC6_THRESHOLD, D_ALL); 2847 MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL); 2848 MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL); 2849 MMIO_D(GEN6_PMINTRMSK, D_ALL); 2850 MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write); 2851 MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write); 2852 MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write); 2853 MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write); 2854 MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write); 2855 MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write); 2856 2857 MMIO_D(RSTDBYCTL, D_ALL); 2858 2859 MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write); 2860 MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write); 2861 MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write); 2862 2863 MMIO_D(TILECTL, D_ALL); 2864 2865 MMIO_D(GEN6_UCGCTL1, D_ALL); 2866 MMIO_D(GEN6_UCGCTL2, D_ALL); 2867 2868 MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL); 2869 2870 MMIO_D(GEN6_PCODE_DATA, D_ALL); 2871 MMIO_D(_MMIO(0x13812c), D_ALL); 2872 MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL); 2873 MMIO_D(HSW_EDRAM_CAP, D_ALL); 2874 MMIO_D(HSW_IDICR, D_ALL); 2875 MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL); 2876 2877 MMIO_D(_MMIO(0x3c), D_ALL); 2878 MMIO_D(_MMIO(0x860), D_ALL); 2879 MMIO_D(ECOSKPD, D_ALL); 2880 MMIO_D(_MMIO(0x121d0), D_ALL); 2881 MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL); 2882 MMIO_D(_MMIO(0x41d0), D_ALL); 2883 MMIO_D(GAC_ECO_BITS, D_ALL); 2884 MMIO_D(_MMIO(0x6200), D_ALL); 2885 MMIO_D(_MMIO(0x6204), D_ALL); 2886 MMIO_D(_MMIO(0x6208), D_ALL); 2887 MMIO_D(_MMIO(0x7118), D_ALL); 2888 MMIO_D(_MMIO(0x7180), D_ALL); 2889 MMIO_D(_MMIO(0x7408), D_ALL); 2890 MMIO_D(_MMIO(0x7c00), D_ALL); 2891 MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write); 2892 MMIO_D(_MMIO(0x911c), D_ALL); 2893 MMIO_D(_MMIO(0x9120), D_ALL); 2894 MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL); 2895 2896 MMIO_D(GAB_CTL, D_ALL); 2897 MMIO_D(_MMIO(0x48800), D_ALL); 2898 MMIO_D(_MMIO(0xce044), D_ALL); 2899 MMIO_D(_MMIO(0xe6500), D_ALL); 2900 MMIO_D(_MMIO(0xe6504), D_ALL); 2901 MMIO_D(_MMIO(0xe6600), D_ALL); 2902 MMIO_D(_MMIO(0xe6604), D_ALL); 2903 MMIO_D(_MMIO(0xe6700), D_ALL); 2904 MMIO_D(_MMIO(0xe6704), D_ALL); 2905 MMIO_D(_MMIO(0xe6800), D_ALL); 2906 MMIO_D(_MMIO(0xe6804), D_ALL); 2907 MMIO_D(PCH_GMBUS4, D_ALL); 2908 MMIO_D(PCH_GMBUS5, D_ALL); 2909 2910 MMIO_D(_MMIO(0x902c), D_ALL); 2911 MMIO_D(_MMIO(0xec008), D_ALL); 2912 MMIO_D(_MMIO(0xec00c), D_ALL); 2913 MMIO_D(_MMIO(0xec008 + 0x18), D_ALL); 2914 MMIO_D(_MMIO(0xec00c + 0x18), D_ALL); 2915 MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL); 2916 MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL); 2917 MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL); 2918 MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL); 2919 MMIO_D(_MMIO(0xec408), D_ALL); 2920 MMIO_D(_MMIO(0xec40c), D_ALL); 2921 MMIO_D(_MMIO(0xec408 + 0x18), D_ALL); 2922 MMIO_D(_MMIO(0xec40c + 0x18), D_ALL); 2923 MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL); 2924 MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL); 2925 MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL); 2926 MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL); 2927 MMIO_D(_MMIO(0xfc810), D_ALL); 2928 MMIO_D(_MMIO(0xfc81c), D_ALL); 2929 MMIO_D(_MMIO(0xfc828), D_ALL); 2930 MMIO_D(_MMIO(0xfc834), D_ALL); 2931 MMIO_D(_MMIO(0xfcc00), D_ALL); 2932 MMIO_D(_MMIO(0xfcc0c), D_ALL); 2933 MMIO_D(_MMIO(0xfcc18), D_ALL); 2934 MMIO_D(_MMIO(0xfcc24), D_ALL); 2935 MMIO_D(_MMIO(0xfd000), D_ALL); 2936 MMIO_D(_MMIO(0xfd00c), D_ALL); 2937 MMIO_D(_MMIO(0xfd018), D_ALL); 2938 MMIO_D(_MMIO(0xfd024), D_ALL); 2939 MMIO_D(_MMIO(0xfd034), D_ALL); 2940 2941 MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write); 2942 MMIO_D(_MMIO(0x2054), D_ALL); 2943 MMIO_D(_MMIO(0x12054), D_ALL); 2944 MMIO_D(_MMIO(0x22054), D_ALL); 2945 MMIO_D(_MMIO(0x1a054), D_ALL); 2946 2947 MMIO_D(_MMIO(0x44070), D_ALL); 2948 MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2949 MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL); 2950 MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL); 2951 MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL); 2952 MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL); 2953 2954 MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL); 2955 MMIO_D(_MMIO(0x2b00), D_BDW_PLUS); 2956 MMIO_D(_MMIO(0x2360), D_BDW_PLUS); 2957 MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2958 MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2959 MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2960 2961 MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2962 MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2963 MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL); 2964 2965 MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2966 MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2967 MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2968 MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2969 MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2970 MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2971 MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2972 MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2973 MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2974 MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2975 MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2976 MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2977 MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2978 MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2979 MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2980 MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2981 MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2982 2983 MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2984 MMIO_RING_GM(RING_BBADDR, D_ALL, NULL, NULL); 2985 MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL); 2986 MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL); 2987 MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL); 2988 MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL); 2989 MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL); 2990 MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2991 MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2992 MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2993 MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2994 2995 MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write); 2996 MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write); 2997 MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL); 2998 2999 return 0; 3000 } 3001 3002 static int init_bdw_mmio_info(struct intel_gvt *gvt) 3003 { 3004 struct drm_i915_private *dev_priv = gvt->gt->i915; 3005 int ret; 3006 3007 MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 3008 MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 3009 MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 3010 MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS); 3011 3012 MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 3013 MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 3014 MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 3015 MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS); 3016 3017 MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 3018 MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 3019 MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 3020 MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS); 3021 3022 MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 3023 MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 3024 MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 3025 MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS); 3026 3027 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL, 3028 intel_vgpu_reg_imr_handler); 3029 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL, 3030 intel_vgpu_reg_ier_handler); 3031 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL, 3032 intel_vgpu_reg_iir_handler); 3033 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS); 3034 3035 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL, 3036 intel_vgpu_reg_imr_handler); 3037 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL, 3038 intel_vgpu_reg_ier_handler); 3039 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL, 3040 intel_vgpu_reg_iir_handler); 3041 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS); 3042 3043 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL, 3044 intel_vgpu_reg_imr_handler); 3045 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL, 3046 intel_vgpu_reg_ier_handler); 3047 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL, 3048 intel_vgpu_reg_iir_handler); 3049 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS); 3050 3051 MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 3052 MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 3053 MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 3054 MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS); 3055 3056 MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 3057 MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 3058 MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 3059 MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS); 3060 3061 MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 3062 MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 3063 MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 3064 MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS); 3065 3066 MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL, 3067 intel_vgpu_reg_master_irq_handler); 3068 3069 MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, 0, 3070 mmio_read_from_hw, NULL); 3071 3072 #define RING_REG(base) _MMIO((base) + 0xd0) 3073 MMIO_RING_F(RING_REG, 4, F_RO, 0, 3074 ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL, 3075 ring_reset_ctl_write); 3076 #undef RING_REG 3077 3078 #define RING_REG(base) _MMIO((base) + 0x230) 3079 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write); 3080 #undef RING_REG 3081 3082 #define RING_REG(base) _MMIO((base) + 0x234) 3083 MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS, 3084 NULL, NULL); 3085 #undef RING_REG 3086 3087 #define RING_REG(base) _MMIO((base) + 0x244) 3088 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 3089 #undef RING_REG 3090 3091 #define RING_REG(base) _MMIO((base) + 0x370) 3092 MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL); 3093 #undef RING_REG 3094 3095 #define RING_REG(base) _MMIO((base) + 0x3a0) 3096 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 3097 #undef RING_REG 3098 3099 MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS); 3100 MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS); 3101 MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS); 3102 MMIO_D(_MMIO(0x1c1d0), D_BDW_PLUS); 3103 MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS); 3104 MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS); 3105 MMIO_D(_MMIO(0x1c054), D_BDW_PLUS); 3106 3107 MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write); 3108 3109 MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS & ~D_BXT); 3110 MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS); 3111 3112 MMIO_D(GAMTARBMODE, D_BDW_PLUS); 3113 3114 #define RING_REG(base) _MMIO((base) + 0x270) 3115 MMIO_RING_F(RING_REG, 32, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL); 3116 #undef RING_REG 3117 3118 MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write); 3119 3120 MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 3121 3122 MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS); 3123 MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS); 3124 MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS); 3125 3126 MMIO_D(WM_MISC, D_BDW); 3127 MMIO_D(_MMIO(_SRD_CTL_EDP), D_BDW); 3128 3129 MMIO_D(_MMIO(0x6671c), D_BDW_PLUS); 3130 MMIO_D(_MMIO(0x66c00), D_BDW_PLUS); 3131 MMIO_D(_MMIO(0x66c04), D_BDW_PLUS); 3132 3133 MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS); 3134 3135 MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS); 3136 MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS); 3137 MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS); 3138 3139 MMIO_D(_MMIO(0xfdc), D_BDW_PLUS); 3140 MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, 3141 NULL, NULL); 3142 MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, 3143 NULL, NULL); 3144 MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 3145 3146 MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL); 3147 MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL); 3148 MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 3149 MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL); 3150 MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL); 3151 MMIO_D(_MMIO(0xb110), D_BDW); 3152 MMIO_D(GEN9_SCRATCH_LNCF1, D_BDW_PLUS); 3153 3154 MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS | F_CMD_WRITE_PATCH, 0, 0, 3155 D_BDW_PLUS, NULL, force_nonpriv_write); 3156 3157 MMIO_D(_MMIO(0x44484), D_BDW_PLUS); 3158 MMIO_D(_MMIO(0x4448c), D_BDW_PLUS); 3159 3160 MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL); 3161 MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS); 3162 3163 MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL); 3164 3165 MMIO_D(_MMIO(0x110000), D_BDW_PLUS); 3166 3167 MMIO_D(_MMIO(0x48400), D_BDW_PLUS); 3168 3169 MMIO_D(_MMIO(0x6e570), D_BDW_PLUS); 3170 MMIO_D(_MMIO(0x65f10), D_BDW_PLUS); 3171 3172 MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 3173 MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 3174 MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 3175 MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 3176 3177 MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL); 3178 3179 MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 3180 MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 3181 MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 3182 MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 3183 MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 3184 MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 3185 MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 3186 MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 3187 MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 3188 MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 3189 return 0; 3190 } 3191 3192 static int init_skl_mmio_info(struct intel_gvt *gvt) 3193 { 3194 struct drm_i915_private *dev_priv = gvt->gt->i915; 3195 int ret; 3196 3197 MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 3198 MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL); 3199 MMIO_DH(FORCEWAKE_GT_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 3200 MMIO_DH(FORCEWAKE_ACK_GT_GEN9, D_SKL_PLUS, NULL, NULL); 3201 MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 3202 MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL); 3203 3204 MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 3205 dp_aux_ch_ctl_mmio_write); 3206 MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 3207 dp_aux_ch_ctl_mmio_write); 3208 MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 3209 dp_aux_ch_ctl_mmio_write); 3210 3211 MMIO_D(HSW_PWR_WELL_CTL1, D_SKL_PLUS); 3212 MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write); 3213 3214 MMIO_DH(DBUF_CTL_S(0), D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write); 3215 3216 MMIO_D(GEN9_PG_ENABLE, D_SKL_PLUS); 3217 MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS); 3218 MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS); 3219 MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 3220 MMIO_DFH(MMCD_MISC_CTRL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 3221 MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL); 3222 MMIO_D(DC_STATE_EN, D_SKL_PLUS); 3223 MMIO_D(DC_STATE_DEBUG, D_SKL_PLUS); 3224 MMIO_D(CDCLK_CTL, D_SKL_PLUS); 3225 MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write); 3226 MMIO_DH(LCPLL2_CTL, D_SKL_PLUS, NULL, skl_lcpll_write); 3227 MMIO_D(_MMIO(_DPLL1_CFGCR1), D_SKL_PLUS); 3228 MMIO_D(_MMIO(_DPLL2_CFGCR1), D_SKL_PLUS); 3229 MMIO_D(_MMIO(_DPLL3_CFGCR1), D_SKL_PLUS); 3230 MMIO_D(_MMIO(_DPLL1_CFGCR2), D_SKL_PLUS); 3231 MMIO_D(_MMIO(_DPLL2_CFGCR2), D_SKL_PLUS); 3232 MMIO_D(_MMIO(_DPLL3_CFGCR2), D_SKL_PLUS); 3233 MMIO_D(DPLL_CTRL1, D_SKL_PLUS); 3234 MMIO_D(DPLL_CTRL2, D_SKL_PLUS); 3235 MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL); 3236 3237 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); 3238 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); 3239 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); 3240 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); 3241 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); 3242 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); 3243 3244 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); 3245 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); 3246 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); 3247 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); 3248 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); 3249 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); 3250 3251 MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); 3252 MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); 3253 MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); 3254 MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); 3255 MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); 3256 MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); 3257 3258 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 3259 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 3260 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 3261 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); 3262 3263 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 3264 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 3265 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 3266 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); 3267 3268 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 3269 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 3270 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 3271 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); 3272 3273 MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL); 3274 MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL); 3275 MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL); 3276 3277 MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 3278 MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 3279 MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 3280 3281 MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 3282 MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 3283 MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 3284 3285 MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 3286 MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 3287 MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 3288 3289 MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 3290 MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 3291 MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 3292 3293 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 3294 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 3295 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 3296 3297 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 3298 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 3299 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 3300 3301 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 3302 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 3303 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 3304 3305 MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL); 3306 MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL); 3307 MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL); 3308 3309 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 3310 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 3311 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 3312 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); 3313 3314 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 3315 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 3316 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 3317 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); 3318 3319 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 3320 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 3321 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 3322 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); 3323 3324 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL); 3325 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL); 3326 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL); 3327 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL); 3328 3329 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL); 3330 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL); 3331 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL); 3332 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL); 3333 3334 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL); 3335 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL); 3336 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL); 3337 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL); 3338 3339 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL); 3340 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL); 3341 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL); 3342 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL); 3343 3344 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL); 3345 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL); 3346 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL); 3347 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL); 3348 3349 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL); 3350 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL); 3351 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL); 3352 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL); 3353 3354 MMIO_D(_MMIO(_PLANE_CTL_3_A), D_SKL_PLUS); 3355 MMIO_D(_MMIO(_PLANE_CTL_3_B), D_SKL_PLUS); 3356 MMIO_D(_MMIO(0x72380), D_SKL_PLUS); 3357 MMIO_D(_MMIO(0x7239c), D_SKL_PLUS); 3358 MMIO_D(_MMIO(_PLANE_SURF_3_A), D_SKL_PLUS); 3359 MMIO_D(_MMIO(_PLANE_SURF_3_B), D_SKL_PLUS); 3360 3361 MMIO_D(DMC_SSP_BASE, D_SKL_PLUS); 3362 MMIO_D(DMC_HTP_SKL, D_SKL_PLUS); 3363 MMIO_D(DMC_LAST_WRITE, D_SKL_PLUS); 3364 3365 MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 3366 3367 MMIO_D(SKL_DFSM, D_SKL_PLUS); 3368 MMIO_D(DISPIO_CR_TX_BMU_CR0, D_SKL_PLUS); 3369 3370 MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS, 3371 NULL, NULL); 3372 MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS, 3373 NULL, NULL); 3374 3375 MMIO_D(RPM_CONFIG0, D_SKL_PLUS); 3376 MMIO_D(_MMIO(0xd08), D_SKL_PLUS); 3377 MMIO_D(RC6_LOCATION, D_SKL_PLUS); 3378 MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS, 3379 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 3380 MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, 3381 NULL, NULL); 3382 3383 /* TRTT */ 3384 MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 3385 MMIO_DFH(TRVATTL3PTRDW(1), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 3386 MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 3387 MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 3388 MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 3389 MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS | F_PM_SAVE, 3390 NULL, gen9_trtte_write); 3391 MMIO_DFH(_MMIO(0x4dfc), D_SKL_PLUS, F_PM_SAVE, 3392 NULL, gen9_trtt_chicken_write); 3393 3394 MMIO_D(_MMIO(0x46430), D_SKL_PLUS); 3395 3396 MMIO_D(_MMIO(0x46520), D_SKL_PLUS); 3397 3398 MMIO_D(_MMIO(0xc403c), D_SKL_PLUS); 3399 MMIO_DFH(GEN8_GARBCNTL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 3400 MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write); 3401 3402 MMIO_D(_MMIO(0x65900), D_SKL_PLUS); 3403 MMIO_D(GEN6_STOLEN_RESERVED, D_SKL_PLUS); 3404 MMIO_D(_MMIO(0x4068), D_SKL_PLUS); 3405 MMIO_D(_MMIO(0x67054), D_SKL_PLUS); 3406 MMIO_D(_MMIO(0x6e560), D_SKL_PLUS); 3407 MMIO_D(_MMIO(0x6e554), D_SKL_PLUS); 3408 MMIO_D(_MMIO(0x2b20), D_SKL_PLUS); 3409 MMIO_D(_MMIO(0x65f00), D_SKL_PLUS); 3410 MMIO_D(_MMIO(0x65f08), D_SKL_PLUS); 3411 MMIO_D(_MMIO(0x320f0), D_SKL_PLUS); 3412 3413 MMIO_D(_MMIO(0x70034), D_SKL_PLUS); 3414 MMIO_D(_MMIO(0x71034), D_SKL_PLUS); 3415 MMIO_D(_MMIO(0x72034), D_SKL_PLUS); 3416 3417 MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A)), D_SKL_PLUS); 3418 MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B)), D_SKL_PLUS); 3419 MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C)), D_SKL_PLUS); 3420 MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A)), D_SKL_PLUS); 3421 MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B)), D_SKL_PLUS); 3422 MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C)), D_SKL_PLUS); 3423 MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A)), D_SKL_PLUS); 3424 MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)), D_SKL_PLUS); 3425 MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)), D_SKL_PLUS); 3426 3427 MMIO_D(_MMIO(0x44500), D_SKL_PLUS); 3428 #define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4) 3429 MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, 3430 NULL, csfe_chicken1_mmio_write); 3431 #undef CSFE_CHICKEN1_REG 3432 MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, 3433 NULL, NULL); 3434 MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, 3435 NULL, NULL); 3436 3437 MMIO_DFH(GAMT_CHKN_BIT_REG, D_KBL | D_CFL, F_CMD_ACCESS, NULL, NULL); 3438 MMIO_D(GEN9_CTX_PREEMPT_REG, D_SKL_PLUS & ~D_BXT); 3439 3440 return 0; 3441 } 3442 3443 static int init_bxt_mmio_info(struct intel_gvt *gvt) 3444 { 3445 struct drm_i915_private *dev_priv = gvt->gt->i915; 3446 int ret; 3447 3448 MMIO_F(_MMIO(0x80000), 0x3000, 0, 0, 0, D_BXT, NULL, NULL); 3449 3450 MMIO_D(GEN7_SAMPLER_INSTDONE, D_BXT); 3451 MMIO_D(GEN7_ROW_INSTDONE, D_BXT); 3452 MMIO_D(GEN8_FAULT_TLB_DATA0, D_BXT); 3453 MMIO_D(GEN8_FAULT_TLB_DATA1, D_BXT); 3454 MMIO_D(ERROR_GEN6, D_BXT); 3455 MMIO_D(DONE_REG, D_BXT); 3456 MMIO_D(EIR, D_BXT); 3457 MMIO_D(PGTBL_ER, D_BXT); 3458 MMIO_D(_MMIO(0x4194), D_BXT); 3459 MMIO_D(_MMIO(0x4294), D_BXT); 3460 MMIO_D(_MMIO(0x4494), D_BXT); 3461 3462 MMIO_RING_D(RING_PSMI_CTL, D_BXT); 3463 MMIO_RING_D(RING_DMA_FADD, D_BXT); 3464 MMIO_RING_D(RING_DMA_FADD_UDW, D_BXT); 3465 MMIO_RING_D(RING_IPEHR, D_BXT); 3466 MMIO_RING_D(RING_INSTPS, D_BXT); 3467 MMIO_RING_D(RING_BBADDR_UDW, D_BXT); 3468 MMIO_RING_D(RING_BBSTATE, D_BXT); 3469 MMIO_RING_D(RING_IPEIR, D_BXT); 3470 3471 MMIO_F(SOFT_SCRATCH(0), 16 * 4, 0, 0, 0, D_BXT, NULL, NULL); 3472 3473 MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write); 3474 MMIO_D(BXT_RP_STATE_CAP, D_BXT); 3475 MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT, 3476 NULL, bxt_phy_ctl_family_write); 3477 MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT, 3478 NULL, bxt_phy_ctl_family_write); 3479 MMIO_D(BXT_PHY_CTL(PORT_A), D_BXT); 3480 MMIO_D(BXT_PHY_CTL(PORT_B), D_BXT); 3481 MMIO_D(BXT_PHY_CTL(PORT_C), D_BXT); 3482 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT, 3483 NULL, bxt_port_pll_enable_write); 3484 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT, 3485 NULL, bxt_port_pll_enable_write); 3486 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL, 3487 bxt_port_pll_enable_write); 3488 3489 MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY0), D_BXT); 3490 MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY0), D_BXT); 3491 MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY0), D_BXT); 3492 MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY0), D_BXT); 3493 MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY0), D_BXT); 3494 MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY0), D_BXT); 3495 MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY0), D_BXT); 3496 MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY0), D_BXT); 3497 MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY0), D_BXT); 3498 3499 MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY1), D_BXT); 3500 MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY1), D_BXT); 3501 MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY1), D_BXT); 3502 MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY1), D_BXT); 3503 MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY1), D_BXT); 3504 MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY1), D_BXT); 3505 MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY1), D_BXT); 3506 MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY1), D_BXT); 3507 MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY1), D_BXT); 3508 3509 MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH0), D_BXT); 3510 MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH0), D_BXT); 3511 MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH0), D_BXT); 3512 MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH0), D_BXT); 3513 MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH0), D_BXT); 3514 MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH0), D_BXT); 3515 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT, 3516 NULL, bxt_pcs_dw12_grp_write); 3517 MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH0), D_BXT); 3518 MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH0), D_BXT); 3519 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT, 3520 bxt_port_tx_dw3_read, NULL); 3521 MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH0), D_BXT); 3522 MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH0), D_BXT); 3523 MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH0), D_BXT); 3524 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT); 3525 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 1), D_BXT); 3526 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 2), D_BXT); 3527 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 3), D_BXT); 3528 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 0), D_BXT); 3529 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 1), D_BXT); 3530 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 2), D_BXT); 3531 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 3), D_BXT); 3532 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 6), D_BXT); 3533 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 8), D_BXT); 3534 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 9), D_BXT); 3535 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 10), D_BXT); 3536 3537 MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH1), D_BXT); 3538 MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH1), D_BXT); 3539 MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH1), D_BXT); 3540 MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH1), D_BXT); 3541 MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH1), D_BXT); 3542 MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH1), D_BXT); 3543 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT, 3544 NULL, bxt_pcs_dw12_grp_write); 3545 MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH1), D_BXT); 3546 MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH1), D_BXT); 3547 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT, 3548 bxt_port_tx_dw3_read, NULL); 3549 MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH1), D_BXT); 3550 MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH1), D_BXT); 3551 MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH1), D_BXT); 3552 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT); 3553 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 1), D_BXT); 3554 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 2), D_BXT); 3555 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 3), D_BXT); 3556 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 0), D_BXT); 3557 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 1), D_BXT); 3558 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 2), D_BXT); 3559 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 3), D_BXT); 3560 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 6), D_BXT); 3561 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 8), D_BXT); 3562 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 9), D_BXT); 3563 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 10), D_BXT); 3564 3565 MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY1, DPIO_CH0), D_BXT); 3566 MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY1, DPIO_CH0), D_BXT); 3567 MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY1, DPIO_CH0), D_BXT); 3568 MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY1, DPIO_CH0), D_BXT); 3569 MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY1, DPIO_CH0), D_BXT); 3570 MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY1, DPIO_CH0), D_BXT); 3571 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT, 3572 NULL, bxt_pcs_dw12_grp_write); 3573 MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY1, DPIO_CH0), D_BXT); 3574 MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY1, DPIO_CH0), D_BXT); 3575 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT, 3576 bxt_port_tx_dw3_read, NULL); 3577 MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY1, DPIO_CH0), D_BXT); 3578 MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY1, DPIO_CH0), D_BXT); 3579 MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY1, DPIO_CH0), D_BXT); 3580 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT); 3581 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 1), D_BXT); 3582 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 2), D_BXT); 3583 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 3), D_BXT); 3584 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 0), D_BXT); 3585 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 1), D_BXT); 3586 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 2), D_BXT); 3587 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 3), D_BXT); 3588 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 6), D_BXT); 3589 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 8), D_BXT); 3590 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 9), D_BXT); 3591 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 10), D_BXT); 3592 3593 MMIO_D(BXT_DE_PLL_CTL, D_BXT); 3594 MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write); 3595 MMIO_D(BXT_DSI_PLL_CTL, D_BXT); 3596 MMIO_D(BXT_DSI_PLL_ENABLE, D_BXT); 3597 3598 MMIO_D(GEN9_CLKGATE_DIS_0, D_BXT); 3599 MMIO_D(GEN9_CLKGATE_DIS_4, D_BXT); 3600 3601 MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_A), D_BXT); 3602 MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT); 3603 MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C), D_BXT); 3604 3605 MMIO_D(RC6_CTX_BASE, D_BXT); 3606 3607 MMIO_D(GEN8_PUSHBUS_CONTROL, D_BXT); 3608 MMIO_D(GEN8_PUSHBUS_ENABLE, D_BXT); 3609 MMIO_D(GEN8_PUSHBUS_SHIFT, D_BXT); 3610 MMIO_D(GEN6_GFXPAUSE, D_BXT); 3611 MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL); 3612 MMIO_DFH(GEN8_L3CNTLREG, D_BXT, F_CMD_ACCESS, NULL, NULL); 3613 MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL); 3614 MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS, 3615 0, 0, D_BXT, NULL, NULL); 3616 MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS, 3617 0, 0, D_BXT, NULL, NULL); 3618 MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS, 3619 0, 0, D_BXT, NULL, NULL); 3620 MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS, 3621 0, 0, D_BXT, NULL, NULL); 3622 3623 MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL); 3624 3625 MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BXT, NULL, bxt_ppat_low_write); 3626 3627 return 0; 3628 } 3629 3630 static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt, 3631 unsigned int offset) 3632 { 3633 unsigned long device = intel_gvt_get_device_type(gvt); 3634 struct gvt_mmio_block *block = gvt->mmio.mmio_block; 3635 int num = gvt->mmio.num_mmio_block; 3636 int i; 3637 3638 for (i = 0; i < num; i++, block++) { 3639 if (!(device & block->device)) 3640 continue; 3641 if (offset >= i915_mmio_reg_offset(block->offset) && 3642 offset < i915_mmio_reg_offset(block->offset) + block->size) 3643 return block; 3644 } 3645 return NULL; 3646 } 3647 3648 /** 3649 * intel_gvt_clean_mmio_info - clean up MMIO information table for GVT device 3650 * @gvt: GVT device 3651 * 3652 * This function is called at the driver unloading stage, to clean up the MMIO 3653 * information table of GVT device 3654 * 3655 */ 3656 void intel_gvt_clean_mmio_info(struct intel_gvt *gvt) 3657 { 3658 struct hlist_node *tmp; 3659 struct intel_gvt_mmio_info *e; 3660 int i; 3661 3662 hash_for_each_safe(gvt->mmio.mmio_info_table, i, tmp, e, node) 3663 kfree(e); 3664 3665 vfree(gvt->mmio.mmio_attribute); 3666 gvt->mmio.mmio_attribute = NULL; 3667 } 3668 3669 /* Special MMIO blocks. registers in MMIO block ranges should not be command 3670 * accessible (should have no F_CMD_ACCESS flag). 3671 * otherwise, need to update cmd_reg_handler in cmd_parser.c 3672 */ 3673 static struct gvt_mmio_block mmio_blocks[] = { 3674 {D_SKL_PLUS, _MMIO(DMC_MMIO_START_RANGE), 0x3000, NULL, NULL}, 3675 {D_ALL, _MMIO(MCHBAR_MIRROR_BASE_SNB), 0x40000, NULL, NULL}, 3676 {D_ALL, _MMIO(VGT_PVINFO_PAGE), VGT_PVINFO_SIZE, 3677 pvinfo_mmio_read, pvinfo_mmio_write}, 3678 {D_ALL, LGC_PALETTE(PIPE_A, 0), 1024, NULL, NULL}, 3679 {D_ALL, LGC_PALETTE(PIPE_B, 0), 1024, NULL, NULL}, 3680 {D_ALL, LGC_PALETTE(PIPE_C, 0), 1024, NULL, NULL}, 3681 }; 3682 3683 /** 3684 * intel_gvt_setup_mmio_info - setup MMIO information table for GVT device 3685 * @gvt: GVT device 3686 * 3687 * This function is called at the initialization stage, to setup the MMIO 3688 * information table for GVT device 3689 * 3690 * Returns: 3691 * zero on success, negative if failed. 3692 */ 3693 int intel_gvt_setup_mmio_info(struct intel_gvt *gvt) 3694 { 3695 struct intel_gvt_device_info *info = &gvt->device_info; 3696 struct drm_i915_private *i915 = gvt->gt->i915; 3697 int size = info->mmio_size / 4 * sizeof(*gvt->mmio.mmio_attribute); 3698 int ret; 3699 3700 gvt->mmio.mmio_attribute = vzalloc(size); 3701 if (!gvt->mmio.mmio_attribute) 3702 return -ENOMEM; 3703 3704 ret = init_generic_mmio_info(gvt); 3705 if (ret) 3706 goto err; 3707 3708 if (IS_BROADWELL(i915)) { 3709 ret = init_bdw_mmio_info(gvt); 3710 if (ret) 3711 goto err; 3712 } else if (IS_SKYLAKE(i915) || 3713 IS_KABYLAKE(i915) || 3714 IS_COFFEELAKE(i915) || 3715 IS_COMETLAKE(i915)) { 3716 ret = init_bdw_mmio_info(gvt); 3717 if (ret) 3718 goto err; 3719 ret = init_skl_mmio_info(gvt); 3720 if (ret) 3721 goto err; 3722 } else if (IS_BROXTON(i915)) { 3723 ret = init_bdw_mmio_info(gvt); 3724 if (ret) 3725 goto err; 3726 ret = init_skl_mmio_info(gvt); 3727 if (ret) 3728 goto err; 3729 ret = init_bxt_mmio_info(gvt); 3730 if (ret) 3731 goto err; 3732 } 3733 3734 gvt->mmio.mmio_block = mmio_blocks; 3735 gvt->mmio.num_mmio_block = ARRAY_SIZE(mmio_blocks); 3736 3737 return 0; 3738 err: 3739 intel_gvt_clean_mmio_info(gvt); 3740 return ret; 3741 } 3742 3743 /** 3744 * intel_gvt_for_each_tracked_mmio - iterate each tracked mmio 3745 * @gvt: a GVT device 3746 * @handler: the handler 3747 * @data: private data given to handler 3748 * 3749 * Returns: 3750 * Zero on success, negative error code if failed. 3751 */ 3752 int intel_gvt_for_each_tracked_mmio(struct intel_gvt *gvt, 3753 int (*handler)(struct intel_gvt *gvt, u32 offset, void *data), 3754 void *data) 3755 { 3756 struct gvt_mmio_block *block = gvt->mmio.mmio_block; 3757 struct intel_gvt_mmio_info *e; 3758 int i, j, ret; 3759 3760 hash_for_each(gvt->mmio.mmio_info_table, i, e, node) { 3761 ret = handler(gvt, e->offset, data); 3762 if (ret) 3763 return ret; 3764 } 3765 3766 for (i = 0; i < gvt->mmio.num_mmio_block; i++, block++) { 3767 /* pvinfo data doesn't come from hw mmio */ 3768 if (i915_mmio_reg_offset(block->offset) == VGT_PVINFO_PAGE) 3769 continue; 3770 3771 for (j = 0; j < block->size; j += 4) { 3772 ret = handler(gvt, 3773 i915_mmio_reg_offset(block->offset) + j, 3774 data); 3775 if (ret) 3776 return ret; 3777 } 3778 } 3779 return 0; 3780 } 3781 3782 /** 3783 * intel_vgpu_default_mmio_read - default MMIO read handler 3784 * @vgpu: a vGPU 3785 * @offset: access offset 3786 * @p_data: data return buffer 3787 * @bytes: access data length 3788 * 3789 * Returns: 3790 * Zero on success, negative error code if failed. 3791 */ 3792 int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 3793 void *p_data, unsigned int bytes) 3794 { 3795 read_vreg(vgpu, offset, p_data, bytes); 3796 return 0; 3797 } 3798 3799 /** 3800 * intel_t_default_mmio_write - default MMIO write handler 3801 * @vgpu: a vGPU 3802 * @offset: access offset 3803 * @p_data: write data buffer 3804 * @bytes: access data length 3805 * 3806 * Returns: 3807 * Zero on success, negative error code if failed. 3808 */ 3809 int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 3810 void *p_data, unsigned int bytes) 3811 { 3812 write_vreg(vgpu, offset, p_data, bytes); 3813 return 0; 3814 } 3815 3816 /** 3817 * intel_vgpu_mask_mmio_write - write mask register 3818 * @vgpu: a vGPU 3819 * @offset: access offset 3820 * @p_data: write data buffer 3821 * @bytes: access data length 3822 * 3823 * Returns: 3824 * Zero on success, negative error code if failed. 3825 */ 3826 int intel_vgpu_mask_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 3827 void *p_data, unsigned int bytes) 3828 { 3829 u32 mask, old_vreg; 3830 3831 old_vreg = vgpu_vreg(vgpu, offset); 3832 write_vreg(vgpu, offset, p_data, bytes); 3833 mask = vgpu_vreg(vgpu, offset) >> 16; 3834 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask) | 3835 (vgpu_vreg(vgpu, offset) & mask); 3836 3837 return 0; 3838 } 3839 3840 /** 3841 * intel_gvt_in_force_nonpriv_whitelist - if a mmio is in whitelist to be 3842 * force-nopriv register 3843 * 3844 * @gvt: a GVT device 3845 * @offset: register offset 3846 * 3847 * Returns: 3848 * True if the register is in force-nonpriv whitelist; 3849 * False if outside; 3850 */ 3851 bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt, 3852 unsigned int offset) 3853 { 3854 return in_whitelist(offset); 3855 } 3856 3857 /** 3858 * intel_vgpu_mmio_reg_rw - emulate tracked mmio registers 3859 * @vgpu: a vGPU 3860 * @offset: register offset 3861 * @pdata: data buffer 3862 * @bytes: data length 3863 * @is_read: read or write 3864 * 3865 * Returns: 3866 * Zero on success, negative error code if failed. 3867 */ 3868 int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset, 3869 void *pdata, unsigned int bytes, bool is_read) 3870 { 3871 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 3872 struct intel_gvt *gvt = vgpu->gvt; 3873 struct intel_gvt_mmio_info *mmio_info; 3874 struct gvt_mmio_block *mmio_block; 3875 gvt_mmio_func func; 3876 int ret; 3877 3878 if (drm_WARN_ON(&i915->drm, bytes > 8)) 3879 return -EINVAL; 3880 3881 /* 3882 * Handle special MMIO blocks. 3883 */ 3884 mmio_block = find_mmio_block(gvt, offset); 3885 if (mmio_block) { 3886 func = is_read ? mmio_block->read : mmio_block->write; 3887 if (func) 3888 return func(vgpu, offset, pdata, bytes); 3889 goto default_rw; 3890 } 3891 3892 /* 3893 * Normal tracked MMIOs. 3894 */ 3895 mmio_info = intel_gvt_find_mmio_info(gvt, offset); 3896 if (!mmio_info) { 3897 gvt_dbg_mmio("untracked MMIO %08x len %d\n", offset, bytes); 3898 goto default_rw; 3899 } 3900 3901 if (is_read) 3902 return mmio_info->read(vgpu, offset, pdata, bytes); 3903 else { 3904 u64 ro_mask = mmio_info->ro_mask; 3905 u32 old_vreg = 0; 3906 u64 data = 0; 3907 3908 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) { 3909 old_vreg = vgpu_vreg(vgpu, offset); 3910 } 3911 3912 if (likely(!ro_mask)) 3913 ret = mmio_info->write(vgpu, offset, pdata, bytes); 3914 else if (!~ro_mask) { 3915 gvt_vgpu_err("try to write RO reg %x\n", offset); 3916 return 0; 3917 } else { 3918 /* keep the RO bits in the virtual register */ 3919 memcpy(&data, pdata, bytes); 3920 data &= ~ro_mask; 3921 data |= vgpu_vreg(vgpu, offset) & ro_mask; 3922 ret = mmio_info->write(vgpu, offset, &data, bytes); 3923 } 3924 3925 /* higher 16bits of mode ctl regs are mask bits for change */ 3926 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) { 3927 u32 mask = vgpu_vreg(vgpu, offset) >> 16; 3928 3929 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask) 3930 | (vgpu_vreg(vgpu, offset) & mask); 3931 } 3932 } 3933 3934 return ret; 3935 3936 default_rw: 3937 return is_read ? 3938 intel_vgpu_default_mmio_read(vgpu, offset, pdata, bytes) : 3939 intel_vgpu_default_mmio_write(vgpu, offset, pdata, bytes); 3940 } 3941 3942 void intel_gvt_restore_fence(struct intel_gvt *gvt) 3943 { 3944 struct intel_vgpu *vgpu; 3945 int i, id; 3946 3947 idr_for_each_entry(&(gvt)->vgpu_idr, vgpu, id) { 3948 mmio_hw_access_pre(gvt->gt); 3949 for (i = 0; i < vgpu_fence_sz(vgpu); i++) 3950 intel_vgpu_write_fence(vgpu, i, vgpu_vreg64(vgpu, fence_num_to_offset(i))); 3951 mmio_hw_access_post(gvt->gt); 3952 } 3953 } 3954 3955 static int mmio_pm_restore_handler(struct intel_gvt *gvt, u32 offset, void *data) 3956 { 3957 struct intel_vgpu *vgpu = data; 3958 struct drm_i915_private *dev_priv = gvt->gt->i915; 3959 3960 if (gvt->mmio.mmio_attribute[offset >> 2] & F_PM_SAVE) 3961 intel_uncore_write(&dev_priv->uncore, _MMIO(offset), vgpu_vreg(vgpu, offset)); 3962 3963 return 0; 3964 } 3965 3966 void intel_gvt_restore_mmio(struct intel_gvt *gvt) 3967 { 3968 struct intel_vgpu *vgpu; 3969 int id; 3970 3971 idr_for_each_entry(&(gvt)->vgpu_idr, vgpu, id) { 3972 mmio_hw_access_pre(gvt->gt); 3973 intel_gvt_for_each_tracked_mmio(gvt, mmio_pm_restore_handler, vgpu); 3974 mmio_hw_access_post(gvt->gt); 3975 } 3976 } 3977