1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Kevin Tian <kevin.tian@intel.com> 25 * Eddie Dong <eddie.dong@intel.com> 26 * Zhiyuan Lv <zhiyuan.lv@intel.com> 27 * 28 * Contributors: 29 * Min He <min.he@intel.com> 30 * Tina Zhang <tina.zhang@intel.com> 31 * Pei Zhang <pei.zhang@intel.com> 32 * Niu Bing <bing.niu@intel.com> 33 * Ping Gao <ping.a.gao@intel.com> 34 * Zhi Wang <zhi.a.wang@intel.com> 35 * 36 37 */ 38 39 #include "i915_drv.h" 40 #include "gvt.h" 41 #include "i915_pvinfo.h" 42 43 /* XXX FIXME i915 has changed PP_XXX definition */ 44 #define PCH_PP_STATUS _MMIO(0xc7200) 45 #define PCH_PP_CONTROL _MMIO(0xc7204) 46 #define PCH_PP_ON_DELAYS _MMIO(0xc7208) 47 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c) 48 #define PCH_PP_DIVISOR _MMIO(0xc7210) 49 50 unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt) 51 { 52 if (IS_BROADWELL(gvt->dev_priv)) 53 return D_BDW; 54 else if (IS_SKYLAKE(gvt->dev_priv)) 55 return D_SKL; 56 else if (IS_KABYLAKE(gvt->dev_priv)) 57 return D_KBL; 58 else if (IS_BROXTON(gvt->dev_priv)) 59 return D_BXT; 60 else if (IS_COFFEELAKE(gvt->dev_priv)) 61 return D_CFL; 62 63 return 0; 64 } 65 66 bool intel_gvt_match_device(struct intel_gvt *gvt, 67 unsigned long device) 68 { 69 return intel_gvt_get_device_type(gvt) & device; 70 } 71 72 static void read_vreg(struct intel_vgpu *vgpu, unsigned int offset, 73 void *p_data, unsigned int bytes) 74 { 75 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); 76 } 77 78 static void write_vreg(struct intel_vgpu *vgpu, unsigned int offset, 79 void *p_data, unsigned int bytes) 80 { 81 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes); 82 } 83 84 static struct intel_gvt_mmio_info *find_mmio_info(struct intel_gvt *gvt, 85 unsigned int offset) 86 { 87 struct intel_gvt_mmio_info *e; 88 89 hash_for_each_possible(gvt->mmio.mmio_info_table, e, node, offset) { 90 if (e->offset == offset) 91 return e; 92 } 93 return NULL; 94 } 95 96 static int new_mmio_info(struct intel_gvt *gvt, 97 u32 offset, u8 flags, u32 size, 98 u32 addr_mask, u32 ro_mask, u32 device, 99 gvt_mmio_func read, gvt_mmio_func write) 100 { 101 struct intel_gvt_mmio_info *info, *p; 102 u32 start, end, i; 103 104 if (!intel_gvt_match_device(gvt, device)) 105 return 0; 106 107 if (WARN_ON(!IS_ALIGNED(offset, 4))) 108 return -EINVAL; 109 110 start = offset; 111 end = offset + size; 112 113 for (i = start; i < end; i += 4) { 114 info = kzalloc(sizeof(*info), GFP_KERNEL); 115 if (!info) 116 return -ENOMEM; 117 118 info->offset = i; 119 p = find_mmio_info(gvt, info->offset); 120 if (p) { 121 WARN(1, "dup mmio definition offset %x\n", 122 info->offset); 123 kfree(info); 124 125 /* We return -EEXIST here to make GVT-g load fail. 126 * So duplicated MMIO can be found as soon as 127 * possible. 128 */ 129 return -EEXIST; 130 } 131 132 info->ro_mask = ro_mask; 133 info->device = device; 134 info->read = read ? read : intel_vgpu_default_mmio_read; 135 info->write = write ? write : intel_vgpu_default_mmio_write; 136 gvt->mmio.mmio_attribute[info->offset / 4] = flags; 137 INIT_HLIST_NODE(&info->node); 138 hash_add(gvt->mmio.mmio_info_table, &info->node, info->offset); 139 gvt->mmio.num_tracked_mmio++; 140 } 141 return 0; 142 } 143 144 /** 145 * intel_gvt_render_mmio_to_ring_id - convert a mmio offset into ring id 146 * @gvt: a GVT device 147 * @offset: register offset 148 * 149 * Returns: 150 * Ring ID on success, negative error code if failed. 151 */ 152 int intel_gvt_render_mmio_to_ring_id(struct intel_gvt *gvt, 153 unsigned int offset) 154 { 155 enum intel_engine_id id; 156 struct intel_engine_cs *engine; 157 158 offset &= ~GENMASK(11, 0); 159 for_each_engine(engine, gvt->dev_priv, id) { 160 if (engine->mmio_base == offset) 161 return id; 162 } 163 return -ENODEV; 164 } 165 166 #define offset_to_fence_num(offset) \ 167 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3) 168 169 #define fence_num_to_offset(num) \ 170 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) 171 172 173 void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason) 174 { 175 switch (reason) { 176 case GVT_FAILSAFE_UNSUPPORTED_GUEST: 177 pr_err("Detected your guest driver doesn't support GVT-g.\n"); 178 break; 179 case GVT_FAILSAFE_INSUFFICIENT_RESOURCE: 180 pr_err("Graphics resource is not enough for the guest\n"); 181 break; 182 case GVT_FAILSAFE_GUEST_ERR: 183 pr_err("GVT Internal error for the guest\n"); 184 break; 185 default: 186 break; 187 } 188 pr_err("Now vgpu %d will enter failsafe mode.\n", vgpu->id); 189 vgpu->failsafe = true; 190 } 191 192 static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu, 193 unsigned int fence_num, void *p_data, unsigned int bytes) 194 { 195 unsigned int max_fence = vgpu_fence_sz(vgpu); 196 197 if (fence_num >= max_fence) { 198 gvt_vgpu_err("access oob fence reg %d/%d\n", 199 fence_num, max_fence); 200 201 /* When guest access oob fence regs without access 202 * pv_info first, we treat guest not supporting GVT, 203 * and we will let vgpu enter failsafe mode. 204 */ 205 if (!vgpu->pv_notified) 206 enter_failsafe_mode(vgpu, 207 GVT_FAILSAFE_UNSUPPORTED_GUEST); 208 209 memset(p_data, 0, bytes); 210 return -EINVAL; 211 } 212 return 0; 213 } 214 215 static int gamw_echo_dev_rw_ia_write(struct intel_vgpu *vgpu, 216 unsigned int offset, void *p_data, unsigned int bytes) 217 { 218 u32 ips = (*(u32 *)p_data) & GAMW_ECO_ENABLE_64K_IPS_FIELD; 219 220 if (INTEL_GEN(vgpu->gvt->dev_priv) <= 10) { 221 if (ips == GAMW_ECO_ENABLE_64K_IPS_FIELD) 222 gvt_dbg_core("vgpu%d: ips enabled\n", vgpu->id); 223 else if (!ips) 224 gvt_dbg_core("vgpu%d: ips disabled\n", vgpu->id); 225 else { 226 /* All engines must be enabled together for vGPU, 227 * since we don't know which engine the ppgtt will 228 * bind to when shadowing. 229 */ 230 gvt_vgpu_err("Unsupported IPS setting %x, cannot enable 64K gtt.\n", 231 ips); 232 return -EINVAL; 233 } 234 } 235 236 write_vreg(vgpu, offset, p_data, bytes); 237 return 0; 238 } 239 240 static int fence_mmio_read(struct intel_vgpu *vgpu, unsigned int off, 241 void *p_data, unsigned int bytes) 242 { 243 int ret; 244 245 ret = sanitize_fence_mmio_access(vgpu, offset_to_fence_num(off), 246 p_data, bytes); 247 if (ret) 248 return ret; 249 read_vreg(vgpu, off, p_data, bytes); 250 return 0; 251 } 252 253 static int fence_mmio_write(struct intel_vgpu *vgpu, unsigned int off, 254 void *p_data, unsigned int bytes) 255 { 256 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 257 unsigned int fence_num = offset_to_fence_num(off); 258 int ret; 259 260 ret = sanitize_fence_mmio_access(vgpu, fence_num, p_data, bytes); 261 if (ret) 262 return ret; 263 write_vreg(vgpu, off, p_data, bytes); 264 265 mmio_hw_access_pre(dev_priv); 266 intel_vgpu_write_fence(vgpu, fence_num, 267 vgpu_vreg64(vgpu, fence_num_to_offset(fence_num))); 268 mmio_hw_access_post(dev_priv); 269 return 0; 270 } 271 272 #define CALC_MODE_MASK_REG(old, new) \ 273 (((new) & GENMASK(31, 16)) \ 274 | ((((old) & GENMASK(15, 0)) & ~((new) >> 16)) \ 275 | ((new) & ((new) >> 16)))) 276 277 static int mul_force_wake_write(struct intel_vgpu *vgpu, 278 unsigned int offset, void *p_data, unsigned int bytes) 279 { 280 u32 old, new; 281 u32 ack_reg_offset; 282 283 old = vgpu_vreg(vgpu, offset); 284 new = CALC_MODE_MASK_REG(old, *(u32 *)p_data); 285 286 if (INTEL_GEN(vgpu->gvt->dev_priv) >= 9) { 287 switch (offset) { 288 case FORCEWAKE_RENDER_GEN9_REG: 289 ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG; 290 break; 291 case FORCEWAKE_BLITTER_GEN9_REG: 292 ack_reg_offset = FORCEWAKE_ACK_BLITTER_GEN9_REG; 293 break; 294 case FORCEWAKE_MEDIA_GEN9_REG: 295 ack_reg_offset = FORCEWAKE_ACK_MEDIA_GEN9_REG; 296 break; 297 default: 298 /*should not hit here*/ 299 gvt_vgpu_err("invalid forcewake offset 0x%x\n", offset); 300 return -EINVAL; 301 } 302 } else { 303 ack_reg_offset = FORCEWAKE_ACK_HSW_REG; 304 } 305 306 vgpu_vreg(vgpu, offset) = new; 307 vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0)); 308 return 0; 309 } 310 311 static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 312 void *p_data, unsigned int bytes) 313 { 314 intel_engine_mask_t engine_mask = 0; 315 u32 data; 316 317 write_vreg(vgpu, offset, p_data, bytes); 318 data = vgpu_vreg(vgpu, offset); 319 320 if (data & GEN6_GRDOM_FULL) { 321 gvt_dbg_mmio("vgpu%d: request full GPU reset\n", vgpu->id); 322 engine_mask = ALL_ENGINES; 323 } else { 324 if (data & GEN6_GRDOM_RENDER) { 325 gvt_dbg_mmio("vgpu%d: request RCS reset\n", vgpu->id); 326 engine_mask |= BIT(RCS0); 327 } 328 if (data & GEN6_GRDOM_MEDIA) { 329 gvt_dbg_mmio("vgpu%d: request VCS reset\n", vgpu->id); 330 engine_mask |= BIT(VCS0); 331 } 332 if (data & GEN6_GRDOM_BLT) { 333 gvt_dbg_mmio("vgpu%d: request BCS Reset\n", vgpu->id); 334 engine_mask |= BIT(BCS0); 335 } 336 if (data & GEN6_GRDOM_VECS) { 337 gvt_dbg_mmio("vgpu%d: request VECS Reset\n", vgpu->id); 338 engine_mask |= BIT(VECS0); 339 } 340 if (data & GEN8_GRDOM_MEDIA2) { 341 gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id); 342 engine_mask |= BIT(VCS1); 343 } 344 engine_mask &= INTEL_INFO(vgpu->gvt->dev_priv)->engine_mask; 345 } 346 347 /* vgpu_lock already hold by emulate mmio r/w */ 348 intel_gvt_reset_vgpu_locked(vgpu, false, engine_mask); 349 350 /* sw will wait for the device to ack the reset request */ 351 vgpu_vreg(vgpu, offset) = 0; 352 353 return 0; 354 } 355 356 static int gmbus_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 357 void *p_data, unsigned int bytes) 358 { 359 return intel_gvt_i2c_handle_gmbus_read(vgpu, offset, p_data, bytes); 360 } 361 362 static int gmbus_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 363 void *p_data, unsigned int bytes) 364 { 365 return intel_gvt_i2c_handle_gmbus_write(vgpu, offset, p_data, bytes); 366 } 367 368 static int pch_pp_control_mmio_write(struct intel_vgpu *vgpu, 369 unsigned int offset, void *p_data, unsigned int bytes) 370 { 371 write_vreg(vgpu, offset, p_data, bytes); 372 373 if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) { 374 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_ON; 375 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE; 376 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN; 377 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE; 378 379 } else 380 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= 381 ~(PP_ON | PP_SEQUENCE_POWER_DOWN 382 | PP_CYCLE_DELAY_ACTIVE); 383 return 0; 384 } 385 386 static int transconf_mmio_write(struct intel_vgpu *vgpu, 387 unsigned int offset, void *p_data, unsigned int bytes) 388 { 389 write_vreg(vgpu, offset, p_data, bytes); 390 391 if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE) 392 vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE; 393 else 394 vgpu_vreg(vgpu, offset) &= ~TRANS_STATE_ENABLE; 395 return 0; 396 } 397 398 static int lcpll_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 399 void *p_data, unsigned int bytes) 400 { 401 write_vreg(vgpu, offset, p_data, bytes); 402 403 if (vgpu_vreg(vgpu, offset) & LCPLL_PLL_DISABLE) 404 vgpu_vreg(vgpu, offset) &= ~LCPLL_PLL_LOCK; 405 else 406 vgpu_vreg(vgpu, offset) |= LCPLL_PLL_LOCK; 407 408 if (vgpu_vreg(vgpu, offset) & LCPLL_CD_SOURCE_FCLK) 409 vgpu_vreg(vgpu, offset) |= LCPLL_CD_SOURCE_FCLK_DONE; 410 else 411 vgpu_vreg(vgpu, offset) &= ~LCPLL_CD_SOURCE_FCLK_DONE; 412 413 return 0; 414 } 415 416 static int dpy_reg_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 417 void *p_data, unsigned int bytes) 418 { 419 switch (offset) { 420 case 0xe651c: 421 case 0xe661c: 422 case 0xe671c: 423 case 0xe681c: 424 vgpu_vreg(vgpu, offset) = 1 << 17; 425 break; 426 case 0xe6c04: 427 vgpu_vreg(vgpu, offset) = 0x3; 428 break; 429 case 0xe6e1c: 430 vgpu_vreg(vgpu, offset) = 0x2f << 16; 431 break; 432 default: 433 return -EINVAL; 434 } 435 436 read_vreg(vgpu, offset, p_data, bytes); 437 return 0; 438 } 439 440 static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 441 void *p_data, unsigned int bytes) 442 { 443 u32 data; 444 445 write_vreg(vgpu, offset, p_data, bytes); 446 data = vgpu_vreg(vgpu, offset); 447 448 if (data & PIPECONF_ENABLE) 449 vgpu_vreg(vgpu, offset) |= I965_PIPECONF_ACTIVE; 450 else 451 vgpu_vreg(vgpu, offset) &= ~I965_PIPECONF_ACTIVE; 452 /* vgpu_lock already hold by emulate mmio r/w */ 453 mutex_unlock(&vgpu->vgpu_lock); 454 intel_gvt_check_vblank_emulation(vgpu->gvt); 455 mutex_lock(&vgpu->vgpu_lock); 456 return 0; 457 } 458 459 /* ascendingly sorted */ 460 static i915_reg_t force_nonpriv_white_list[] = { 461 GEN9_CS_DEBUG_MODE1, //_MMIO(0x20ec) 462 GEN9_CTX_PREEMPT_REG,//_MMIO(0x2248) 463 PS_INVOCATION_COUNT,//_MMIO(0x2348) 464 GEN8_CS_CHICKEN1,//_MMIO(0x2580) 465 _MMIO(0x2690), 466 _MMIO(0x2694), 467 _MMIO(0x2698), 468 _MMIO(0x2754), 469 _MMIO(0x28a0), 470 _MMIO(0x4de0), 471 _MMIO(0x4de4), 472 _MMIO(0x4dfc), 473 GEN7_COMMON_SLICE_CHICKEN1,//_MMIO(0x7010) 474 _MMIO(0x7014), 475 HDC_CHICKEN0,//_MMIO(0x7300) 476 GEN8_HDC_CHICKEN1,//_MMIO(0x7304) 477 _MMIO(0x7700), 478 _MMIO(0x7704), 479 _MMIO(0x7708), 480 _MMIO(0x770c), 481 _MMIO(0x83a8), 482 _MMIO(0xb110), 483 GEN8_L3SQCREG4,//_MMIO(0xb118) 484 _MMIO(0xe100), 485 _MMIO(0xe18c), 486 _MMIO(0xe48c), 487 _MMIO(0xe5f4), 488 }; 489 490 /* a simple bsearch */ 491 static inline bool in_whitelist(unsigned int reg) 492 { 493 int left = 0, right = ARRAY_SIZE(force_nonpriv_white_list); 494 i915_reg_t *array = force_nonpriv_white_list; 495 496 while (left < right) { 497 int mid = (left + right)/2; 498 499 if (reg > array[mid].reg) 500 left = mid + 1; 501 else if (reg < array[mid].reg) 502 right = mid; 503 else 504 return true; 505 } 506 return false; 507 } 508 509 static int force_nonpriv_write(struct intel_vgpu *vgpu, 510 unsigned int offset, void *p_data, unsigned int bytes) 511 { 512 u32 reg_nonpriv = (*(u32 *)p_data) & REG_GENMASK(25, 2); 513 int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset); 514 u32 ring_base; 515 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 516 int ret = -EINVAL; 517 518 if ((bytes != 4) || ((offset & (bytes - 1)) != 0) || ring_id < 0) { 519 gvt_err("vgpu(%d) ring %d Invalid FORCE_NONPRIV offset %x(%dB)\n", 520 vgpu->id, ring_id, offset, bytes); 521 return ret; 522 } 523 524 ring_base = dev_priv->engine[ring_id]->mmio_base; 525 526 if (in_whitelist(reg_nonpriv) || 527 reg_nonpriv == i915_mmio_reg_offset(RING_NOPID(ring_base))) { 528 ret = intel_vgpu_default_mmio_write(vgpu, offset, p_data, 529 bytes); 530 } else 531 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x at offset %x\n", 532 vgpu->id, *(u32 *)p_data, offset); 533 534 return 0; 535 } 536 537 static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 538 void *p_data, unsigned int bytes) 539 { 540 write_vreg(vgpu, offset, p_data, bytes); 541 542 if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) { 543 vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE; 544 } else { 545 vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE; 546 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E))) 547 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) 548 &= ~DP_TP_STATUS_AUTOTRAIN_DONE; 549 } 550 return 0; 551 } 552 553 static int fdi_rx_iir_mmio_write(struct intel_vgpu *vgpu, 554 unsigned int offset, void *p_data, unsigned int bytes) 555 { 556 vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data; 557 return 0; 558 } 559 560 #define FDI_LINK_TRAIN_PATTERN1 0 561 #define FDI_LINK_TRAIN_PATTERN2 1 562 563 static int fdi_auto_training_started(struct intel_vgpu *vgpu) 564 { 565 u32 ddi_buf_ctl = vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_E)); 566 u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL); 567 u32 tx_ctl = vgpu_vreg_t(vgpu, DP_TP_CTL(PORT_E)); 568 569 if ((ddi_buf_ctl & DDI_BUF_CTL_ENABLE) && 570 (rx_ctl & FDI_RX_ENABLE) && 571 (rx_ctl & FDI_AUTO_TRAINING) && 572 (tx_ctl & DP_TP_CTL_ENABLE) && 573 (tx_ctl & DP_TP_CTL_FDI_AUTOTRAIN)) 574 return 1; 575 else 576 return 0; 577 } 578 579 static int check_fdi_rx_train_status(struct intel_vgpu *vgpu, 580 enum pipe pipe, unsigned int train_pattern) 581 { 582 i915_reg_t fdi_rx_imr, fdi_tx_ctl, fdi_rx_ctl; 583 unsigned int fdi_rx_check_bits, fdi_tx_check_bits; 584 unsigned int fdi_rx_train_bits, fdi_tx_train_bits; 585 unsigned int fdi_iir_check_bits; 586 587 fdi_rx_imr = FDI_RX_IMR(pipe); 588 fdi_tx_ctl = FDI_TX_CTL(pipe); 589 fdi_rx_ctl = FDI_RX_CTL(pipe); 590 591 if (train_pattern == FDI_LINK_TRAIN_PATTERN1) { 592 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_1_CPT; 593 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_1; 594 fdi_iir_check_bits = FDI_RX_BIT_LOCK; 595 } else if (train_pattern == FDI_LINK_TRAIN_PATTERN2) { 596 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_2_CPT; 597 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_2; 598 fdi_iir_check_bits = FDI_RX_SYMBOL_LOCK; 599 } else { 600 gvt_vgpu_err("Invalid train pattern %d\n", train_pattern); 601 return -EINVAL; 602 } 603 604 fdi_rx_check_bits = FDI_RX_ENABLE | fdi_rx_train_bits; 605 fdi_tx_check_bits = FDI_TX_ENABLE | fdi_tx_train_bits; 606 607 /* If imr bit has been masked */ 608 if (vgpu_vreg_t(vgpu, fdi_rx_imr) & fdi_iir_check_bits) 609 return 0; 610 611 if (((vgpu_vreg_t(vgpu, fdi_tx_ctl) & fdi_tx_check_bits) 612 == fdi_tx_check_bits) 613 && ((vgpu_vreg_t(vgpu, fdi_rx_ctl) & fdi_rx_check_bits) 614 == fdi_rx_check_bits)) 615 return 1; 616 else 617 return 0; 618 } 619 620 #define INVALID_INDEX (~0U) 621 622 static unsigned int calc_index(unsigned int offset, unsigned int start, 623 unsigned int next, unsigned int end, i915_reg_t i915_end) 624 { 625 unsigned int range = next - start; 626 627 if (!end) 628 end = i915_mmio_reg_offset(i915_end); 629 if (offset < start || offset > end) 630 return INVALID_INDEX; 631 offset -= start; 632 return offset / range; 633 } 634 635 #define FDI_RX_CTL_TO_PIPE(offset) \ 636 calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, 0, FDI_RX_CTL(PIPE_C)) 637 638 #define FDI_TX_CTL_TO_PIPE(offset) \ 639 calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, 0, FDI_TX_CTL(PIPE_C)) 640 641 #define FDI_RX_IMR_TO_PIPE(offset) \ 642 calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, 0, FDI_RX_IMR(PIPE_C)) 643 644 static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu, 645 unsigned int offset, void *p_data, unsigned int bytes) 646 { 647 i915_reg_t fdi_rx_iir; 648 unsigned int index; 649 int ret; 650 651 if (FDI_RX_CTL_TO_PIPE(offset) != INVALID_INDEX) 652 index = FDI_RX_CTL_TO_PIPE(offset); 653 else if (FDI_TX_CTL_TO_PIPE(offset) != INVALID_INDEX) 654 index = FDI_TX_CTL_TO_PIPE(offset); 655 else if (FDI_RX_IMR_TO_PIPE(offset) != INVALID_INDEX) 656 index = FDI_RX_IMR_TO_PIPE(offset); 657 else { 658 gvt_vgpu_err("Unsupport registers %x\n", offset); 659 return -EINVAL; 660 } 661 662 write_vreg(vgpu, offset, p_data, bytes); 663 664 fdi_rx_iir = FDI_RX_IIR(index); 665 666 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN1); 667 if (ret < 0) 668 return ret; 669 if (ret) 670 vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK; 671 672 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN2); 673 if (ret < 0) 674 return ret; 675 if (ret) 676 vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK; 677 678 if (offset == _FDI_RXA_CTL) 679 if (fdi_auto_training_started(vgpu)) 680 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) |= 681 DP_TP_STATUS_AUTOTRAIN_DONE; 682 return 0; 683 } 684 685 #define DP_TP_CTL_TO_PORT(offset) \ 686 calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, 0, DP_TP_CTL(PORT_E)) 687 688 static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 689 void *p_data, unsigned int bytes) 690 { 691 i915_reg_t status_reg; 692 unsigned int index; 693 u32 data; 694 695 write_vreg(vgpu, offset, p_data, bytes); 696 697 index = DP_TP_CTL_TO_PORT(offset); 698 data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8; 699 if (data == 0x2) { 700 status_reg = DP_TP_STATUS(index); 701 vgpu_vreg_t(vgpu, status_reg) |= (1 << 25); 702 } 703 return 0; 704 } 705 706 static int dp_tp_status_mmio_write(struct intel_vgpu *vgpu, 707 unsigned int offset, void *p_data, unsigned int bytes) 708 { 709 u32 reg_val; 710 u32 sticky_mask; 711 712 reg_val = *((u32 *)p_data); 713 sticky_mask = GENMASK(27, 26) | (1 << 24); 714 715 vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) | 716 (vgpu_vreg(vgpu, offset) & sticky_mask); 717 vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask); 718 return 0; 719 } 720 721 static int pch_adpa_mmio_write(struct intel_vgpu *vgpu, 722 unsigned int offset, void *p_data, unsigned int bytes) 723 { 724 u32 data; 725 726 write_vreg(vgpu, offset, p_data, bytes); 727 data = vgpu_vreg(vgpu, offset); 728 729 if (data & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) 730 vgpu_vreg(vgpu, offset) &= ~ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 731 return 0; 732 } 733 734 static int south_chicken2_mmio_write(struct intel_vgpu *vgpu, 735 unsigned int offset, void *p_data, unsigned int bytes) 736 { 737 u32 data; 738 739 write_vreg(vgpu, offset, p_data, bytes); 740 data = vgpu_vreg(vgpu, offset); 741 742 if (data & FDI_MPHY_IOSFSB_RESET_CTL) 743 vgpu_vreg(vgpu, offset) |= FDI_MPHY_IOSFSB_RESET_STATUS; 744 else 745 vgpu_vreg(vgpu, offset) &= ~FDI_MPHY_IOSFSB_RESET_STATUS; 746 return 0; 747 } 748 749 #define DSPSURF_TO_PIPE(offset) \ 750 calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C)) 751 752 static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 753 void *p_data, unsigned int bytes) 754 { 755 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 756 u32 pipe = DSPSURF_TO_PIPE(offset); 757 int event = SKL_FLIP_EVENT(pipe, PLANE_PRIMARY); 758 759 write_vreg(vgpu, offset, p_data, bytes); 760 vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); 761 762 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++; 763 764 if (vgpu_vreg_t(vgpu, DSPCNTR(pipe)) & PLANE_CTL_ASYNC_FLIP) 765 intel_vgpu_trigger_virtual_event(vgpu, event); 766 else 767 set_bit(event, vgpu->irq.flip_done_event[pipe]); 768 769 return 0; 770 } 771 772 #define SPRSURF_TO_PIPE(offset) \ 773 calc_index(offset, _SPRA_SURF, _SPRB_SURF, 0, SPRSURF(PIPE_C)) 774 775 static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 776 void *p_data, unsigned int bytes) 777 { 778 u32 pipe = SPRSURF_TO_PIPE(offset); 779 int event = SKL_FLIP_EVENT(pipe, PLANE_SPRITE0); 780 781 write_vreg(vgpu, offset, p_data, bytes); 782 vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); 783 784 if (vgpu_vreg_t(vgpu, SPRCTL(pipe)) & PLANE_CTL_ASYNC_FLIP) 785 intel_vgpu_trigger_virtual_event(vgpu, event); 786 else 787 set_bit(event, vgpu->irq.flip_done_event[pipe]); 788 789 return 0; 790 } 791 792 static int reg50080_mmio_write(struct intel_vgpu *vgpu, 793 unsigned int offset, void *p_data, 794 unsigned int bytes) 795 { 796 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 797 enum pipe pipe = REG_50080_TO_PIPE(offset); 798 enum plane_id plane = REG_50080_TO_PLANE(offset); 799 int event = SKL_FLIP_EVENT(pipe, plane); 800 801 write_vreg(vgpu, offset, p_data, bytes); 802 if (plane == PLANE_PRIMARY) { 803 vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); 804 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++; 805 } else { 806 vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); 807 } 808 809 if ((vgpu_vreg(vgpu, offset) & REG50080_FLIP_TYPE_MASK) == REG50080_FLIP_TYPE_ASYNC) 810 intel_vgpu_trigger_virtual_event(vgpu, event); 811 else 812 set_bit(event, vgpu->irq.flip_done_event[pipe]); 813 814 return 0; 815 } 816 817 static int trigger_aux_channel_interrupt(struct intel_vgpu *vgpu, 818 unsigned int reg) 819 { 820 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 821 enum intel_gvt_event_type event; 822 823 if (reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_A))) 824 event = AUX_CHANNEL_A; 825 else if (reg == _PCH_DPB_AUX_CH_CTL || 826 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_B))) 827 event = AUX_CHANNEL_B; 828 else if (reg == _PCH_DPC_AUX_CH_CTL || 829 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_C))) 830 event = AUX_CHANNEL_C; 831 else if (reg == _PCH_DPD_AUX_CH_CTL || 832 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_D))) 833 event = AUX_CHANNEL_D; 834 else { 835 WARN_ON(true); 836 return -EINVAL; 837 } 838 839 intel_vgpu_trigger_virtual_event(vgpu, event); 840 return 0; 841 } 842 843 static int dp_aux_ch_ctl_trans_done(struct intel_vgpu *vgpu, u32 value, 844 unsigned int reg, int len, bool data_valid) 845 { 846 /* mark transaction done */ 847 value |= DP_AUX_CH_CTL_DONE; 848 value &= ~DP_AUX_CH_CTL_SEND_BUSY; 849 value &= ~DP_AUX_CH_CTL_RECEIVE_ERROR; 850 851 if (data_valid) 852 value &= ~DP_AUX_CH_CTL_TIME_OUT_ERROR; 853 else 854 value |= DP_AUX_CH_CTL_TIME_OUT_ERROR; 855 856 /* message size */ 857 value &= ~(0xf << 20); 858 value |= (len << 20); 859 vgpu_vreg(vgpu, reg) = value; 860 861 if (value & DP_AUX_CH_CTL_INTERRUPT) 862 return trigger_aux_channel_interrupt(vgpu, reg); 863 return 0; 864 } 865 866 static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd, 867 u8 t) 868 { 869 if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == DPCD_TRAINING_PATTERN_1) { 870 /* training pattern 1 for CR */ 871 /* set LANE0_CR_DONE, LANE1_CR_DONE */ 872 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_CR_DONE; 873 /* set LANE2_CR_DONE, LANE3_CR_DONE */ 874 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_CR_DONE; 875 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == 876 DPCD_TRAINING_PATTERN_2) { 877 /* training pattern 2 for EQ */ 878 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane0_1 */ 879 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_EQ_DONE; 880 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_SYMBOL_LOCKED; 881 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane2_3 */ 882 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_EQ_DONE; 883 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_SYMBOL_LOCKED; 884 /* set INTERLANE_ALIGN_DONE */ 885 dpcd->data[DPCD_LANE_ALIGN_STATUS_UPDATED] |= 886 DPCD_INTERLANE_ALIGN_DONE; 887 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == 888 DPCD_LINK_TRAINING_DISABLED) { 889 /* finish link training */ 890 /* set sink status as synchronized */ 891 dpcd->data[DPCD_SINK_STATUS] = DPCD_SINK_IN_SYNC; 892 } 893 } 894 895 #define _REG_HSW_DP_AUX_CH_CTL(dp) \ 896 ((dp) ? (_PCH_DPB_AUX_CH_CTL + ((dp)-1)*0x100) : 0x64010) 897 898 #define _REG_SKL_DP_AUX_CH_CTL(dp) (0x64010 + (dp) * 0x100) 899 900 #define OFFSET_TO_DP_AUX_PORT(offset) (((offset) & 0xF00) >> 8) 901 902 #define dpy_is_valid_port(port) \ 903 (((port) >= PORT_A) && ((port) < I915_MAX_PORTS)) 904 905 static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu, 906 unsigned int offset, void *p_data, unsigned int bytes) 907 { 908 struct intel_vgpu_display *display = &vgpu->display; 909 int msg, addr, ctrl, op, len; 910 int port_index = OFFSET_TO_DP_AUX_PORT(offset); 911 struct intel_vgpu_dpcd_data *dpcd = NULL; 912 struct intel_vgpu_port *port = NULL; 913 u32 data; 914 915 if (!dpy_is_valid_port(port_index)) { 916 gvt_vgpu_err("Unsupported DP port access!\n"); 917 return 0; 918 } 919 920 write_vreg(vgpu, offset, p_data, bytes); 921 data = vgpu_vreg(vgpu, offset); 922 923 if ((INTEL_GEN(vgpu->gvt->dev_priv) >= 9) 924 && offset != _REG_SKL_DP_AUX_CH_CTL(port_index)) { 925 /* SKL DPB/C/D aux ctl register changed */ 926 return 0; 927 } else if (IS_BROADWELL(vgpu->gvt->dev_priv) && 928 offset != _REG_HSW_DP_AUX_CH_CTL(port_index)) { 929 /* write to the data registers */ 930 return 0; 931 } 932 933 if (!(data & DP_AUX_CH_CTL_SEND_BUSY)) { 934 /* just want to clear the sticky bits */ 935 vgpu_vreg(vgpu, offset) = 0; 936 return 0; 937 } 938 939 port = &display->ports[port_index]; 940 dpcd = port->dpcd; 941 942 /* read out message from DATA1 register */ 943 msg = vgpu_vreg(vgpu, offset + 4); 944 addr = (msg >> 8) & 0xffff; 945 ctrl = (msg >> 24) & 0xff; 946 len = msg & 0xff; 947 op = ctrl >> 4; 948 949 if (op == GVT_AUX_NATIVE_WRITE) { 950 int t; 951 u8 buf[16]; 952 953 if ((addr + len + 1) >= DPCD_SIZE) { 954 /* 955 * Write request exceeds what we supported, 956 * DCPD spec: When a Source Device is writing a DPCD 957 * address not supported by the Sink Device, the Sink 958 * Device shall reply with AUX NACK and “M” equal to 959 * zero. 960 */ 961 962 /* NAK the write */ 963 vgpu_vreg(vgpu, offset + 4) = AUX_NATIVE_REPLY_NAK; 964 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 2, true); 965 return 0; 966 } 967 968 /* 969 * Write request format: Headr (command + address + size) occupies 970 * 4 bytes, followed by (len + 1) bytes of data. See details at 971 * intel_dp_aux_transfer(). 972 */ 973 if ((len + 1 + 4) > AUX_BURST_SIZE) { 974 gvt_vgpu_err("dp_aux_header: len %d is too large\n", len); 975 return -EINVAL; 976 } 977 978 /* unpack data from vreg to buf */ 979 for (t = 0; t < 4; t++) { 980 u32 r = vgpu_vreg(vgpu, offset + 8 + t * 4); 981 982 buf[t * 4] = (r >> 24) & 0xff; 983 buf[t * 4 + 1] = (r >> 16) & 0xff; 984 buf[t * 4 + 2] = (r >> 8) & 0xff; 985 buf[t * 4 + 3] = r & 0xff; 986 } 987 988 /* write to virtual DPCD */ 989 if (dpcd && dpcd->data_valid) { 990 for (t = 0; t <= len; t++) { 991 int p = addr + t; 992 993 dpcd->data[p] = buf[t]; 994 /* check for link training */ 995 if (p == DPCD_TRAINING_PATTERN_SET) 996 dp_aux_ch_ctl_link_training(dpcd, 997 buf[t]); 998 } 999 } 1000 1001 /* ACK the write */ 1002 vgpu_vreg(vgpu, offset + 4) = 0; 1003 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 1, 1004 dpcd && dpcd->data_valid); 1005 return 0; 1006 } 1007 1008 if (op == GVT_AUX_NATIVE_READ) { 1009 int idx, i, ret = 0; 1010 1011 if ((addr + len + 1) >= DPCD_SIZE) { 1012 /* 1013 * read request exceeds what we supported 1014 * DPCD spec: A Sink Device receiving a Native AUX CH 1015 * read request for an unsupported DPCD address must 1016 * reply with an AUX ACK and read data set equal to 1017 * zero instead of replying with AUX NACK. 1018 */ 1019 1020 /* ACK the READ*/ 1021 vgpu_vreg(vgpu, offset + 4) = 0; 1022 vgpu_vreg(vgpu, offset + 8) = 0; 1023 vgpu_vreg(vgpu, offset + 12) = 0; 1024 vgpu_vreg(vgpu, offset + 16) = 0; 1025 vgpu_vreg(vgpu, offset + 20) = 0; 1026 1027 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2, 1028 true); 1029 return 0; 1030 } 1031 1032 for (idx = 1; idx <= 5; idx++) { 1033 /* clear the data registers */ 1034 vgpu_vreg(vgpu, offset + 4 * idx) = 0; 1035 } 1036 1037 /* 1038 * Read reply format: ACK (1 byte) plus (len + 1) bytes of data. 1039 */ 1040 if ((len + 2) > AUX_BURST_SIZE) { 1041 gvt_vgpu_err("dp_aux_header: len %d is too large\n", len); 1042 return -EINVAL; 1043 } 1044 1045 /* read from virtual DPCD to vreg */ 1046 /* first 4 bytes: [ACK][addr][addr+1][addr+2] */ 1047 if (dpcd && dpcd->data_valid) { 1048 for (i = 1; i <= (len + 1); i++) { 1049 int t; 1050 1051 t = dpcd->data[addr + i - 1]; 1052 t <<= (24 - 8 * (i % 4)); 1053 ret |= t; 1054 1055 if ((i % 4 == 3) || (i == (len + 1))) { 1056 vgpu_vreg(vgpu, offset + 1057 (i / 4 + 1) * 4) = ret; 1058 ret = 0; 1059 } 1060 } 1061 } 1062 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2, 1063 dpcd && dpcd->data_valid); 1064 return 0; 1065 } 1066 1067 /* i2c transaction starts */ 1068 intel_gvt_i2c_handle_aux_ch_write(vgpu, port_index, offset, p_data); 1069 1070 if (data & DP_AUX_CH_CTL_INTERRUPT) 1071 trigger_aux_channel_interrupt(vgpu, offset); 1072 return 0; 1073 } 1074 1075 static int mbctl_write(struct intel_vgpu *vgpu, unsigned int offset, 1076 void *p_data, unsigned int bytes) 1077 { 1078 *(u32 *)p_data &= (~GEN6_MBCTL_ENABLE_BOOT_FETCH); 1079 write_vreg(vgpu, offset, p_data, bytes); 1080 return 0; 1081 } 1082 1083 static int vga_control_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1084 void *p_data, unsigned int bytes) 1085 { 1086 bool vga_disable; 1087 1088 write_vreg(vgpu, offset, p_data, bytes); 1089 vga_disable = vgpu_vreg(vgpu, offset) & VGA_DISP_DISABLE; 1090 1091 gvt_dbg_core("vgpu%d: %s VGA mode\n", vgpu->id, 1092 vga_disable ? "Disable" : "Enable"); 1093 return 0; 1094 } 1095 1096 static u32 read_virtual_sbi_register(struct intel_vgpu *vgpu, 1097 unsigned int sbi_offset) 1098 { 1099 struct intel_vgpu_display *display = &vgpu->display; 1100 int num = display->sbi.number; 1101 int i; 1102 1103 for (i = 0; i < num; ++i) 1104 if (display->sbi.registers[i].offset == sbi_offset) 1105 break; 1106 1107 if (i == num) 1108 return 0; 1109 1110 return display->sbi.registers[i].value; 1111 } 1112 1113 static void write_virtual_sbi_register(struct intel_vgpu *vgpu, 1114 unsigned int offset, u32 value) 1115 { 1116 struct intel_vgpu_display *display = &vgpu->display; 1117 int num = display->sbi.number; 1118 int i; 1119 1120 for (i = 0; i < num; ++i) { 1121 if (display->sbi.registers[i].offset == offset) 1122 break; 1123 } 1124 1125 if (i == num) { 1126 if (num == SBI_REG_MAX) { 1127 gvt_vgpu_err("SBI caching meets maximum limits\n"); 1128 return; 1129 } 1130 display->sbi.number++; 1131 } 1132 1133 display->sbi.registers[i].offset = offset; 1134 display->sbi.registers[i].value = value; 1135 } 1136 1137 static int sbi_data_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 1138 void *p_data, unsigned int bytes) 1139 { 1140 if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> 1141 SBI_OPCODE_SHIFT) == SBI_CMD_CRRD) { 1142 unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) & 1143 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; 1144 vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu, 1145 sbi_offset); 1146 } 1147 read_vreg(vgpu, offset, p_data, bytes); 1148 return 0; 1149 } 1150 1151 static int sbi_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1152 void *p_data, unsigned int bytes) 1153 { 1154 u32 data; 1155 1156 write_vreg(vgpu, offset, p_data, bytes); 1157 data = vgpu_vreg(vgpu, offset); 1158 1159 data &= ~(SBI_STAT_MASK << SBI_STAT_SHIFT); 1160 data |= SBI_READY; 1161 1162 data &= ~(SBI_RESPONSE_MASK << SBI_RESPONSE_SHIFT); 1163 data |= SBI_RESPONSE_SUCCESS; 1164 1165 vgpu_vreg(vgpu, offset) = data; 1166 1167 if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> 1168 SBI_OPCODE_SHIFT) == SBI_CMD_CRWR) { 1169 unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) & 1170 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; 1171 1172 write_virtual_sbi_register(vgpu, sbi_offset, 1173 vgpu_vreg_t(vgpu, SBI_DATA)); 1174 } 1175 return 0; 1176 } 1177 1178 #define _vgtif_reg(x) \ 1179 (VGT_PVINFO_PAGE + offsetof(struct vgt_if, x)) 1180 1181 static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 1182 void *p_data, unsigned int bytes) 1183 { 1184 bool invalid_read = false; 1185 1186 read_vreg(vgpu, offset, p_data, bytes); 1187 1188 switch (offset) { 1189 case _vgtif_reg(magic) ... _vgtif_reg(vgt_id): 1190 if (offset + bytes > _vgtif_reg(vgt_id) + 4) 1191 invalid_read = true; 1192 break; 1193 case _vgtif_reg(avail_rs.mappable_gmadr.base) ... 1194 _vgtif_reg(avail_rs.fence_num): 1195 if (offset + bytes > 1196 _vgtif_reg(avail_rs.fence_num) + 4) 1197 invalid_read = true; 1198 break; 1199 case 0x78010: /* vgt_caps */ 1200 case 0x7881c: 1201 break; 1202 default: 1203 invalid_read = true; 1204 break; 1205 } 1206 if (invalid_read) 1207 gvt_vgpu_err("invalid pvinfo read: [%x:%x] = %x\n", 1208 offset, bytes, *(u32 *)p_data); 1209 vgpu->pv_notified = true; 1210 return 0; 1211 } 1212 1213 static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification) 1214 { 1215 enum intel_gvt_gtt_type root_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY; 1216 struct intel_vgpu_mm *mm; 1217 u64 *pdps; 1218 1219 pdps = (u64 *)&vgpu_vreg64_t(vgpu, vgtif_reg(pdp[0])); 1220 1221 switch (notification) { 1222 case VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE: 1223 root_entry_type = GTT_TYPE_PPGTT_ROOT_L3_ENTRY; 1224 /* fall through */ 1225 case VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE: 1226 mm = intel_vgpu_get_ppgtt_mm(vgpu, root_entry_type, pdps); 1227 return PTR_ERR_OR_ZERO(mm); 1228 case VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY: 1229 case VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY: 1230 return intel_vgpu_put_ppgtt_mm(vgpu, pdps); 1231 case VGT_G2V_EXECLIST_CONTEXT_CREATE: 1232 case VGT_G2V_EXECLIST_CONTEXT_DESTROY: 1233 case 1: /* Remove this in guest driver. */ 1234 break; 1235 default: 1236 gvt_vgpu_err("Invalid PV notification %d\n", notification); 1237 } 1238 return 0; 1239 } 1240 1241 static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready) 1242 { 1243 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1244 struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj; 1245 char *env[3] = {NULL, NULL, NULL}; 1246 char vmid_str[20]; 1247 char display_ready_str[20]; 1248 1249 snprintf(display_ready_str, 20, "GVT_DISPLAY_READY=%d", ready); 1250 env[0] = display_ready_str; 1251 1252 snprintf(vmid_str, 20, "VMID=%d", vgpu->id); 1253 env[1] = vmid_str; 1254 1255 return kobject_uevent_env(kobj, KOBJ_ADD, env); 1256 } 1257 1258 static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1259 void *p_data, unsigned int bytes) 1260 { 1261 u32 data = *(u32 *)p_data; 1262 bool invalid_write = false; 1263 1264 switch (offset) { 1265 case _vgtif_reg(display_ready): 1266 send_display_ready_uevent(vgpu, data ? 1 : 0); 1267 break; 1268 case _vgtif_reg(g2v_notify): 1269 handle_g2v_notification(vgpu, data); 1270 break; 1271 /* add xhot and yhot to handled list to avoid error log */ 1272 case _vgtif_reg(cursor_x_hot): 1273 case _vgtif_reg(cursor_y_hot): 1274 case _vgtif_reg(pdp[0].lo): 1275 case _vgtif_reg(pdp[0].hi): 1276 case _vgtif_reg(pdp[1].lo): 1277 case _vgtif_reg(pdp[1].hi): 1278 case _vgtif_reg(pdp[2].lo): 1279 case _vgtif_reg(pdp[2].hi): 1280 case _vgtif_reg(pdp[3].lo): 1281 case _vgtif_reg(pdp[3].hi): 1282 case _vgtif_reg(execlist_context_descriptor_lo): 1283 case _vgtif_reg(execlist_context_descriptor_hi): 1284 break; 1285 case _vgtif_reg(rsv5[0])..._vgtif_reg(rsv5[3]): 1286 invalid_write = true; 1287 enter_failsafe_mode(vgpu, GVT_FAILSAFE_INSUFFICIENT_RESOURCE); 1288 break; 1289 default: 1290 invalid_write = true; 1291 gvt_vgpu_err("invalid pvinfo write offset %x bytes %x data %x\n", 1292 offset, bytes, data); 1293 break; 1294 } 1295 1296 if (!invalid_write) 1297 write_vreg(vgpu, offset, p_data, bytes); 1298 1299 return 0; 1300 } 1301 1302 static int pf_write(struct intel_vgpu *vgpu, 1303 unsigned int offset, void *p_data, unsigned int bytes) 1304 { 1305 u32 val = *(u32 *)p_data; 1306 1307 if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL || 1308 offset == _PS_1B_CTRL || offset == _PS_2B_CTRL || 1309 offset == _PS_1C_CTRL) && (val & PS_PLANE_SEL_MASK) != 0) { 1310 WARN_ONCE(true, "VM(%d): guest is trying to scaling a plane\n", 1311 vgpu->id); 1312 return 0; 1313 } 1314 1315 return intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes); 1316 } 1317 1318 static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu, 1319 unsigned int offset, void *p_data, unsigned int bytes) 1320 { 1321 write_vreg(vgpu, offset, p_data, bytes); 1322 1323 if (vgpu_vreg(vgpu, offset) & 1324 HSW_PWR_WELL_CTL_REQ(HSW_PW_CTL_IDX_GLOBAL)) 1325 vgpu_vreg(vgpu, offset) |= 1326 HSW_PWR_WELL_CTL_STATE(HSW_PW_CTL_IDX_GLOBAL); 1327 else 1328 vgpu_vreg(vgpu, offset) &= 1329 ~HSW_PWR_WELL_CTL_STATE(HSW_PW_CTL_IDX_GLOBAL); 1330 return 0; 1331 } 1332 1333 static int gen9_dbuf_ctl_mmio_write(struct intel_vgpu *vgpu, 1334 unsigned int offset, void *p_data, unsigned int bytes) 1335 { 1336 write_vreg(vgpu, offset, p_data, bytes); 1337 1338 if (vgpu_vreg(vgpu, offset) & DBUF_POWER_REQUEST) 1339 vgpu_vreg(vgpu, offset) |= DBUF_POWER_STATE; 1340 else 1341 vgpu_vreg(vgpu, offset) &= ~DBUF_POWER_STATE; 1342 1343 return 0; 1344 } 1345 1346 static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu, 1347 unsigned int offset, void *p_data, unsigned int bytes) 1348 { 1349 write_vreg(vgpu, offset, p_data, bytes); 1350 1351 if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM) 1352 vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM; 1353 return 0; 1354 } 1355 1356 static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset, 1357 void *p_data, unsigned int bytes) 1358 { 1359 u32 mode; 1360 1361 write_vreg(vgpu, offset, p_data, bytes); 1362 mode = vgpu_vreg(vgpu, offset); 1363 1364 if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) { 1365 WARN_ONCE(1, "VM(%d): iGVT-g doesn't support GuC\n", 1366 vgpu->id); 1367 return 0; 1368 } 1369 1370 return 0; 1371 } 1372 1373 static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset, 1374 void *p_data, unsigned int bytes) 1375 { 1376 u32 trtte = *(u32 *)p_data; 1377 1378 if ((trtte & 1) && (trtte & (1 << 1)) == 0) { 1379 WARN(1, "VM(%d): Use physical address for TRTT!\n", 1380 vgpu->id); 1381 return -EINVAL; 1382 } 1383 write_vreg(vgpu, offset, p_data, bytes); 1384 1385 return 0; 1386 } 1387 1388 static int gen9_trtt_chicken_write(struct intel_vgpu *vgpu, unsigned int offset, 1389 void *p_data, unsigned int bytes) 1390 { 1391 write_vreg(vgpu, offset, p_data, bytes); 1392 return 0; 1393 } 1394 1395 static int dpll_status_read(struct intel_vgpu *vgpu, unsigned int offset, 1396 void *p_data, unsigned int bytes) 1397 { 1398 u32 v = 0; 1399 1400 if (vgpu_vreg(vgpu, 0x46010) & (1 << 31)) 1401 v |= (1 << 0); 1402 1403 if (vgpu_vreg(vgpu, 0x46014) & (1 << 31)) 1404 v |= (1 << 8); 1405 1406 if (vgpu_vreg(vgpu, 0x46040) & (1 << 31)) 1407 v |= (1 << 16); 1408 1409 if (vgpu_vreg(vgpu, 0x46060) & (1 << 31)) 1410 v |= (1 << 24); 1411 1412 vgpu_vreg(vgpu, offset) = v; 1413 1414 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1415 } 1416 1417 static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset, 1418 void *p_data, unsigned int bytes) 1419 { 1420 u32 value = *(u32 *)p_data; 1421 u32 cmd = value & 0xff; 1422 u32 *data0 = &vgpu_vreg_t(vgpu, GEN6_PCODE_DATA); 1423 1424 switch (cmd) { 1425 case GEN9_PCODE_READ_MEM_LATENCY: 1426 if (IS_SKYLAKE(vgpu->gvt->dev_priv) 1427 || IS_KABYLAKE(vgpu->gvt->dev_priv) 1428 || IS_COFFEELAKE(vgpu->gvt->dev_priv)) { 1429 /** 1430 * "Read memory latency" command on gen9. 1431 * Below memory latency values are read 1432 * from skylake platform. 1433 */ 1434 if (!*data0) 1435 *data0 = 0x1e1a1100; 1436 else 1437 *data0 = 0x61514b3d; 1438 } else if (IS_BROXTON(vgpu->gvt->dev_priv)) { 1439 /** 1440 * "Read memory latency" command on gen9. 1441 * Below memory latency values are read 1442 * from Broxton MRB. 1443 */ 1444 if (!*data0) 1445 *data0 = 0x16080707; 1446 else 1447 *data0 = 0x16161616; 1448 } 1449 break; 1450 case SKL_PCODE_CDCLK_CONTROL: 1451 if (IS_SKYLAKE(vgpu->gvt->dev_priv) 1452 || IS_KABYLAKE(vgpu->gvt->dev_priv) 1453 || IS_COFFEELAKE(vgpu->gvt->dev_priv)) 1454 *data0 = SKL_CDCLK_READY_FOR_CHANGE; 1455 break; 1456 case GEN6_PCODE_READ_RC6VIDS: 1457 *data0 |= 0x1; 1458 break; 1459 } 1460 1461 gvt_dbg_core("VM(%d) write %x to mailbox, return data0 %x\n", 1462 vgpu->id, value, *data0); 1463 /** 1464 * PCODE_READY clear means ready for pcode read/write, 1465 * PCODE_ERROR_MASK clear means no error happened. In GVT-g we 1466 * always emulate as pcode read/write success and ready for access 1467 * anytime, since we don't touch real physical registers here. 1468 */ 1469 value &= ~(GEN6_PCODE_READY | GEN6_PCODE_ERROR_MASK); 1470 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes); 1471 } 1472 1473 static int hws_pga_write(struct intel_vgpu *vgpu, unsigned int offset, 1474 void *p_data, unsigned int bytes) 1475 { 1476 u32 value = *(u32 *)p_data; 1477 int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset); 1478 1479 if (!intel_gvt_ggtt_validate_range(vgpu, value, I915_GTT_PAGE_SIZE)) { 1480 gvt_vgpu_err("write invalid HWSP address, reg:0x%x, value:0x%x\n", 1481 offset, value); 1482 return -EINVAL; 1483 } 1484 /* 1485 * Need to emulate all the HWSP register write to ensure host can 1486 * update the VM CSB status correctly. Here listed registers can 1487 * support BDW, SKL or other platforms with same HWSP registers. 1488 */ 1489 if (unlikely(ring_id < 0 || ring_id >= I915_NUM_ENGINES)) { 1490 gvt_vgpu_err("access unknown hardware status page register:0x%x\n", 1491 offset); 1492 return -EINVAL; 1493 } 1494 vgpu->hws_pga[ring_id] = value; 1495 gvt_dbg_mmio("VM(%d) write: 0x%x to HWSP: 0x%x\n", 1496 vgpu->id, value, offset); 1497 1498 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes); 1499 } 1500 1501 static int skl_power_well_ctl_write(struct intel_vgpu *vgpu, 1502 unsigned int offset, void *p_data, unsigned int bytes) 1503 { 1504 u32 v = *(u32 *)p_data; 1505 1506 if (IS_BROXTON(vgpu->gvt->dev_priv)) 1507 v &= (1 << 31) | (1 << 29); 1508 else 1509 v &= (1 << 31) | (1 << 29) | (1 << 9) | 1510 (1 << 7) | (1 << 5) | (1 << 3) | (1 << 1); 1511 v |= (v >> 1); 1512 1513 return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes); 1514 } 1515 1516 static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset, 1517 void *p_data, unsigned int bytes) 1518 { 1519 u32 v = *(u32 *)p_data; 1520 1521 /* other bits are MBZ. */ 1522 v &= (1 << 31) | (1 << 30); 1523 v & (1 << 31) ? (v |= (1 << 30)) : (v &= ~(1 << 30)); 1524 1525 vgpu_vreg(vgpu, offset) = v; 1526 1527 return 0; 1528 } 1529 1530 static int bxt_de_pll_enable_write(struct intel_vgpu *vgpu, 1531 unsigned int offset, void *p_data, unsigned int bytes) 1532 { 1533 u32 v = *(u32 *)p_data; 1534 1535 if (v & BXT_DE_PLL_PLL_ENABLE) 1536 v |= BXT_DE_PLL_LOCK; 1537 1538 vgpu_vreg(vgpu, offset) = v; 1539 1540 return 0; 1541 } 1542 1543 static int bxt_port_pll_enable_write(struct intel_vgpu *vgpu, 1544 unsigned int offset, void *p_data, unsigned int bytes) 1545 { 1546 u32 v = *(u32 *)p_data; 1547 1548 if (v & PORT_PLL_ENABLE) 1549 v |= PORT_PLL_LOCK; 1550 1551 vgpu_vreg(vgpu, offset) = v; 1552 1553 return 0; 1554 } 1555 1556 static int bxt_phy_ctl_family_write(struct intel_vgpu *vgpu, 1557 unsigned int offset, void *p_data, unsigned int bytes) 1558 { 1559 u32 v = *(u32 *)p_data; 1560 u32 data = v & COMMON_RESET_DIS ? BXT_PHY_LANE_ENABLED : 0; 1561 1562 switch (offset) { 1563 case _PHY_CTL_FAMILY_EDP: 1564 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_A) = data; 1565 break; 1566 case _PHY_CTL_FAMILY_DDI: 1567 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_B) = data; 1568 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_C) = data; 1569 break; 1570 } 1571 1572 vgpu_vreg(vgpu, offset) = v; 1573 1574 return 0; 1575 } 1576 1577 static int bxt_port_tx_dw3_read(struct intel_vgpu *vgpu, 1578 unsigned int offset, void *p_data, unsigned int bytes) 1579 { 1580 u32 v = vgpu_vreg(vgpu, offset); 1581 1582 v &= ~UNIQUE_TRANGE_EN_METHOD; 1583 1584 vgpu_vreg(vgpu, offset) = v; 1585 1586 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1587 } 1588 1589 static int bxt_pcs_dw12_grp_write(struct intel_vgpu *vgpu, 1590 unsigned int offset, void *p_data, unsigned int bytes) 1591 { 1592 u32 v = *(u32 *)p_data; 1593 1594 if (offset == _PORT_PCS_DW12_GRP_A || offset == _PORT_PCS_DW12_GRP_B) { 1595 vgpu_vreg(vgpu, offset - 0x600) = v; 1596 vgpu_vreg(vgpu, offset - 0x800) = v; 1597 } else { 1598 vgpu_vreg(vgpu, offset - 0x400) = v; 1599 vgpu_vreg(vgpu, offset - 0x600) = v; 1600 } 1601 1602 vgpu_vreg(vgpu, offset) = v; 1603 1604 return 0; 1605 } 1606 1607 static int bxt_gt_disp_pwron_write(struct intel_vgpu *vgpu, 1608 unsigned int offset, void *p_data, unsigned int bytes) 1609 { 1610 u32 v = *(u32 *)p_data; 1611 1612 if (v & BIT(0)) { 1613 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &= 1614 ~PHY_RESERVED; 1615 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |= 1616 PHY_POWER_GOOD; 1617 } 1618 1619 if (v & BIT(1)) { 1620 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &= 1621 ~PHY_RESERVED; 1622 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |= 1623 PHY_POWER_GOOD; 1624 } 1625 1626 1627 vgpu_vreg(vgpu, offset) = v; 1628 1629 return 0; 1630 } 1631 1632 static int edp_psr_imr_iir_write(struct intel_vgpu *vgpu, 1633 unsigned int offset, void *p_data, unsigned int bytes) 1634 { 1635 vgpu_vreg(vgpu, offset) = 0; 1636 return 0; 1637 } 1638 1639 static int mmio_read_from_hw(struct intel_vgpu *vgpu, 1640 unsigned int offset, void *p_data, unsigned int bytes) 1641 { 1642 struct intel_gvt *gvt = vgpu->gvt; 1643 struct drm_i915_private *dev_priv = gvt->dev_priv; 1644 int ring_id; 1645 u32 ring_base; 1646 1647 ring_id = intel_gvt_render_mmio_to_ring_id(gvt, offset); 1648 /** 1649 * Read HW reg in following case 1650 * a. the offset isn't a ring mmio 1651 * b. the offset's ring is running on hw. 1652 * c. the offset is ring time stamp mmio 1653 */ 1654 if (ring_id >= 0) 1655 ring_base = dev_priv->engine[ring_id]->mmio_base; 1656 1657 if (ring_id < 0 || vgpu == gvt->scheduler.engine_owner[ring_id] || 1658 offset == i915_mmio_reg_offset(RING_TIMESTAMP(ring_base)) || 1659 offset == i915_mmio_reg_offset(RING_TIMESTAMP_UDW(ring_base))) { 1660 mmio_hw_access_pre(dev_priv); 1661 vgpu_vreg(vgpu, offset) = I915_READ(_MMIO(offset)); 1662 mmio_hw_access_post(dev_priv); 1663 } 1664 1665 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1666 } 1667 1668 static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1669 void *p_data, unsigned int bytes) 1670 { 1671 int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset); 1672 struct intel_vgpu_execlist *execlist; 1673 u32 data = *(u32 *)p_data; 1674 int ret = 0; 1675 1676 if (WARN_ON(ring_id < 0 || ring_id >= I915_NUM_ENGINES)) 1677 return -EINVAL; 1678 1679 execlist = &vgpu->submission.execlist[ring_id]; 1680 1681 execlist->elsp_dwords.data[3 - execlist->elsp_dwords.index] = data; 1682 if (execlist->elsp_dwords.index == 3) { 1683 ret = intel_vgpu_submit_execlist(vgpu, ring_id); 1684 if(ret) 1685 gvt_vgpu_err("fail submit workload on ring %d\n", 1686 ring_id); 1687 } 1688 1689 ++execlist->elsp_dwords.index; 1690 execlist->elsp_dwords.index &= 0x3; 1691 return ret; 1692 } 1693 1694 static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1695 void *p_data, unsigned int bytes) 1696 { 1697 u32 data = *(u32 *)p_data; 1698 int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset); 1699 bool enable_execlist; 1700 int ret; 1701 1702 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(1); 1703 if (IS_COFFEELAKE(vgpu->gvt->dev_priv)) 1704 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(2); 1705 write_vreg(vgpu, offset, p_data, bytes); 1706 1707 if (data & _MASKED_BIT_ENABLE(1)) { 1708 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); 1709 return 0; 1710 } 1711 1712 if (IS_COFFEELAKE(vgpu->gvt->dev_priv) && 1713 data & _MASKED_BIT_ENABLE(2)) { 1714 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); 1715 return 0; 1716 } 1717 1718 /* when PPGTT mode enabled, we will check if guest has called 1719 * pvinfo, if not, we will treat this guest as non-gvtg-aware 1720 * guest, and stop emulating its cfg space, mmio, gtt, etc. 1721 */ 1722 if (((data & _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)) || 1723 (data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE))) 1724 && !vgpu->pv_notified) { 1725 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); 1726 return 0; 1727 } 1728 if ((data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)) 1729 || (data & _MASKED_BIT_DISABLE(GFX_RUN_LIST_ENABLE))) { 1730 enable_execlist = !!(data & GFX_RUN_LIST_ENABLE); 1731 1732 gvt_dbg_core("EXECLIST %s on ring %d\n", 1733 (enable_execlist ? "enabling" : "disabling"), 1734 ring_id); 1735 1736 if (!enable_execlist) 1737 return 0; 1738 1739 ret = intel_vgpu_select_submission_ops(vgpu, 1740 BIT(ring_id), 1741 INTEL_VGPU_EXECLIST_SUBMISSION); 1742 if (ret) 1743 return ret; 1744 1745 intel_vgpu_start_schedule(vgpu); 1746 } 1747 return 0; 1748 } 1749 1750 static int gvt_reg_tlb_control_handler(struct intel_vgpu *vgpu, 1751 unsigned int offset, void *p_data, unsigned int bytes) 1752 { 1753 unsigned int id = 0; 1754 1755 write_vreg(vgpu, offset, p_data, bytes); 1756 vgpu_vreg(vgpu, offset) = 0; 1757 1758 switch (offset) { 1759 case 0x4260: 1760 id = RCS0; 1761 break; 1762 case 0x4264: 1763 id = VCS0; 1764 break; 1765 case 0x4268: 1766 id = VCS1; 1767 break; 1768 case 0x426c: 1769 id = BCS0; 1770 break; 1771 case 0x4270: 1772 id = VECS0; 1773 break; 1774 default: 1775 return -EINVAL; 1776 } 1777 set_bit(id, (void *)vgpu->submission.tlb_handle_pending); 1778 1779 return 0; 1780 } 1781 1782 static int ring_reset_ctl_write(struct intel_vgpu *vgpu, 1783 unsigned int offset, void *p_data, unsigned int bytes) 1784 { 1785 u32 data; 1786 1787 write_vreg(vgpu, offset, p_data, bytes); 1788 data = vgpu_vreg(vgpu, offset); 1789 1790 if (data & _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET)) 1791 data |= RESET_CTL_READY_TO_RESET; 1792 else if (data & _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET)) 1793 data &= ~RESET_CTL_READY_TO_RESET; 1794 1795 vgpu_vreg(vgpu, offset) = data; 1796 return 0; 1797 } 1798 1799 static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu, 1800 unsigned int offset, void *p_data, 1801 unsigned int bytes) 1802 { 1803 u32 data = *(u32 *)p_data; 1804 1805 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(0x18); 1806 write_vreg(vgpu, offset, p_data, bytes); 1807 1808 if (data & _MASKED_BIT_ENABLE(0x10) || data & _MASKED_BIT_ENABLE(0x8)) 1809 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); 1810 1811 return 0; 1812 } 1813 1814 #define MMIO_F(reg, s, f, am, rm, d, r, w) do { \ 1815 ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \ 1816 f, s, am, rm, d, r, w); \ 1817 if (ret) \ 1818 return ret; \ 1819 } while (0) 1820 1821 #define MMIO_D(reg, d) \ 1822 MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL) 1823 1824 #define MMIO_DH(reg, d, r, w) \ 1825 MMIO_F(reg, 4, 0, 0, 0, d, r, w) 1826 1827 #define MMIO_DFH(reg, d, f, r, w) \ 1828 MMIO_F(reg, 4, f, 0, 0, d, r, w) 1829 1830 #define MMIO_GM(reg, d, r, w) \ 1831 MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w) 1832 1833 #define MMIO_GM_RDR(reg, d, r, w) \ 1834 MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w) 1835 1836 #define MMIO_RO(reg, d, f, rm, r, w) \ 1837 MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w) 1838 1839 #define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \ 1840 MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \ 1841 MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \ 1842 MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \ 1843 MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \ 1844 if (HAS_ENGINE(dev_priv, VCS1)) \ 1845 MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \ 1846 } while (0) 1847 1848 #define MMIO_RING_D(prefix, d) \ 1849 MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL) 1850 1851 #define MMIO_RING_DFH(prefix, d, f, r, w) \ 1852 MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w) 1853 1854 #define MMIO_RING_GM(prefix, d, r, w) \ 1855 MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w) 1856 1857 #define MMIO_RING_GM_RDR(prefix, d, r, w) \ 1858 MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w) 1859 1860 #define MMIO_RING_RO(prefix, d, f, rm, r, w) \ 1861 MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w) 1862 1863 static int init_generic_mmio_info(struct intel_gvt *gvt) 1864 { 1865 struct drm_i915_private *dev_priv = gvt->dev_priv; 1866 int ret; 1867 1868 MMIO_RING_DFH(RING_IMR, D_ALL, F_CMD_ACCESS, NULL, 1869 intel_vgpu_reg_imr_handler); 1870 1871 MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler); 1872 MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler); 1873 MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler); 1874 MMIO_D(SDEISR, D_ALL); 1875 1876 MMIO_RING_DFH(RING_HWSTAM, D_ALL, F_CMD_ACCESS, NULL, NULL); 1877 1878 MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL, 1879 gamw_echo_dev_rw_ia_write); 1880 1881 MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1882 MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1883 MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1884 1885 #define RING_REG(base) _MMIO((base) + 0x28) 1886 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL); 1887 #undef RING_REG 1888 1889 #define RING_REG(base) _MMIO((base) + 0x134) 1890 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL); 1891 #undef RING_REG 1892 1893 #define RING_REG(base) _MMIO((base) + 0x6c) 1894 MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL); 1895 #undef RING_REG 1896 MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL); 1897 1898 MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL); 1899 MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL); 1900 MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL); 1901 MMIO_D(GEN7_CXT_SIZE, D_ALL); 1902 1903 MMIO_RING_DFH(RING_TAIL, D_ALL, F_CMD_ACCESS, NULL, NULL); 1904 MMIO_RING_DFH(RING_HEAD, D_ALL, F_CMD_ACCESS, NULL, NULL); 1905 MMIO_RING_DFH(RING_CTL, D_ALL, F_CMD_ACCESS, NULL, NULL); 1906 MMIO_RING_DFH(RING_ACTHD, D_ALL, F_CMD_ACCESS, mmio_read_from_hw, NULL); 1907 MMIO_RING_GM_RDR(RING_START, D_ALL, NULL, NULL); 1908 1909 /* RING MODE */ 1910 #define RING_REG(base) _MMIO((base) + 0x29c) 1911 MMIO_RING_DFH(RING_REG, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, 1912 ring_mode_mmio_write); 1913 #undef RING_REG 1914 1915 MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 1916 NULL, NULL); 1917 MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 1918 NULL, NULL); 1919 MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS, 1920 mmio_read_from_hw, NULL); 1921 MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS, 1922 mmio_read_from_hw, NULL); 1923 1924 MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1925 MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 1926 NULL, NULL); 1927 MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1928 MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1929 MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1930 1931 MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1932 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1933 MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1934 MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL, 1935 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1936 MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1937 MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL); 1938 MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 1939 NULL, NULL); 1940 MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 1941 NULL, NULL); 1942 MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL); 1943 MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL); 1944 MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL); 1945 MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL); 1946 MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL); 1947 MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL); 1948 MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL); 1949 MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1950 MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1951 MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1952 1953 /* display */ 1954 MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL); 1955 MMIO_D(_MMIO(0x602a0), D_ALL); 1956 1957 MMIO_D(_MMIO(0x65050), D_ALL); 1958 MMIO_D(_MMIO(0x650b4), D_ALL); 1959 1960 MMIO_D(_MMIO(0xc4040), D_ALL); 1961 MMIO_D(DERRMR, D_ALL); 1962 1963 MMIO_D(PIPEDSL(PIPE_A), D_ALL); 1964 MMIO_D(PIPEDSL(PIPE_B), D_ALL); 1965 MMIO_D(PIPEDSL(PIPE_C), D_ALL); 1966 MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL); 1967 1968 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write); 1969 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write); 1970 MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write); 1971 MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write); 1972 1973 MMIO_D(PIPESTAT(PIPE_A), D_ALL); 1974 MMIO_D(PIPESTAT(PIPE_B), D_ALL); 1975 MMIO_D(PIPESTAT(PIPE_C), D_ALL); 1976 MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL); 1977 1978 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL); 1979 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL); 1980 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL); 1981 MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL); 1982 1983 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL); 1984 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL); 1985 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL); 1986 MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL); 1987 1988 MMIO_D(CURCNTR(PIPE_A), D_ALL); 1989 MMIO_D(CURCNTR(PIPE_B), D_ALL); 1990 MMIO_D(CURCNTR(PIPE_C), D_ALL); 1991 1992 MMIO_D(CURPOS(PIPE_A), D_ALL); 1993 MMIO_D(CURPOS(PIPE_B), D_ALL); 1994 MMIO_D(CURPOS(PIPE_C), D_ALL); 1995 1996 MMIO_D(CURBASE(PIPE_A), D_ALL); 1997 MMIO_D(CURBASE(PIPE_B), D_ALL); 1998 MMIO_D(CURBASE(PIPE_C), D_ALL); 1999 2000 MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL); 2001 MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL); 2002 MMIO_D(CUR_FBC_CTL(PIPE_C), D_ALL); 2003 2004 MMIO_D(_MMIO(0x700ac), D_ALL); 2005 MMIO_D(_MMIO(0x710ac), D_ALL); 2006 MMIO_D(_MMIO(0x720ac), D_ALL); 2007 2008 MMIO_D(_MMIO(0x70090), D_ALL); 2009 MMIO_D(_MMIO(0x70094), D_ALL); 2010 MMIO_D(_MMIO(0x70098), D_ALL); 2011 MMIO_D(_MMIO(0x7009c), D_ALL); 2012 2013 MMIO_D(DSPCNTR(PIPE_A), D_ALL); 2014 MMIO_D(DSPADDR(PIPE_A), D_ALL); 2015 MMIO_D(DSPSTRIDE(PIPE_A), D_ALL); 2016 MMIO_D(DSPPOS(PIPE_A), D_ALL); 2017 MMIO_D(DSPSIZE(PIPE_A), D_ALL); 2018 MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write); 2019 MMIO_D(DSPOFFSET(PIPE_A), D_ALL); 2020 MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL); 2021 MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL, 2022 reg50080_mmio_write); 2023 2024 MMIO_D(DSPCNTR(PIPE_B), D_ALL); 2025 MMIO_D(DSPADDR(PIPE_B), D_ALL); 2026 MMIO_D(DSPSTRIDE(PIPE_B), D_ALL); 2027 MMIO_D(DSPPOS(PIPE_B), D_ALL); 2028 MMIO_D(DSPSIZE(PIPE_B), D_ALL); 2029 MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write); 2030 MMIO_D(DSPOFFSET(PIPE_B), D_ALL); 2031 MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL); 2032 MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL, 2033 reg50080_mmio_write); 2034 2035 MMIO_D(DSPCNTR(PIPE_C), D_ALL); 2036 MMIO_D(DSPADDR(PIPE_C), D_ALL); 2037 MMIO_D(DSPSTRIDE(PIPE_C), D_ALL); 2038 MMIO_D(DSPPOS(PIPE_C), D_ALL); 2039 MMIO_D(DSPSIZE(PIPE_C), D_ALL); 2040 MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write); 2041 MMIO_D(DSPOFFSET(PIPE_C), D_ALL); 2042 MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL); 2043 MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL, 2044 reg50080_mmio_write); 2045 2046 MMIO_D(SPRCTL(PIPE_A), D_ALL); 2047 MMIO_D(SPRLINOFF(PIPE_A), D_ALL); 2048 MMIO_D(SPRSTRIDE(PIPE_A), D_ALL); 2049 MMIO_D(SPRPOS(PIPE_A), D_ALL); 2050 MMIO_D(SPRSIZE(PIPE_A), D_ALL); 2051 MMIO_D(SPRKEYVAL(PIPE_A), D_ALL); 2052 MMIO_D(SPRKEYMSK(PIPE_A), D_ALL); 2053 MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write); 2054 MMIO_D(SPRKEYMAX(PIPE_A), D_ALL); 2055 MMIO_D(SPROFFSET(PIPE_A), D_ALL); 2056 MMIO_D(SPRSCALE(PIPE_A), D_ALL); 2057 MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL); 2058 MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL, 2059 reg50080_mmio_write); 2060 2061 MMIO_D(SPRCTL(PIPE_B), D_ALL); 2062 MMIO_D(SPRLINOFF(PIPE_B), D_ALL); 2063 MMIO_D(SPRSTRIDE(PIPE_B), D_ALL); 2064 MMIO_D(SPRPOS(PIPE_B), D_ALL); 2065 MMIO_D(SPRSIZE(PIPE_B), D_ALL); 2066 MMIO_D(SPRKEYVAL(PIPE_B), D_ALL); 2067 MMIO_D(SPRKEYMSK(PIPE_B), D_ALL); 2068 MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write); 2069 MMIO_D(SPRKEYMAX(PIPE_B), D_ALL); 2070 MMIO_D(SPROFFSET(PIPE_B), D_ALL); 2071 MMIO_D(SPRSCALE(PIPE_B), D_ALL); 2072 MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL); 2073 MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL, 2074 reg50080_mmio_write); 2075 2076 MMIO_D(SPRCTL(PIPE_C), D_ALL); 2077 MMIO_D(SPRLINOFF(PIPE_C), D_ALL); 2078 MMIO_D(SPRSTRIDE(PIPE_C), D_ALL); 2079 MMIO_D(SPRPOS(PIPE_C), D_ALL); 2080 MMIO_D(SPRSIZE(PIPE_C), D_ALL); 2081 MMIO_D(SPRKEYVAL(PIPE_C), D_ALL); 2082 MMIO_D(SPRKEYMSK(PIPE_C), D_ALL); 2083 MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write); 2084 MMIO_D(SPRKEYMAX(PIPE_C), D_ALL); 2085 MMIO_D(SPROFFSET(PIPE_C), D_ALL); 2086 MMIO_D(SPRSCALE(PIPE_C), D_ALL); 2087 MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL); 2088 MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL, 2089 reg50080_mmio_write); 2090 2091 MMIO_D(HTOTAL(TRANSCODER_A), D_ALL); 2092 MMIO_D(HBLANK(TRANSCODER_A), D_ALL); 2093 MMIO_D(HSYNC(TRANSCODER_A), D_ALL); 2094 MMIO_D(VTOTAL(TRANSCODER_A), D_ALL); 2095 MMIO_D(VBLANK(TRANSCODER_A), D_ALL); 2096 MMIO_D(VSYNC(TRANSCODER_A), D_ALL); 2097 MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL); 2098 MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL); 2099 MMIO_D(PIPESRC(TRANSCODER_A), D_ALL); 2100 2101 MMIO_D(HTOTAL(TRANSCODER_B), D_ALL); 2102 MMIO_D(HBLANK(TRANSCODER_B), D_ALL); 2103 MMIO_D(HSYNC(TRANSCODER_B), D_ALL); 2104 MMIO_D(VTOTAL(TRANSCODER_B), D_ALL); 2105 MMIO_D(VBLANK(TRANSCODER_B), D_ALL); 2106 MMIO_D(VSYNC(TRANSCODER_B), D_ALL); 2107 MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL); 2108 MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL); 2109 MMIO_D(PIPESRC(TRANSCODER_B), D_ALL); 2110 2111 MMIO_D(HTOTAL(TRANSCODER_C), D_ALL); 2112 MMIO_D(HBLANK(TRANSCODER_C), D_ALL); 2113 MMIO_D(HSYNC(TRANSCODER_C), D_ALL); 2114 MMIO_D(VTOTAL(TRANSCODER_C), D_ALL); 2115 MMIO_D(VBLANK(TRANSCODER_C), D_ALL); 2116 MMIO_D(VSYNC(TRANSCODER_C), D_ALL); 2117 MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL); 2118 MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL); 2119 MMIO_D(PIPESRC(TRANSCODER_C), D_ALL); 2120 2121 MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL); 2122 MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL); 2123 MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL); 2124 MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL); 2125 MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL); 2126 MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL); 2127 MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL); 2128 MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL); 2129 2130 MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL); 2131 MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL); 2132 MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL); 2133 MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL); 2134 MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL); 2135 MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL); 2136 MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL); 2137 MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL); 2138 2139 MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL); 2140 MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL); 2141 MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL); 2142 MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL); 2143 MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL); 2144 MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL); 2145 MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL); 2146 MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL); 2147 2148 MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL); 2149 MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL); 2150 MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL); 2151 MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL); 2152 MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL); 2153 MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL); 2154 MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL); 2155 MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL); 2156 2157 MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL); 2158 MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL); 2159 MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL); 2160 MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL); 2161 MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL); 2162 MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL); 2163 MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL); 2164 MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL); 2165 2166 MMIO_D(PF_CTL(PIPE_A), D_ALL); 2167 MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL); 2168 MMIO_D(PF_WIN_POS(PIPE_A), D_ALL); 2169 MMIO_D(PF_VSCALE(PIPE_A), D_ALL); 2170 MMIO_D(PF_HSCALE(PIPE_A), D_ALL); 2171 2172 MMIO_D(PF_CTL(PIPE_B), D_ALL); 2173 MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL); 2174 MMIO_D(PF_WIN_POS(PIPE_B), D_ALL); 2175 MMIO_D(PF_VSCALE(PIPE_B), D_ALL); 2176 MMIO_D(PF_HSCALE(PIPE_B), D_ALL); 2177 2178 MMIO_D(PF_CTL(PIPE_C), D_ALL); 2179 MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL); 2180 MMIO_D(PF_WIN_POS(PIPE_C), D_ALL); 2181 MMIO_D(PF_VSCALE(PIPE_C), D_ALL); 2182 MMIO_D(PF_HSCALE(PIPE_C), D_ALL); 2183 2184 MMIO_D(WM0_PIPEA_ILK, D_ALL); 2185 MMIO_D(WM0_PIPEB_ILK, D_ALL); 2186 MMIO_D(WM0_PIPEC_IVB, D_ALL); 2187 MMIO_D(WM1_LP_ILK, D_ALL); 2188 MMIO_D(WM2_LP_ILK, D_ALL); 2189 MMIO_D(WM3_LP_ILK, D_ALL); 2190 MMIO_D(WM1S_LP_ILK, D_ALL); 2191 MMIO_D(WM2S_LP_IVB, D_ALL); 2192 MMIO_D(WM3S_LP_IVB, D_ALL); 2193 2194 MMIO_D(BLC_PWM_CPU_CTL2, D_ALL); 2195 MMIO_D(BLC_PWM_CPU_CTL, D_ALL); 2196 MMIO_D(BLC_PWM_PCH_CTL1, D_ALL); 2197 MMIO_D(BLC_PWM_PCH_CTL2, D_ALL); 2198 2199 MMIO_D(_MMIO(0x48268), D_ALL); 2200 2201 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read, 2202 gmbus_mmio_write); 2203 MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL); 2204 MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL); 2205 2206 MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 2207 dp_aux_ch_ctl_mmio_write); 2208 MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 2209 dp_aux_ch_ctl_mmio_write); 2210 MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 2211 dp_aux_ch_ctl_mmio_write); 2212 2213 MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write); 2214 2215 MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write); 2216 MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write); 2217 2218 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write); 2219 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write); 2220 MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write); 2221 MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); 2222 MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); 2223 MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); 2224 MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); 2225 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); 2226 MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); 2227 2228 MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A), D_ALL); 2229 MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A), D_ALL); 2230 MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A), D_ALL); 2231 MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A), D_ALL); 2232 MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A), D_ALL); 2233 MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A), D_ALL); 2234 MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A), D_ALL); 2235 2236 MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B), D_ALL); 2237 MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B), D_ALL); 2238 MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B), D_ALL); 2239 MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B), D_ALL); 2240 MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B), D_ALL); 2241 MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B), D_ALL); 2242 MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B), D_ALL); 2243 2244 MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1), D_ALL); 2245 MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1), D_ALL); 2246 MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2), D_ALL); 2247 MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2), D_ALL); 2248 MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1), D_ALL); 2249 MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1), D_ALL); 2250 MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2), D_ALL); 2251 MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2), D_ALL); 2252 2253 MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL); 2254 MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL); 2255 MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL); 2256 2257 MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL); 2258 MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL); 2259 MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL); 2260 2261 MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL); 2262 MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL); 2263 MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL); 2264 2265 MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL); 2266 MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL); 2267 MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL); 2268 2269 MMIO_D(_MMIO(_FDI_RXA_MISC), D_ALL); 2270 MMIO_D(_MMIO(_FDI_RXB_MISC), D_ALL); 2271 MMIO_D(_MMIO(_FDI_RXA_TUSIZE1), D_ALL); 2272 MMIO_D(_MMIO(_FDI_RXA_TUSIZE2), D_ALL); 2273 MMIO_D(_MMIO(_FDI_RXB_TUSIZE1), D_ALL); 2274 MMIO_D(_MMIO(_FDI_RXB_TUSIZE2), D_ALL); 2275 2276 MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write); 2277 MMIO_D(PCH_PP_DIVISOR, D_ALL); 2278 MMIO_D(PCH_PP_STATUS, D_ALL); 2279 MMIO_D(PCH_LVDS, D_ALL); 2280 MMIO_D(_MMIO(_PCH_DPLL_A), D_ALL); 2281 MMIO_D(_MMIO(_PCH_DPLL_B), D_ALL); 2282 MMIO_D(_MMIO(_PCH_FPA0), D_ALL); 2283 MMIO_D(_MMIO(_PCH_FPA1), D_ALL); 2284 MMIO_D(_MMIO(_PCH_FPB0), D_ALL); 2285 MMIO_D(_MMIO(_PCH_FPB1), D_ALL); 2286 MMIO_D(PCH_DREF_CONTROL, D_ALL); 2287 MMIO_D(PCH_RAWCLK_FREQ, D_ALL); 2288 MMIO_D(PCH_DPLL_SEL, D_ALL); 2289 2290 MMIO_D(_MMIO(0x61208), D_ALL); 2291 MMIO_D(_MMIO(0x6120c), D_ALL); 2292 MMIO_D(PCH_PP_ON_DELAYS, D_ALL); 2293 MMIO_D(PCH_PP_OFF_DELAYS, D_ALL); 2294 2295 MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL); 2296 MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL); 2297 MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL); 2298 MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL); 2299 MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL); 2300 MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL); 2301 2302 MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0, 2303 PORTA_HOTPLUG_STATUS_MASK 2304 | PORTB_HOTPLUG_STATUS_MASK 2305 | PORTC_HOTPLUG_STATUS_MASK 2306 | PORTD_HOTPLUG_STATUS_MASK, 2307 NULL, NULL); 2308 2309 MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write); 2310 MMIO_D(FUSE_STRAP, D_ALL); 2311 MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL); 2312 2313 MMIO_D(DISP_ARB_CTL, D_ALL); 2314 MMIO_D(DISP_ARB_CTL2, D_ALL); 2315 2316 MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL); 2317 MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL); 2318 MMIO_D(ILK_DSPCLK_GATE_D, D_ALL); 2319 2320 MMIO_D(SOUTH_CHICKEN1, D_ALL); 2321 MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write); 2322 MMIO_D(_MMIO(_TRANSA_CHICKEN1), D_ALL); 2323 MMIO_D(_MMIO(_TRANSB_CHICKEN1), D_ALL); 2324 MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL); 2325 MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL); 2326 MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL); 2327 2328 MMIO_D(ILK_DPFC_CB_BASE, D_ALL); 2329 MMIO_D(ILK_DPFC_CONTROL, D_ALL); 2330 MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL); 2331 MMIO_D(ILK_DPFC_STATUS, D_ALL); 2332 MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL); 2333 MMIO_D(ILK_DPFC_CHICKEN, D_ALL); 2334 MMIO_D(ILK_FBC_RT_BASE, D_ALL); 2335 2336 MMIO_D(IPS_CTL, D_ALL); 2337 2338 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL); 2339 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL); 2340 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL); 2341 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL); 2342 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL); 2343 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL); 2344 MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL); 2345 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL); 2346 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL); 2347 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL); 2348 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL); 2349 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL); 2350 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL); 2351 2352 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL); 2353 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL); 2354 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL); 2355 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL); 2356 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL); 2357 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL); 2358 MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL); 2359 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL); 2360 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL); 2361 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL); 2362 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL); 2363 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL); 2364 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL); 2365 2366 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL); 2367 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL); 2368 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL); 2369 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL); 2370 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL); 2371 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL); 2372 MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL); 2373 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL); 2374 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL); 2375 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL); 2376 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL); 2377 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL); 2378 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL); 2379 2380 MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL); 2381 MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL); 2382 MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 2383 2384 MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL); 2385 MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL); 2386 MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 2387 2388 MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL); 2389 MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL); 2390 MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 2391 2392 MMIO_D(_MMIO(0x60110), D_ALL); 2393 MMIO_D(_MMIO(0x61110), D_ALL); 2394 MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL); 2395 MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL); 2396 MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL); 2397 MMIO_F(_MMIO(0x70440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2398 MMIO_F(_MMIO(0x71440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2399 MMIO_F(_MMIO(0x72440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2400 MMIO_F(_MMIO(0x7044c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2401 MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2402 MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2403 2404 MMIO_D(PIPE_WM_LINETIME(PIPE_A), D_ALL); 2405 MMIO_D(PIPE_WM_LINETIME(PIPE_B), D_ALL); 2406 MMIO_D(PIPE_WM_LINETIME(PIPE_C), D_ALL); 2407 MMIO_D(SPLL_CTL, D_ALL); 2408 MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL); 2409 MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL); 2410 MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL); 2411 MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL); 2412 MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL); 2413 MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL); 2414 MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL); 2415 MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL); 2416 MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL); 2417 MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL); 2418 2419 MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL); 2420 MMIO_D(_MMIO(0x46508), D_ALL); 2421 2422 MMIO_D(_MMIO(0x49080), D_ALL); 2423 MMIO_D(_MMIO(0x49180), D_ALL); 2424 MMIO_D(_MMIO(0x49280), D_ALL); 2425 2426 MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL); 2427 MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL); 2428 MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL); 2429 2430 MMIO_D(GAMMA_MODE(PIPE_A), D_ALL); 2431 MMIO_D(GAMMA_MODE(PIPE_B), D_ALL); 2432 MMIO_D(GAMMA_MODE(PIPE_C), D_ALL); 2433 2434 MMIO_D(PIPE_MULT(PIPE_A), D_ALL); 2435 MMIO_D(PIPE_MULT(PIPE_B), D_ALL); 2436 MMIO_D(PIPE_MULT(PIPE_C), D_ALL); 2437 2438 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL); 2439 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL); 2440 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL); 2441 2442 MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL); 2443 MMIO_D(SBI_ADDR, D_ALL); 2444 MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL); 2445 MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write); 2446 MMIO_D(PIXCLK_GATE, D_ALL); 2447 2448 MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL, 2449 dp_aux_ch_ctl_mmio_write); 2450 2451 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2452 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2453 MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2454 MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2455 MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2456 2457 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write); 2458 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write); 2459 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write); 2460 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write); 2461 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write); 2462 2463 MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write); 2464 MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write); 2465 MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write); 2466 MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write); 2467 MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL); 2468 2469 MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2470 MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2471 MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2472 MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2473 MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2474 2475 MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL); 2476 MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL); 2477 MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A), D_ALL); 2478 2479 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL); 2480 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL); 2481 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL); 2482 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL); 2483 2484 MMIO_D(_MMIO(_TRANSA_MSA_MISC), D_ALL); 2485 MMIO_D(_MMIO(_TRANSB_MSA_MISC), D_ALL); 2486 MMIO_D(_MMIO(_TRANSC_MSA_MISC), D_ALL); 2487 MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC), D_ALL); 2488 2489 MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL); 2490 MMIO_D(FORCEWAKE_ACK, D_ALL); 2491 MMIO_D(GEN6_GT_CORE_STATUS, D_ALL); 2492 MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL); 2493 MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL); 2494 MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL); 2495 MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write); 2496 MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL); 2497 MMIO_D(ECOBUS, D_ALL); 2498 MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL); 2499 MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL); 2500 MMIO_D(GEN6_RPNSWREQ, D_ALL); 2501 MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL); 2502 MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL); 2503 MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL); 2504 MMIO_D(GEN6_RPSTAT1, D_ALL); 2505 MMIO_D(GEN6_RP_CONTROL, D_ALL); 2506 MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL); 2507 MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL); 2508 MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL); 2509 MMIO_D(GEN6_RP_CUR_UP, D_ALL); 2510 MMIO_D(GEN6_RP_PREV_UP, D_ALL); 2511 MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL); 2512 MMIO_D(GEN6_RP_CUR_DOWN, D_ALL); 2513 MMIO_D(GEN6_RP_PREV_DOWN, D_ALL); 2514 MMIO_D(GEN6_RP_UP_EI, D_ALL); 2515 MMIO_D(GEN6_RP_DOWN_EI, D_ALL); 2516 MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL); 2517 MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL); 2518 MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL); 2519 MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL); 2520 MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL); 2521 MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL); 2522 MMIO_D(GEN6_RC_SLEEP, D_ALL); 2523 MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL); 2524 MMIO_D(GEN6_RC6_THRESHOLD, D_ALL); 2525 MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL); 2526 MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL); 2527 MMIO_D(GEN6_PMINTRMSK, D_ALL); 2528 MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write); 2529 MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write); 2530 MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write); 2531 MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write); 2532 MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write); 2533 MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write); 2534 2535 MMIO_D(RSTDBYCTL, D_ALL); 2536 2537 MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write); 2538 MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write); 2539 MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write); 2540 2541 MMIO_D(TILECTL, D_ALL); 2542 2543 MMIO_D(GEN6_UCGCTL1, D_ALL); 2544 MMIO_D(GEN6_UCGCTL2, D_ALL); 2545 2546 MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL); 2547 2548 MMIO_D(GEN6_PCODE_DATA, D_ALL); 2549 MMIO_D(_MMIO(0x13812c), D_ALL); 2550 MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL); 2551 MMIO_D(HSW_EDRAM_CAP, D_ALL); 2552 MMIO_D(HSW_IDICR, D_ALL); 2553 MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL); 2554 2555 MMIO_D(_MMIO(0x3c), D_ALL); 2556 MMIO_D(_MMIO(0x860), D_ALL); 2557 MMIO_D(ECOSKPD, D_ALL); 2558 MMIO_D(_MMIO(0x121d0), D_ALL); 2559 MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL); 2560 MMIO_D(_MMIO(0x41d0), D_ALL); 2561 MMIO_D(GAC_ECO_BITS, D_ALL); 2562 MMIO_D(_MMIO(0x6200), D_ALL); 2563 MMIO_D(_MMIO(0x6204), D_ALL); 2564 MMIO_D(_MMIO(0x6208), D_ALL); 2565 MMIO_D(_MMIO(0x7118), D_ALL); 2566 MMIO_D(_MMIO(0x7180), D_ALL); 2567 MMIO_D(_MMIO(0x7408), D_ALL); 2568 MMIO_D(_MMIO(0x7c00), D_ALL); 2569 MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write); 2570 MMIO_D(_MMIO(0x911c), D_ALL); 2571 MMIO_D(_MMIO(0x9120), D_ALL); 2572 MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL); 2573 2574 MMIO_D(GAB_CTL, D_ALL); 2575 MMIO_D(_MMIO(0x48800), D_ALL); 2576 MMIO_D(_MMIO(0xce044), D_ALL); 2577 MMIO_D(_MMIO(0xe6500), D_ALL); 2578 MMIO_D(_MMIO(0xe6504), D_ALL); 2579 MMIO_D(_MMIO(0xe6600), D_ALL); 2580 MMIO_D(_MMIO(0xe6604), D_ALL); 2581 MMIO_D(_MMIO(0xe6700), D_ALL); 2582 MMIO_D(_MMIO(0xe6704), D_ALL); 2583 MMIO_D(_MMIO(0xe6800), D_ALL); 2584 MMIO_D(_MMIO(0xe6804), D_ALL); 2585 MMIO_D(PCH_GMBUS4, D_ALL); 2586 MMIO_D(PCH_GMBUS5, D_ALL); 2587 2588 MMIO_D(_MMIO(0x902c), D_ALL); 2589 MMIO_D(_MMIO(0xec008), D_ALL); 2590 MMIO_D(_MMIO(0xec00c), D_ALL); 2591 MMIO_D(_MMIO(0xec008 + 0x18), D_ALL); 2592 MMIO_D(_MMIO(0xec00c + 0x18), D_ALL); 2593 MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL); 2594 MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL); 2595 MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL); 2596 MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL); 2597 MMIO_D(_MMIO(0xec408), D_ALL); 2598 MMIO_D(_MMIO(0xec40c), D_ALL); 2599 MMIO_D(_MMIO(0xec408 + 0x18), D_ALL); 2600 MMIO_D(_MMIO(0xec40c + 0x18), D_ALL); 2601 MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL); 2602 MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL); 2603 MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL); 2604 MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL); 2605 MMIO_D(_MMIO(0xfc810), D_ALL); 2606 MMIO_D(_MMIO(0xfc81c), D_ALL); 2607 MMIO_D(_MMIO(0xfc828), D_ALL); 2608 MMIO_D(_MMIO(0xfc834), D_ALL); 2609 MMIO_D(_MMIO(0xfcc00), D_ALL); 2610 MMIO_D(_MMIO(0xfcc0c), D_ALL); 2611 MMIO_D(_MMIO(0xfcc18), D_ALL); 2612 MMIO_D(_MMIO(0xfcc24), D_ALL); 2613 MMIO_D(_MMIO(0xfd000), D_ALL); 2614 MMIO_D(_MMIO(0xfd00c), D_ALL); 2615 MMIO_D(_MMIO(0xfd018), D_ALL); 2616 MMIO_D(_MMIO(0xfd024), D_ALL); 2617 MMIO_D(_MMIO(0xfd034), D_ALL); 2618 2619 MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write); 2620 MMIO_D(_MMIO(0x2054), D_ALL); 2621 MMIO_D(_MMIO(0x12054), D_ALL); 2622 MMIO_D(_MMIO(0x22054), D_ALL); 2623 MMIO_D(_MMIO(0x1a054), D_ALL); 2624 2625 MMIO_D(_MMIO(0x44070), D_ALL); 2626 MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2627 MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL); 2628 MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL); 2629 MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL); 2630 MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL); 2631 2632 MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL); 2633 MMIO_D(_MMIO(0x2b00), D_BDW_PLUS); 2634 MMIO_D(_MMIO(0x2360), D_BDW_PLUS); 2635 MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2636 MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2637 MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2638 2639 MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2640 MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2641 MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL); 2642 2643 MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2644 MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2645 MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2646 MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2647 MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2648 MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2649 MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2650 MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2651 MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2652 MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2653 MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2654 MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2655 MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2656 MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2657 MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2658 MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2659 MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2660 2661 MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2662 MMIO_RING_GM_RDR(RING_BBADDR, D_ALL, NULL, NULL); 2663 MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL); 2664 MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL); 2665 MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL); 2666 MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL); 2667 MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL); 2668 MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2669 MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2670 MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2671 MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2672 2673 MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write); 2674 MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write); 2675 return 0; 2676 } 2677 2678 static int init_broadwell_mmio_info(struct intel_gvt *gvt) 2679 { 2680 struct drm_i915_private *dev_priv = gvt->dev_priv; 2681 int ret; 2682 2683 MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2684 MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2685 MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2686 MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS); 2687 2688 MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2689 MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2690 MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2691 MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS); 2692 2693 MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2694 MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2695 MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2696 MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS); 2697 2698 MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2699 MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2700 MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2701 MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS); 2702 2703 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL, 2704 intel_vgpu_reg_imr_handler); 2705 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL, 2706 intel_vgpu_reg_ier_handler); 2707 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL, 2708 intel_vgpu_reg_iir_handler); 2709 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS); 2710 2711 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL, 2712 intel_vgpu_reg_imr_handler); 2713 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL, 2714 intel_vgpu_reg_ier_handler); 2715 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL, 2716 intel_vgpu_reg_iir_handler); 2717 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS); 2718 2719 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL, 2720 intel_vgpu_reg_imr_handler); 2721 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL, 2722 intel_vgpu_reg_ier_handler); 2723 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL, 2724 intel_vgpu_reg_iir_handler); 2725 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS); 2726 2727 MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2728 MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2729 MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2730 MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS); 2731 2732 MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2733 MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2734 MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2735 MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS); 2736 2737 MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2738 MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2739 MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2740 MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS); 2741 2742 MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL, 2743 intel_vgpu_reg_master_irq_handler); 2744 2745 MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, F_CMD_ACCESS, 2746 mmio_read_from_hw, NULL); 2747 2748 #define RING_REG(base) _MMIO((base) + 0xd0) 2749 MMIO_RING_F(RING_REG, 4, F_RO, 0, 2750 ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL, 2751 ring_reset_ctl_write); 2752 #undef RING_REG 2753 2754 #define RING_REG(base) _MMIO((base) + 0x230) 2755 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write); 2756 #undef RING_REG 2757 2758 #define RING_REG(base) _MMIO((base) + 0x234) 2759 MMIO_RING_F(RING_REG, 8, F_RO | F_CMD_ACCESS, 0, ~0, D_BDW_PLUS, 2760 NULL, NULL); 2761 #undef RING_REG 2762 2763 #define RING_REG(base) _MMIO((base) + 0x244) 2764 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2765 #undef RING_REG 2766 2767 #define RING_REG(base) _MMIO((base) + 0x370) 2768 MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL); 2769 #undef RING_REG 2770 2771 #define RING_REG(base) _MMIO((base) + 0x3a0) 2772 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2773 #undef RING_REG 2774 2775 MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS); 2776 MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS); 2777 MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS); 2778 MMIO_D(_MMIO(0x1c1d0), D_BDW_PLUS); 2779 MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS); 2780 MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS); 2781 MMIO_D(_MMIO(0x1c054), D_BDW_PLUS); 2782 2783 MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write); 2784 2785 MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS); 2786 MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS); 2787 2788 MMIO_D(GAMTARBMODE, D_BDW_PLUS); 2789 2790 #define RING_REG(base) _MMIO((base) + 0x270) 2791 MMIO_RING_F(RING_REG, 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL); 2792 #undef RING_REG 2793 2794 MMIO_RING_GM_RDR(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write); 2795 2796 MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2797 2798 MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS); 2799 MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS); 2800 MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS); 2801 2802 MMIO_D(WM_MISC, D_BDW); 2803 MMIO_D(_MMIO(_SRD_CTL_EDP), D_BDW); 2804 2805 MMIO_D(_MMIO(0x6671c), D_BDW_PLUS); 2806 MMIO_D(_MMIO(0x66c00), D_BDW_PLUS); 2807 MMIO_D(_MMIO(0x66c04), D_BDW_PLUS); 2808 2809 MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS); 2810 2811 MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS); 2812 MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS); 2813 MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS); 2814 2815 MMIO_D(_MMIO(0xfdc), D_BDW_PLUS); 2816 MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2817 NULL, NULL); 2818 MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2819 NULL, NULL); 2820 MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2821 2822 MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL); 2823 MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL); 2824 MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2825 MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL); 2826 MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL); 2827 MMIO_D(_MMIO(0xb110), D_BDW); 2828 2829 MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, 2830 NULL, force_nonpriv_write); 2831 2832 MMIO_D(_MMIO(0x44484), D_BDW_PLUS); 2833 MMIO_D(_MMIO(0x4448c), D_BDW_PLUS); 2834 2835 MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL); 2836 MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS); 2837 2838 MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL); 2839 2840 MMIO_D(_MMIO(0x110000), D_BDW_PLUS); 2841 2842 MMIO_D(_MMIO(0x48400), D_BDW_PLUS); 2843 2844 MMIO_D(_MMIO(0x6e570), D_BDW_PLUS); 2845 MMIO_D(_MMIO(0x65f10), D_BDW_PLUS); 2846 2847 MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2848 MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2849 MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2850 MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2851 2852 MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL); 2853 2854 MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2855 MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2856 MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2857 MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2858 MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2859 MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2860 MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2861 MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2862 MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2863 MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2864 return 0; 2865 } 2866 2867 static int init_skl_mmio_info(struct intel_gvt *gvt) 2868 { 2869 struct drm_i915_private *dev_priv = gvt->dev_priv; 2870 int ret; 2871 2872 MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2873 MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL); 2874 MMIO_DH(FORCEWAKE_BLITTER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2875 MMIO_DH(FORCEWAKE_ACK_BLITTER_GEN9, D_SKL_PLUS, NULL, NULL); 2876 MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2877 MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL); 2878 2879 MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 2880 dp_aux_ch_ctl_mmio_write); 2881 MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 2882 dp_aux_ch_ctl_mmio_write); 2883 MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 2884 dp_aux_ch_ctl_mmio_write); 2885 2886 MMIO_D(HSW_PWR_WELL_CTL1, D_SKL_PLUS); 2887 MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write); 2888 2889 MMIO_DH(DBUF_CTL, D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write); 2890 2891 MMIO_D(GEN9_PG_ENABLE, D_SKL_PLUS); 2892 MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS); 2893 MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS); 2894 MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2895 MMIO_DH(MMCD_MISC_CTRL, D_SKL_PLUS, NULL, NULL); 2896 MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL); 2897 MMIO_D(DC_STATE_EN, D_SKL_PLUS); 2898 MMIO_D(DC_STATE_DEBUG, D_SKL_PLUS); 2899 MMIO_D(CDCLK_CTL, D_SKL_PLUS); 2900 MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write); 2901 MMIO_DH(LCPLL2_CTL, D_SKL_PLUS, NULL, skl_lcpll_write); 2902 MMIO_D(_MMIO(_DPLL1_CFGCR1), D_SKL_PLUS); 2903 MMIO_D(_MMIO(_DPLL2_CFGCR1), D_SKL_PLUS); 2904 MMIO_D(_MMIO(_DPLL3_CFGCR1), D_SKL_PLUS); 2905 MMIO_D(_MMIO(_DPLL1_CFGCR2), D_SKL_PLUS); 2906 MMIO_D(_MMIO(_DPLL2_CFGCR2), D_SKL_PLUS); 2907 MMIO_D(_MMIO(_DPLL3_CFGCR2), D_SKL_PLUS); 2908 MMIO_D(DPLL_CTRL1, D_SKL_PLUS); 2909 MMIO_D(DPLL_CTRL2, D_SKL_PLUS); 2910 MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL); 2911 2912 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); 2913 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); 2914 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); 2915 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); 2916 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); 2917 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); 2918 2919 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); 2920 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); 2921 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); 2922 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); 2923 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); 2924 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); 2925 2926 MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); 2927 MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); 2928 MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); 2929 MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); 2930 MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); 2931 MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); 2932 2933 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 2934 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 2935 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 2936 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); 2937 2938 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 2939 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 2940 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 2941 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); 2942 2943 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 2944 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 2945 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2946 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); 2947 2948 MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL); 2949 MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL); 2950 MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL); 2951 2952 MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2953 MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2954 MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2955 2956 MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2957 MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2958 MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2959 2960 MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2961 MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2962 MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2963 2964 MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2965 MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2966 MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2967 2968 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 2969 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 2970 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 2971 2972 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 2973 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 2974 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 2975 2976 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 2977 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 2978 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2979 2980 MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL); 2981 MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL); 2982 MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL); 2983 2984 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 2985 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 2986 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 2987 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); 2988 2989 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 2990 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 2991 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 2992 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); 2993 2994 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 2995 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 2996 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2997 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); 2998 2999 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL); 3000 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL); 3001 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL); 3002 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL); 3003 3004 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL); 3005 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL); 3006 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL); 3007 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL); 3008 3009 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL); 3010 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL); 3011 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL); 3012 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL); 3013 3014 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL); 3015 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL); 3016 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL); 3017 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL); 3018 3019 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL); 3020 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL); 3021 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL); 3022 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL); 3023 3024 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL); 3025 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL); 3026 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL); 3027 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL); 3028 3029 MMIO_D(_MMIO(_PLANE_CTL_3_A), D_SKL_PLUS); 3030 MMIO_D(_MMIO(_PLANE_CTL_3_B), D_SKL_PLUS); 3031 MMIO_D(_MMIO(0x72380), D_SKL_PLUS); 3032 MMIO_D(_MMIO(0x7239c), D_SKL_PLUS); 3033 MMIO_D(_MMIO(_PLANE_SURF_3_A), D_SKL_PLUS); 3034 3035 MMIO_D(CSR_SSP_BASE, D_SKL_PLUS); 3036 MMIO_D(CSR_HTP_SKL, D_SKL_PLUS); 3037 MMIO_D(CSR_LAST_WRITE, D_SKL_PLUS); 3038 3039 MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 3040 3041 MMIO_D(SKL_DFSM, D_SKL_PLUS); 3042 MMIO_D(DISPIO_CR_TX_BMU_CR0, D_SKL_PLUS); 3043 3044 MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS, 3045 NULL, NULL); 3046 MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS, 3047 NULL, NULL); 3048 3049 MMIO_D(RPM_CONFIG0, D_SKL_PLUS); 3050 MMIO_D(_MMIO(0xd08), D_SKL_PLUS); 3051 MMIO_D(RC6_LOCATION, D_SKL_PLUS); 3052 MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS, 3053 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 3054 MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, 3055 NULL, NULL); 3056 3057 /* TRTT */ 3058 MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 3059 MMIO_DFH(TRVATTL3PTRDW(1), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 3060 MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 3061 MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 3062 MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 3063 MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS, 3064 NULL, gen9_trtte_write); 3065 MMIO_DH(_MMIO(0x4dfc), D_SKL_PLUS, NULL, gen9_trtt_chicken_write); 3066 3067 MMIO_D(_MMIO(0x46430), D_SKL_PLUS); 3068 3069 MMIO_D(_MMIO(0x46520), D_SKL_PLUS); 3070 3071 MMIO_D(_MMIO(0xc403c), D_SKL_PLUS); 3072 MMIO_DFH(GEN8_GARBCNTL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 3073 MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write); 3074 3075 MMIO_D(_MMIO(0x65900), D_SKL_PLUS); 3076 MMIO_D(GEN6_STOLEN_RESERVED, D_SKL_PLUS); 3077 MMIO_D(_MMIO(0x4068), D_SKL_PLUS); 3078 MMIO_D(_MMIO(0x67054), D_SKL_PLUS); 3079 MMIO_D(_MMIO(0x6e560), D_SKL_PLUS); 3080 MMIO_D(_MMIO(0x6e554), D_SKL_PLUS); 3081 MMIO_D(_MMIO(0x2b20), D_SKL_PLUS); 3082 MMIO_D(_MMIO(0x65f00), D_SKL_PLUS); 3083 MMIO_D(_MMIO(0x65f08), D_SKL_PLUS); 3084 MMIO_D(_MMIO(0x320f0), D_SKL_PLUS); 3085 3086 MMIO_D(_MMIO(0x70034), D_SKL_PLUS); 3087 MMIO_D(_MMIO(0x71034), D_SKL_PLUS); 3088 MMIO_D(_MMIO(0x72034), D_SKL_PLUS); 3089 3090 MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A)), D_SKL_PLUS); 3091 MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B)), D_SKL_PLUS); 3092 MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C)), D_SKL_PLUS); 3093 MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A)), D_SKL_PLUS); 3094 MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B)), D_SKL_PLUS); 3095 MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C)), D_SKL_PLUS); 3096 MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A)), D_SKL_PLUS); 3097 MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)), D_SKL_PLUS); 3098 MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)), D_SKL_PLUS); 3099 3100 MMIO_D(_MMIO(0x44500), D_SKL_PLUS); 3101 #define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4) 3102 MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, 3103 NULL, csfe_chicken1_mmio_write); 3104 #undef CSFE_CHICKEN1_REG 3105 MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, 3106 NULL, NULL); 3107 MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, 3108 NULL, NULL); 3109 3110 MMIO_D(GAMT_CHKN_BIT_REG, D_KBL); 3111 MMIO_D(GEN9_CTX_PREEMPT_REG, D_KBL | D_SKL); 3112 3113 return 0; 3114 } 3115 3116 static int init_bxt_mmio_info(struct intel_gvt *gvt) 3117 { 3118 struct drm_i915_private *dev_priv = gvt->dev_priv; 3119 int ret; 3120 3121 MMIO_F(_MMIO(0x80000), 0x3000, 0, 0, 0, D_BXT, NULL, NULL); 3122 3123 MMIO_D(GEN7_SAMPLER_INSTDONE, D_BXT); 3124 MMIO_D(GEN7_ROW_INSTDONE, D_BXT); 3125 MMIO_D(GEN8_FAULT_TLB_DATA0, D_BXT); 3126 MMIO_D(GEN8_FAULT_TLB_DATA1, D_BXT); 3127 MMIO_D(ERROR_GEN6, D_BXT); 3128 MMIO_D(DONE_REG, D_BXT); 3129 MMIO_D(EIR, D_BXT); 3130 MMIO_D(PGTBL_ER, D_BXT); 3131 MMIO_D(_MMIO(0x4194), D_BXT); 3132 MMIO_D(_MMIO(0x4294), D_BXT); 3133 MMIO_D(_MMIO(0x4494), D_BXT); 3134 3135 MMIO_RING_D(RING_PSMI_CTL, D_BXT); 3136 MMIO_RING_D(RING_DMA_FADD, D_BXT); 3137 MMIO_RING_D(RING_DMA_FADD_UDW, D_BXT); 3138 MMIO_RING_D(RING_IPEHR, D_BXT); 3139 MMIO_RING_D(RING_INSTPS, D_BXT); 3140 MMIO_RING_D(RING_BBADDR_UDW, D_BXT); 3141 MMIO_RING_D(RING_BBSTATE, D_BXT); 3142 MMIO_RING_D(RING_IPEIR, D_BXT); 3143 3144 MMIO_F(SOFT_SCRATCH(0), 16 * 4, 0, 0, 0, D_BXT, NULL, NULL); 3145 3146 MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write); 3147 MMIO_D(BXT_RP_STATE_CAP, D_BXT); 3148 MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT, 3149 NULL, bxt_phy_ctl_family_write); 3150 MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT, 3151 NULL, bxt_phy_ctl_family_write); 3152 MMIO_D(BXT_PHY_CTL(PORT_A), D_BXT); 3153 MMIO_D(BXT_PHY_CTL(PORT_B), D_BXT); 3154 MMIO_D(BXT_PHY_CTL(PORT_C), D_BXT); 3155 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT, 3156 NULL, bxt_port_pll_enable_write); 3157 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT, 3158 NULL, bxt_port_pll_enable_write); 3159 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL, 3160 bxt_port_pll_enable_write); 3161 3162 MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY0), D_BXT); 3163 MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY0), D_BXT); 3164 MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY0), D_BXT); 3165 MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY0), D_BXT); 3166 MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY0), D_BXT); 3167 MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY0), D_BXT); 3168 MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY0), D_BXT); 3169 MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY0), D_BXT); 3170 MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY0), D_BXT); 3171 3172 MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY1), D_BXT); 3173 MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY1), D_BXT); 3174 MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY1), D_BXT); 3175 MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY1), D_BXT); 3176 MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY1), D_BXT); 3177 MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY1), D_BXT); 3178 MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY1), D_BXT); 3179 MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY1), D_BXT); 3180 MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY1), D_BXT); 3181 3182 MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH0), D_BXT); 3183 MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH0), D_BXT); 3184 MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH0), D_BXT); 3185 MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH0), D_BXT); 3186 MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH0), D_BXT); 3187 MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH0), D_BXT); 3188 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT, 3189 NULL, bxt_pcs_dw12_grp_write); 3190 MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH0), D_BXT); 3191 MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH0), D_BXT); 3192 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT, 3193 bxt_port_tx_dw3_read, NULL); 3194 MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH0), D_BXT); 3195 MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH0), D_BXT); 3196 MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH0), D_BXT); 3197 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT); 3198 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 1), D_BXT); 3199 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 2), D_BXT); 3200 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 3), D_BXT); 3201 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 0), D_BXT); 3202 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 1), D_BXT); 3203 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 2), D_BXT); 3204 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 3), D_BXT); 3205 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 6), D_BXT); 3206 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 8), D_BXT); 3207 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 9), D_BXT); 3208 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 10), D_BXT); 3209 3210 MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH1), D_BXT); 3211 MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH1), D_BXT); 3212 MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH1), D_BXT); 3213 MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH1), D_BXT); 3214 MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH1), D_BXT); 3215 MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH1), D_BXT); 3216 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT, 3217 NULL, bxt_pcs_dw12_grp_write); 3218 MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH1), D_BXT); 3219 MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH1), D_BXT); 3220 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT, 3221 bxt_port_tx_dw3_read, NULL); 3222 MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH1), D_BXT); 3223 MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH1), D_BXT); 3224 MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH1), D_BXT); 3225 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT); 3226 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 1), D_BXT); 3227 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 2), D_BXT); 3228 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 3), D_BXT); 3229 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 0), D_BXT); 3230 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 1), D_BXT); 3231 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 2), D_BXT); 3232 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 3), D_BXT); 3233 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 6), D_BXT); 3234 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 8), D_BXT); 3235 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 9), D_BXT); 3236 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 10), D_BXT); 3237 3238 MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY1, DPIO_CH0), D_BXT); 3239 MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY1, DPIO_CH0), D_BXT); 3240 MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY1, DPIO_CH0), D_BXT); 3241 MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY1, DPIO_CH0), D_BXT); 3242 MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY1, DPIO_CH0), D_BXT); 3243 MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY1, DPIO_CH0), D_BXT); 3244 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT, 3245 NULL, bxt_pcs_dw12_grp_write); 3246 MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY1, DPIO_CH0), D_BXT); 3247 MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY1, DPIO_CH0), D_BXT); 3248 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT, 3249 bxt_port_tx_dw3_read, NULL); 3250 MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY1, DPIO_CH0), D_BXT); 3251 MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY1, DPIO_CH0), D_BXT); 3252 MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY1, DPIO_CH0), D_BXT); 3253 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT); 3254 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 1), D_BXT); 3255 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 2), D_BXT); 3256 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 3), D_BXT); 3257 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 0), D_BXT); 3258 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 1), D_BXT); 3259 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 2), D_BXT); 3260 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 3), D_BXT); 3261 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 6), D_BXT); 3262 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 8), D_BXT); 3263 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 9), D_BXT); 3264 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 10), D_BXT); 3265 3266 MMIO_D(BXT_DE_PLL_CTL, D_BXT); 3267 MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write); 3268 MMIO_D(BXT_DSI_PLL_CTL, D_BXT); 3269 MMIO_D(BXT_DSI_PLL_ENABLE, D_BXT); 3270 3271 MMIO_D(GEN9_CLKGATE_DIS_0, D_BXT); 3272 MMIO_D(GEN9_CLKGATE_DIS_4, D_BXT); 3273 3274 MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_A), D_BXT); 3275 MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT); 3276 MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C), D_BXT); 3277 3278 MMIO_D(RC6_CTX_BASE, D_BXT); 3279 3280 MMIO_D(GEN8_PUSHBUS_CONTROL, D_BXT); 3281 MMIO_D(GEN8_PUSHBUS_ENABLE, D_BXT); 3282 MMIO_D(GEN8_PUSHBUS_SHIFT, D_BXT); 3283 MMIO_D(GEN6_GFXPAUSE, D_BXT); 3284 MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL); 3285 3286 MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL); 3287 3288 return 0; 3289 } 3290 3291 static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt, 3292 unsigned int offset) 3293 { 3294 unsigned long device = intel_gvt_get_device_type(gvt); 3295 struct gvt_mmio_block *block = gvt->mmio.mmio_block; 3296 int num = gvt->mmio.num_mmio_block; 3297 int i; 3298 3299 for (i = 0; i < num; i++, block++) { 3300 if (!(device & block->device)) 3301 continue; 3302 if (offset >= i915_mmio_reg_offset(block->offset) && 3303 offset < i915_mmio_reg_offset(block->offset) + block->size) 3304 return block; 3305 } 3306 return NULL; 3307 } 3308 3309 /** 3310 * intel_gvt_clean_mmio_info - clean up MMIO information table for GVT device 3311 * @gvt: GVT device 3312 * 3313 * This function is called at the driver unloading stage, to clean up the MMIO 3314 * information table of GVT device 3315 * 3316 */ 3317 void intel_gvt_clean_mmio_info(struct intel_gvt *gvt) 3318 { 3319 struct hlist_node *tmp; 3320 struct intel_gvt_mmio_info *e; 3321 int i; 3322 3323 hash_for_each_safe(gvt->mmio.mmio_info_table, i, tmp, e, node) 3324 kfree(e); 3325 3326 vfree(gvt->mmio.mmio_attribute); 3327 gvt->mmio.mmio_attribute = NULL; 3328 } 3329 3330 /* Special MMIO blocks. */ 3331 static struct gvt_mmio_block mmio_blocks[] = { 3332 {D_SKL_PLUS, _MMIO(CSR_MMIO_START_RANGE), 0x3000, NULL, NULL}, 3333 {D_ALL, _MMIO(MCHBAR_MIRROR_BASE_SNB), 0x40000, NULL, NULL}, 3334 {D_ALL, _MMIO(VGT_PVINFO_PAGE), VGT_PVINFO_SIZE, 3335 pvinfo_mmio_read, pvinfo_mmio_write}, 3336 {D_ALL, LGC_PALETTE(PIPE_A, 0), 1024, NULL, NULL}, 3337 {D_ALL, LGC_PALETTE(PIPE_B, 0), 1024, NULL, NULL}, 3338 {D_ALL, LGC_PALETTE(PIPE_C, 0), 1024, NULL, NULL}, 3339 }; 3340 3341 /** 3342 * intel_gvt_setup_mmio_info - setup MMIO information table for GVT device 3343 * @gvt: GVT device 3344 * 3345 * This function is called at the initialization stage, to setup the MMIO 3346 * information table for GVT device 3347 * 3348 * Returns: 3349 * zero on success, negative if failed. 3350 */ 3351 int intel_gvt_setup_mmio_info(struct intel_gvt *gvt) 3352 { 3353 struct intel_gvt_device_info *info = &gvt->device_info; 3354 struct drm_i915_private *dev_priv = gvt->dev_priv; 3355 int size = info->mmio_size / 4 * sizeof(*gvt->mmio.mmio_attribute); 3356 int ret; 3357 3358 gvt->mmio.mmio_attribute = vzalloc(size); 3359 if (!gvt->mmio.mmio_attribute) 3360 return -ENOMEM; 3361 3362 ret = init_generic_mmio_info(gvt); 3363 if (ret) 3364 goto err; 3365 3366 if (IS_BROADWELL(dev_priv)) { 3367 ret = init_broadwell_mmio_info(gvt); 3368 if (ret) 3369 goto err; 3370 } else if (IS_SKYLAKE(dev_priv) 3371 || IS_KABYLAKE(dev_priv) 3372 || IS_COFFEELAKE(dev_priv)) { 3373 ret = init_broadwell_mmio_info(gvt); 3374 if (ret) 3375 goto err; 3376 ret = init_skl_mmio_info(gvt); 3377 if (ret) 3378 goto err; 3379 } else if (IS_BROXTON(dev_priv)) { 3380 ret = init_broadwell_mmio_info(gvt); 3381 if (ret) 3382 goto err; 3383 ret = init_skl_mmio_info(gvt); 3384 if (ret) 3385 goto err; 3386 ret = init_bxt_mmio_info(gvt); 3387 if (ret) 3388 goto err; 3389 } 3390 3391 gvt->mmio.mmio_block = mmio_blocks; 3392 gvt->mmio.num_mmio_block = ARRAY_SIZE(mmio_blocks); 3393 3394 return 0; 3395 err: 3396 intel_gvt_clean_mmio_info(gvt); 3397 return ret; 3398 } 3399 3400 /** 3401 * intel_gvt_for_each_tracked_mmio - iterate each tracked mmio 3402 * @gvt: a GVT device 3403 * @handler: the handler 3404 * @data: private data given to handler 3405 * 3406 * Returns: 3407 * Zero on success, negative error code if failed. 3408 */ 3409 int intel_gvt_for_each_tracked_mmio(struct intel_gvt *gvt, 3410 int (*handler)(struct intel_gvt *gvt, u32 offset, void *data), 3411 void *data) 3412 { 3413 struct gvt_mmio_block *block = gvt->mmio.mmio_block; 3414 struct intel_gvt_mmio_info *e; 3415 int i, j, ret; 3416 3417 hash_for_each(gvt->mmio.mmio_info_table, i, e, node) { 3418 ret = handler(gvt, e->offset, data); 3419 if (ret) 3420 return ret; 3421 } 3422 3423 for (i = 0; i < gvt->mmio.num_mmio_block; i++, block++) { 3424 /* pvinfo data doesn't come from hw mmio */ 3425 if (i915_mmio_reg_offset(block->offset) == VGT_PVINFO_PAGE) 3426 continue; 3427 3428 for (j = 0; j < block->size; j += 4) { 3429 ret = handler(gvt, 3430 i915_mmio_reg_offset(block->offset) + j, 3431 data); 3432 if (ret) 3433 return ret; 3434 } 3435 } 3436 return 0; 3437 } 3438 3439 /** 3440 * intel_vgpu_default_mmio_read - default MMIO read handler 3441 * @vgpu: a vGPU 3442 * @offset: access offset 3443 * @p_data: data return buffer 3444 * @bytes: access data length 3445 * 3446 * Returns: 3447 * Zero on success, negative error code if failed. 3448 */ 3449 int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 3450 void *p_data, unsigned int bytes) 3451 { 3452 read_vreg(vgpu, offset, p_data, bytes); 3453 return 0; 3454 } 3455 3456 /** 3457 * intel_t_default_mmio_write - default MMIO write handler 3458 * @vgpu: a vGPU 3459 * @offset: access offset 3460 * @p_data: write data buffer 3461 * @bytes: access data length 3462 * 3463 * Returns: 3464 * Zero on success, negative error code if failed. 3465 */ 3466 int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 3467 void *p_data, unsigned int bytes) 3468 { 3469 write_vreg(vgpu, offset, p_data, bytes); 3470 return 0; 3471 } 3472 3473 /** 3474 * intel_vgpu_mask_mmio_write - write mask register 3475 * @vgpu: a vGPU 3476 * @offset: access offset 3477 * @p_data: write data buffer 3478 * @bytes: access data length 3479 * 3480 * Returns: 3481 * Zero on success, negative error code if failed. 3482 */ 3483 int intel_vgpu_mask_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 3484 void *p_data, unsigned int bytes) 3485 { 3486 u32 mask, old_vreg; 3487 3488 old_vreg = vgpu_vreg(vgpu, offset); 3489 write_vreg(vgpu, offset, p_data, bytes); 3490 mask = vgpu_vreg(vgpu, offset) >> 16; 3491 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask) | 3492 (vgpu_vreg(vgpu, offset) & mask); 3493 3494 return 0; 3495 } 3496 3497 /** 3498 * intel_gvt_in_force_nonpriv_whitelist - if a mmio is in whitelist to be 3499 * force-nopriv register 3500 * 3501 * @gvt: a GVT device 3502 * @offset: register offset 3503 * 3504 * Returns: 3505 * True if the register is in force-nonpriv whitelist; 3506 * False if outside; 3507 */ 3508 bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt, 3509 unsigned int offset) 3510 { 3511 return in_whitelist(offset); 3512 } 3513 3514 /** 3515 * intel_vgpu_mmio_reg_rw - emulate tracked mmio registers 3516 * @vgpu: a vGPU 3517 * @offset: register offset 3518 * @pdata: data buffer 3519 * @bytes: data length 3520 * @is_read: read or write 3521 * 3522 * Returns: 3523 * Zero on success, negative error code if failed. 3524 */ 3525 int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset, 3526 void *pdata, unsigned int bytes, bool is_read) 3527 { 3528 struct intel_gvt *gvt = vgpu->gvt; 3529 struct intel_gvt_mmio_info *mmio_info; 3530 struct gvt_mmio_block *mmio_block; 3531 gvt_mmio_func func; 3532 int ret; 3533 3534 if (WARN_ON(bytes > 8)) 3535 return -EINVAL; 3536 3537 /* 3538 * Handle special MMIO blocks. 3539 */ 3540 mmio_block = find_mmio_block(gvt, offset); 3541 if (mmio_block) { 3542 func = is_read ? mmio_block->read : mmio_block->write; 3543 if (func) 3544 return func(vgpu, offset, pdata, bytes); 3545 goto default_rw; 3546 } 3547 3548 /* 3549 * Normal tracked MMIOs. 3550 */ 3551 mmio_info = find_mmio_info(gvt, offset); 3552 if (!mmio_info) { 3553 gvt_dbg_mmio("untracked MMIO %08x len %d\n", offset, bytes); 3554 goto default_rw; 3555 } 3556 3557 if (is_read) 3558 return mmio_info->read(vgpu, offset, pdata, bytes); 3559 else { 3560 u64 ro_mask = mmio_info->ro_mask; 3561 u32 old_vreg = 0; 3562 u64 data = 0; 3563 3564 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) { 3565 old_vreg = vgpu_vreg(vgpu, offset); 3566 } 3567 3568 if (likely(!ro_mask)) 3569 ret = mmio_info->write(vgpu, offset, pdata, bytes); 3570 else if (!~ro_mask) { 3571 gvt_vgpu_err("try to write RO reg %x\n", offset); 3572 return 0; 3573 } else { 3574 /* keep the RO bits in the virtual register */ 3575 memcpy(&data, pdata, bytes); 3576 data &= ~ro_mask; 3577 data |= vgpu_vreg(vgpu, offset) & ro_mask; 3578 ret = mmio_info->write(vgpu, offset, &data, bytes); 3579 } 3580 3581 /* higher 16bits of mode ctl regs are mask bits for change */ 3582 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) { 3583 u32 mask = vgpu_vreg(vgpu, offset) >> 16; 3584 3585 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask) 3586 | (vgpu_vreg(vgpu, offset) & mask); 3587 } 3588 } 3589 3590 return ret; 3591 3592 default_rw: 3593 return is_read ? 3594 intel_vgpu_default_mmio_read(vgpu, offset, pdata, bytes) : 3595 intel_vgpu_default_mmio_write(vgpu, offset, pdata, bytes); 3596 } 3597