1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Kevin Tian <kevin.tian@intel.com> 25 * Eddie Dong <eddie.dong@intel.com> 26 * Zhiyuan Lv <zhiyuan.lv@intel.com> 27 * 28 * Contributors: 29 * Min He <min.he@intel.com> 30 * Tina Zhang <tina.zhang@intel.com> 31 * Pei Zhang <pei.zhang@intel.com> 32 * Niu Bing <bing.niu@intel.com> 33 * Ping Gao <ping.a.gao@intel.com> 34 * Zhi Wang <zhi.a.wang@intel.com> 35 * 36 37 */ 38 39 #include "i915_drv.h" 40 #include "gvt.h" 41 #include "i915_pvinfo.h" 42 43 /* XXX FIXME i915 has changed PP_XXX definition */ 44 #define PCH_PP_STATUS _MMIO(0xc7200) 45 #define PCH_PP_CONTROL _MMIO(0xc7204) 46 #define PCH_PP_ON_DELAYS _MMIO(0xc7208) 47 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c) 48 #define PCH_PP_DIVISOR _MMIO(0xc7210) 49 50 unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt) 51 { 52 if (IS_BROADWELL(gvt->dev_priv)) 53 return D_BDW; 54 else if (IS_SKYLAKE(gvt->dev_priv)) 55 return D_SKL; 56 else if (IS_KABYLAKE(gvt->dev_priv)) 57 return D_KBL; 58 else if (IS_BROXTON(gvt->dev_priv)) 59 return D_BXT; 60 61 return 0; 62 } 63 64 bool intel_gvt_match_device(struct intel_gvt *gvt, 65 unsigned long device) 66 { 67 return intel_gvt_get_device_type(gvt) & device; 68 } 69 70 static void read_vreg(struct intel_vgpu *vgpu, unsigned int offset, 71 void *p_data, unsigned int bytes) 72 { 73 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); 74 } 75 76 static void write_vreg(struct intel_vgpu *vgpu, unsigned int offset, 77 void *p_data, unsigned int bytes) 78 { 79 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes); 80 } 81 82 static struct intel_gvt_mmio_info *find_mmio_info(struct intel_gvt *gvt, 83 unsigned int offset) 84 { 85 struct intel_gvt_mmio_info *e; 86 87 hash_for_each_possible(gvt->mmio.mmio_info_table, e, node, offset) { 88 if (e->offset == offset) 89 return e; 90 } 91 return NULL; 92 } 93 94 static int new_mmio_info(struct intel_gvt *gvt, 95 u32 offset, u8 flags, u32 size, 96 u32 addr_mask, u32 ro_mask, u32 device, 97 gvt_mmio_func read, gvt_mmio_func write) 98 { 99 struct intel_gvt_mmio_info *info, *p; 100 u32 start, end, i; 101 102 if (!intel_gvt_match_device(gvt, device)) 103 return 0; 104 105 if (WARN_ON(!IS_ALIGNED(offset, 4))) 106 return -EINVAL; 107 108 start = offset; 109 end = offset + size; 110 111 for (i = start; i < end; i += 4) { 112 info = kzalloc(sizeof(*info), GFP_KERNEL); 113 if (!info) 114 return -ENOMEM; 115 116 info->offset = i; 117 p = find_mmio_info(gvt, info->offset); 118 if (p) { 119 WARN(1, "dup mmio definition offset %x\n", 120 info->offset); 121 kfree(info); 122 123 /* We return -EEXIST here to make GVT-g load fail. 124 * So duplicated MMIO can be found as soon as 125 * possible. 126 */ 127 return -EEXIST; 128 } 129 130 info->ro_mask = ro_mask; 131 info->device = device; 132 info->read = read ? read : intel_vgpu_default_mmio_read; 133 info->write = write ? write : intel_vgpu_default_mmio_write; 134 gvt->mmio.mmio_attribute[info->offset / 4] = flags; 135 INIT_HLIST_NODE(&info->node); 136 hash_add(gvt->mmio.mmio_info_table, &info->node, info->offset); 137 gvt->mmio.num_tracked_mmio++; 138 } 139 return 0; 140 } 141 142 /** 143 * intel_gvt_render_mmio_to_ring_id - convert a mmio offset into ring id 144 * @gvt: a GVT device 145 * @offset: register offset 146 * 147 * Returns: 148 * Ring ID on success, negative error code if failed. 149 */ 150 int intel_gvt_render_mmio_to_ring_id(struct intel_gvt *gvt, 151 unsigned int offset) 152 { 153 enum intel_engine_id id; 154 struct intel_engine_cs *engine; 155 156 offset &= ~GENMASK(11, 0); 157 for_each_engine(engine, gvt->dev_priv, id) { 158 if (engine->mmio_base == offset) 159 return id; 160 } 161 return -ENODEV; 162 } 163 164 #define offset_to_fence_num(offset) \ 165 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3) 166 167 #define fence_num_to_offset(num) \ 168 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) 169 170 171 void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason) 172 { 173 switch (reason) { 174 case GVT_FAILSAFE_UNSUPPORTED_GUEST: 175 pr_err("Detected your guest driver doesn't support GVT-g.\n"); 176 break; 177 case GVT_FAILSAFE_INSUFFICIENT_RESOURCE: 178 pr_err("Graphics resource is not enough for the guest\n"); 179 break; 180 case GVT_FAILSAFE_GUEST_ERR: 181 pr_err("GVT Internal error for the guest\n"); 182 break; 183 default: 184 break; 185 } 186 pr_err("Now vgpu %d will enter failsafe mode.\n", vgpu->id); 187 vgpu->failsafe = true; 188 } 189 190 static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu, 191 unsigned int fence_num, void *p_data, unsigned int bytes) 192 { 193 unsigned int max_fence = vgpu_fence_sz(vgpu); 194 195 if (fence_num >= max_fence) { 196 gvt_vgpu_err("access oob fence reg %d/%d\n", 197 fence_num, max_fence); 198 199 /* When guest access oob fence regs without access 200 * pv_info first, we treat guest not supporting GVT, 201 * and we will let vgpu enter failsafe mode. 202 */ 203 if (!vgpu->pv_notified) 204 enter_failsafe_mode(vgpu, 205 GVT_FAILSAFE_UNSUPPORTED_GUEST); 206 207 memset(p_data, 0, bytes); 208 return -EINVAL; 209 } 210 return 0; 211 } 212 213 static int fence_mmio_read(struct intel_vgpu *vgpu, unsigned int off, 214 void *p_data, unsigned int bytes) 215 { 216 int ret; 217 218 ret = sanitize_fence_mmio_access(vgpu, offset_to_fence_num(off), 219 p_data, bytes); 220 if (ret) 221 return ret; 222 read_vreg(vgpu, off, p_data, bytes); 223 return 0; 224 } 225 226 static int fence_mmio_write(struct intel_vgpu *vgpu, unsigned int off, 227 void *p_data, unsigned int bytes) 228 { 229 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 230 unsigned int fence_num = offset_to_fence_num(off); 231 int ret; 232 233 ret = sanitize_fence_mmio_access(vgpu, fence_num, p_data, bytes); 234 if (ret) 235 return ret; 236 write_vreg(vgpu, off, p_data, bytes); 237 238 mmio_hw_access_pre(dev_priv); 239 intel_vgpu_write_fence(vgpu, fence_num, 240 vgpu_vreg64(vgpu, fence_num_to_offset(fence_num))); 241 mmio_hw_access_post(dev_priv); 242 return 0; 243 } 244 245 #define CALC_MODE_MASK_REG(old, new) \ 246 (((new) & GENMASK(31, 16)) \ 247 | ((((old) & GENMASK(15, 0)) & ~((new) >> 16)) \ 248 | ((new) & ((new) >> 16)))) 249 250 static int mul_force_wake_write(struct intel_vgpu *vgpu, 251 unsigned int offset, void *p_data, unsigned int bytes) 252 { 253 u32 old, new; 254 uint32_t ack_reg_offset; 255 256 old = vgpu_vreg(vgpu, offset); 257 new = CALC_MODE_MASK_REG(old, *(u32 *)p_data); 258 259 if (IS_SKYLAKE(vgpu->gvt->dev_priv) 260 || IS_KABYLAKE(vgpu->gvt->dev_priv) 261 || IS_BROXTON(vgpu->gvt->dev_priv)) { 262 switch (offset) { 263 case FORCEWAKE_RENDER_GEN9_REG: 264 ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG; 265 break; 266 case FORCEWAKE_BLITTER_GEN9_REG: 267 ack_reg_offset = FORCEWAKE_ACK_BLITTER_GEN9_REG; 268 break; 269 case FORCEWAKE_MEDIA_GEN9_REG: 270 ack_reg_offset = FORCEWAKE_ACK_MEDIA_GEN9_REG; 271 break; 272 default: 273 /*should not hit here*/ 274 gvt_vgpu_err("invalid forcewake offset 0x%x\n", offset); 275 return -EINVAL; 276 } 277 } else { 278 ack_reg_offset = FORCEWAKE_ACK_HSW_REG; 279 } 280 281 vgpu_vreg(vgpu, offset) = new; 282 vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0)); 283 return 0; 284 } 285 286 static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 287 void *p_data, unsigned int bytes) 288 { 289 unsigned int engine_mask = 0; 290 u32 data; 291 292 write_vreg(vgpu, offset, p_data, bytes); 293 data = vgpu_vreg(vgpu, offset); 294 295 if (data & GEN6_GRDOM_FULL) { 296 gvt_dbg_mmio("vgpu%d: request full GPU reset\n", vgpu->id); 297 engine_mask = ALL_ENGINES; 298 } else { 299 if (data & GEN6_GRDOM_RENDER) { 300 gvt_dbg_mmio("vgpu%d: request RCS reset\n", vgpu->id); 301 engine_mask |= (1 << RCS); 302 } 303 if (data & GEN6_GRDOM_MEDIA) { 304 gvt_dbg_mmio("vgpu%d: request VCS reset\n", vgpu->id); 305 engine_mask |= (1 << VCS); 306 } 307 if (data & GEN6_GRDOM_BLT) { 308 gvt_dbg_mmio("vgpu%d: request BCS Reset\n", vgpu->id); 309 engine_mask |= (1 << BCS); 310 } 311 if (data & GEN6_GRDOM_VECS) { 312 gvt_dbg_mmio("vgpu%d: request VECS Reset\n", vgpu->id); 313 engine_mask |= (1 << VECS); 314 } 315 if (data & GEN8_GRDOM_MEDIA2) { 316 gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id); 317 if (HAS_BSD2(vgpu->gvt->dev_priv)) 318 engine_mask |= (1 << VCS2); 319 } 320 } 321 322 /* vgpu_lock already hold by emulate mmio r/w */ 323 intel_gvt_reset_vgpu_locked(vgpu, false, engine_mask); 324 325 /* sw will wait for the device to ack the reset request */ 326 vgpu_vreg(vgpu, offset) = 0; 327 328 return 0; 329 } 330 331 static int gmbus_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 332 void *p_data, unsigned int bytes) 333 { 334 return intel_gvt_i2c_handle_gmbus_read(vgpu, offset, p_data, bytes); 335 } 336 337 static int gmbus_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 338 void *p_data, unsigned int bytes) 339 { 340 return intel_gvt_i2c_handle_gmbus_write(vgpu, offset, p_data, bytes); 341 } 342 343 static int pch_pp_control_mmio_write(struct intel_vgpu *vgpu, 344 unsigned int offset, void *p_data, unsigned int bytes) 345 { 346 write_vreg(vgpu, offset, p_data, bytes); 347 348 if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) { 349 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_ON; 350 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE; 351 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN; 352 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE; 353 354 } else 355 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= 356 ~(PP_ON | PP_SEQUENCE_POWER_DOWN 357 | PP_CYCLE_DELAY_ACTIVE); 358 return 0; 359 } 360 361 static int transconf_mmio_write(struct intel_vgpu *vgpu, 362 unsigned int offset, void *p_data, unsigned int bytes) 363 { 364 write_vreg(vgpu, offset, p_data, bytes); 365 366 if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE) 367 vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE; 368 else 369 vgpu_vreg(vgpu, offset) &= ~TRANS_STATE_ENABLE; 370 return 0; 371 } 372 373 static int lcpll_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 374 void *p_data, unsigned int bytes) 375 { 376 write_vreg(vgpu, offset, p_data, bytes); 377 378 if (vgpu_vreg(vgpu, offset) & LCPLL_PLL_DISABLE) 379 vgpu_vreg(vgpu, offset) &= ~LCPLL_PLL_LOCK; 380 else 381 vgpu_vreg(vgpu, offset) |= LCPLL_PLL_LOCK; 382 383 if (vgpu_vreg(vgpu, offset) & LCPLL_CD_SOURCE_FCLK) 384 vgpu_vreg(vgpu, offset) |= LCPLL_CD_SOURCE_FCLK_DONE; 385 else 386 vgpu_vreg(vgpu, offset) &= ~LCPLL_CD_SOURCE_FCLK_DONE; 387 388 return 0; 389 } 390 391 static int dpy_reg_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 392 void *p_data, unsigned int bytes) 393 { 394 switch (offset) { 395 case 0xe651c: 396 case 0xe661c: 397 case 0xe671c: 398 case 0xe681c: 399 vgpu_vreg(vgpu, offset) = 1 << 17; 400 break; 401 case 0xe6c04: 402 vgpu_vreg(vgpu, offset) = 0x3; 403 break; 404 case 0xe6e1c: 405 vgpu_vreg(vgpu, offset) = 0x2f << 16; 406 break; 407 default: 408 return -EINVAL; 409 } 410 411 read_vreg(vgpu, offset, p_data, bytes); 412 return 0; 413 } 414 415 static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 416 void *p_data, unsigned int bytes) 417 { 418 u32 data; 419 420 write_vreg(vgpu, offset, p_data, bytes); 421 data = vgpu_vreg(vgpu, offset); 422 423 if (data & PIPECONF_ENABLE) 424 vgpu_vreg(vgpu, offset) |= I965_PIPECONF_ACTIVE; 425 else 426 vgpu_vreg(vgpu, offset) &= ~I965_PIPECONF_ACTIVE; 427 /* vgpu_lock already hold by emulate mmio r/w */ 428 mutex_unlock(&vgpu->vgpu_lock); 429 intel_gvt_check_vblank_emulation(vgpu->gvt); 430 mutex_lock(&vgpu->vgpu_lock); 431 return 0; 432 } 433 434 /* ascendingly sorted */ 435 static i915_reg_t force_nonpriv_white_list[] = { 436 GEN9_CS_DEBUG_MODE1, //_MMIO(0x20ec) 437 GEN9_CTX_PREEMPT_REG,//_MMIO(0x2248) 438 GEN8_CS_CHICKEN1,//_MMIO(0x2580) 439 _MMIO(0x2690), 440 _MMIO(0x2694), 441 _MMIO(0x2698), 442 _MMIO(0x4de0), 443 _MMIO(0x4de4), 444 _MMIO(0x4dfc), 445 GEN7_COMMON_SLICE_CHICKEN1,//_MMIO(0x7010) 446 _MMIO(0x7014), 447 HDC_CHICKEN0,//_MMIO(0x7300) 448 GEN8_HDC_CHICKEN1,//_MMIO(0x7304) 449 _MMIO(0x7700), 450 _MMIO(0x7704), 451 _MMIO(0x7708), 452 _MMIO(0x770c), 453 _MMIO(0xb110), 454 GEN8_L3SQCREG4,//_MMIO(0xb118) 455 _MMIO(0xe100), 456 _MMIO(0xe18c), 457 _MMIO(0xe48c), 458 _MMIO(0xe5f4), 459 }; 460 461 /* a simple bsearch */ 462 static inline bool in_whitelist(unsigned int reg) 463 { 464 int left = 0, right = ARRAY_SIZE(force_nonpriv_white_list); 465 i915_reg_t *array = force_nonpriv_white_list; 466 467 while (left < right) { 468 int mid = (left + right)/2; 469 470 if (reg > array[mid].reg) 471 left = mid + 1; 472 else if (reg < array[mid].reg) 473 right = mid; 474 else 475 return true; 476 } 477 return false; 478 } 479 480 static int force_nonpriv_write(struct intel_vgpu *vgpu, 481 unsigned int offset, void *p_data, unsigned int bytes) 482 { 483 u32 reg_nonpriv = *(u32 *)p_data; 484 int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset); 485 u32 ring_base; 486 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 487 int ret = -EINVAL; 488 489 if ((bytes != 4) || ((offset & (bytes - 1)) != 0) || ring_id < 0) { 490 gvt_err("vgpu(%d) ring %d Invalid FORCE_NONPRIV offset %x(%dB)\n", 491 vgpu->id, ring_id, offset, bytes); 492 return ret; 493 } 494 495 ring_base = dev_priv->engine[ring_id]->mmio_base; 496 497 if (in_whitelist(reg_nonpriv) || 498 reg_nonpriv == i915_mmio_reg_offset(RING_NOPID(ring_base))) { 499 ret = intel_vgpu_default_mmio_write(vgpu, offset, p_data, 500 bytes); 501 } else 502 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x at offset %x\n", 503 vgpu->id, reg_nonpriv, offset); 504 505 return 0; 506 } 507 508 static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 509 void *p_data, unsigned int bytes) 510 { 511 write_vreg(vgpu, offset, p_data, bytes); 512 513 if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) { 514 vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE; 515 } else { 516 vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE; 517 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E))) 518 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) 519 &= ~DP_TP_STATUS_AUTOTRAIN_DONE; 520 } 521 return 0; 522 } 523 524 static int fdi_rx_iir_mmio_write(struct intel_vgpu *vgpu, 525 unsigned int offset, void *p_data, unsigned int bytes) 526 { 527 vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data; 528 return 0; 529 } 530 531 #define FDI_LINK_TRAIN_PATTERN1 0 532 #define FDI_LINK_TRAIN_PATTERN2 1 533 534 static int fdi_auto_training_started(struct intel_vgpu *vgpu) 535 { 536 u32 ddi_buf_ctl = vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_E)); 537 u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL); 538 u32 tx_ctl = vgpu_vreg_t(vgpu, DP_TP_CTL(PORT_E)); 539 540 if ((ddi_buf_ctl & DDI_BUF_CTL_ENABLE) && 541 (rx_ctl & FDI_RX_ENABLE) && 542 (rx_ctl & FDI_AUTO_TRAINING) && 543 (tx_ctl & DP_TP_CTL_ENABLE) && 544 (tx_ctl & DP_TP_CTL_FDI_AUTOTRAIN)) 545 return 1; 546 else 547 return 0; 548 } 549 550 static int check_fdi_rx_train_status(struct intel_vgpu *vgpu, 551 enum pipe pipe, unsigned int train_pattern) 552 { 553 i915_reg_t fdi_rx_imr, fdi_tx_ctl, fdi_rx_ctl; 554 unsigned int fdi_rx_check_bits, fdi_tx_check_bits; 555 unsigned int fdi_rx_train_bits, fdi_tx_train_bits; 556 unsigned int fdi_iir_check_bits; 557 558 fdi_rx_imr = FDI_RX_IMR(pipe); 559 fdi_tx_ctl = FDI_TX_CTL(pipe); 560 fdi_rx_ctl = FDI_RX_CTL(pipe); 561 562 if (train_pattern == FDI_LINK_TRAIN_PATTERN1) { 563 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_1_CPT; 564 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_1; 565 fdi_iir_check_bits = FDI_RX_BIT_LOCK; 566 } else if (train_pattern == FDI_LINK_TRAIN_PATTERN2) { 567 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_2_CPT; 568 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_2; 569 fdi_iir_check_bits = FDI_RX_SYMBOL_LOCK; 570 } else { 571 gvt_vgpu_err("Invalid train pattern %d\n", train_pattern); 572 return -EINVAL; 573 } 574 575 fdi_rx_check_bits = FDI_RX_ENABLE | fdi_rx_train_bits; 576 fdi_tx_check_bits = FDI_TX_ENABLE | fdi_tx_train_bits; 577 578 /* If imr bit has been masked */ 579 if (vgpu_vreg_t(vgpu, fdi_rx_imr) & fdi_iir_check_bits) 580 return 0; 581 582 if (((vgpu_vreg_t(vgpu, fdi_tx_ctl) & fdi_tx_check_bits) 583 == fdi_tx_check_bits) 584 && ((vgpu_vreg_t(vgpu, fdi_rx_ctl) & fdi_rx_check_bits) 585 == fdi_rx_check_bits)) 586 return 1; 587 else 588 return 0; 589 } 590 591 #define INVALID_INDEX (~0U) 592 593 static unsigned int calc_index(unsigned int offset, unsigned int start, 594 unsigned int next, unsigned int end, i915_reg_t i915_end) 595 { 596 unsigned int range = next - start; 597 598 if (!end) 599 end = i915_mmio_reg_offset(i915_end); 600 if (offset < start || offset > end) 601 return INVALID_INDEX; 602 offset -= start; 603 return offset / range; 604 } 605 606 #define FDI_RX_CTL_TO_PIPE(offset) \ 607 calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, 0, FDI_RX_CTL(PIPE_C)) 608 609 #define FDI_TX_CTL_TO_PIPE(offset) \ 610 calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, 0, FDI_TX_CTL(PIPE_C)) 611 612 #define FDI_RX_IMR_TO_PIPE(offset) \ 613 calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, 0, FDI_RX_IMR(PIPE_C)) 614 615 static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu, 616 unsigned int offset, void *p_data, unsigned int bytes) 617 { 618 i915_reg_t fdi_rx_iir; 619 unsigned int index; 620 int ret; 621 622 if (FDI_RX_CTL_TO_PIPE(offset) != INVALID_INDEX) 623 index = FDI_RX_CTL_TO_PIPE(offset); 624 else if (FDI_TX_CTL_TO_PIPE(offset) != INVALID_INDEX) 625 index = FDI_TX_CTL_TO_PIPE(offset); 626 else if (FDI_RX_IMR_TO_PIPE(offset) != INVALID_INDEX) 627 index = FDI_RX_IMR_TO_PIPE(offset); 628 else { 629 gvt_vgpu_err("Unsupport registers %x\n", offset); 630 return -EINVAL; 631 } 632 633 write_vreg(vgpu, offset, p_data, bytes); 634 635 fdi_rx_iir = FDI_RX_IIR(index); 636 637 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN1); 638 if (ret < 0) 639 return ret; 640 if (ret) 641 vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK; 642 643 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN2); 644 if (ret < 0) 645 return ret; 646 if (ret) 647 vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK; 648 649 if (offset == _FDI_RXA_CTL) 650 if (fdi_auto_training_started(vgpu)) 651 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) |= 652 DP_TP_STATUS_AUTOTRAIN_DONE; 653 return 0; 654 } 655 656 #define DP_TP_CTL_TO_PORT(offset) \ 657 calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, 0, DP_TP_CTL(PORT_E)) 658 659 static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 660 void *p_data, unsigned int bytes) 661 { 662 i915_reg_t status_reg; 663 unsigned int index; 664 u32 data; 665 666 write_vreg(vgpu, offset, p_data, bytes); 667 668 index = DP_TP_CTL_TO_PORT(offset); 669 data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8; 670 if (data == 0x2) { 671 status_reg = DP_TP_STATUS(index); 672 vgpu_vreg_t(vgpu, status_reg) |= (1 << 25); 673 } 674 return 0; 675 } 676 677 static int dp_tp_status_mmio_write(struct intel_vgpu *vgpu, 678 unsigned int offset, void *p_data, unsigned int bytes) 679 { 680 u32 reg_val; 681 u32 sticky_mask; 682 683 reg_val = *((u32 *)p_data); 684 sticky_mask = GENMASK(27, 26) | (1 << 24); 685 686 vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) | 687 (vgpu_vreg(vgpu, offset) & sticky_mask); 688 vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask); 689 return 0; 690 } 691 692 static int pch_adpa_mmio_write(struct intel_vgpu *vgpu, 693 unsigned int offset, void *p_data, unsigned int bytes) 694 { 695 u32 data; 696 697 write_vreg(vgpu, offset, p_data, bytes); 698 data = vgpu_vreg(vgpu, offset); 699 700 if (data & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) 701 vgpu_vreg(vgpu, offset) &= ~ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 702 return 0; 703 } 704 705 static int south_chicken2_mmio_write(struct intel_vgpu *vgpu, 706 unsigned int offset, void *p_data, unsigned int bytes) 707 { 708 u32 data; 709 710 write_vreg(vgpu, offset, p_data, bytes); 711 data = vgpu_vreg(vgpu, offset); 712 713 if (data & FDI_MPHY_IOSFSB_RESET_CTL) 714 vgpu_vreg(vgpu, offset) |= FDI_MPHY_IOSFSB_RESET_STATUS; 715 else 716 vgpu_vreg(vgpu, offset) &= ~FDI_MPHY_IOSFSB_RESET_STATUS; 717 return 0; 718 } 719 720 #define DSPSURF_TO_PIPE(offset) \ 721 calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C)) 722 723 static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 724 void *p_data, unsigned int bytes) 725 { 726 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 727 unsigned int index = DSPSURF_TO_PIPE(offset); 728 i915_reg_t surflive_reg = DSPSURFLIVE(index); 729 int flip_event[] = { 730 [PIPE_A] = PRIMARY_A_FLIP_DONE, 731 [PIPE_B] = PRIMARY_B_FLIP_DONE, 732 [PIPE_C] = PRIMARY_C_FLIP_DONE, 733 }; 734 735 write_vreg(vgpu, offset, p_data, bytes); 736 vgpu_vreg_t(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset); 737 738 set_bit(flip_event[index], vgpu->irq.flip_done_event[index]); 739 return 0; 740 } 741 742 #define SPRSURF_TO_PIPE(offset) \ 743 calc_index(offset, _SPRA_SURF, _SPRB_SURF, 0, SPRSURF(PIPE_C)) 744 745 static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 746 void *p_data, unsigned int bytes) 747 { 748 unsigned int index = SPRSURF_TO_PIPE(offset); 749 i915_reg_t surflive_reg = SPRSURFLIVE(index); 750 int flip_event[] = { 751 [PIPE_A] = SPRITE_A_FLIP_DONE, 752 [PIPE_B] = SPRITE_B_FLIP_DONE, 753 [PIPE_C] = SPRITE_C_FLIP_DONE, 754 }; 755 756 write_vreg(vgpu, offset, p_data, bytes); 757 vgpu_vreg_t(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset); 758 759 set_bit(flip_event[index], vgpu->irq.flip_done_event[index]); 760 return 0; 761 } 762 763 static int trigger_aux_channel_interrupt(struct intel_vgpu *vgpu, 764 unsigned int reg) 765 { 766 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 767 enum intel_gvt_event_type event; 768 769 if (reg == _DPA_AUX_CH_CTL) 770 event = AUX_CHANNEL_A; 771 else if (reg == _PCH_DPB_AUX_CH_CTL || reg == _DPB_AUX_CH_CTL) 772 event = AUX_CHANNEL_B; 773 else if (reg == _PCH_DPC_AUX_CH_CTL || reg == _DPC_AUX_CH_CTL) 774 event = AUX_CHANNEL_C; 775 else if (reg == _PCH_DPD_AUX_CH_CTL || reg == _DPD_AUX_CH_CTL) 776 event = AUX_CHANNEL_D; 777 else { 778 WARN_ON(true); 779 return -EINVAL; 780 } 781 782 intel_vgpu_trigger_virtual_event(vgpu, event); 783 return 0; 784 } 785 786 static int dp_aux_ch_ctl_trans_done(struct intel_vgpu *vgpu, u32 value, 787 unsigned int reg, int len, bool data_valid) 788 { 789 /* mark transaction done */ 790 value |= DP_AUX_CH_CTL_DONE; 791 value &= ~DP_AUX_CH_CTL_SEND_BUSY; 792 value &= ~DP_AUX_CH_CTL_RECEIVE_ERROR; 793 794 if (data_valid) 795 value &= ~DP_AUX_CH_CTL_TIME_OUT_ERROR; 796 else 797 value |= DP_AUX_CH_CTL_TIME_OUT_ERROR; 798 799 /* message size */ 800 value &= ~(0xf << 20); 801 value |= (len << 20); 802 vgpu_vreg(vgpu, reg) = value; 803 804 if (value & DP_AUX_CH_CTL_INTERRUPT) 805 return trigger_aux_channel_interrupt(vgpu, reg); 806 return 0; 807 } 808 809 static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd, 810 uint8_t t) 811 { 812 if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == DPCD_TRAINING_PATTERN_1) { 813 /* training pattern 1 for CR */ 814 /* set LANE0_CR_DONE, LANE1_CR_DONE */ 815 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_CR_DONE; 816 /* set LANE2_CR_DONE, LANE3_CR_DONE */ 817 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_CR_DONE; 818 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == 819 DPCD_TRAINING_PATTERN_2) { 820 /* training pattern 2 for EQ */ 821 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane0_1 */ 822 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_EQ_DONE; 823 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_SYMBOL_LOCKED; 824 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane2_3 */ 825 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_EQ_DONE; 826 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_SYMBOL_LOCKED; 827 /* set INTERLANE_ALIGN_DONE */ 828 dpcd->data[DPCD_LANE_ALIGN_STATUS_UPDATED] |= 829 DPCD_INTERLANE_ALIGN_DONE; 830 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == 831 DPCD_LINK_TRAINING_DISABLED) { 832 /* finish link training */ 833 /* set sink status as synchronized */ 834 dpcd->data[DPCD_SINK_STATUS] = DPCD_SINK_IN_SYNC; 835 } 836 } 837 838 #define _REG_HSW_DP_AUX_CH_CTL(dp) \ 839 ((dp) ? (_PCH_DPB_AUX_CH_CTL + ((dp)-1)*0x100) : 0x64010) 840 841 #define _REG_SKL_DP_AUX_CH_CTL(dp) (0x64010 + (dp) * 0x100) 842 843 #define OFFSET_TO_DP_AUX_PORT(offset) (((offset) & 0xF00) >> 8) 844 845 #define dpy_is_valid_port(port) \ 846 (((port) >= PORT_A) && ((port) < I915_MAX_PORTS)) 847 848 static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu, 849 unsigned int offset, void *p_data, unsigned int bytes) 850 { 851 struct intel_vgpu_display *display = &vgpu->display; 852 int msg, addr, ctrl, op, len; 853 int port_index = OFFSET_TO_DP_AUX_PORT(offset); 854 struct intel_vgpu_dpcd_data *dpcd = NULL; 855 struct intel_vgpu_port *port = NULL; 856 u32 data; 857 858 if (!dpy_is_valid_port(port_index)) { 859 gvt_vgpu_err("Unsupported DP port access!\n"); 860 return 0; 861 } 862 863 write_vreg(vgpu, offset, p_data, bytes); 864 data = vgpu_vreg(vgpu, offset); 865 866 if ((IS_SKYLAKE(vgpu->gvt->dev_priv) 867 || IS_KABYLAKE(vgpu->gvt->dev_priv) 868 || IS_BROXTON(vgpu->gvt->dev_priv)) 869 && offset != _REG_SKL_DP_AUX_CH_CTL(port_index)) { 870 /* SKL DPB/C/D aux ctl register changed */ 871 return 0; 872 } else if (IS_BROADWELL(vgpu->gvt->dev_priv) && 873 offset != _REG_HSW_DP_AUX_CH_CTL(port_index)) { 874 /* write to the data registers */ 875 return 0; 876 } 877 878 if (!(data & DP_AUX_CH_CTL_SEND_BUSY)) { 879 /* just want to clear the sticky bits */ 880 vgpu_vreg(vgpu, offset) = 0; 881 return 0; 882 } 883 884 port = &display->ports[port_index]; 885 dpcd = port->dpcd; 886 887 /* read out message from DATA1 register */ 888 msg = vgpu_vreg(vgpu, offset + 4); 889 addr = (msg >> 8) & 0xffff; 890 ctrl = (msg >> 24) & 0xff; 891 len = msg & 0xff; 892 op = ctrl >> 4; 893 894 if (op == GVT_AUX_NATIVE_WRITE) { 895 int t; 896 uint8_t buf[16]; 897 898 if ((addr + len + 1) >= DPCD_SIZE) { 899 /* 900 * Write request exceeds what we supported, 901 * DCPD spec: When a Source Device is writing a DPCD 902 * address not supported by the Sink Device, the Sink 903 * Device shall reply with AUX NACK and “M” equal to 904 * zero. 905 */ 906 907 /* NAK the write */ 908 vgpu_vreg(vgpu, offset + 4) = AUX_NATIVE_REPLY_NAK; 909 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 2, true); 910 return 0; 911 } 912 913 /* 914 * Write request format: Headr (command + address + size) occupies 915 * 4 bytes, followed by (len + 1) bytes of data. See details at 916 * intel_dp_aux_transfer(). 917 */ 918 if ((len + 1 + 4) > AUX_BURST_SIZE) { 919 gvt_vgpu_err("dp_aux_header: len %d is too large\n", len); 920 return -EINVAL; 921 } 922 923 /* unpack data from vreg to buf */ 924 for (t = 0; t < 4; t++) { 925 u32 r = vgpu_vreg(vgpu, offset + 8 + t * 4); 926 927 buf[t * 4] = (r >> 24) & 0xff; 928 buf[t * 4 + 1] = (r >> 16) & 0xff; 929 buf[t * 4 + 2] = (r >> 8) & 0xff; 930 buf[t * 4 + 3] = r & 0xff; 931 } 932 933 /* write to virtual DPCD */ 934 if (dpcd && dpcd->data_valid) { 935 for (t = 0; t <= len; t++) { 936 int p = addr + t; 937 938 dpcd->data[p] = buf[t]; 939 /* check for link training */ 940 if (p == DPCD_TRAINING_PATTERN_SET) 941 dp_aux_ch_ctl_link_training(dpcd, 942 buf[t]); 943 } 944 } 945 946 /* ACK the write */ 947 vgpu_vreg(vgpu, offset + 4) = 0; 948 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 1, 949 dpcd && dpcd->data_valid); 950 return 0; 951 } 952 953 if (op == GVT_AUX_NATIVE_READ) { 954 int idx, i, ret = 0; 955 956 if ((addr + len + 1) >= DPCD_SIZE) { 957 /* 958 * read request exceeds what we supported 959 * DPCD spec: A Sink Device receiving a Native AUX CH 960 * read request for an unsupported DPCD address must 961 * reply with an AUX ACK and read data set equal to 962 * zero instead of replying with AUX NACK. 963 */ 964 965 /* ACK the READ*/ 966 vgpu_vreg(vgpu, offset + 4) = 0; 967 vgpu_vreg(vgpu, offset + 8) = 0; 968 vgpu_vreg(vgpu, offset + 12) = 0; 969 vgpu_vreg(vgpu, offset + 16) = 0; 970 vgpu_vreg(vgpu, offset + 20) = 0; 971 972 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2, 973 true); 974 return 0; 975 } 976 977 for (idx = 1; idx <= 5; idx++) { 978 /* clear the data registers */ 979 vgpu_vreg(vgpu, offset + 4 * idx) = 0; 980 } 981 982 /* 983 * Read reply format: ACK (1 byte) plus (len + 1) bytes of data. 984 */ 985 if ((len + 2) > AUX_BURST_SIZE) { 986 gvt_vgpu_err("dp_aux_header: len %d is too large\n", len); 987 return -EINVAL; 988 } 989 990 /* read from virtual DPCD to vreg */ 991 /* first 4 bytes: [ACK][addr][addr+1][addr+2] */ 992 if (dpcd && dpcd->data_valid) { 993 for (i = 1; i <= (len + 1); i++) { 994 int t; 995 996 t = dpcd->data[addr + i - 1]; 997 t <<= (24 - 8 * (i % 4)); 998 ret |= t; 999 1000 if ((i % 4 == 3) || (i == (len + 1))) { 1001 vgpu_vreg(vgpu, offset + 1002 (i / 4 + 1) * 4) = ret; 1003 ret = 0; 1004 } 1005 } 1006 } 1007 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2, 1008 dpcd && dpcd->data_valid); 1009 return 0; 1010 } 1011 1012 /* i2c transaction starts */ 1013 intel_gvt_i2c_handle_aux_ch_write(vgpu, port_index, offset, p_data); 1014 1015 if (data & DP_AUX_CH_CTL_INTERRUPT) 1016 trigger_aux_channel_interrupt(vgpu, offset); 1017 return 0; 1018 } 1019 1020 static int mbctl_write(struct intel_vgpu *vgpu, unsigned int offset, 1021 void *p_data, unsigned int bytes) 1022 { 1023 *(u32 *)p_data &= (~GEN6_MBCTL_ENABLE_BOOT_FETCH); 1024 write_vreg(vgpu, offset, p_data, bytes); 1025 return 0; 1026 } 1027 1028 static int vga_control_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1029 void *p_data, unsigned int bytes) 1030 { 1031 bool vga_disable; 1032 1033 write_vreg(vgpu, offset, p_data, bytes); 1034 vga_disable = vgpu_vreg(vgpu, offset) & VGA_DISP_DISABLE; 1035 1036 gvt_dbg_core("vgpu%d: %s VGA mode\n", vgpu->id, 1037 vga_disable ? "Disable" : "Enable"); 1038 return 0; 1039 } 1040 1041 static u32 read_virtual_sbi_register(struct intel_vgpu *vgpu, 1042 unsigned int sbi_offset) 1043 { 1044 struct intel_vgpu_display *display = &vgpu->display; 1045 int num = display->sbi.number; 1046 int i; 1047 1048 for (i = 0; i < num; ++i) 1049 if (display->sbi.registers[i].offset == sbi_offset) 1050 break; 1051 1052 if (i == num) 1053 return 0; 1054 1055 return display->sbi.registers[i].value; 1056 } 1057 1058 static void write_virtual_sbi_register(struct intel_vgpu *vgpu, 1059 unsigned int offset, u32 value) 1060 { 1061 struct intel_vgpu_display *display = &vgpu->display; 1062 int num = display->sbi.number; 1063 int i; 1064 1065 for (i = 0; i < num; ++i) { 1066 if (display->sbi.registers[i].offset == offset) 1067 break; 1068 } 1069 1070 if (i == num) { 1071 if (num == SBI_REG_MAX) { 1072 gvt_vgpu_err("SBI caching meets maximum limits\n"); 1073 return; 1074 } 1075 display->sbi.number++; 1076 } 1077 1078 display->sbi.registers[i].offset = offset; 1079 display->sbi.registers[i].value = value; 1080 } 1081 1082 static int sbi_data_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 1083 void *p_data, unsigned int bytes) 1084 { 1085 if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> 1086 SBI_OPCODE_SHIFT) == SBI_CMD_CRRD) { 1087 unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) & 1088 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; 1089 vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu, 1090 sbi_offset); 1091 } 1092 read_vreg(vgpu, offset, p_data, bytes); 1093 return 0; 1094 } 1095 1096 static int sbi_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1097 void *p_data, unsigned int bytes) 1098 { 1099 u32 data; 1100 1101 write_vreg(vgpu, offset, p_data, bytes); 1102 data = vgpu_vreg(vgpu, offset); 1103 1104 data &= ~(SBI_STAT_MASK << SBI_STAT_SHIFT); 1105 data |= SBI_READY; 1106 1107 data &= ~(SBI_RESPONSE_MASK << SBI_RESPONSE_SHIFT); 1108 data |= SBI_RESPONSE_SUCCESS; 1109 1110 vgpu_vreg(vgpu, offset) = data; 1111 1112 if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> 1113 SBI_OPCODE_SHIFT) == SBI_CMD_CRWR) { 1114 unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) & 1115 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; 1116 1117 write_virtual_sbi_register(vgpu, sbi_offset, 1118 vgpu_vreg_t(vgpu, SBI_DATA)); 1119 } 1120 return 0; 1121 } 1122 1123 #define _vgtif_reg(x) \ 1124 (VGT_PVINFO_PAGE + offsetof(struct vgt_if, x)) 1125 1126 static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 1127 void *p_data, unsigned int bytes) 1128 { 1129 bool invalid_read = false; 1130 1131 read_vreg(vgpu, offset, p_data, bytes); 1132 1133 switch (offset) { 1134 case _vgtif_reg(magic) ... _vgtif_reg(vgt_id): 1135 if (offset + bytes > _vgtif_reg(vgt_id) + 4) 1136 invalid_read = true; 1137 break; 1138 case _vgtif_reg(avail_rs.mappable_gmadr.base) ... 1139 _vgtif_reg(avail_rs.fence_num): 1140 if (offset + bytes > 1141 _vgtif_reg(avail_rs.fence_num) + 4) 1142 invalid_read = true; 1143 break; 1144 case 0x78010: /* vgt_caps */ 1145 case 0x7881c: 1146 break; 1147 default: 1148 invalid_read = true; 1149 break; 1150 } 1151 if (invalid_read) 1152 gvt_vgpu_err("invalid pvinfo read: [%x:%x] = %x\n", 1153 offset, bytes, *(u32 *)p_data); 1154 vgpu->pv_notified = true; 1155 return 0; 1156 } 1157 1158 static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification) 1159 { 1160 intel_gvt_gtt_type_t root_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY; 1161 struct intel_vgpu_mm *mm; 1162 u64 *pdps; 1163 1164 pdps = (u64 *)&vgpu_vreg64_t(vgpu, vgtif_reg(pdp[0])); 1165 1166 switch (notification) { 1167 case VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE: 1168 root_entry_type = GTT_TYPE_PPGTT_ROOT_L3_ENTRY; 1169 /* fall through */ 1170 case VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE: 1171 mm = intel_vgpu_get_ppgtt_mm(vgpu, root_entry_type, pdps); 1172 return PTR_ERR_OR_ZERO(mm); 1173 case VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY: 1174 case VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY: 1175 return intel_vgpu_put_ppgtt_mm(vgpu, pdps); 1176 case VGT_G2V_EXECLIST_CONTEXT_CREATE: 1177 case VGT_G2V_EXECLIST_CONTEXT_DESTROY: 1178 case 1: /* Remove this in guest driver. */ 1179 break; 1180 default: 1181 gvt_vgpu_err("Invalid PV notification %d\n", notification); 1182 } 1183 return 0; 1184 } 1185 1186 static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready) 1187 { 1188 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1189 struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj; 1190 char *env[3] = {NULL, NULL, NULL}; 1191 char vmid_str[20]; 1192 char display_ready_str[20]; 1193 1194 snprintf(display_ready_str, 20, "GVT_DISPLAY_READY=%d", ready); 1195 env[0] = display_ready_str; 1196 1197 snprintf(vmid_str, 20, "VMID=%d", vgpu->id); 1198 env[1] = vmid_str; 1199 1200 return kobject_uevent_env(kobj, KOBJ_ADD, env); 1201 } 1202 1203 static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1204 void *p_data, unsigned int bytes) 1205 { 1206 u32 data; 1207 int ret; 1208 1209 write_vreg(vgpu, offset, p_data, bytes); 1210 data = vgpu_vreg(vgpu, offset); 1211 1212 switch (offset) { 1213 case _vgtif_reg(display_ready): 1214 send_display_ready_uevent(vgpu, data ? 1 : 0); 1215 break; 1216 case _vgtif_reg(g2v_notify): 1217 ret = handle_g2v_notification(vgpu, data); 1218 break; 1219 /* add xhot and yhot to handled list to avoid error log */ 1220 case _vgtif_reg(cursor_x_hot): 1221 case _vgtif_reg(cursor_y_hot): 1222 case _vgtif_reg(pdp[0].lo): 1223 case _vgtif_reg(pdp[0].hi): 1224 case _vgtif_reg(pdp[1].lo): 1225 case _vgtif_reg(pdp[1].hi): 1226 case _vgtif_reg(pdp[2].lo): 1227 case _vgtif_reg(pdp[2].hi): 1228 case _vgtif_reg(pdp[3].lo): 1229 case _vgtif_reg(pdp[3].hi): 1230 case _vgtif_reg(execlist_context_descriptor_lo): 1231 case _vgtif_reg(execlist_context_descriptor_hi): 1232 break; 1233 case _vgtif_reg(rsv5[0])..._vgtif_reg(rsv5[3]): 1234 enter_failsafe_mode(vgpu, GVT_FAILSAFE_INSUFFICIENT_RESOURCE); 1235 break; 1236 default: 1237 gvt_vgpu_err("invalid pvinfo write offset %x bytes %x data %x\n", 1238 offset, bytes, data); 1239 break; 1240 } 1241 return 0; 1242 } 1243 1244 static int pf_write(struct intel_vgpu *vgpu, 1245 unsigned int offset, void *p_data, unsigned int bytes) 1246 { 1247 u32 val = *(u32 *)p_data; 1248 1249 if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL || 1250 offset == _PS_1B_CTRL || offset == _PS_2B_CTRL || 1251 offset == _PS_1C_CTRL) && (val & PS_PLANE_SEL_MASK) != 0) { 1252 WARN_ONCE(true, "VM(%d): guest is trying to scaling a plane\n", 1253 vgpu->id); 1254 return 0; 1255 } 1256 1257 return intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes); 1258 } 1259 1260 static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu, 1261 unsigned int offset, void *p_data, unsigned int bytes) 1262 { 1263 write_vreg(vgpu, offset, p_data, bytes); 1264 1265 if (vgpu_vreg(vgpu, offset) & HSW_PWR_WELL_CTL_REQ(HSW_DISP_PW_GLOBAL)) 1266 vgpu_vreg(vgpu, offset) |= 1267 HSW_PWR_WELL_CTL_STATE(HSW_DISP_PW_GLOBAL); 1268 else 1269 vgpu_vreg(vgpu, offset) &= 1270 ~HSW_PWR_WELL_CTL_STATE(HSW_DISP_PW_GLOBAL); 1271 return 0; 1272 } 1273 1274 static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu, 1275 unsigned int offset, void *p_data, unsigned int bytes) 1276 { 1277 write_vreg(vgpu, offset, p_data, bytes); 1278 1279 if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM) 1280 vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM; 1281 return 0; 1282 } 1283 1284 static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset, 1285 void *p_data, unsigned int bytes) 1286 { 1287 u32 mode; 1288 1289 write_vreg(vgpu, offset, p_data, bytes); 1290 mode = vgpu_vreg(vgpu, offset); 1291 1292 if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) { 1293 WARN_ONCE(1, "VM(%d): iGVT-g doesn't support GuC\n", 1294 vgpu->id); 1295 return 0; 1296 } 1297 1298 return 0; 1299 } 1300 1301 static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset, 1302 void *p_data, unsigned int bytes) 1303 { 1304 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1305 u32 trtte = *(u32 *)p_data; 1306 1307 if ((trtte & 1) && (trtte & (1 << 1)) == 0) { 1308 WARN(1, "VM(%d): Use physical address for TRTT!\n", 1309 vgpu->id); 1310 return -EINVAL; 1311 } 1312 write_vreg(vgpu, offset, p_data, bytes); 1313 /* TRTTE is not per-context */ 1314 1315 mmio_hw_access_pre(dev_priv); 1316 I915_WRITE(_MMIO(offset), vgpu_vreg(vgpu, offset)); 1317 mmio_hw_access_post(dev_priv); 1318 1319 return 0; 1320 } 1321 1322 static int gen9_trtt_chicken_write(struct intel_vgpu *vgpu, unsigned int offset, 1323 void *p_data, unsigned int bytes) 1324 { 1325 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1326 u32 val = *(u32 *)p_data; 1327 1328 if (val & 1) { 1329 /* unblock hw logic */ 1330 mmio_hw_access_pre(dev_priv); 1331 I915_WRITE(_MMIO(offset), val); 1332 mmio_hw_access_post(dev_priv); 1333 } 1334 write_vreg(vgpu, offset, p_data, bytes); 1335 return 0; 1336 } 1337 1338 static int dpll_status_read(struct intel_vgpu *vgpu, unsigned int offset, 1339 void *p_data, unsigned int bytes) 1340 { 1341 u32 v = 0; 1342 1343 if (vgpu_vreg(vgpu, 0x46010) & (1 << 31)) 1344 v |= (1 << 0); 1345 1346 if (vgpu_vreg(vgpu, 0x46014) & (1 << 31)) 1347 v |= (1 << 8); 1348 1349 if (vgpu_vreg(vgpu, 0x46040) & (1 << 31)) 1350 v |= (1 << 16); 1351 1352 if (vgpu_vreg(vgpu, 0x46060) & (1 << 31)) 1353 v |= (1 << 24); 1354 1355 vgpu_vreg(vgpu, offset) = v; 1356 1357 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1358 } 1359 1360 static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset, 1361 void *p_data, unsigned int bytes) 1362 { 1363 u32 value = *(u32 *)p_data; 1364 u32 cmd = value & 0xff; 1365 u32 *data0 = &vgpu_vreg_t(vgpu, GEN6_PCODE_DATA); 1366 1367 switch (cmd) { 1368 case GEN9_PCODE_READ_MEM_LATENCY: 1369 if (IS_SKYLAKE(vgpu->gvt->dev_priv) 1370 || IS_KABYLAKE(vgpu->gvt->dev_priv)) { 1371 /** 1372 * "Read memory latency" command on gen9. 1373 * Below memory latency values are read 1374 * from skylake platform. 1375 */ 1376 if (!*data0) 1377 *data0 = 0x1e1a1100; 1378 else 1379 *data0 = 0x61514b3d; 1380 } else if (IS_BROXTON(vgpu->gvt->dev_priv)) { 1381 /** 1382 * "Read memory latency" command on gen9. 1383 * Below memory latency values are read 1384 * from Broxton MRB. 1385 */ 1386 if (!*data0) 1387 *data0 = 0x16080707; 1388 else 1389 *data0 = 0x16161616; 1390 } 1391 break; 1392 case SKL_PCODE_CDCLK_CONTROL: 1393 if (IS_SKYLAKE(vgpu->gvt->dev_priv) 1394 || IS_KABYLAKE(vgpu->gvt->dev_priv)) 1395 *data0 = SKL_CDCLK_READY_FOR_CHANGE; 1396 break; 1397 case GEN6_PCODE_READ_RC6VIDS: 1398 *data0 |= 0x1; 1399 break; 1400 } 1401 1402 gvt_dbg_core("VM(%d) write %x to mailbox, return data0 %x\n", 1403 vgpu->id, value, *data0); 1404 /** 1405 * PCODE_READY clear means ready for pcode read/write, 1406 * PCODE_ERROR_MASK clear means no error happened. In GVT-g we 1407 * always emulate as pcode read/write success and ready for access 1408 * anytime, since we don't touch real physical registers here. 1409 */ 1410 value &= ~(GEN6_PCODE_READY | GEN6_PCODE_ERROR_MASK); 1411 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes); 1412 } 1413 1414 static int hws_pga_write(struct intel_vgpu *vgpu, unsigned int offset, 1415 void *p_data, unsigned int bytes) 1416 { 1417 u32 value = *(u32 *)p_data; 1418 int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset); 1419 1420 if (!intel_gvt_ggtt_validate_range(vgpu, value, I915_GTT_PAGE_SIZE)) { 1421 gvt_vgpu_err("write invalid HWSP address, reg:0x%x, value:0x%x\n", 1422 offset, value); 1423 return -EINVAL; 1424 } 1425 /* 1426 * Need to emulate all the HWSP register write to ensure host can 1427 * update the VM CSB status correctly. Here listed registers can 1428 * support BDW, SKL or other platforms with same HWSP registers. 1429 */ 1430 if (unlikely(ring_id < 0 || ring_id >= I915_NUM_ENGINES)) { 1431 gvt_vgpu_err("access unknown hardware status page register:0x%x\n", 1432 offset); 1433 return -EINVAL; 1434 } 1435 vgpu->hws_pga[ring_id] = value; 1436 gvt_dbg_mmio("VM(%d) write: 0x%x to HWSP: 0x%x\n", 1437 vgpu->id, value, offset); 1438 1439 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes); 1440 } 1441 1442 static int skl_power_well_ctl_write(struct intel_vgpu *vgpu, 1443 unsigned int offset, void *p_data, unsigned int bytes) 1444 { 1445 u32 v = *(u32 *)p_data; 1446 1447 if (IS_BROXTON(vgpu->gvt->dev_priv)) 1448 v &= (1 << 31) | (1 << 29); 1449 else 1450 v &= (1 << 31) | (1 << 29) | (1 << 9) | 1451 (1 << 7) | (1 << 5) | (1 << 3) | (1 << 1); 1452 v |= (v >> 1); 1453 1454 return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes); 1455 } 1456 1457 static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset, 1458 void *p_data, unsigned int bytes) 1459 { 1460 u32 v = *(u32 *)p_data; 1461 1462 /* other bits are MBZ. */ 1463 v &= (1 << 31) | (1 << 30); 1464 v & (1 << 31) ? (v |= (1 << 30)) : (v &= ~(1 << 30)); 1465 1466 vgpu_vreg(vgpu, offset) = v; 1467 1468 return 0; 1469 } 1470 1471 static int bxt_de_pll_enable_write(struct intel_vgpu *vgpu, 1472 unsigned int offset, void *p_data, unsigned int bytes) 1473 { 1474 u32 v = *(u32 *)p_data; 1475 1476 if (v & BXT_DE_PLL_PLL_ENABLE) 1477 v |= BXT_DE_PLL_LOCK; 1478 1479 vgpu_vreg(vgpu, offset) = v; 1480 1481 return 0; 1482 } 1483 1484 static int bxt_port_pll_enable_write(struct intel_vgpu *vgpu, 1485 unsigned int offset, void *p_data, unsigned int bytes) 1486 { 1487 u32 v = *(u32 *)p_data; 1488 1489 if (v & PORT_PLL_ENABLE) 1490 v |= PORT_PLL_LOCK; 1491 1492 vgpu_vreg(vgpu, offset) = v; 1493 1494 return 0; 1495 } 1496 1497 static int bxt_phy_ctl_family_write(struct intel_vgpu *vgpu, 1498 unsigned int offset, void *p_data, unsigned int bytes) 1499 { 1500 u32 v = *(u32 *)p_data; 1501 u32 data = v & COMMON_RESET_DIS ? BXT_PHY_LANE_ENABLED : 0; 1502 1503 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_A) = data; 1504 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_B) = data; 1505 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_C) = data; 1506 1507 vgpu_vreg(vgpu, offset) = v; 1508 1509 return 0; 1510 } 1511 1512 static int bxt_port_tx_dw3_read(struct intel_vgpu *vgpu, 1513 unsigned int offset, void *p_data, unsigned int bytes) 1514 { 1515 u32 v = vgpu_vreg(vgpu, offset); 1516 1517 v &= ~UNIQUE_TRANGE_EN_METHOD; 1518 1519 vgpu_vreg(vgpu, offset) = v; 1520 1521 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1522 } 1523 1524 static int bxt_pcs_dw12_grp_write(struct intel_vgpu *vgpu, 1525 unsigned int offset, void *p_data, unsigned int bytes) 1526 { 1527 u32 v = *(u32 *)p_data; 1528 1529 if (offset == _PORT_PCS_DW12_GRP_A || offset == _PORT_PCS_DW12_GRP_B) { 1530 vgpu_vreg(vgpu, offset - 0x600) = v; 1531 vgpu_vreg(vgpu, offset - 0x800) = v; 1532 } else { 1533 vgpu_vreg(vgpu, offset - 0x400) = v; 1534 vgpu_vreg(vgpu, offset - 0x600) = v; 1535 } 1536 1537 vgpu_vreg(vgpu, offset) = v; 1538 1539 return 0; 1540 } 1541 1542 static int bxt_gt_disp_pwron_write(struct intel_vgpu *vgpu, 1543 unsigned int offset, void *p_data, unsigned int bytes) 1544 { 1545 u32 v = *(u32 *)p_data; 1546 1547 if (v & BIT(0)) { 1548 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &= 1549 ~PHY_RESERVED; 1550 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |= 1551 PHY_POWER_GOOD; 1552 } 1553 1554 if (v & BIT(1)) { 1555 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &= 1556 ~PHY_RESERVED; 1557 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |= 1558 PHY_POWER_GOOD; 1559 } 1560 1561 1562 vgpu_vreg(vgpu, offset) = v; 1563 1564 return 0; 1565 } 1566 1567 static int mmio_read_from_hw(struct intel_vgpu *vgpu, 1568 unsigned int offset, void *p_data, unsigned int bytes) 1569 { 1570 struct intel_gvt *gvt = vgpu->gvt; 1571 struct drm_i915_private *dev_priv = gvt->dev_priv; 1572 int ring_id; 1573 u32 ring_base; 1574 1575 ring_id = intel_gvt_render_mmio_to_ring_id(gvt, offset); 1576 /** 1577 * Read HW reg in following case 1578 * a. the offset isn't a ring mmio 1579 * b. the offset's ring is running on hw. 1580 * c. the offset is ring time stamp mmio 1581 */ 1582 if (ring_id >= 0) 1583 ring_base = dev_priv->engine[ring_id]->mmio_base; 1584 1585 if (ring_id < 0 || vgpu == gvt->scheduler.engine_owner[ring_id] || 1586 offset == i915_mmio_reg_offset(RING_TIMESTAMP(ring_base)) || 1587 offset == i915_mmio_reg_offset(RING_TIMESTAMP_UDW(ring_base))) { 1588 mmio_hw_access_pre(dev_priv); 1589 vgpu_vreg(vgpu, offset) = I915_READ(_MMIO(offset)); 1590 mmio_hw_access_post(dev_priv); 1591 } 1592 1593 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1594 } 1595 1596 static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1597 void *p_data, unsigned int bytes) 1598 { 1599 int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset); 1600 struct intel_vgpu_execlist *execlist; 1601 u32 data = *(u32 *)p_data; 1602 int ret = 0; 1603 1604 if (WARN_ON(ring_id < 0 || ring_id >= I915_NUM_ENGINES)) 1605 return -EINVAL; 1606 1607 execlist = &vgpu->submission.execlist[ring_id]; 1608 1609 execlist->elsp_dwords.data[3 - execlist->elsp_dwords.index] = data; 1610 if (execlist->elsp_dwords.index == 3) { 1611 ret = intel_vgpu_submit_execlist(vgpu, ring_id); 1612 if(ret) 1613 gvt_vgpu_err("fail submit workload on ring %d\n", 1614 ring_id); 1615 } 1616 1617 ++execlist->elsp_dwords.index; 1618 execlist->elsp_dwords.index &= 0x3; 1619 return ret; 1620 } 1621 1622 static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1623 void *p_data, unsigned int bytes) 1624 { 1625 u32 data = *(u32 *)p_data; 1626 int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset); 1627 bool enable_execlist; 1628 int ret; 1629 1630 write_vreg(vgpu, offset, p_data, bytes); 1631 1632 /* when PPGTT mode enabled, we will check if guest has called 1633 * pvinfo, if not, we will treat this guest as non-gvtg-aware 1634 * guest, and stop emulating its cfg space, mmio, gtt, etc. 1635 */ 1636 if (((data & _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)) || 1637 (data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE))) 1638 && !vgpu->pv_notified) { 1639 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); 1640 return 0; 1641 } 1642 if ((data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)) 1643 || (data & _MASKED_BIT_DISABLE(GFX_RUN_LIST_ENABLE))) { 1644 enable_execlist = !!(data & GFX_RUN_LIST_ENABLE); 1645 1646 gvt_dbg_core("EXECLIST %s on ring %d\n", 1647 (enable_execlist ? "enabling" : "disabling"), 1648 ring_id); 1649 1650 if (!enable_execlist) 1651 return 0; 1652 1653 ret = intel_vgpu_select_submission_ops(vgpu, 1654 ENGINE_MASK(ring_id), 1655 INTEL_VGPU_EXECLIST_SUBMISSION); 1656 if (ret) 1657 return ret; 1658 1659 intel_vgpu_start_schedule(vgpu); 1660 } 1661 return 0; 1662 } 1663 1664 static int gvt_reg_tlb_control_handler(struct intel_vgpu *vgpu, 1665 unsigned int offset, void *p_data, unsigned int bytes) 1666 { 1667 unsigned int id = 0; 1668 1669 write_vreg(vgpu, offset, p_data, bytes); 1670 vgpu_vreg(vgpu, offset) = 0; 1671 1672 switch (offset) { 1673 case 0x4260: 1674 id = RCS; 1675 break; 1676 case 0x4264: 1677 id = VCS; 1678 break; 1679 case 0x4268: 1680 id = VCS2; 1681 break; 1682 case 0x426c: 1683 id = BCS; 1684 break; 1685 case 0x4270: 1686 id = VECS; 1687 break; 1688 default: 1689 return -EINVAL; 1690 } 1691 set_bit(id, (void *)vgpu->submission.tlb_handle_pending); 1692 1693 return 0; 1694 } 1695 1696 static int ring_reset_ctl_write(struct intel_vgpu *vgpu, 1697 unsigned int offset, void *p_data, unsigned int bytes) 1698 { 1699 u32 data; 1700 1701 write_vreg(vgpu, offset, p_data, bytes); 1702 data = vgpu_vreg(vgpu, offset); 1703 1704 if (data & _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET)) 1705 data |= RESET_CTL_READY_TO_RESET; 1706 else if (data & _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET)) 1707 data &= ~RESET_CTL_READY_TO_RESET; 1708 1709 vgpu_vreg(vgpu, offset) = data; 1710 return 0; 1711 } 1712 1713 #define MMIO_F(reg, s, f, am, rm, d, r, w) do { \ 1714 ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \ 1715 f, s, am, rm, d, r, w); \ 1716 if (ret) \ 1717 return ret; \ 1718 } while (0) 1719 1720 #define MMIO_D(reg, d) \ 1721 MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL) 1722 1723 #define MMIO_DH(reg, d, r, w) \ 1724 MMIO_F(reg, 4, 0, 0, 0, d, r, w) 1725 1726 #define MMIO_DFH(reg, d, f, r, w) \ 1727 MMIO_F(reg, 4, f, 0, 0, d, r, w) 1728 1729 #define MMIO_GM(reg, d, r, w) \ 1730 MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w) 1731 1732 #define MMIO_GM_RDR(reg, d, r, w) \ 1733 MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w) 1734 1735 #define MMIO_RO(reg, d, f, rm, r, w) \ 1736 MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w) 1737 1738 #define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \ 1739 MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \ 1740 MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \ 1741 MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \ 1742 MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \ 1743 if (HAS_BSD2(dev_priv)) \ 1744 MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \ 1745 } while (0) 1746 1747 #define MMIO_RING_D(prefix, d) \ 1748 MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL) 1749 1750 #define MMIO_RING_DFH(prefix, d, f, r, w) \ 1751 MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w) 1752 1753 #define MMIO_RING_GM(prefix, d, r, w) \ 1754 MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w) 1755 1756 #define MMIO_RING_GM_RDR(prefix, d, r, w) \ 1757 MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w) 1758 1759 #define MMIO_RING_RO(prefix, d, f, rm, r, w) \ 1760 MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w) 1761 1762 static int init_generic_mmio_info(struct intel_gvt *gvt) 1763 { 1764 struct drm_i915_private *dev_priv = gvt->dev_priv; 1765 int ret; 1766 1767 MMIO_RING_DFH(RING_IMR, D_ALL, F_CMD_ACCESS, NULL, 1768 intel_vgpu_reg_imr_handler); 1769 1770 MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler); 1771 MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler); 1772 MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler); 1773 MMIO_D(SDEISR, D_ALL); 1774 1775 MMIO_RING_DFH(RING_HWSTAM, D_ALL, F_CMD_ACCESS, NULL, NULL); 1776 1777 MMIO_GM_RDR(RENDER_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1778 MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1779 MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1780 MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1781 1782 #define RING_REG(base) _MMIO((base) + 0x28) 1783 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL); 1784 #undef RING_REG 1785 1786 #define RING_REG(base) _MMIO((base) + 0x134) 1787 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL); 1788 #undef RING_REG 1789 1790 #define RING_REG(base) _MMIO((base) + 0x6c) 1791 MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL); 1792 #undef RING_REG 1793 MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL); 1794 1795 MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL); 1796 MMIO_GM_RDR(CCID, D_ALL, NULL, NULL); 1797 MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL); 1798 MMIO_D(GEN7_CXT_SIZE, D_ALL); 1799 1800 MMIO_RING_DFH(RING_TAIL, D_ALL, F_CMD_ACCESS, NULL, NULL); 1801 MMIO_RING_DFH(RING_HEAD, D_ALL, F_CMD_ACCESS, NULL, NULL); 1802 MMIO_RING_DFH(RING_CTL, D_ALL, F_CMD_ACCESS, NULL, NULL); 1803 MMIO_RING_DFH(RING_ACTHD, D_ALL, F_CMD_ACCESS, mmio_read_from_hw, NULL); 1804 MMIO_RING_GM_RDR(RING_START, D_ALL, NULL, NULL); 1805 1806 /* RING MODE */ 1807 #define RING_REG(base) _MMIO((base) + 0x29c) 1808 MMIO_RING_DFH(RING_REG, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, 1809 ring_mode_mmio_write); 1810 #undef RING_REG 1811 1812 MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 1813 NULL, NULL); 1814 MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 1815 NULL, NULL); 1816 MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS, 1817 mmio_read_from_hw, NULL); 1818 MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS, 1819 mmio_read_from_hw, NULL); 1820 1821 MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1822 MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 1823 NULL, NULL); 1824 MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1825 MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1826 MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1827 1828 MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1829 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1830 MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1831 MMIO_DFH(_MMIO(0x20e4), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1832 MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1833 MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL); 1834 MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 1835 NULL, NULL); 1836 MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 1837 NULL, NULL); 1838 MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL); 1839 MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL); 1840 MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL); 1841 MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL); 1842 MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL); 1843 MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL); 1844 MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL); 1845 MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1846 MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1847 MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1848 1849 /* display */ 1850 MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL); 1851 MMIO_D(_MMIO(0x602a0), D_ALL); 1852 1853 MMIO_D(_MMIO(0x65050), D_ALL); 1854 MMIO_D(_MMIO(0x650b4), D_ALL); 1855 1856 MMIO_D(_MMIO(0xc4040), D_ALL); 1857 MMIO_D(DERRMR, D_ALL); 1858 1859 MMIO_D(PIPEDSL(PIPE_A), D_ALL); 1860 MMIO_D(PIPEDSL(PIPE_B), D_ALL); 1861 MMIO_D(PIPEDSL(PIPE_C), D_ALL); 1862 MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL); 1863 1864 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write); 1865 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write); 1866 MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write); 1867 MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write); 1868 1869 MMIO_D(PIPESTAT(PIPE_A), D_ALL); 1870 MMIO_D(PIPESTAT(PIPE_B), D_ALL); 1871 MMIO_D(PIPESTAT(PIPE_C), D_ALL); 1872 MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL); 1873 1874 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL); 1875 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL); 1876 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL); 1877 MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL); 1878 1879 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL); 1880 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL); 1881 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL); 1882 MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL); 1883 1884 MMIO_D(CURCNTR(PIPE_A), D_ALL); 1885 MMIO_D(CURCNTR(PIPE_B), D_ALL); 1886 MMIO_D(CURCNTR(PIPE_C), D_ALL); 1887 1888 MMIO_D(CURPOS(PIPE_A), D_ALL); 1889 MMIO_D(CURPOS(PIPE_B), D_ALL); 1890 MMIO_D(CURPOS(PIPE_C), D_ALL); 1891 1892 MMIO_D(CURBASE(PIPE_A), D_ALL); 1893 MMIO_D(CURBASE(PIPE_B), D_ALL); 1894 MMIO_D(CURBASE(PIPE_C), D_ALL); 1895 1896 MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL); 1897 MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL); 1898 MMIO_D(CUR_FBC_CTL(PIPE_C), D_ALL); 1899 1900 MMIO_D(_MMIO(0x700ac), D_ALL); 1901 MMIO_D(_MMIO(0x710ac), D_ALL); 1902 MMIO_D(_MMIO(0x720ac), D_ALL); 1903 1904 MMIO_D(_MMIO(0x70090), D_ALL); 1905 MMIO_D(_MMIO(0x70094), D_ALL); 1906 MMIO_D(_MMIO(0x70098), D_ALL); 1907 MMIO_D(_MMIO(0x7009c), D_ALL); 1908 1909 MMIO_D(DSPCNTR(PIPE_A), D_ALL); 1910 MMIO_D(DSPADDR(PIPE_A), D_ALL); 1911 MMIO_D(DSPSTRIDE(PIPE_A), D_ALL); 1912 MMIO_D(DSPPOS(PIPE_A), D_ALL); 1913 MMIO_D(DSPSIZE(PIPE_A), D_ALL); 1914 MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write); 1915 MMIO_D(DSPOFFSET(PIPE_A), D_ALL); 1916 MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL); 1917 1918 MMIO_D(DSPCNTR(PIPE_B), D_ALL); 1919 MMIO_D(DSPADDR(PIPE_B), D_ALL); 1920 MMIO_D(DSPSTRIDE(PIPE_B), D_ALL); 1921 MMIO_D(DSPPOS(PIPE_B), D_ALL); 1922 MMIO_D(DSPSIZE(PIPE_B), D_ALL); 1923 MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write); 1924 MMIO_D(DSPOFFSET(PIPE_B), D_ALL); 1925 MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL); 1926 1927 MMIO_D(DSPCNTR(PIPE_C), D_ALL); 1928 MMIO_D(DSPADDR(PIPE_C), D_ALL); 1929 MMIO_D(DSPSTRIDE(PIPE_C), D_ALL); 1930 MMIO_D(DSPPOS(PIPE_C), D_ALL); 1931 MMIO_D(DSPSIZE(PIPE_C), D_ALL); 1932 MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write); 1933 MMIO_D(DSPOFFSET(PIPE_C), D_ALL); 1934 MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL); 1935 1936 MMIO_D(SPRCTL(PIPE_A), D_ALL); 1937 MMIO_D(SPRLINOFF(PIPE_A), D_ALL); 1938 MMIO_D(SPRSTRIDE(PIPE_A), D_ALL); 1939 MMIO_D(SPRPOS(PIPE_A), D_ALL); 1940 MMIO_D(SPRSIZE(PIPE_A), D_ALL); 1941 MMIO_D(SPRKEYVAL(PIPE_A), D_ALL); 1942 MMIO_D(SPRKEYMSK(PIPE_A), D_ALL); 1943 MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write); 1944 MMIO_D(SPRKEYMAX(PIPE_A), D_ALL); 1945 MMIO_D(SPROFFSET(PIPE_A), D_ALL); 1946 MMIO_D(SPRSCALE(PIPE_A), D_ALL); 1947 MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL); 1948 1949 MMIO_D(SPRCTL(PIPE_B), D_ALL); 1950 MMIO_D(SPRLINOFF(PIPE_B), D_ALL); 1951 MMIO_D(SPRSTRIDE(PIPE_B), D_ALL); 1952 MMIO_D(SPRPOS(PIPE_B), D_ALL); 1953 MMIO_D(SPRSIZE(PIPE_B), D_ALL); 1954 MMIO_D(SPRKEYVAL(PIPE_B), D_ALL); 1955 MMIO_D(SPRKEYMSK(PIPE_B), D_ALL); 1956 MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write); 1957 MMIO_D(SPRKEYMAX(PIPE_B), D_ALL); 1958 MMIO_D(SPROFFSET(PIPE_B), D_ALL); 1959 MMIO_D(SPRSCALE(PIPE_B), D_ALL); 1960 MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL); 1961 1962 MMIO_D(SPRCTL(PIPE_C), D_ALL); 1963 MMIO_D(SPRLINOFF(PIPE_C), D_ALL); 1964 MMIO_D(SPRSTRIDE(PIPE_C), D_ALL); 1965 MMIO_D(SPRPOS(PIPE_C), D_ALL); 1966 MMIO_D(SPRSIZE(PIPE_C), D_ALL); 1967 MMIO_D(SPRKEYVAL(PIPE_C), D_ALL); 1968 MMIO_D(SPRKEYMSK(PIPE_C), D_ALL); 1969 MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write); 1970 MMIO_D(SPRKEYMAX(PIPE_C), D_ALL); 1971 MMIO_D(SPROFFSET(PIPE_C), D_ALL); 1972 MMIO_D(SPRSCALE(PIPE_C), D_ALL); 1973 MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL); 1974 1975 MMIO_D(HTOTAL(TRANSCODER_A), D_ALL); 1976 MMIO_D(HBLANK(TRANSCODER_A), D_ALL); 1977 MMIO_D(HSYNC(TRANSCODER_A), D_ALL); 1978 MMIO_D(VTOTAL(TRANSCODER_A), D_ALL); 1979 MMIO_D(VBLANK(TRANSCODER_A), D_ALL); 1980 MMIO_D(VSYNC(TRANSCODER_A), D_ALL); 1981 MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL); 1982 MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL); 1983 MMIO_D(PIPESRC(TRANSCODER_A), D_ALL); 1984 1985 MMIO_D(HTOTAL(TRANSCODER_B), D_ALL); 1986 MMIO_D(HBLANK(TRANSCODER_B), D_ALL); 1987 MMIO_D(HSYNC(TRANSCODER_B), D_ALL); 1988 MMIO_D(VTOTAL(TRANSCODER_B), D_ALL); 1989 MMIO_D(VBLANK(TRANSCODER_B), D_ALL); 1990 MMIO_D(VSYNC(TRANSCODER_B), D_ALL); 1991 MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL); 1992 MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL); 1993 MMIO_D(PIPESRC(TRANSCODER_B), D_ALL); 1994 1995 MMIO_D(HTOTAL(TRANSCODER_C), D_ALL); 1996 MMIO_D(HBLANK(TRANSCODER_C), D_ALL); 1997 MMIO_D(HSYNC(TRANSCODER_C), D_ALL); 1998 MMIO_D(VTOTAL(TRANSCODER_C), D_ALL); 1999 MMIO_D(VBLANK(TRANSCODER_C), D_ALL); 2000 MMIO_D(VSYNC(TRANSCODER_C), D_ALL); 2001 MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL); 2002 MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL); 2003 MMIO_D(PIPESRC(TRANSCODER_C), D_ALL); 2004 2005 MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL); 2006 MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL); 2007 MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL); 2008 MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL); 2009 MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL); 2010 MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL); 2011 MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL); 2012 MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL); 2013 2014 MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL); 2015 MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL); 2016 MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL); 2017 MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL); 2018 MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL); 2019 MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL); 2020 MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL); 2021 MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL); 2022 2023 MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL); 2024 MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL); 2025 MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL); 2026 MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL); 2027 MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL); 2028 MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL); 2029 MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL); 2030 MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL); 2031 2032 MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL); 2033 MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL); 2034 MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL); 2035 MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL); 2036 MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL); 2037 MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL); 2038 MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL); 2039 MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL); 2040 2041 MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL); 2042 MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL); 2043 MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL); 2044 MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL); 2045 MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL); 2046 MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL); 2047 MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL); 2048 MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL); 2049 2050 MMIO_D(PF_CTL(PIPE_A), D_ALL); 2051 MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL); 2052 MMIO_D(PF_WIN_POS(PIPE_A), D_ALL); 2053 MMIO_D(PF_VSCALE(PIPE_A), D_ALL); 2054 MMIO_D(PF_HSCALE(PIPE_A), D_ALL); 2055 2056 MMIO_D(PF_CTL(PIPE_B), D_ALL); 2057 MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL); 2058 MMIO_D(PF_WIN_POS(PIPE_B), D_ALL); 2059 MMIO_D(PF_VSCALE(PIPE_B), D_ALL); 2060 MMIO_D(PF_HSCALE(PIPE_B), D_ALL); 2061 2062 MMIO_D(PF_CTL(PIPE_C), D_ALL); 2063 MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL); 2064 MMIO_D(PF_WIN_POS(PIPE_C), D_ALL); 2065 MMIO_D(PF_VSCALE(PIPE_C), D_ALL); 2066 MMIO_D(PF_HSCALE(PIPE_C), D_ALL); 2067 2068 MMIO_D(WM0_PIPEA_ILK, D_ALL); 2069 MMIO_D(WM0_PIPEB_ILK, D_ALL); 2070 MMIO_D(WM0_PIPEC_IVB, D_ALL); 2071 MMIO_D(WM1_LP_ILK, D_ALL); 2072 MMIO_D(WM2_LP_ILK, D_ALL); 2073 MMIO_D(WM3_LP_ILK, D_ALL); 2074 MMIO_D(WM1S_LP_ILK, D_ALL); 2075 MMIO_D(WM2S_LP_IVB, D_ALL); 2076 MMIO_D(WM3S_LP_IVB, D_ALL); 2077 2078 MMIO_D(BLC_PWM_CPU_CTL2, D_ALL); 2079 MMIO_D(BLC_PWM_CPU_CTL, D_ALL); 2080 MMIO_D(BLC_PWM_PCH_CTL1, D_ALL); 2081 MMIO_D(BLC_PWM_PCH_CTL2, D_ALL); 2082 2083 MMIO_D(_MMIO(0x48268), D_ALL); 2084 2085 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read, 2086 gmbus_mmio_write); 2087 MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL); 2088 MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL); 2089 2090 MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 2091 dp_aux_ch_ctl_mmio_write); 2092 MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 2093 dp_aux_ch_ctl_mmio_write); 2094 MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 2095 dp_aux_ch_ctl_mmio_write); 2096 2097 MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write); 2098 2099 MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write); 2100 MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write); 2101 2102 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write); 2103 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write); 2104 MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write); 2105 MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); 2106 MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); 2107 MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); 2108 MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); 2109 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); 2110 MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); 2111 2112 MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A), D_ALL); 2113 MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A), D_ALL); 2114 MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A), D_ALL); 2115 MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A), D_ALL); 2116 MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A), D_ALL); 2117 MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A), D_ALL); 2118 MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A), D_ALL); 2119 2120 MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B), D_ALL); 2121 MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B), D_ALL); 2122 MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B), D_ALL); 2123 MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B), D_ALL); 2124 MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B), D_ALL); 2125 MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B), D_ALL); 2126 MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B), D_ALL); 2127 2128 MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1), D_ALL); 2129 MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1), D_ALL); 2130 MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2), D_ALL); 2131 MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2), D_ALL); 2132 MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1), D_ALL); 2133 MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1), D_ALL); 2134 MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2), D_ALL); 2135 MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2), D_ALL); 2136 2137 MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL); 2138 MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL); 2139 MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL); 2140 2141 MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL); 2142 MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL); 2143 MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL); 2144 2145 MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL); 2146 MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL); 2147 MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL); 2148 2149 MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL); 2150 MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL); 2151 MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL); 2152 2153 MMIO_D(_MMIO(_FDI_RXA_MISC), D_ALL); 2154 MMIO_D(_MMIO(_FDI_RXB_MISC), D_ALL); 2155 MMIO_D(_MMIO(_FDI_RXA_TUSIZE1), D_ALL); 2156 MMIO_D(_MMIO(_FDI_RXA_TUSIZE2), D_ALL); 2157 MMIO_D(_MMIO(_FDI_RXB_TUSIZE1), D_ALL); 2158 MMIO_D(_MMIO(_FDI_RXB_TUSIZE2), D_ALL); 2159 2160 MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write); 2161 MMIO_D(PCH_PP_DIVISOR, D_ALL); 2162 MMIO_D(PCH_PP_STATUS, D_ALL); 2163 MMIO_D(PCH_LVDS, D_ALL); 2164 MMIO_D(_MMIO(_PCH_DPLL_A), D_ALL); 2165 MMIO_D(_MMIO(_PCH_DPLL_B), D_ALL); 2166 MMIO_D(_MMIO(_PCH_FPA0), D_ALL); 2167 MMIO_D(_MMIO(_PCH_FPA1), D_ALL); 2168 MMIO_D(_MMIO(_PCH_FPB0), D_ALL); 2169 MMIO_D(_MMIO(_PCH_FPB1), D_ALL); 2170 MMIO_D(PCH_DREF_CONTROL, D_ALL); 2171 MMIO_D(PCH_RAWCLK_FREQ, D_ALL); 2172 MMIO_D(PCH_DPLL_SEL, D_ALL); 2173 2174 MMIO_D(_MMIO(0x61208), D_ALL); 2175 MMIO_D(_MMIO(0x6120c), D_ALL); 2176 MMIO_D(PCH_PP_ON_DELAYS, D_ALL); 2177 MMIO_D(PCH_PP_OFF_DELAYS, D_ALL); 2178 2179 MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL); 2180 MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL); 2181 MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL); 2182 MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL); 2183 MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL); 2184 MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL); 2185 2186 MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0, 2187 PORTA_HOTPLUG_STATUS_MASK 2188 | PORTB_HOTPLUG_STATUS_MASK 2189 | PORTC_HOTPLUG_STATUS_MASK 2190 | PORTD_HOTPLUG_STATUS_MASK, 2191 NULL, NULL); 2192 2193 MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write); 2194 MMIO_D(FUSE_STRAP, D_ALL); 2195 MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL); 2196 2197 MMIO_D(DISP_ARB_CTL, D_ALL); 2198 MMIO_D(DISP_ARB_CTL2, D_ALL); 2199 2200 MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL); 2201 MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL); 2202 MMIO_D(ILK_DSPCLK_GATE_D, D_ALL); 2203 2204 MMIO_D(SOUTH_CHICKEN1, D_ALL); 2205 MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write); 2206 MMIO_D(_MMIO(_TRANSA_CHICKEN1), D_ALL); 2207 MMIO_D(_MMIO(_TRANSB_CHICKEN1), D_ALL); 2208 MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL); 2209 MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL); 2210 MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL); 2211 2212 MMIO_D(ILK_DPFC_CB_BASE, D_ALL); 2213 MMIO_D(ILK_DPFC_CONTROL, D_ALL); 2214 MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL); 2215 MMIO_D(ILK_DPFC_STATUS, D_ALL); 2216 MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL); 2217 MMIO_D(ILK_DPFC_CHICKEN, D_ALL); 2218 MMIO_D(ILK_FBC_RT_BASE, D_ALL); 2219 2220 MMIO_D(IPS_CTL, D_ALL); 2221 2222 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL); 2223 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL); 2224 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL); 2225 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL); 2226 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL); 2227 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL); 2228 MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL); 2229 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL); 2230 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL); 2231 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL); 2232 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL); 2233 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL); 2234 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL); 2235 2236 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL); 2237 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL); 2238 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL); 2239 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL); 2240 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL); 2241 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL); 2242 MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL); 2243 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL); 2244 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL); 2245 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL); 2246 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL); 2247 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL); 2248 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL); 2249 2250 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL); 2251 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL); 2252 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL); 2253 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL); 2254 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL); 2255 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL); 2256 MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL); 2257 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL); 2258 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL); 2259 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL); 2260 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL); 2261 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL); 2262 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL); 2263 2264 MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL); 2265 MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL); 2266 MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 2267 2268 MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL); 2269 MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL); 2270 MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 2271 2272 MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL); 2273 MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL); 2274 MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 2275 2276 MMIO_D(_MMIO(0x60110), D_ALL); 2277 MMIO_D(_MMIO(0x61110), D_ALL); 2278 MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL); 2279 MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL); 2280 MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL); 2281 MMIO_F(_MMIO(0x70440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2282 MMIO_F(_MMIO(0x71440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2283 MMIO_F(_MMIO(0x72440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2284 MMIO_F(_MMIO(0x7044c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2285 MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2286 MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2287 2288 MMIO_D(PIPE_WM_LINETIME(PIPE_A), D_ALL); 2289 MMIO_D(PIPE_WM_LINETIME(PIPE_B), D_ALL); 2290 MMIO_D(PIPE_WM_LINETIME(PIPE_C), D_ALL); 2291 MMIO_D(SPLL_CTL, D_ALL); 2292 MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL); 2293 MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL); 2294 MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL); 2295 MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL); 2296 MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL); 2297 MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL); 2298 MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL); 2299 MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL); 2300 MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL); 2301 MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL); 2302 2303 MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL); 2304 MMIO_D(_MMIO(0x46508), D_ALL); 2305 2306 MMIO_D(_MMIO(0x49080), D_ALL); 2307 MMIO_D(_MMIO(0x49180), D_ALL); 2308 MMIO_D(_MMIO(0x49280), D_ALL); 2309 2310 MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL); 2311 MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL); 2312 MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL); 2313 2314 MMIO_D(GAMMA_MODE(PIPE_A), D_ALL); 2315 MMIO_D(GAMMA_MODE(PIPE_B), D_ALL); 2316 MMIO_D(GAMMA_MODE(PIPE_C), D_ALL); 2317 2318 MMIO_D(PIPE_MULT(PIPE_A), D_ALL); 2319 MMIO_D(PIPE_MULT(PIPE_B), D_ALL); 2320 MMIO_D(PIPE_MULT(PIPE_C), D_ALL); 2321 2322 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL); 2323 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL); 2324 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL); 2325 2326 MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL); 2327 MMIO_D(SBI_ADDR, D_ALL); 2328 MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL); 2329 MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write); 2330 MMIO_D(PIXCLK_GATE, D_ALL); 2331 2332 MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL, 2333 dp_aux_ch_ctl_mmio_write); 2334 2335 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2336 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2337 MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2338 MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2339 MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2340 2341 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write); 2342 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write); 2343 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write); 2344 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write); 2345 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write); 2346 2347 MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write); 2348 MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write); 2349 MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write); 2350 MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write); 2351 MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL); 2352 2353 MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2354 MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2355 MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2356 MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2357 MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2358 2359 MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL); 2360 MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL); 2361 MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A), D_ALL); 2362 2363 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL); 2364 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL); 2365 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL); 2366 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL); 2367 2368 MMIO_D(_MMIO(_TRANSA_MSA_MISC), D_ALL); 2369 MMIO_D(_MMIO(_TRANSB_MSA_MISC), D_ALL); 2370 MMIO_D(_MMIO(_TRANSC_MSA_MISC), D_ALL); 2371 MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC), D_ALL); 2372 2373 MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL); 2374 MMIO_D(FORCEWAKE_ACK, D_ALL); 2375 MMIO_D(GEN6_GT_CORE_STATUS, D_ALL); 2376 MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL); 2377 MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL); 2378 MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL); 2379 MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write); 2380 MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL); 2381 MMIO_D(ECOBUS, D_ALL); 2382 MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL); 2383 MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL); 2384 MMIO_D(GEN6_RPNSWREQ, D_ALL); 2385 MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL); 2386 MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL); 2387 MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL); 2388 MMIO_D(GEN6_RPSTAT1, D_ALL); 2389 MMIO_D(GEN6_RP_CONTROL, D_ALL); 2390 MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL); 2391 MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL); 2392 MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL); 2393 MMIO_D(GEN6_RP_CUR_UP, D_ALL); 2394 MMIO_D(GEN6_RP_PREV_UP, D_ALL); 2395 MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL); 2396 MMIO_D(GEN6_RP_CUR_DOWN, D_ALL); 2397 MMIO_D(GEN6_RP_PREV_DOWN, D_ALL); 2398 MMIO_D(GEN6_RP_UP_EI, D_ALL); 2399 MMIO_D(GEN6_RP_DOWN_EI, D_ALL); 2400 MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL); 2401 MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL); 2402 MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL); 2403 MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL); 2404 MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL); 2405 MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL); 2406 MMIO_D(GEN6_RC_SLEEP, D_ALL); 2407 MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL); 2408 MMIO_D(GEN6_RC6_THRESHOLD, D_ALL); 2409 MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL); 2410 MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL); 2411 MMIO_D(GEN6_PMINTRMSK, D_ALL); 2412 /* 2413 * Use an arbitrary power well controlled by the PWR_WELL_CTL 2414 * register. 2415 */ 2416 MMIO_DH(HSW_PWR_WELL_CTL_BIOS(HSW_DISP_PW_GLOBAL), D_BDW, NULL, 2417 power_well_ctl_mmio_write); 2418 MMIO_DH(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL), D_BDW, NULL, 2419 power_well_ctl_mmio_write); 2420 MMIO_DH(HSW_PWR_WELL_CTL_KVMR, D_BDW, NULL, power_well_ctl_mmio_write); 2421 MMIO_DH(HSW_PWR_WELL_CTL_DEBUG(HSW_DISP_PW_GLOBAL), D_BDW, NULL, 2422 power_well_ctl_mmio_write); 2423 MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write); 2424 MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write); 2425 2426 MMIO_D(RSTDBYCTL, D_ALL); 2427 2428 MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write); 2429 MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write); 2430 MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write); 2431 2432 MMIO_D(TILECTL, D_ALL); 2433 2434 MMIO_D(GEN6_UCGCTL1, D_ALL); 2435 MMIO_D(GEN6_UCGCTL2, D_ALL); 2436 2437 MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL); 2438 2439 MMIO_D(GEN6_PCODE_DATA, D_ALL); 2440 MMIO_D(_MMIO(0x13812c), D_ALL); 2441 MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL); 2442 MMIO_D(HSW_EDRAM_CAP, D_ALL); 2443 MMIO_D(HSW_IDICR, D_ALL); 2444 MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL); 2445 2446 MMIO_D(_MMIO(0x3c), D_ALL); 2447 MMIO_D(_MMIO(0x860), D_ALL); 2448 MMIO_D(ECOSKPD, D_ALL); 2449 MMIO_D(_MMIO(0x121d0), D_ALL); 2450 MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL); 2451 MMIO_D(_MMIO(0x41d0), D_ALL); 2452 MMIO_D(GAC_ECO_BITS, D_ALL); 2453 MMIO_D(_MMIO(0x6200), D_ALL); 2454 MMIO_D(_MMIO(0x6204), D_ALL); 2455 MMIO_D(_MMIO(0x6208), D_ALL); 2456 MMIO_D(_MMIO(0x7118), D_ALL); 2457 MMIO_D(_MMIO(0x7180), D_ALL); 2458 MMIO_D(_MMIO(0x7408), D_ALL); 2459 MMIO_D(_MMIO(0x7c00), D_ALL); 2460 MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write); 2461 MMIO_D(_MMIO(0x911c), D_ALL); 2462 MMIO_D(_MMIO(0x9120), D_ALL); 2463 MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL); 2464 2465 MMIO_D(GAB_CTL, D_ALL); 2466 MMIO_D(_MMIO(0x48800), D_ALL); 2467 MMIO_D(_MMIO(0xce044), D_ALL); 2468 MMIO_D(_MMIO(0xe6500), D_ALL); 2469 MMIO_D(_MMIO(0xe6504), D_ALL); 2470 MMIO_D(_MMIO(0xe6600), D_ALL); 2471 MMIO_D(_MMIO(0xe6604), D_ALL); 2472 MMIO_D(_MMIO(0xe6700), D_ALL); 2473 MMIO_D(_MMIO(0xe6704), D_ALL); 2474 MMIO_D(_MMIO(0xe6800), D_ALL); 2475 MMIO_D(_MMIO(0xe6804), D_ALL); 2476 MMIO_D(PCH_GMBUS4, D_ALL); 2477 MMIO_D(PCH_GMBUS5, D_ALL); 2478 2479 MMIO_D(_MMIO(0x902c), D_ALL); 2480 MMIO_D(_MMIO(0xec008), D_ALL); 2481 MMIO_D(_MMIO(0xec00c), D_ALL); 2482 MMIO_D(_MMIO(0xec008 + 0x18), D_ALL); 2483 MMIO_D(_MMIO(0xec00c + 0x18), D_ALL); 2484 MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL); 2485 MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL); 2486 MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL); 2487 MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL); 2488 MMIO_D(_MMIO(0xec408), D_ALL); 2489 MMIO_D(_MMIO(0xec40c), D_ALL); 2490 MMIO_D(_MMIO(0xec408 + 0x18), D_ALL); 2491 MMIO_D(_MMIO(0xec40c + 0x18), D_ALL); 2492 MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL); 2493 MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL); 2494 MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL); 2495 MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL); 2496 MMIO_D(_MMIO(0xfc810), D_ALL); 2497 MMIO_D(_MMIO(0xfc81c), D_ALL); 2498 MMIO_D(_MMIO(0xfc828), D_ALL); 2499 MMIO_D(_MMIO(0xfc834), D_ALL); 2500 MMIO_D(_MMIO(0xfcc00), D_ALL); 2501 MMIO_D(_MMIO(0xfcc0c), D_ALL); 2502 MMIO_D(_MMIO(0xfcc18), D_ALL); 2503 MMIO_D(_MMIO(0xfcc24), D_ALL); 2504 MMIO_D(_MMIO(0xfd000), D_ALL); 2505 MMIO_D(_MMIO(0xfd00c), D_ALL); 2506 MMIO_D(_MMIO(0xfd018), D_ALL); 2507 MMIO_D(_MMIO(0xfd024), D_ALL); 2508 MMIO_D(_MMIO(0xfd034), D_ALL); 2509 2510 MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write); 2511 MMIO_D(_MMIO(0x2054), D_ALL); 2512 MMIO_D(_MMIO(0x12054), D_ALL); 2513 MMIO_D(_MMIO(0x22054), D_ALL); 2514 MMIO_D(_MMIO(0x1a054), D_ALL); 2515 2516 MMIO_D(_MMIO(0x44070), D_ALL); 2517 MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2518 MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL); 2519 MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL); 2520 MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL); 2521 MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL); 2522 2523 MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL); 2524 MMIO_D(_MMIO(0x2b00), D_BDW_PLUS); 2525 MMIO_D(_MMIO(0x2360), D_BDW_PLUS); 2526 MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2527 MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2528 MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2529 2530 MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2531 MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2532 MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL); 2533 2534 MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2535 MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2536 MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2537 MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2538 MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2539 MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2540 MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2541 MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2542 MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2543 MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2544 MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2545 MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2546 MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2547 MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2548 MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2549 MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2550 MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2551 2552 MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2553 MMIO_RING_GM_RDR(RING_BBADDR, D_ALL, NULL, NULL); 2554 MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL); 2555 MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL); 2556 MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL); 2557 MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL); 2558 MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL); 2559 MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2560 MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2561 MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2562 MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2563 return 0; 2564 } 2565 2566 static int init_broadwell_mmio_info(struct intel_gvt *gvt) 2567 { 2568 struct drm_i915_private *dev_priv = gvt->dev_priv; 2569 int ret; 2570 2571 MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2572 MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2573 MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2574 MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS); 2575 2576 MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2577 MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2578 MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2579 MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS); 2580 2581 MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2582 MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2583 MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2584 MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS); 2585 2586 MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2587 MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2588 MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2589 MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS); 2590 2591 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL, 2592 intel_vgpu_reg_imr_handler); 2593 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL, 2594 intel_vgpu_reg_ier_handler); 2595 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL, 2596 intel_vgpu_reg_iir_handler); 2597 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS); 2598 2599 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL, 2600 intel_vgpu_reg_imr_handler); 2601 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL, 2602 intel_vgpu_reg_ier_handler); 2603 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL, 2604 intel_vgpu_reg_iir_handler); 2605 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS); 2606 2607 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL, 2608 intel_vgpu_reg_imr_handler); 2609 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL, 2610 intel_vgpu_reg_ier_handler); 2611 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL, 2612 intel_vgpu_reg_iir_handler); 2613 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS); 2614 2615 MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2616 MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2617 MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2618 MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS); 2619 2620 MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2621 MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2622 MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2623 MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS); 2624 2625 MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2626 MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2627 MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2628 MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS); 2629 2630 MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL, 2631 intel_vgpu_reg_master_irq_handler); 2632 2633 MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, F_CMD_ACCESS, 2634 mmio_read_from_hw, NULL); 2635 2636 #define RING_REG(base) _MMIO((base) + 0xd0) 2637 MMIO_RING_F(RING_REG, 4, F_RO, 0, 2638 ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL, 2639 ring_reset_ctl_write); 2640 #undef RING_REG 2641 2642 #define RING_REG(base) _MMIO((base) + 0x230) 2643 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write); 2644 #undef RING_REG 2645 2646 #define RING_REG(base) _MMIO((base) + 0x234) 2647 MMIO_RING_F(RING_REG, 8, F_RO | F_CMD_ACCESS, 0, ~0, D_BDW_PLUS, 2648 NULL, NULL); 2649 #undef RING_REG 2650 2651 #define RING_REG(base) _MMIO((base) + 0x244) 2652 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2653 #undef RING_REG 2654 2655 #define RING_REG(base) _MMIO((base) + 0x370) 2656 MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL); 2657 #undef RING_REG 2658 2659 #define RING_REG(base) _MMIO((base) + 0x3a0) 2660 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2661 #undef RING_REG 2662 2663 MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS); 2664 MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS); 2665 MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS); 2666 MMIO_D(_MMIO(0x1c1d0), D_BDW_PLUS); 2667 MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS); 2668 MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS); 2669 MMIO_D(_MMIO(0x1c054), D_BDW_PLUS); 2670 2671 MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write); 2672 2673 MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS); 2674 MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS); 2675 2676 MMIO_D(GAMTARBMODE, D_BDW_PLUS); 2677 2678 #define RING_REG(base) _MMIO((base) + 0x270) 2679 MMIO_RING_F(RING_REG, 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL); 2680 #undef RING_REG 2681 2682 MMIO_RING_GM_RDR(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write); 2683 2684 MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2685 2686 MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS); 2687 MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS); 2688 MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS); 2689 2690 MMIO_D(WM_MISC, D_BDW); 2691 MMIO_D(_MMIO(BDW_EDP_PSR_BASE), D_BDW); 2692 2693 MMIO_D(_MMIO(0x6671c), D_BDW_PLUS); 2694 MMIO_D(_MMIO(0x66c00), D_BDW_PLUS); 2695 MMIO_D(_MMIO(0x66c04), D_BDW_PLUS); 2696 2697 MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS); 2698 2699 MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS); 2700 MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS); 2701 MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS); 2702 2703 MMIO_D(_MMIO(0xfdc), D_BDW_PLUS); 2704 MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2705 NULL, NULL); 2706 MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2707 NULL, NULL); 2708 MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2709 2710 MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL); 2711 MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL); 2712 MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2713 MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL); 2714 MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL); 2715 MMIO_D(_MMIO(0xb110), D_BDW); 2716 2717 MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, 2718 NULL, force_nonpriv_write); 2719 2720 MMIO_D(_MMIO(0x44484), D_BDW_PLUS); 2721 MMIO_D(_MMIO(0x4448c), D_BDW_PLUS); 2722 2723 MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL); 2724 MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS); 2725 2726 MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL); 2727 2728 MMIO_D(_MMIO(0x110000), D_BDW_PLUS); 2729 2730 MMIO_D(_MMIO(0x48400), D_BDW_PLUS); 2731 2732 MMIO_D(_MMIO(0x6e570), D_BDW_PLUS); 2733 MMIO_D(_MMIO(0x65f10), D_BDW_PLUS); 2734 2735 MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2736 MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2737 MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2738 MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2739 2740 MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL); 2741 2742 MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2743 MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2744 MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2745 MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2746 MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2747 MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2748 MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2749 MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2750 MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2751 return 0; 2752 } 2753 2754 static int init_skl_mmio_info(struct intel_gvt *gvt) 2755 { 2756 struct drm_i915_private *dev_priv = gvt->dev_priv; 2757 int ret; 2758 2759 MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2760 MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL); 2761 MMIO_DH(FORCEWAKE_BLITTER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2762 MMIO_DH(FORCEWAKE_ACK_BLITTER_GEN9, D_SKL_PLUS, NULL, NULL); 2763 MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2764 MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL); 2765 2766 MMIO_F(_MMIO(_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 2767 dp_aux_ch_ctl_mmio_write); 2768 MMIO_F(_MMIO(_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 2769 dp_aux_ch_ctl_mmio_write); 2770 MMIO_F(_MMIO(_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 2771 dp_aux_ch_ctl_mmio_write); 2772 2773 /* 2774 * Use an arbitrary power well controlled by the PWR_WELL_CTL 2775 * register. 2776 */ 2777 MMIO_D(HSW_PWR_WELL_CTL_BIOS(SKL_DISP_PW_MISC_IO), D_SKL_PLUS); 2778 MMIO_DH(HSW_PWR_WELL_CTL_DRIVER(SKL_DISP_PW_MISC_IO), D_SKL_PLUS, NULL, 2779 skl_power_well_ctl_write); 2780 2781 MMIO_D(_MMIO(0xa210), D_SKL_PLUS); 2782 MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS); 2783 MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS); 2784 MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2785 MMIO_DH(_MMIO(0x4ddc), D_SKL_PLUS, NULL, NULL); 2786 MMIO_DH(_MMIO(0x42080), D_SKL_PLUS, NULL, NULL); 2787 MMIO_D(_MMIO(0x45504), D_SKL_PLUS); 2788 MMIO_D(_MMIO(0x45520), D_SKL_PLUS); 2789 MMIO_D(_MMIO(0x46000), D_SKL_PLUS); 2790 MMIO_DH(_MMIO(0x46010), D_SKL_PLUS, NULL, skl_lcpll_write); 2791 MMIO_DH(_MMIO(0x46014), D_SKL_PLUS, NULL, skl_lcpll_write); 2792 MMIO_D(_MMIO(0x6C040), D_SKL_PLUS); 2793 MMIO_D(_MMIO(0x6C048), D_SKL_PLUS); 2794 MMIO_D(_MMIO(0x6C050), D_SKL_PLUS); 2795 MMIO_D(_MMIO(0x6C044), D_SKL_PLUS); 2796 MMIO_D(_MMIO(0x6C04C), D_SKL_PLUS); 2797 MMIO_D(_MMIO(0x6C054), D_SKL_PLUS); 2798 MMIO_D(_MMIO(0x6c058), D_SKL_PLUS); 2799 MMIO_D(_MMIO(0x6c05c), D_SKL_PLUS); 2800 MMIO_DH(_MMIO(0x6c060), D_SKL_PLUS, dpll_status_read, NULL); 2801 2802 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); 2803 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); 2804 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); 2805 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); 2806 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); 2807 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); 2808 2809 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); 2810 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); 2811 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); 2812 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); 2813 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); 2814 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); 2815 2816 MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); 2817 MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); 2818 MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); 2819 MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); 2820 MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); 2821 MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); 2822 2823 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 2824 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 2825 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 2826 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); 2827 2828 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 2829 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 2830 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 2831 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); 2832 2833 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 2834 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 2835 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2836 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); 2837 2838 MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL); 2839 MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL); 2840 MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL); 2841 2842 MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2843 MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2844 MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2845 2846 MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2847 MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2848 MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2849 2850 MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2851 MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2852 MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2853 2854 MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2855 MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2856 MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2857 2858 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 2859 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 2860 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 2861 2862 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 2863 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 2864 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 2865 2866 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 2867 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 2868 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2869 2870 MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL); 2871 MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL); 2872 MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL); 2873 2874 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 2875 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 2876 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 2877 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); 2878 2879 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 2880 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 2881 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 2882 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); 2883 2884 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 2885 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 2886 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2887 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); 2888 2889 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL); 2890 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL); 2891 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL); 2892 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL); 2893 2894 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL); 2895 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL); 2896 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL); 2897 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL); 2898 2899 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL); 2900 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL); 2901 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL); 2902 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL); 2903 2904 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL); 2905 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL); 2906 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL); 2907 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL); 2908 2909 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL); 2910 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL); 2911 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL); 2912 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL); 2913 2914 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL); 2915 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL); 2916 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL); 2917 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL); 2918 2919 MMIO_D(_MMIO(0x70380), D_SKL_PLUS); 2920 MMIO_D(_MMIO(0x71380), D_SKL_PLUS); 2921 MMIO_D(_MMIO(0x72380), D_SKL_PLUS); 2922 MMIO_D(_MMIO(0x7239c), D_SKL_PLUS); 2923 MMIO_D(_MMIO(0x7039c), D_SKL_PLUS); 2924 2925 MMIO_D(_MMIO(0x8f074), D_SKL_PLUS); 2926 MMIO_D(_MMIO(0x8f004), D_SKL_PLUS); 2927 MMIO_D(_MMIO(0x8f034), D_SKL_PLUS); 2928 2929 MMIO_D(_MMIO(0xb11c), D_SKL_PLUS); 2930 2931 MMIO_D(_MMIO(0x51000), D_SKL_PLUS); 2932 MMIO_D(_MMIO(0x6c00c), D_SKL_PLUS); 2933 2934 MMIO_F(_MMIO(0xc800), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS, 2935 NULL, NULL); 2936 MMIO_F(_MMIO(0xb020), 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS, 2937 NULL, NULL); 2938 2939 MMIO_D(RPM_CONFIG0, D_SKL_PLUS); 2940 MMIO_D(_MMIO(0xd08), D_SKL_PLUS); 2941 MMIO_D(RC6_LOCATION, D_SKL_PLUS); 2942 MMIO_DFH(_MMIO(0x20e0), D_SKL_PLUS, F_MODE_MASK, NULL, NULL); 2943 MMIO_DFH(_MMIO(0x20ec), D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2944 NULL, NULL); 2945 2946 /* TRTT */ 2947 MMIO_DFH(_MMIO(0x4de0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2948 MMIO_DFH(_MMIO(0x4de4), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2949 MMIO_DFH(_MMIO(0x4de8), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2950 MMIO_DFH(_MMIO(0x4dec), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2951 MMIO_DFH(_MMIO(0x4df0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2952 MMIO_DFH(_MMIO(0x4df4), D_SKL_PLUS, F_CMD_ACCESS, 2953 NULL, gen9_trtte_write); 2954 MMIO_DH(_MMIO(0x4dfc), D_SKL_PLUS, NULL, gen9_trtt_chicken_write); 2955 2956 MMIO_D(_MMIO(0x45008), D_SKL_PLUS); 2957 2958 MMIO_D(_MMIO(0x46430), D_SKL_PLUS); 2959 2960 MMIO_D(_MMIO(0x46520), D_SKL_PLUS); 2961 2962 MMIO_D(_MMIO(0xc403c), D_SKL_PLUS); 2963 MMIO_D(_MMIO(0xb004), D_SKL_PLUS); 2964 MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write); 2965 2966 MMIO_D(_MMIO(0x65900), D_SKL_PLUS); 2967 MMIO_D(_MMIO(0x1082c0), D_SKL_PLUS); 2968 MMIO_D(_MMIO(0x4068), D_SKL_PLUS); 2969 MMIO_D(_MMIO(0x67054), D_SKL_PLUS); 2970 MMIO_D(_MMIO(0x6e560), D_SKL_PLUS); 2971 MMIO_D(_MMIO(0x6e554), D_SKL_PLUS); 2972 MMIO_D(_MMIO(0x2b20), D_SKL_PLUS); 2973 MMIO_D(_MMIO(0x65f00), D_SKL_PLUS); 2974 MMIO_D(_MMIO(0x65f08), D_SKL_PLUS); 2975 MMIO_D(_MMIO(0x320f0), D_SKL_PLUS); 2976 2977 MMIO_D(_MMIO(0x70034), D_SKL_PLUS); 2978 MMIO_D(_MMIO(0x71034), D_SKL_PLUS); 2979 MMIO_D(_MMIO(0x72034), D_SKL_PLUS); 2980 2981 MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A)), D_SKL_PLUS); 2982 MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B)), D_SKL_PLUS); 2983 MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C)), D_SKL_PLUS); 2984 MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A)), D_SKL_PLUS); 2985 MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B)), D_SKL_PLUS); 2986 MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C)), D_SKL_PLUS); 2987 MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A)), D_SKL_PLUS); 2988 MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)), D_SKL_PLUS); 2989 MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)), D_SKL_PLUS); 2990 2991 MMIO_D(_MMIO(0x44500), D_SKL_PLUS); 2992 MMIO_DFH(GEN9_CSFE_CHICKEN1_RCS, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2993 MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2994 NULL, NULL); 2995 2996 MMIO_D(_MMIO(0x4ab8), D_KBL); 2997 MMIO_D(_MMIO(0x2248), D_KBL | D_SKL); 2998 2999 return 0; 3000 } 3001 3002 static int init_bxt_mmio_info(struct intel_gvt *gvt) 3003 { 3004 struct drm_i915_private *dev_priv = gvt->dev_priv; 3005 int ret; 3006 3007 MMIO_F(_MMIO(0x80000), 0x3000, 0, 0, 0, D_BXT, NULL, NULL); 3008 3009 MMIO_D(GEN7_SAMPLER_INSTDONE, D_BXT); 3010 MMIO_D(GEN7_ROW_INSTDONE, D_BXT); 3011 MMIO_D(GEN8_FAULT_TLB_DATA0, D_BXT); 3012 MMIO_D(GEN8_FAULT_TLB_DATA1, D_BXT); 3013 MMIO_D(ERROR_GEN6, D_BXT); 3014 MMIO_D(DONE_REG, D_BXT); 3015 MMIO_D(EIR, D_BXT); 3016 MMIO_D(PGTBL_ER, D_BXT); 3017 MMIO_D(_MMIO(0x4194), D_BXT); 3018 MMIO_D(_MMIO(0x4294), D_BXT); 3019 MMIO_D(_MMIO(0x4494), D_BXT); 3020 3021 MMIO_RING_D(RING_PSMI_CTL, D_BXT); 3022 MMIO_RING_D(RING_DMA_FADD, D_BXT); 3023 MMIO_RING_D(RING_DMA_FADD_UDW, D_BXT); 3024 MMIO_RING_D(RING_IPEHR, D_BXT); 3025 MMIO_RING_D(RING_INSTPS, D_BXT); 3026 MMIO_RING_D(RING_BBADDR_UDW, D_BXT); 3027 MMIO_RING_D(RING_BBSTATE, D_BXT); 3028 MMIO_RING_D(RING_IPEIR, D_BXT); 3029 3030 MMIO_F(SOFT_SCRATCH(0), 16 * 4, 0, 0, 0, D_BXT, NULL, NULL); 3031 3032 MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write); 3033 MMIO_D(BXT_RP_STATE_CAP, D_BXT); 3034 MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT, 3035 NULL, bxt_phy_ctl_family_write); 3036 MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT, 3037 NULL, bxt_phy_ctl_family_write); 3038 MMIO_D(BXT_PHY_CTL(PORT_A), D_BXT); 3039 MMIO_D(BXT_PHY_CTL(PORT_B), D_BXT); 3040 MMIO_D(BXT_PHY_CTL(PORT_C), D_BXT); 3041 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT, 3042 NULL, bxt_port_pll_enable_write); 3043 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT, 3044 NULL, bxt_port_pll_enable_write); 3045 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL, 3046 bxt_port_pll_enable_write); 3047 3048 MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY0), D_BXT); 3049 MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY0), D_BXT); 3050 MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY0), D_BXT); 3051 MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY0), D_BXT); 3052 MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY0), D_BXT); 3053 MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY0), D_BXT); 3054 MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY0), D_BXT); 3055 MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY0), D_BXT); 3056 MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY0), D_BXT); 3057 3058 MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY1), D_BXT); 3059 MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY1), D_BXT); 3060 MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY1), D_BXT); 3061 MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY1), D_BXT); 3062 MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY1), D_BXT); 3063 MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY1), D_BXT); 3064 MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY1), D_BXT); 3065 MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY1), D_BXT); 3066 MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY1), D_BXT); 3067 3068 MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH0), D_BXT); 3069 MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH0), D_BXT); 3070 MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH0), D_BXT); 3071 MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH0), D_BXT); 3072 MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH0), D_BXT); 3073 MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH0), D_BXT); 3074 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT, 3075 NULL, bxt_pcs_dw12_grp_write); 3076 MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH0), D_BXT); 3077 MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH0), D_BXT); 3078 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT, 3079 bxt_port_tx_dw3_read, NULL); 3080 MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH0), D_BXT); 3081 MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH0), D_BXT); 3082 MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH0), D_BXT); 3083 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT); 3084 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 1), D_BXT); 3085 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 2), D_BXT); 3086 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 3), D_BXT); 3087 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 0), D_BXT); 3088 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 1), D_BXT); 3089 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 2), D_BXT); 3090 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 3), D_BXT); 3091 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 6), D_BXT); 3092 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 8), D_BXT); 3093 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 9), D_BXT); 3094 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 10), D_BXT); 3095 3096 MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH1), D_BXT); 3097 MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH1), D_BXT); 3098 MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH1), D_BXT); 3099 MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH1), D_BXT); 3100 MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH1), D_BXT); 3101 MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH1), D_BXT); 3102 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT, 3103 NULL, bxt_pcs_dw12_grp_write); 3104 MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH1), D_BXT); 3105 MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH1), D_BXT); 3106 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT, 3107 bxt_port_tx_dw3_read, NULL); 3108 MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH1), D_BXT); 3109 MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH1), D_BXT); 3110 MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH1), D_BXT); 3111 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT); 3112 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 1), D_BXT); 3113 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 2), D_BXT); 3114 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 3), D_BXT); 3115 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 0), D_BXT); 3116 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 1), D_BXT); 3117 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 2), D_BXT); 3118 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 3), D_BXT); 3119 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 6), D_BXT); 3120 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 8), D_BXT); 3121 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 9), D_BXT); 3122 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 10), D_BXT); 3123 3124 MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY1, DPIO_CH0), D_BXT); 3125 MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY1, DPIO_CH0), D_BXT); 3126 MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY1, DPIO_CH0), D_BXT); 3127 MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY1, DPIO_CH0), D_BXT); 3128 MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY1, DPIO_CH0), D_BXT); 3129 MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY1, DPIO_CH0), D_BXT); 3130 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT, 3131 NULL, bxt_pcs_dw12_grp_write); 3132 MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY1, DPIO_CH0), D_BXT); 3133 MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY1, DPIO_CH0), D_BXT); 3134 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT, 3135 bxt_port_tx_dw3_read, NULL); 3136 MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY1, DPIO_CH0), D_BXT); 3137 MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY1, DPIO_CH0), D_BXT); 3138 MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY1, DPIO_CH0), D_BXT); 3139 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT); 3140 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 1), D_BXT); 3141 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 2), D_BXT); 3142 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 3), D_BXT); 3143 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 0), D_BXT); 3144 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 1), D_BXT); 3145 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 2), D_BXT); 3146 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 3), D_BXT); 3147 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 6), D_BXT); 3148 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 8), D_BXT); 3149 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 9), D_BXT); 3150 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 10), D_BXT); 3151 3152 MMIO_D(BXT_DE_PLL_CTL, D_BXT); 3153 MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write); 3154 MMIO_D(BXT_DSI_PLL_CTL, D_BXT); 3155 MMIO_D(BXT_DSI_PLL_ENABLE, D_BXT); 3156 3157 MMIO_D(GEN9_CLKGATE_DIS_0, D_BXT); 3158 3159 MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_A), D_BXT); 3160 MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT); 3161 MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C), D_BXT); 3162 3163 MMIO_D(RC6_CTX_BASE, D_BXT); 3164 3165 MMIO_D(GEN8_PUSHBUS_CONTROL, D_BXT); 3166 MMIO_D(GEN8_PUSHBUS_ENABLE, D_BXT); 3167 MMIO_D(GEN8_PUSHBUS_SHIFT, D_BXT); 3168 MMIO_D(GEN6_GFXPAUSE, D_BXT); 3169 MMIO_D(GEN8_L3SQCREG1, D_BXT); 3170 3171 MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL); 3172 3173 return 0; 3174 } 3175 3176 static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt, 3177 unsigned int offset) 3178 { 3179 unsigned long device = intel_gvt_get_device_type(gvt); 3180 struct gvt_mmio_block *block = gvt->mmio.mmio_block; 3181 int num = gvt->mmio.num_mmio_block; 3182 int i; 3183 3184 for (i = 0; i < num; i++, block++) { 3185 if (!(device & block->device)) 3186 continue; 3187 if (offset >= i915_mmio_reg_offset(block->offset) && 3188 offset < i915_mmio_reg_offset(block->offset) + block->size) 3189 return block; 3190 } 3191 return NULL; 3192 } 3193 3194 /** 3195 * intel_gvt_clean_mmio_info - clean up MMIO information table for GVT device 3196 * @gvt: GVT device 3197 * 3198 * This function is called at the driver unloading stage, to clean up the MMIO 3199 * information table of GVT device 3200 * 3201 */ 3202 void intel_gvt_clean_mmio_info(struct intel_gvt *gvt) 3203 { 3204 struct hlist_node *tmp; 3205 struct intel_gvt_mmio_info *e; 3206 int i; 3207 3208 hash_for_each_safe(gvt->mmio.mmio_info_table, i, tmp, e, node) 3209 kfree(e); 3210 3211 vfree(gvt->mmio.mmio_attribute); 3212 gvt->mmio.mmio_attribute = NULL; 3213 } 3214 3215 /* Special MMIO blocks. */ 3216 static struct gvt_mmio_block mmio_blocks[] = { 3217 {D_SKL_PLUS, _MMIO(CSR_MMIO_START_RANGE), 0x3000, NULL, NULL}, 3218 {D_ALL, _MMIO(MCHBAR_MIRROR_BASE_SNB), 0x40000, NULL, NULL}, 3219 {D_ALL, _MMIO(VGT_PVINFO_PAGE), VGT_PVINFO_SIZE, 3220 pvinfo_mmio_read, pvinfo_mmio_write}, 3221 {D_ALL, LGC_PALETTE(PIPE_A, 0), 1024, NULL, NULL}, 3222 {D_ALL, LGC_PALETTE(PIPE_B, 0), 1024, NULL, NULL}, 3223 {D_ALL, LGC_PALETTE(PIPE_C, 0), 1024, NULL, NULL}, 3224 }; 3225 3226 /** 3227 * intel_gvt_setup_mmio_info - setup MMIO information table for GVT device 3228 * @gvt: GVT device 3229 * 3230 * This function is called at the initialization stage, to setup the MMIO 3231 * information table for GVT device 3232 * 3233 * Returns: 3234 * zero on success, negative if failed. 3235 */ 3236 int intel_gvt_setup_mmio_info(struct intel_gvt *gvt) 3237 { 3238 struct intel_gvt_device_info *info = &gvt->device_info; 3239 struct drm_i915_private *dev_priv = gvt->dev_priv; 3240 int size = info->mmio_size / 4 * sizeof(*gvt->mmio.mmio_attribute); 3241 int ret; 3242 3243 gvt->mmio.mmio_attribute = vzalloc(size); 3244 if (!gvt->mmio.mmio_attribute) 3245 return -ENOMEM; 3246 3247 ret = init_generic_mmio_info(gvt); 3248 if (ret) 3249 goto err; 3250 3251 if (IS_BROADWELL(dev_priv)) { 3252 ret = init_broadwell_mmio_info(gvt); 3253 if (ret) 3254 goto err; 3255 } else if (IS_SKYLAKE(dev_priv) 3256 || IS_KABYLAKE(dev_priv)) { 3257 ret = init_broadwell_mmio_info(gvt); 3258 if (ret) 3259 goto err; 3260 ret = init_skl_mmio_info(gvt); 3261 if (ret) 3262 goto err; 3263 } else if (IS_BROXTON(dev_priv)) { 3264 ret = init_broadwell_mmio_info(gvt); 3265 if (ret) 3266 goto err; 3267 ret = init_skl_mmio_info(gvt); 3268 if (ret) 3269 goto err; 3270 ret = init_bxt_mmio_info(gvt); 3271 if (ret) 3272 goto err; 3273 } 3274 3275 gvt->mmio.mmio_block = mmio_blocks; 3276 gvt->mmio.num_mmio_block = ARRAY_SIZE(mmio_blocks); 3277 3278 return 0; 3279 err: 3280 intel_gvt_clean_mmio_info(gvt); 3281 return ret; 3282 } 3283 3284 /** 3285 * intel_gvt_for_each_tracked_mmio - iterate each tracked mmio 3286 * @gvt: a GVT device 3287 * @handler: the handler 3288 * @data: private data given to handler 3289 * 3290 * Returns: 3291 * Zero on success, negative error code if failed. 3292 */ 3293 int intel_gvt_for_each_tracked_mmio(struct intel_gvt *gvt, 3294 int (*handler)(struct intel_gvt *gvt, u32 offset, void *data), 3295 void *data) 3296 { 3297 struct gvt_mmio_block *block = gvt->mmio.mmio_block; 3298 struct intel_gvt_mmio_info *e; 3299 int i, j, ret; 3300 3301 hash_for_each(gvt->mmio.mmio_info_table, i, e, node) { 3302 ret = handler(gvt, e->offset, data); 3303 if (ret) 3304 return ret; 3305 } 3306 3307 for (i = 0; i < gvt->mmio.num_mmio_block; i++, block++) { 3308 for (j = 0; j < block->size; j += 4) { 3309 ret = handler(gvt, 3310 i915_mmio_reg_offset(block->offset) + j, 3311 data); 3312 if (ret) 3313 return ret; 3314 } 3315 } 3316 return 0; 3317 } 3318 3319 /** 3320 * intel_vgpu_default_mmio_read - default MMIO read handler 3321 * @vgpu: a vGPU 3322 * @offset: access offset 3323 * @p_data: data return buffer 3324 * @bytes: access data length 3325 * 3326 * Returns: 3327 * Zero on success, negative error code if failed. 3328 */ 3329 int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 3330 void *p_data, unsigned int bytes) 3331 { 3332 read_vreg(vgpu, offset, p_data, bytes); 3333 return 0; 3334 } 3335 3336 /** 3337 * intel_t_default_mmio_write - default MMIO write handler 3338 * @vgpu: a vGPU 3339 * @offset: access offset 3340 * @p_data: write data buffer 3341 * @bytes: access data length 3342 * 3343 * Returns: 3344 * Zero on success, negative error code if failed. 3345 */ 3346 int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 3347 void *p_data, unsigned int bytes) 3348 { 3349 write_vreg(vgpu, offset, p_data, bytes); 3350 return 0; 3351 } 3352 3353 /** 3354 * intel_gvt_in_force_nonpriv_whitelist - if a mmio is in whitelist to be 3355 * force-nopriv register 3356 * 3357 * @gvt: a GVT device 3358 * @offset: register offset 3359 * 3360 * Returns: 3361 * True if the register is in force-nonpriv whitelist; 3362 * False if outside; 3363 */ 3364 bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt, 3365 unsigned int offset) 3366 { 3367 return in_whitelist(offset); 3368 } 3369 3370 /** 3371 * intel_vgpu_mmio_reg_rw - emulate tracked mmio registers 3372 * @vgpu: a vGPU 3373 * @offset: register offset 3374 * @pdata: data buffer 3375 * @bytes: data length 3376 * 3377 * Returns: 3378 * Zero on success, negative error code if failed. 3379 */ 3380 int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset, 3381 void *pdata, unsigned int bytes, bool is_read) 3382 { 3383 struct intel_gvt *gvt = vgpu->gvt; 3384 struct intel_gvt_mmio_info *mmio_info; 3385 struct gvt_mmio_block *mmio_block; 3386 gvt_mmio_func func; 3387 int ret; 3388 3389 if (WARN_ON(bytes > 8)) 3390 return -EINVAL; 3391 3392 /* 3393 * Handle special MMIO blocks. 3394 */ 3395 mmio_block = find_mmio_block(gvt, offset); 3396 if (mmio_block) { 3397 func = is_read ? mmio_block->read : mmio_block->write; 3398 if (func) 3399 return func(vgpu, offset, pdata, bytes); 3400 goto default_rw; 3401 } 3402 3403 /* 3404 * Normal tracked MMIOs. 3405 */ 3406 mmio_info = find_mmio_info(gvt, offset); 3407 if (!mmio_info) { 3408 gvt_dbg_mmio("untracked MMIO %08x len %d\n", offset, bytes); 3409 goto default_rw; 3410 } 3411 3412 if (is_read) 3413 return mmio_info->read(vgpu, offset, pdata, bytes); 3414 else { 3415 u64 ro_mask = mmio_info->ro_mask; 3416 u32 old_vreg = 0, old_sreg = 0; 3417 u64 data = 0; 3418 3419 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) { 3420 old_vreg = vgpu_vreg(vgpu, offset); 3421 old_sreg = vgpu_sreg(vgpu, offset); 3422 } 3423 3424 if (likely(!ro_mask)) 3425 ret = mmio_info->write(vgpu, offset, pdata, bytes); 3426 else if (!~ro_mask) { 3427 gvt_vgpu_err("try to write RO reg %x\n", offset); 3428 return 0; 3429 } else { 3430 /* keep the RO bits in the virtual register */ 3431 memcpy(&data, pdata, bytes); 3432 data &= ~ro_mask; 3433 data |= vgpu_vreg(vgpu, offset) & ro_mask; 3434 ret = mmio_info->write(vgpu, offset, &data, bytes); 3435 } 3436 3437 /* higher 16bits of mode ctl regs are mask bits for change */ 3438 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) { 3439 u32 mask = vgpu_vreg(vgpu, offset) >> 16; 3440 3441 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask) 3442 | (vgpu_vreg(vgpu, offset) & mask); 3443 vgpu_sreg(vgpu, offset) = (old_sreg & ~mask) 3444 | (vgpu_sreg(vgpu, offset) & mask); 3445 } 3446 } 3447 3448 return ret; 3449 3450 default_rw: 3451 return is_read ? 3452 intel_vgpu_default_mmio_read(vgpu, offset, pdata, bytes) : 3453 intel_vgpu_default_mmio_write(vgpu, offset, pdata, bytes); 3454 } 3455