1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Kevin Tian <kevin.tian@intel.com> 25 * Eddie Dong <eddie.dong@intel.com> 26 * Zhiyuan Lv <zhiyuan.lv@intel.com> 27 * 28 * Contributors: 29 * Min He <min.he@intel.com> 30 * Tina Zhang <tina.zhang@intel.com> 31 * Pei Zhang <pei.zhang@intel.com> 32 * Niu Bing <bing.niu@intel.com> 33 * Ping Gao <ping.a.gao@intel.com> 34 * Zhi Wang <zhi.a.wang@intel.com> 35 * 36 37 */ 38 39 #include "i915_drv.h" 40 #include "gvt.h" 41 #include "i915_pvinfo.h" 42 43 /* XXX FIXME i915 has changed PP_XXX definition */ 44 #define PCH_PP_STATUS _MMIO(0xc7200) 45 #define PCH_PP_CONTROL _MMIO(0xc7204) 46 #define PCH_PP_ON_DELAYS _MMIO(0xc7208) 47 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c) 48 #define PCH_PP_DIVISOR _MMIO(0xc7210) 49 50 unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt) 51 { 52 if (IS_BROADWELL(gvt->dev_priv)) 53 return D_BDW; 54 else if (IS_SKYLAKE(gvt->dev_priv)) 55 return D_SKL; 56 else if (IS_KABYLAKE(gvt->dev_priv)) 57 return D_KBL; 58 59 return 0; 60 } 61 62 bool intel_gvt_match_device(struct intel_gvt *gvt, 63 unsigned long device) 64 { 65 return intel_gvt_get_device_type(gvt) & device; 66 } 67 68 static void read_vreg(struct intel_vgpu *vgpu, unsigned int offset, 69 void *p_data, unsigned int bytes) 70 { 71 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); 72 } 73 74 static void write_vreg(struct intel_vgpu *vgpu, unsigned int offset, 75 void *p_data, unsigned int bytes) 76 { 77 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes); 78 } 79 80 static struct intel_gvt_mmio_info *find_mmio_info(struct intel_gvt *gvt, 81 unsigned int offset) 82 { 83 struct intel_gvt_mmio_info *e; 84 85 hash_for_each_possible(gvt->mmio.mmio_info_table, e, node, offset) { 86 if (e->offset == offset) 87 return e; 88 } 89 return NULL; 90 } 91 92 static int new_mmio_info(struct intel_gvt *gvt, 93 u32 offset, u8 flags, u32 size, 94 u32 addr_mask, u32 ro_mask, u32 device, 95 gvt_mmio_func read, gvt_mmio_func write) 96 { 97 struct intel_gvt_mmio_info *info, *p; 98 u32 start, end, i; 99 100 if (!intel_gvt_match_device(gvt, device)) 101 return 0; 102 103 if (WARN_ON(!IS_ALIGNED(offset, 4))) 104 return -EINVAL; 105 106 start = offset; 107 end = offset + size; 108 109 for (i = start; i < end; i += 4) { 110 info = kzalloc(sizeof(*info), GFP_KERNEL); 111 if (!info) 112 return -ENOMEM; 113 114 info->offset = i; 115 p = find_mmio_info(gvt, info->offset); 116 if (p) { 117 WARN(1, "dup mmio definition offset %x\n", 118 info->offset); 119 kfree(info); 120 121 /* We return -EEXIST here to make GVT-g load fail. 122 * So duplicated MMIO can be found as soon as 123 * possible. 124 */ 125 return -EEXIST; 126 } 127 128 info->ro_mask = ro_mask; 129 info->device = device; 130 info->read = read ? read : intel_vgpu_default_mmio_read; 131 info->write = write ? write : intel_vgpu_default_mmio_write; 132 gvt->mmio.mmio_attribute[info->offset / 4] = flags; 133 INIT_HLIST_NODE(&info->node); 134 hash_add(gvt->mmio.mmio_info_table, &info->node, info->offset); 135 gvt->mmio.num_tracked_mmio++; 136 } 137 return 0; 138 } 139 140 /** 141 * intel_gvt_render_mmio_to_ring_id - convert a mmio offset into ring id 142 * @gvt: a GVT device 143 * @offset: register offset 144 * 145 * Returns: 146 * Ring ID on success, negative error code if failed. 147 */ 148 int intel_gvt_render_mmio_to_ring_id(struct intel_gvt *gvt, 149 unsigned int offset) 150 { 151 enum intel_engine_id id; 152 struct intel_engine_cs *engine; 153 154 offset &= ~GENMASK(11, 0); 155 for_each_engine(engine, gvt->dev_priv, id) { 156 if (engine->mmio_base == offset) 157 return id; 158 } 159 return -ENODEV; 160 } 161 162 #define offset_to_fence_num(offset) \ 163 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3) 164 165 #define fence_num_to_offset(num) \ 166 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) 167 168 169 void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason) 170 { 171 switch (reason) { 172 case GVT_FAILSAFE_UNSUPPORTED_GUEST: 173 pr_err("Detected your guest driver doesn't support GVT-g.\n"); 174 break; 175 case GVT_FAILSAFE_INSUFFICIENT_RESOURCE: 176 pr_err("Graphics resource is not enough for the guest\n"); 177 break; 178 case GVT_FAILSAFE_GUEST_ERR: 179 pr_err("GVT Internal error for the guest\n"); 180 break; 181 default: 182 break; 183 } 184 pr_err("Now vgpu %d will enter failsafe mode.\n", vgpu->id); 185 vgpu->failsafe = true; 186 } 187 188 static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu, 189 unsigned int fence_num, void *p_data, unsigned int bytes) 190 { 191 unsigned int max_fence = vgpu_fence_sz(vgpu); 192 193 if (fence_num >= max_fence) { 194 195 /* When guest access oob fence regs without access 196 * pv_info first, we treat guest not supporting GVT, 197 * and we will let vgpu enter failsafe mode. 198 */ 199 if (!vgpu->pv_notified) 200 enter_failsafe_mode(vgpu, 201 GVT_FAILSAFE_UNSUPPORTED_GUEST); 202 203 if (!vgpu->mmio.disable_warn_untrack) { 204 gvt_vgpu_err("found oob fence register access\n"); 205 gvt_vgpu_err("total fence %d, access fence %d\n", 206 max_fence, fence_num); 207 } 208 memset(p_data, 0, bytes); 209 return -EINVAL; 210 } 211 return 0; 212 } 213 214 static int fence_mmio_read(struct intel_vgpu *vgpu, unsigned int off, 215 void *p_data, unsigned int bytes) 216 { 217 int ret; 218 219 ret = sanitize_fence_mmio_access(vgpu, offset_to_fence_num(off), 220 p_data, bytes); 221 if (ret) 222 return ret; 223 read_vreg(vgpu, off, p_data, bytes); 224 return 0; 225 } 226 227 static int fence_mmio_write(struct intel_vgpu *vgpu, unsigned int off, 228 void *p_data, unsigned int bytes) 229 { 230 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 231 unsigned int fence_num = offset_to_fence_num(off); 232 int ret; 233 234 ret = sanitize_fence_mmio_access(vgpu, fence_num, p_data, bytes); 235 if (ret) 236 return ret; 237 write_vreg(vgpu, off, p_data, bytes); 238 239 mmio_hw_access_pre(dev_priv); 240 intel_vgpu_write_fence(vgpu, fence_num, 241 vgpu_vreg64(vgpu, fence_num_to_offset(fence_num))); 242 mmio_hw_access_post(dev_priv); 243 return 0; 244 } 245 246 #define CALC_MODE_MASK_REG(old, new) \ 247 (((new) & GENMASK(31, 16)) \ 248 | ((((old) & GENMASK(15, 0)) & ~((new) >> 16)) \ 249 | ((new) & ((new) >> 16)))) 250 251 static int mul_force_wake_write(struct intel_vgpu *vgpu, 252 unsigned int offset, void *p_data, unsigned int bytes) 253 { 254 u32 old, new; 255 uint32_t ack_reg_offset; 256 257 old = vgpu_vreg(vgpu, offset); 258 new = CALC_MODE_MASK_REG(old, *(u32 *)p_data); 259 260 if (IS_SKYLAKE(vgpu->gvt->dev_priv) 261 || IS_KABYLAKE(vgpu->gvt->dev_priv)) { 262 switch (offset) { 263 case FORCEWAKE_RENDER_GEN9_REG: 264 ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG; 265 break; 266 case FORCEWAKE_BLITTER_GEN9_REG: 267 ack_reg_offset = FORCEWAKE_ACK_BLITTER_GEN9_REG; 268 break; 269 case FORCEWAKE_MEDIA_GEN9_REG: 270 ack_reg_offset = FORCEWAKE_ACK_MEDIA_GEN9_REG; 271 break; 272 default: 273 /*should not hit here*/ 274 gvt_vgpu_err("invalid forcewake offset 0x%x\n", offset); 275 return -EINVAL; 276 } 277 } else { 278 ack_reg_offset = FORCEWAKE_ACK_HSW_REG; 279 } 280 281 vgpu_vreg(vgpu, offset) = new; 282 vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0)); 283 return 0; 284 } 285 286 static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 287 void *p_data, unsigned int bytes) 288 { 289 unsigned int engine_mask = 0; 290 u32 data; 291 292 write_vreg(vgpu, offset, p_data, bytes); 293 data = vgpu_vreg(vgpu, offset); 294 295 if (data & GEN6_GRDOM_FULL) { 296 gvt_dbg_mmio("vgpu%d: request full GPU reset\n", vgpu->id); 297 engine_mask = ALL_ENGINES; 298 } else { 299 if (data & GEN6_GRDOM_RENDER) { 300 gvt_dbg_mmio("vgpu%d: request RCS reset\n", vgpu->id); 301 engine_mask |= (1 << RCS); 302 } 303 if (data & GEN6_GRDOM_MEDIA) { 304 gvt_dbg_mmio("vgpu%d: request VCS reset\n", vgpu->id); 305 engine_mask |= (1 << VCS); 306 } 307 if (data & GEN6_GRDOM_BLT) { 308 gvt_dbg_mmio("vgpu%d: request BCS Reset\n", vgpu->id); 309 engine_mask |= (1 << BCS); 310 } 311 if (data & GEN6_GRDOM_VECS) { 312 gvt_dbg_mmio("vgpu%d: request VECS Reset\n", vgpu->id); 313 engine_mask |= (1 << VECS); 314 } 315 if (data & GEN8_GRDOM_MEDIA2) { 316 gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id); 317 if (HAS_BSD2(vgpu->gvt->dev_priv)) 318 engine_mask |= (1 << VCS2); 319 } 320 } 321 322 intel_gvt_reset_vgpu_locked(vgpu, false, engine_mask); 323 324 /* sw will wait for the device to ack the reset request */ 325 vgpu_vreg(vgpu, offset) = 0; 326 327 return 0; 328 } 329 330 static int gmbus_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 331 void *p_data, unsigned int bytes) 332 { 333 return intel_gvt_i2c_handle_gmbus_read(vgpu, offset, p_data, bytes); 334 } 335 336 static int gmbus_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 337 void *p_data, unsigned int bytes) 338 { 339 return intel_gvt_i2c_handle_gmbus_write(vgpu, offset, p_data, bytes); 340 } 341 342 static int pch_pp_control_mmio_write(struct intel_vgpu *vgpu, 343 unsigned int offset, void *p_data, unsigned int bytes) 344 { 345 write_vreg(vgpu, offset, p_data, bytes); 346 347 if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) { 348 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_ON; 349 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE; 350 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN; 351 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE; 352 353 } else 354 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= 355 ~(PP_ON | PP_SEQUENCE_POWER_DOWN 356 | PP_CYCLE_DELAY_ACTIVE); 357 return 0; 358 } 359 360 static int transconf_mmio_write(struct intel_vgpu *vgpu, 361 unsigned int offset, void *p_data, unsigned int bytes) 362 { 363 write_vreg(vgpu, offset, p_data, bytes); 364 365 if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE) 366 vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE; 367 else 368 vgpu_vreg(vgpu, offset) &= ~TRANS_STATE_ENABLE; 369 return 0; 370 } 371 372 static int lcpll_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 373 void *p_data, unsigned int bytes) 374 { 375 write_vreg(vgpu, offset, p_data, bytes); 376 377 if (vgpu_vreg(vgpu, offset) & LCPLL_PLL_DISABLE) 378 vgpu_vreg(vgpu, offset) &= ~LCPLL_PLL_LOCK; 379 else 380 vgpu_vreg(vgpu, offset) |= LCPLL_PLL_LOCK; 381 382 if (vgpu_vreg(vgpu, offset) & LCPLL_CD_SOURCE_FCLK) 383 vgpu_vreg(vgpu, offset) |= LCPLL_CD_SOURCE_FCLK_DONE; 384 else 385 vgpu_vreg(vgpu, offset) &= ~LCPLL_CD_SOURCE_FCLK_DONE; 386 387 return 0; 388 } 389 390 static int dpy_reg_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 391 void *p_data, unsigned int bytes) 392 { 393 switch (offset) { 394 case 0xe651c: 395 case 0xe661c: 396 case 0xe671c: 397 case 0xe681c: 398 vgpu_vreg(vgpu, offset) = 1 << 17; 399 break; 400 case 0xe6c04: 401 vgpu_vreg(vgpu, offset) = 0x3; 402 break; 403 case 0xe6e1c: 404 vgpu_vreg(vgpu, offset) = 0x2f << 16; 405 break; 406 default: 407 return -EINVAL; 408 } 409 410 read_vreg(vgpu, offset, p_data, bytes); 411 return 0; 412 } 413 414 static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 415 void *p_data, unsigned int bytes) 416 { 417 u32 data; 418 419 write_vreg(vgpu, offset, p_data, bytes); 420 data = vgpu_vreg(vgpu, offset); 421 422 if (data & PIPECONF_ENABLE) 423 vgpu_vreg(vgpu, offset) |= I965_PIPECONF_ACTIVE; 424 else 425 vgpu_vreg(vgpu, offset) &= ~I965_PIPECONF_ACTIVE; 426 intel_gvt_check_vblank_emulation(vgpu->gvt); 427 return 0; 428 } 429 430 /* ascendingly sorted */ 431 static i915_reg_t force_nonpriv_white_list[] = { 432 GEN9_CS_DEBUG_MODE1, //_MMIO(0x20ec) 433 GEN9_CTX_PREEMPT_REG,//_MMIO(0x2248) 434 GEN8_CS_CHICKEN1,//_MMIO(0x2580) 435 _MMIO(0x2690), 436 _MMIO(0x2694), 437 _MMIO(0x2698), 438 _MMIO(0x4de0), 439 _MMIO(0x4de4), 440 _MMIO(0x4dfc), 441 GEN7_COMMON_SLICE_CHICKEN1,//_MMIO(0x7010) 442 _MMIO(0x7014), 443 HDC_CHICKEN0,//_MMIO(0x7300) 444 GEN8_HDC_CHICKEN1,//_MMIO(0x7304) 445 _MMIO(0x7700), 446 _MMIO(0x7704), 447 _MMIO(0x7708), 448 _MMIO(0x770c), 449 _MMIO(0xb110), 450 GEN8_L3SQCREG4,//_MMIO(0xb118) 451 _MMIO(0xe100), 452 _MMIO(0xe18c), 453 _MMIO(0xe48c), 454 _MMIO(0xe5f4), 455 }; 456 457 /* a simple bsearch */ 458 static inline bool in_whitelist(unsigned int reg) 459 { 460 int left = 0, right = ARRAY_SIZE(force_nonpriv_white_list); 461 i915_reg_t *array = force_nonpriv_white_list; 462 463 while (left < right) { 464 int mid = (left + right)/2; 465 466 if (reg > array[mid].reg) 467 left = mid + 1; 468 else if (reg < array[mid].reg) 469 right = mid; 470 else 471 return true; 472 } 473 return false; 474 } 475 476 static int force_nonpriv_write(struct intel_vgpu *vgpu, 477 unsigned int offset, void *p_data, unsigned int bytes) 478 { 479 u32 reg_nonpriv = *(u32 *)p_data; 480 int ret = -EINVAL; 481 482 if ((bytes != 4) || ((offset & (bytes - 1)) != 0)) { 483 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV offset %x(%dB)\n", 484 vgpu->id, offset, bytes); 485 return ret; 486 } 487 488 if (in_whitelist(reg_nonpriv)) { 489 ret = intel_vgpu_default_mmio_write(vgpu, offset, p_data, 490 bytes); 491 } else { 492 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x\n", 493 vgpu->id, reg_nonpriv); 494 } 495 return ret; 496 } 497 498 static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 499 void *p_data, unsigned int bytes) 500 { 501 write_vreg(vgpu, offset, p_data, bytes); 502 503 if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) { 504 vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE; 505 } else { 506 vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE; 507 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E))) 508 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) 509 &= ~DP_TP_STATUS_AUTOTRAIN_DONE; 510 } 511 return 0; 512 } 513 514 static int fdi_rx_iir_mmio_write(struct intel_vgpu *vgpu, 515 unsigned int offset, void *p_data, unsigned int bytes) 516 { 517 vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data; 518 return 0; 519 } 520 521 #define FDI_LINK_TRAIN_PATTERN1 0 522 #define FDI_LINK_TRAIN_PATTERN2 1 523 524 static int fdi_auto_training_started(struct intel_vgpu *vgpu) 525 { 526 u32 ddi_buf_ctl = vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_E)); 527 u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL); 528 u32 tx_ctl = vgpu_vreg_t(vgpu, DP_TP_CTL(PORT_E)); 529 530 if ((ddi_buf_ctl & DDI_BUF_CTL_ENABLE) && 531 (rx_ctl & FDI_RX_ENABLE) && 532 (rx_ctl & FDI_AUTO_TRAINING) && 533 (tx_ctl & DP_TP_CTL_ENABLE) && 534 (tx_ctl & DP_TP_CTL_FDI_AUTOTRAIN)) 535 return 1; 536 else 537 return 0; 538 } 539 540 static int check_fdi_rx_train_status(struct intel_vgpu *vgpu, 541 enum pipe pipe, unsigned int train_pattern) 542 { 543 i915_reg_t fdi_rx_imr, fdi_tx_ctl, fdi_rx_ctl; 544 unsigned int fdi_rx_check_bits, fdi_tx_check_bits; 545 unsigned int fdi_rx_train_bits, fdi_tx_train_bits; 546 unsigned int fdi_iir_check_bits; 547 548 fdi_rx_imr = FDI_RX_IMR(pipe); 549 fdi_tx_ctl = FDI_TX_CTL(pipe); 550 fdi_rx_ctl = FDI_RX_CTL(pipe); 551 552 if (train_pattern == FDI_LINK_TRAIN_PATTERN1) { 553 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_1_CPT; 554 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_1; 555 fdi_iir_check_bits = FDI_RX_BIT_LOCK; 556 } else if (train_pattern == FDI_LINK_TRAIN_PATTERN2) { 557 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_2_CPT; 558 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_2; 559 fdi_iir_check_bits = FDI_RX_SYMBOL_LOCK; 560 } else { 561 gvt_vgpu_err("Invalid train pattern %d\n", train_pattern); 562 return -EINVAL; 563 } 564 565 fdi_rx_check_bits = FDI_RX_ENABLE | fdi_rx_train_bits; 566 fdi_tx_check_bits = FDI_TX_ENABLE | fdi_tx_train_bits; 567 568 /* If imr bit has been masked */ 569 if (vgpu_vreg_t(vgpu, fdi_rx_imr) & fdi_iir_check_bits) 570 return 0; 571 572 if (((vgpu_vreg_t(vgpu, fdi_tx_ctl) & fdi_tx_check_bits) 573 == fdi_tx_check_bits) 574 && ((vgpu_vreg_t(vgpu, fdi_rx_ctl) & fdi_rx_check_bits) 575 == fdi_rx_check_bits)) 576 return 1; 577 else 578 return 0; 579 } 580 581 #define INVALID_INDEX (~0U) 582 583 static unsigned int calc_index(unsigned int offset, unsigned int start, 584 unsigned int next, unsigned int end, i915_reg_t i915_end) 585 { 586 unsigned int range = next - start; 587 588 if (!end) 589 end = i915_mmio_reg_offset(i915_end); 590 if (offset < start || offset > end) 591 return INVALID_INDEX; 592 offset -= start; 593 return offset / range; 594 } 595 596 #define FDI_RX_CTL_TO_PIPE(offset) \ 597 calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, 0, FDI_RX_CTL(PIPE_C)) 598 599 #define FDI_TX_CTL_TO_PIPE(offset) \ 600 calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, 0, FDI_TX_CTL(PIPE_C)) 601 602 #define FDI_RX_IMR_TO_PIPE(offset) \ 603 calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, 0, FDI_RX_IMR(PIPE_C)) 604 605 static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu, 606 unsigned int offset, void *p_data, unsigned int bytes) 607 { 608 i915_reg_t fdi_rx_iir; 609 unsigned int index; 610 int ret; 611 612 if (FDI_RX_CTL_TO_PIPE(offset) != INVALID_INDEX) 613 index = FDI_RX_CTL_TO_PIPE(offset); 614 else if (FDI_TX_CTL_TO_PIPE(offset) != INVALID_INDEX) 615 index = FDI_TX_CTL_TO_PIPE(offset); 616 else if (FDI_RX_IMR_TO_PIPE(offset) != INVALID_INDEX) 617 index = FDI_RX_IMR_TO_PIPE(offset); 618 else { 619 gvt_vgpu_err("Unsupport registers %x\n", offset); 620 return -EINVAL; 621 } 622 623 write_vreg(vgpu, offset, p_data, bytes); 624 625 fdi_rx_iir = FDI_RX_IIR(index); 626 627 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN1); 628 if (ret < 0) 629 return ret; 630 if (ret) 631 vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK; 632 633 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN2); 634 if (ret < 0) 635 return ret; 636 if (ret) 637 vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK; 638 639 if (offset == _FDI_RXA_CTL) 640 if (fdi_auto_training_started(vgpu)) 641 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) |= 642 DP_TP_STATUS_AUTOTRAIN_DONE; 643 return 0; 644 } 645 646 #define DP_TP_CTL_TO_PORT(offset) \ 647 calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, 0, DP_TP_CTL(PORT_E)) 648 649 static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 650 void *p_data, unsigned int bytes) 651 { 652 i915_reg_t status_reg; 653 unsigned int index; 654 u32 data; 655 656 write_vreg(vgpu, offset, p_data, bytes); 657 658 index = DP_TP_CTL_TO_PORT(offset); 659 data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8; 660 if (data == 0x2) { 661 status_reg = DP_TP_STATUS(index); 662 vgpu_vreg_t(vgpu, status_reg) |= (1 << 25); 663 } 664 return 0; 665 } 666 667 static int dp_tp_status_mmio_write(struct intel_vgpu *vgpu, 668 unsigned int offset, void *p_data, unsigned int bytes) 669 { 670 u32 reg_val; 671 u32 sticky_mask; 672 673 reg_val = *((u32 *)p_data); 674 sticky_mask = GENMASK(27, 26) | (1 << 24); 675 676 vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) | 677 (vgpu_vreg(vgpu, offset) & sticky_mask); 678 vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask); 679 return 0; 680 } 681 682 static int pch_adpa_mmio_write(struct intel_vgpu *vgpu, 683 unsigned int offset, void *p_data, unsigned int bytes) 684 { 685 u32 data; 686 687 write_vreg(vgpu, offset, p_data, bytes); 688 data = vgpu_vreg(vgpu, offset); 689 690 if (data & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) 691 vgpu_vreg(vgpu, offset) &= ~ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 692 return 0; 693 } 694 695 static int south_chicken2_mmio_write(struct intel_vgpu *vgpu, 696 unsigned int offset, void *p_data, unsigned int bytes) 697 { 698 u32 data; 699 700 write_vreg(vgpu, offset, p_data, bytes); 701 data = vgpu_vreg(vgpu, offset); 702 703 if (data & FDI_MPHY_IOSFSB_RESET_CTL) 704 vgpu_vreg(vgpu, offset) |= FDI_MPHY_IOSFSB_RESET_STATUS; 705 else 706 vgpu_vreg(vgpu, offset) &= ~FDI_MPHY_IOSFSB_RESET_STATUS; 707 return 0; 708 } 709 710 #define DSPSURF_TO_PIPE(offset) \ 711 calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C)) 712 713 static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 714 void *p_data, unsigned int bytes) 715 { 716 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 717 unsigned int index = DSPSURF_TO_PIPE(offset); 718 i915_reg_t surflive_reg = DSPSURFLIVE(index); 719 int flip_event[] = { 720 [PIPE_A] = PRIMARY_A_FLIP_DONE, 721 [PIPE_B] = PRIMARY_B_FLIP_DONE, 722 [PIPE_C] = PRIMARY_C_FLIP_DONE, 723 }; 724 725 write_vreg(vgpu, offset, p_data, bytes); 726 vgpu_vreg_t(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset); 727 728 set_bit(flip_event[index], vgpu->irq.flip_done_event[index]); 729 return 0; 730 } 731 732 #define SPRSURF_TO_PIPE(offset) \ 733 calc_index(offset, _SPRA_SURF, _SPRB_SURF, 0, SPRSURF(PIPE_C)) 734 735 static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 736 void *p_data, unsigned int bytes) 737 { 738 unsigned int index = SPRSURF_TO_PIPE(offset); 739 i915_reg_t surflive_reg = SPRSURFLIVE(index); 740 int flip_event[] = { 741 [PIPE_A] = SPRITE_A_FLIP_DONE, 742 [PIPE_B] = SPRITE_B_FLIP_DONE, 743 [PIPE_C] = SPRITE_C_FLIP_DONE, 744 }; 745 746 write_vreg(vgpu, offset, p_data, bytes); 747 vgpu_vreg_t(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset); 748 749 set_bit(flip_event[index], vgpu->irq.flip_done_event[index]); 750 return 0; 751 } 752 753 static int trigger_aux_channel_interrupt(struct intel_vgpu *vgpu, 754 unsigned int reg) 755 { 756 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 757 enum intel_gvt_event_type event; 758 759 if (reg == _DPA_AUX_CH_CTL) 760 event = AUX_CHANNEL_A; 761 else if (reg == _PCH_DPB_AUX_CH_CTL || reg == _DPB_AUX_CH_CTL) 762 event = AUX_CHANNEL_B; 763 else if (reg == _PCH_DPC_AUX_CH_CTL || reg == _DPC_AUX_CH_CTL) 764 event = AUX_CHANNEL_C; 765 else if (reg == _PCH_DPD_AUX_CH_CTL || reg == _DPD_AUX_CH_CTL) 766 event = AUX_CHANNEL_D; 767 else { 768 WARN_ON(true); 769 return -EINVAL; 770 } 771 772 intel_vgpu_trigger_virtual_event(vgpu, event); 773 return 0; 774 } 775 776 static int dp_aux_ch_ctl_trans_done(struct intel_vgpu *vgpu, u32 value, 777 unsigned int reg, int len, bool data_valid) 778 { 779 /* mark transaction done */ 780 value |= DP_AUX_CH_CTL_DONE; 781 value &= ~DP_AUX_CH_CTL_SEND_BUSY; 782 value &= ~DP_AUX_CH_CTL_RECEIVE_ERROR; 783 784 if (data_valid) 785 value &= ~DP_AUX_CH_CTL_TIME_OUT_ERROR; 786 else 787 value |= DP_AUX_CH_CTL_TIME_OUT_ERROR; 788 789 /* message size */ 790 value &= ~(0xf << 20); 791 value |= (len << 20); 792 vgpu_vreg(vgpu, reg) = value; 793 794 if (value & DP_AUX_CH_CTL_INTERRUPT) 795 return trigger_aux_channel_interrupt(vgpu, reg); 796 return 0; 797 } 798 799 static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd, 800 uint8_t t) 801 { 802 if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == DPCD_TRAINING_PATTERN_1) { 803 /* training pattern 1 for CR */ 804 /* set LANE0_CR_DONE, LANE1_CR_DONE */ 805 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_CR_DONE; 806 /* set LANE2_CR_DONE, LANE3_CR_DONE */ 807 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_CR_DONE; 808 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == 809 DPCD_TRAINING_PATTERN_2) { 810 /* training pattern 2 for EQ */ 811 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane0_1 */ 812 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_EQ_DONE; 813 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_SYMBOL_LOCKED; 814 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane2_3 */ 815 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_EQ_DONE; 816 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_SYMBOL_LOCKED; 817 /* set INTERLANE_ALIGN_DONE */ 818 dpcd->data[DPCD_LANE_ALIGN_STATUS_UPDATED] |= 819 DPCD_INTERLANE_ALIGN_DONE; 820 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == 821 DPCD_LINK_TRAINING_DISABLED) { 822 /* finish link training */ 823 /* set sink status as synchronized */ 824 dpcd->data[DPCD_SINK_STATUS] = DPCD_SINK_IN_SYNC; 825 } 826 } 827 828 #define _REG_HSW_DP_AUX_CH_CTL(dp) \ 829 ((dp) ? (_PCH_DPB_AUX_CH_CTL + ((dp)-1)*0x100) : 0x64010) 830 831 #define _REG_SKL_DP_AUX_CH_CTL(dp) (0x64010 + (dp) * 0x100) 832 833 #define OFFSET_TO_DP_AUX_PORT(offset) (((offset) & 0xF00) >> 8) 834 835 #define dpy_is_valid_port(port) \ 836 (((port) >= PORT_A) && ((port) < I915_MAX_PORTS)) 837 838 static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu, 839 unsigned int offset, void *p_data, unsigned int bytes) 840 { 841 struct intel_vgpu_display *display = &vgpu->display; 842 int msg, addr, ctrl, op, len; 843 int port_index = OFFSET_TO_DP_AUX_PORT(offset); 844 struct intel_vgpu_dpcd_data *dpcd = NULL; 845 struct intel_vgpu_port *port = NULL; 846 u32 data; 847 848 if (!dpy_is_valid_port(port_index)) { 849 gvt_vgpu_err("Unsupported DP port access!\n"); 850 return 0; 851 } 852 853 write_vreg(vgpu, offset, p_data, bytes); 854 data = vgpu_vreg(vgpu, offset); 855 856 if ((IS_SKYLAKE(vgpu->gvt->dev_priv) 857 || IS_KABYLAKE(vgpu->gvt->dev_priv)) 858 && offset != _REG_SKL_DP_AUX_CH_CTL(port_index)) { 859 /* SKL DPB/C/D aux ctl register changed */ 860 return 0; 861 } else if (IS_BROADWELL(vgpu->gvt->dev_priv) && 862 offset != _REG_HSW_DP_AUX_CH_CTL(port_index)) { 863 /* write to the data registers */ 864 return 0; 865 } 866 867 if (!(data & DP_AUX_CH_CTL_SEND_BUSY)) { 868 /* just want to clear the sticky bits */ 869 vgpu_vreg(vgpu, offset) = 0; 870 return 0; 871 } 872 873 port = &display->ports[port_index]; 874 dpcd = port->dpcd; 875 876 /* read out message from DATA1 register */ 877 msg = vgpu_vreg(vgpu, offset + 4); 878 addr = (msg >> 8) & 0xffff; 879 ctrl = (msg >> 24) & 0xff; 880 len = msg & 0xff; 881 op = ctrl >> 4; 882 883 if (op == GVT_AUX_NATIVE_WRITE) { 884 int t; 885 uint8_t buf[16]; 886 887 if ((addr + len + 1) >= DPCD_SIZE) { 888 /* 889 * Write request exceeds what we supported, 890 * DCPD spec: When a Source Device is writing a DPCD 891 * address not supported by the Sink Device, the Sink 892 * Device shall reply with AUX NACK and “M” equal to 893 * zero. 894 */ 895 896 /* NAK the write */ 897 vgpu_vreg(vgpu, offset + 4) = AUX_NATIVE_REPLY_NAK; 898 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 2, true); 899 return 0; 900 } 901 902 /* 903 * Write request format: (command + address) occupies 904 * 3 bytes, followed by (len + 1) bytes of data. 905 */ 906 if (WARN_ON((len + 4) > AUX_BURST_SIZE)) 907 return -EINVAL; 908 909 /* unpack data from vreg to buf */ 910 for (t = 0; t < 4; t++) { 911 u32 r = vgpu_vreg(vgpu, offset + 8 + t * 4); 912 913 buf[t * 4] = (r >> 24) & 0xff; 914 buf[t * 4 + 1] = (r >> 16) & 0xff; 915 buf[t * 4 + 2] = (r >> 8) & 0xff; 916 buf[t * 4 + 3] = r & 0xff; 917 } 918 919 /* write to virtual DPCD */ 920 if (dpcd && dpcd->data_valid) { 921 for (t = 0; t <= len; t++) { 922 int p = addr + t; 923 924 dpcd->data[p] = buf[t]; 925 /* check for link training */ 926 if (p == DPCD_TRAINING_PATTERN_SET) 927 dp_aux_ch_ctl_link_training(dpcd, 928 buf[t]); 929 } 930 } 931 932 /* ACK the write */ 933 vgpu_vreg(vgpu, offset + 4) = 0; 934 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 1, 935 dpcd && dpcd->data_valid); 936 return 0; 937 } 938 939 if (op == GVT_AUX_NATIVE_READ) { 940 int idx, i, ret = 0; 941 942 if ((addr + len + 1) >= DPCD_SIZE) { 943 /* 944 * read request exceeds what we supported 945 * DPCD spec: A Sink Device receiving a Native AUX CH 946 * read request for an unsupported DPCD address must 947 * reply with an AUX ACK and read data set equal to 948 * zero instead of replying with AUX NACK. 949 */ 950 951 /* ACK the READ*/ 952 vgpu_vreg(vgpu, offset + 4) = 0; 953 vgpu_vreg(vgpu, offset + 8) = 0; 954 vgpu_vreg(vgpu, offset + 12) = 0; 955 vgpu_vreg(vgpu, offset + 16) = 0; 956 vgpu_vreg(vgpu, offset + 20) = 0; 957 958 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2, 959 true); 960 return 0; 961 } 962 963 for (idx = 1; idx <= 5; idx++) { 964 /* clear the data registers */ 965 vgpu_vreg(vgpu, offset + 4 * idx) = 0; 966 } 967 968 /* 969 * Read reply format: ACK (1 byte) plus (len + 1) bytes of data. 970 */ 971 if (WARN_ON((len + 2) > AUX_BURST_SIZE)) 972 return -EINVAL; 973 974 /* read from virtual DPCD to vreg */ 975 /* first 4 bytes: [ACK][addr][addr+1][addr+2] */ 976 if (dpcd && dpcd->data_valid) { 977 for (i = 1; i <= (len + 1); i++) { 978 int t; 979 980 t = dpcd->data[addr + i - 1]; 981 t <<= (24 - 8 * (i % 4)); 982 ret |= t; 983 984 if ((i % 4 == 3) || (i == (len + 1))) { 985 vgpu_vreg(vgpu, offset + 986 (i / 4 + 1) * 4) = ret; 987 ret = 0; 988 } 989 } 990 } 991 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2, 992 dpcd && dpcd->data_valid); 993 return 0; 994 } 995 996 /* i2c transaction starts */ 997 intel_gvt_i2c_handle_aux_ch_write(vgpu, port_index, offset, p_data); 998 999 if (data & DP_AUX_CH_CTL_INTERRUPT) 1000 trigger_aux_channel_interrupt(vgpu, offset); 1001 return 0; 1002 } 1003 1004 static int mbctl_write(struct intel_vgpu *vgpu, unsigned int offset, 1005 void *p_data, unsigned int bytes) 1006 { 1007 *(u32 *)p_data &= (~GEN6_MBCTL_ENABLE_BOOT_FETCH); 1008 write_vreg(vgpu, offset, p_data, bytes); 1009 return 0; 1010 } 1011 1012 static int vga_control_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1013 void *p_data, unsigned int bytes) 1014 { 1015 bool vga_disable; 1016 1017 write_vreg(vgpu, offset, p_data, bytes); 1018 vga_disable = vgpu_vreg(vgpu, offset) & VGA_DISP_DISABLE; 1019 1020 gvt_dbg_core("vgpu%d: %s VGA mode\n", vgpu->id, 1021 vga_disable ? "Disable" : "Enable"); 1022 return 0; 1023 } 1024 1025 static u32 read_virtual_sbi_register(struct intel_vgpu *vgpu, 1026 unsigned int sbi_offset) 1027 { 1028 struct intel_vgpu_display *display = &vgpu->display; 1029 int num = display->sbi.number; 1030 int i; 1031 1032 for (i = 0; i < num; ++i) 1033 if (display->sbi.registers[i].offset == sbi_offset) 1034 break; 1035 1036 if (i == num) 1037 return 0; 1038 1039 return display->sbi.registers[i].value; 1040 } 1041 1042 static void write_virtual_sbi_register(struct intel_vgpu *vgpu, 1043 unsigned int offset, u32 value) 1044 { 1045 struct intel_vgpu_display *display = &vgpu->display; 1046 int num = display->sbi.number; 1047 int i; 1048 1049 for (i = 0; i < num; ++i) { 1050 if (display->sbi.registers[i].offset == offset) 1051 break; 1052 } 1053 1054 if (i == num) { 1055 if (num == SBI_REG_MAX) { 1056 gvt_vgpu_err("SBI caching meets maximum limits\n"); 1057 return; 1058 } 1059 display->sbi.number++; 1060 } 1061 1062 display->sbi.registers[i].offset = offset; 1063 display->sbi.registers[i].value = value; 1064 } 1065 1066 static int sbi_data_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 1067 void *p_data, unsigned int bytes) 1068 { 1069 if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> 1070 SBI_OPCODE_SHIFT) == SBI_CMD_CRRD) { 1071 unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) & 1072 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; 1073 vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu, 1074 sbi_offset); 1075 } 1076 read_vreg(vgpu, offset, p_data, bytes); 1077 return 0; 1078 } 1079 1080 static int sbi_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1081 void *p_data, unsigned int bytes) 1082 { 1083 u32 data; 1084 1085 write_vreg(vgpu, offset, p_data, bytes); 1086 data = vgpu_vreg(vgpu, offset); 1087 1088 data &= ~(SBI_STAT_MASK << SBI_STAT_SHIFT); 1089 data |= SBI_READY; 1090 1091 data &= ~(SBI_RESPONSE_MASK << SBI_RESPONSE_SHIFT); 1092 data |= SBI_RESPONSE_SUCCESS; 1093 1094 vgpu_vreg(vgpu, offset) = data; 1095 1096 if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> 1097 SBI_OPCODE_SHIFT) == SBI_CMD_CRWR) { 1098 unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) & 1099 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; 1100 1101 write_virtual_sbi_register(vgpu, sbi_offset, 1102 vgpu_vreg_t(vgpu, SBI_DATA)); 1103 } 1104 return 0; 1105 } 1106 1107 #define _vgtif_reg(x) \ 1108 (VGT_PVINFO_PAGE + offsetof(struct vgt_if, x)) 1109 1110 static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 1111 void *p_data, unsigned int bytes) 1112 { 1113 bool invalid_read = false; 1114 1115 read_vreg(vgpu, offset, p_data, bytes); 1116 1117 switch (offset) { 1118 case _vgtif_reg(magic) ... _vgtif_reg(vgt_id): 1119 if (offset + bytes > _vgtif_reg(vgt_id) + 4) 1120 invalid_read = true; 1121 break; 1122 case _vgtif_reg(avail_rs.mappable_gmadr.base) ... 1123 _vgtif_reg(avail_rs.fence_num): 1124 if (offset + bytes > 1125 _vgtif_reg(avail_rs.fence_num) + 4) 1126 invalid_read = true; 1127 break; 1128 case 0x78010: /* vgt_caps */ 1129 case 0x7881c: 1130 break; 1131 default: 1132 invalid_read = true; 1133 break; 1134 } 1135 if (invalid_read) 1136 gvt_vgpu_err("invalid pvinfo read: [%x:%x] = %x\n", 1137 offset, bytes, *(u32 *)p_data); 1138 vgpu->pv_notified = true; 1139 return 0; 1140 } 1141 1142 static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification) 1143 { 1144 intel_gvt_gtt_type_t root_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY; 1145 struct intel_vgpu_mm *mm; 1146 u64 *pdps; 1147 1148 pdps = (u64 *)&vgpu_vreg64_t(vgpu, vgtif_reg(pdp[0])); 1149 1150 switch (notification) { 1151 case VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE: 1152 root_entry_type = GTT_TYPE_PPGTT_ROOT_L3_ENTRY; 1153 case VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE: 1154 mm = intel_vgpu_get_ppgtt_mm(vgpu, root_entry_type, pdps); 1155 return PTR_ERR_OR_ZERO(mm); 1156 case VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY: 1157 case VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY: 1158 return intel_vgpu_put_ppgtt_mm(vgpu, pdps); 1159 case VGT_G2V_EXECLIST_CONTEXT_CREATE: 1160 case VGT_G2V_EXECLIST_CONTEXT_DESTROY: 1161 case 1: /* Remove this in guest driver. */ 1162 break; 1163 default: 1164 gvt_vgpu_err("Invalid PV notification %d\n", notification); 1165 } 1166 return 0; 1167 } 1168 1169 static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready) 1170 { 1171 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1172 struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj; 1173 char *env[3] = {NULL, NULL, NULL}; 1174 char vmid_str[20]; 1175 char display_ready_str[20]; 1176 1177 snprintf(display_ready_str, 20, "GVT_DISPLAY_READY=%d", ready); 1178 env[0] = display_ready_str; 1179 1180 snprintf(vmid_str, 20, "VMID=%d", vgpu->id); 1181 env[1] = vmid_str; 1182 1183 return kobject_uevent_env(kobj, KOBJ_ADD, env); 1184 } 1185 1186 static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1187 void *p_data, unsigned int bytes) 1188 { 1189 u32 data; 1190 int ret; 1191 1192 write_vreg(vgpu, offset, p_data, bytes); 1193 data = vgpu_vreg(vgpu, offset); 1194 1195 switch (offset) { 1196 case _vgtif_reg(display_ready): 1197 send_display_ready_uevent(vgpu, data ? 1 : 0); 1198 break; 1199 case _vgtif_reg(g2v_notify): 1200 ret = handle_g2v_notification(vgpu, data); 1201 break; 1202 /* add xhot and yhot to handled list to avoid error log */ 1203 case 0x78830: 1204 case 0x78834: 1205 case _vgtif_reg(pdp[0].lo): 1206 case _vgtif_reg(pdp[0].hi): 1207 case _vgtif_reg(pdp[1].lo): 1208 case _vgtif_reg(pdp[1].hi): 1209 case _vgtif_reg(pdp[2].lo): 1210 case _vgtif_reg(pdp[2].hi): 1211 case _vgtif_reg(pdp[3].lo): 1212 case _vgtif_reg(pdp[3].hi): 1213 case _vgtif_reg(execlist_context_descriptor_lo): 1214 case _vgtif_reg(execlist_context_descriptor_hi): 1215 break; 1216 case _vgtif_reg(rsv5[0])..._vgtif_reg(rsv5[3]): 1217 enter_failsafe_mode(vgpu, GVT_FAILSAFE_INSUFFICIENT_RESOURCE); 1218 break; 1219 default: 1220 gvt_vgpu_err("invalid pvinfo write offset %x bytes %x data %x\n", 1221 offset, bytes, data); 1222 break; 1223 } 1224 return 0; 1225 } 1226 1227 static int pf_write(struct intel_vgpu *vgpu, 1228 unsigned int offset, void *p_data, unsigned int bytes) 1229 { 1230 u32 val = *(u32 *)p_data; 1231 1232 if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL || 1233 offset == _PS_1B_CTRL || offset == _PS_2B_CTRL || 1234 offset == _PS_1C_CTRL) && (val & PS_PLANE_SEL_MASK) != 0) { 1235 WARN_ONCE(true, "VM(%d): guest is trying to scaling a plane\n", 1236 vgpu->id); 1237 return 0; 1238 } 1239 1240 return intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes); 1241 } 1242 1243 static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu, 1244 unsigned int offset, void *p_data, unsigned int bytes) 1245 { 1246 write_vreg(vgpu, offset, p_data, bytes); 1247 1248 if (vgpu_vreg(vgpu, offset) & HSW_PWR_WELL_CTL_REQ(HSW_DISP_PW_GLOBAL)) 1249 vgpu_vreg(vgpu, offset) |= 1250 HSW_PWR_WELL_CTL_STATE(HSW_DISP_PW_GLOBAL); 1251 else 1252 vgpu_vreg(vgpu, offset) &= 1253 ~HSW_PWR_WELL_CTL_STATE(HSW_DISP_PW_GLOBAL); 1254 return 0; 1255 } 1256 1257 static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu, 1258 unsigned int offset, void *p_data, unsigned int bytes) 1259 { 1260 write_vreg(vgpu, offset, p_data, bytes); 1261 1262 if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM) 1263 vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM; 1264 return 0; 1265 } 1266 1267 static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset, 1268 void *p_data, unsigned int bytes) 1269 { 1270 u32 mode; 1271 1272 write_vreg(vgpu, offset, p_data, bytes); 1273 mode = vgpu_vreg(vgpu, offset); 1274 1275 if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) { 1276 WARN_ONCE(1, "VM(%d): iGVT-g doesn't support GuC\n", 1277 vgpu->id); 1278 return 0; 1279 } 1280 1281 return 0; 1282 } 1283 1284 static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset, 1285 void *p_data, unsigned int bytes) 1286 { 1287 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1288 u32 trtte = *(u32 *)p_data; 1289 1290 if ((trtte & 1) && (trtte & (1 << 1)) == 0) { 1291 WARN(1, "VM(%d): Use physical address for TRTT!\n", 1292 vgpu->id); 1293 return -EINVAL; 1294 } 1295 write_vreg(vgpu, offset, p_data, bytes); 1296 /* TRTTE is not per-context */ 1297 1298 mmio_hw_access_pre(dev_priv); 1299 I915_WRITE(_MMIO(offset), vgpu_vreg(vgpu, offset)); 1300 mmio_hw_access_post(dev_priv); 1301 1302 return 0; 1303 } 1304 1305 static int gen9_trtt_chicken_write(struct intel_vgpu *vgpu, unsigned int offset, 1306 void *p_data, unsigned int bytes) 1307 { 1308 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1309 u32 val = *(u32 *)p_data; 1310 1311 if (val & 1) { 1312 /* unblock hw logic */ 1313 mmio_hw_access_pre(dev_priv); 1314 I915_WRITE(_MMIO(offset), val); 1315 mmio_hw_access_post(dev_priv); 1316 } 1317 write_vreg(vgpu, offset, p_data, bytes); 1318 return 0; 1319 } 1320 1321 static int dpll_status_read(struct intel_vgpu *vgpu, unsigned int offset, 1322 void *p_data, unsigned int bytes) 1323 { 1324 u32 v = 0; 1325 1326 if (vgpu_vreg(vgpu, 0x46010) & (1 << 31)) 1327 v |= (1 << 0); 1328 1329 if (vgpu_vreg(vgpu, 0x46014) & (1 << 31)) 1330 v |= (1 << 8); 1331 1332 if (vgpu_vreg(vgpu, 0x46040) & (1 << 31)) 1333 v |= (1 << 16); 1334 1335 if (vgpu_vreg(vgpu, 0x46060) & (1 << 31)) 1336 v |= (1 << 24); 1337 1338 vgpu_vreg(vgpu, offset) = v; 1339 1340 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1341 } 1342 1343 static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset, 1344 void *p_data, unsigned int bytes) 1345 { 1346 u32 value = *(u32 *)p_data; 1347 u32 cmd = value & 0xff; 1348 u32 *data0 = &vgpu_vreg_t(vgpu, GEN6_PCODE_DATA); 1349 1350 switch (cmd) { 1351 case GEN9_PCODE_READ_MEM_LATENCY: 1352 if (IS_SKYLAKE(vgpu->gvt->dev_priv) 1353 || IS_KABYLAKE(vgpu->gvt->dev_priv)) { 1354 /** 1355 * "Read memory latency" command on gen9. 1356 * Below memory latency values are read 1357 * from skylake platform. 1358 */ 1359 if (!*data0) 1360 *data0 = 0x1e1a1100; 1361 else 1362 *data0 = 0x61514b3d; 1363 } 1364 break; 1365 case SKL_PCODE_CDCLK_CONTROL: 1366 if (IS_SKYLAKE(vgpu->gvt->dev_priv) 1367 || IS_KABYLAKE(vgpu->gvt->dev_priv)) 1368 *data0 = SKL_CDCLK_READY_FOR_CHANGE; 1369 break; 1370 case GEN6_PCODE_READ_RC6VIDS: 1371 *data0 |= 0x1; 1372 break; 1373 } 1374 1375 gvt_dbg_core("VM(%d) write %x to mailbox, return data0 %x\n", 1376 vgpu->id, value, *data0); 1377 /** 1378 * PCODE_READY clear means ready for pcode read/write, 1379 * PCODE_ERROR_MASK clear means no error happened. In GVT-g we 1380 * always emulate as pcode read/write success and ready for access 1381 * anytime, since we don't touch real physical registers here. 1382 */ 1383 value &= ~(GEN6_PCODE_READY | GEN6_PCODE_ERROR_MASK); 1384 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes); 1385 } 1386 1387 static int hws_pga_write(struct intel_vgpu *vgpu, unsigned int offset, 1388 void *p_data, unsigned int bytes) 1389 { 1390 u32 value = *(u32 *)p_data; 1391 int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset); 1392 1393 if (!intel_gvt_ggtt_validate_range(vgpu, value, I915_GTT_PAGE_SIZE)) { 1394 gvt_vgpu_err("write invalid HWSP address, reg:0x%x, value:0x%x\n", 1395 offset, value); 1396 return -EINVAL; 1397 } 1398 /* 1399 * Need to emulate all the HWSP register write to ensure host can 1400 * update the VM CSB status correctly. Here listed registers can 1401 * support BDW, SKL or other platforms with same HWSP registers. 1402 */ 1403 if (unlikely(ring_id < 0 || ring_id >= I915_NUM_ENGINES)) { 1404 gvt_vgpu_err("access unknown hardware status page register:0x%x\n", 1405 offset); 1406 return -EINVAL; 1407 } 1408 vgpu->hws_pga[ring_id] = value; 1409 gvt_dbg_mmio("VM(%d) write: 0x%x to HWSP: 0x%x\n", 1410 vgpu->id, value, offset); 1411 1412 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes); 1413 } 1414 1415 static int skl_power_well_ctl_write(struct intel_vgpu *vgpu, 1416 unsigned int offset, void *p_data, unsigned int bytes) 1417 { 1418 u32 v = *(u32 *)p_data; 1419 1420 v &= (1 << 31) | (1 << 29) | (1 << 9) | 1421 (1 << 7) | (1 << 5) | (1 << 3) | (1 << 1); 1422 v |= (v >> 1); 1423 1424 return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes); 1425 } 1426 1427 static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset, 1428 void *p_data, unsigned int bytes) 1429 { 1430 u32 v = *(u32 *)p_data; 1431 1432 /* other bits are MBZ. */ 1433 v &= (1 << 31) | (1 << 30); 1434 v & (1 << 31) ? (v |= (1 << 30)) : (v &= ~(1 << 30)); 1435 1436 vgpu_vreg(vgpu, offset) = v; 1437 1438 return 0; 1439 } 1440 1441 static int mmio_read_from_hw(struct intel_vgpu *vgpu, 1442 unsigned int offset, void *p_data, unsigned int bytes) 1443 { 1444 struct intel_gvt *gvt = vgpu->gvt; 1445 struct drm_i915_private *dev_priv = gvt->dev_priv; 1446 int ring_id; 1447 u32 ring_base; 1448 1449 ring_id = intel_gvt_render_mmio_to_ring_id(gvt, offset); 1450 /** 1451 * Read HW reg in following case 1452 * a. the offset isn't a ring mmio 1453 * b. the offset's ring is running on hw. 1454 * c. the offset is ring time stamp mmio 1455 */ 1456 if (ring_id >= 0) 1457 ring_base = dev_priv->engine[ring_id]->mmio_base; 1458 1459 if (ring_id < 0 || vgpu == gvt->scheduler.engine_owner[ring_id] || 1460 offset == i915_mmio_reg_offset(RING_TIMESTAMP(ring_base)) || 1461 offset == i915_mmio_reg_offset(RING_TIMESTAMP_UDW(ring_base))) { 1462 mmio_hw_access_pre(dev_priv); 1463 vgpu_vreg(vgpu, offset) = I915_READ(_MMIO(offset)); 1464 mmio_hw_access_post(dev_priv); 1465 } 1466 1467 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1468 } 1469 1470 static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1471 void *p_data, unsigned int bytes) 1472 { 1473 int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset); 1474 struct intel_vgpu_execlist *execlist; 1475 u32 data = *(u32 *)p_data; 1476 int ret = 0; 1477 1478 if (WARN_ON(ring_id < 0 || ring_id >= I915_NUM_ENGINES)) 1479 return -EINVAL; 1480 1481 execlist = &vgpu->submission.execlist[ring_id]; 1482 1483 execlist->elsp_dwords.data[3 - execlist->elsp_dwords.index] = data; 1484 if (execlist->elsp_dwords.index == 3) { 1485 ret = intel_vgpu_submit_execlist(vgpu, ring_id); 1486 if(ret) 1487 gvt_vgpu_err("fail submit workload on ring %d\n", 1488 ring_id); 1489 } 1490 1491 ++execlist->elsp_dwords.index; 1492 execlist->elsp_dwords.index &= 0x3; 1493 return ret; 1494 } 1495 1496 static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1497 void *p_data, unsigned int bytes) 1498 { 1499 u32 data = *(u32 *)p_data; 1500 int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset); 1501 bool enable_execlist; 1502 int ret; 1503 1504 write_vreg(vgpu, offset, p_data, bytes); 1505 1506 /* when PPGTT mode enabled, we will check if guest has called 1507 * pvinfo, if not, we will treat this guest as non-gvtg-aware 1508 * guest, and stop emulating its cfg space, mmio, gtt, etc. 1509 */ 1510 if (((data & _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)) || 1511 (data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE))) 1512 && !vgpu->pv_notified) { 1513 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); 1514 return 0; 1515 } 1516 if ((data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)) 1517 || (data & _MASKED_BIT_DISABLE(GFX_RUN_LIST_ENABLE))) { 1518 enable_execlist = !!(data & GFX_RUN_LIST_ENABLE); 1519 1520 gvt_dbg_core("EXECLIST %s on ring %d\n", 1521 (enable_execlist ? "enabling" : "disabling"), 1522 ring_id); 1523 1524 if (!enable_execlist) 1525 return 0; 1526 1527 ret = intel_vgpu_select_submission_ops(vgpu, 1528 ENGINE_MASK(ring_id), 1529 INTEL_VGPU_EXECLIST_SUBMISSION); 1530 if (ret) 1531 return ret; 1532 1533 intel_vgpu_start_schedule(vgpu); 1534 } 1535 return 0; 1536 } 1537 1538 static int gvt_reg_tlb_control_handler(struct intel_vgpu *vgpu, 1539 unsigned int offset, void *p_data, unsigned int bytes) 1540 { 1541 unsigned int id = 0; 1542 1543 write_vreg(vgpu, offset, p_data, bytes); 1544 vgpu_vreg(vgpu, offset) = 0; 1545 1546 switch (offset) { 1547 case 0x4260: 1548 id = RCS; 1549 break; 1550 case 0x4264: 1551 id = VCS; 1552 break; 1553 case 0x4268: 1554 id = VCS2; 1555 break; 1556 case 0x426c: 1557 id = BCS; 1558 break; 1559 case 0x4270: 1560 id = VECS; 1561 break; 1562 default: 1563 return -EINVAL; 1564 } 1565 set_bit(id, (void *)vgpu->submission.tlb_handle_pending); 1566 1567 return 0; 1568 } 1569 1570 static int ring_reset_ctl_write(struct intel_vgpu *vgpu, 1571 unsigned int offset, void *p_data, unsigned int bytes) 1572 { 1573 u32 data; 1574 1575 write_vreg(vgpu, offset, p_data, bytes); 1576 data = vgpu_vreg(vgpu, offset); 1577 1578 if (data & _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET)) 1579 data |= RESET_CTL_READY_TO_RESET; 1580 else if (data & _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET)) 1581 data &= ~RESET_CTL_READY_TO_RESET; 1582 1583 vgpu_vreg(vgpu, offset) = data; 1584 return 0; 1585 } 1586 1587 #define MMIO_F(reg, s, f, am, rm, d, r, w) do { \ 1588 ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \ 1589 f, s, am, rm, d, r, w); \ 1590 if (ret) \ 1591 return ret; \ 1592 } while (0) 1593 1594 #define MMIO_D(reg, d) \ 1595 MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL) 1596 1597 #define MMIO_DH(reg, d, r, w) \ 1598 MMIO_F(reg, 4, 0, 0, 0, d, r, w) 1599 1600 #define MMIO_DFH(reg, d, f, r, w) \ 1601 MMIO_F(reg, 4, f, 0, 0, d, r, w) 1602 1603 #define MMIO_GM(reg, d, r, w) \ 1604 MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w) 1605 1606 #define MMIO_GM_RDR(reg, d, r, w) \ 1607 MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w) 1608 1609 #define MMIO_RO(reg, d, f, rm, r, w) \ 1610 MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w) 1611 1612 #define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \ 1613 MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \ 1614 MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \ 1615 MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \ 1616 MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \ 1617 if (HAS_BSD2(dev_priv)) \ 1618 MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \ 1619 } while (0) 1620 1621 #define MMIO_RING_D(prefix, d) \ 1622 MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL) 1623 1624 #define MMIO_RING_DFH(prefix, d, f, r, w) \ 1625 MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w) 1626 1627 #define MMIO_RING_GM(prefix, d, r, w) \ 1628 MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w) 1629 1630 #define MMIO_RING_GM_RDR(prefix, d, r, w) \ 1631 MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w) 1632 1633 #define MMIO_RING_RO(prefix, d, f, rm, r, w) \ 1634 MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w) 1635 1636 static int init_generic_mmio_info(struct intel_gvt *gvt) 1637 { 1638 struct drm_i915_private *dev_priv = gvt->dev_priv; 1639 int ret; 1640 1641 MMIO_RING_DFH(RING_IMR, D_ALL, F_CMD_ACCESS, NULL, 1642 intel_vgpu_reg_imr_handler); 1643 1644 MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler); 1645 MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler); 1646 MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler); 1647 MMIO_D(SDEISR, D_ALL); 1648 1649 MMIO_RING_DFH(RING_HWSTAM, D_ALL, F_CMD_ACCESS, NULL, NULL); 1650 1651 MMIO_GM_RDR(RENDER_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1652 MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1653 MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1654 MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1655 1656 #define RING_REG(base) _MMIO((base) + 0x28) 1657 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL); 1658 #undef RING_REG 1659 1660 #define RING_REG(base) _MMIO((base) + 0x134) 1661 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL); 1662 #undef RING_REG 1663 1664 #define RING_REG(base) _MMIO((base) + 0x6c) 1665 MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL); 1666 #undef RING_REG 1667 MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL); 1668 1669 MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL); 1670 MMIO_GM_RDR(CCID, D_ALL, NULL, NULL); 1671 MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL); 1672 MMIO_D(GEN7_CXT_SIZE, D_ALL); 1673 1674 MMIO_RING_DFH(RING_TAIL, D_ALL, F_CMD_ACCESS, NULL, NULL); 1675 MMIO_RING_DFH(RING_HEAD, D_ALL, F_CMD_ACCESS, NULL, NULL); 1676 MMIO_RING_DFH(RING_CTL, D_ALL, F_CMD_ACCESS, NULL, NULL); 1677 MMIO_RING_DFH(RING_ACTHD, D_ALL, F_CMD_ACCESS, mmio_read_from_hw, NULL); 1678 MMIO_RING_GM_RDR(RING_START, D_ALL, NULL, NULL); 1679 1680 /* RING MODE */ 1681 #define RING_REG(base) _MMIO((base) + 0x29c) 1682 MMIO_RING_DFH(RING_REG, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, 1683 ring_mode_mmio_write); 1684 #undef RING_REG 1685 1686 MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 1687 NULL, NULL); 1688 MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 1689 NULL, NULL); 1690 MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS, 1691 mmio_read_from_hw, NULL); 1692 MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS, 1693 mmio_read_from_hw, NULL); 1694 1695 MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1696 MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 1697 NULL, NULL); 1698 MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1699 MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1700 MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1701 1702 MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1703 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1704 MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1705 MMIO_DFH(_MMIO(0x20e4), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1706 MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1707 MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL); 1708 MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 1709 NULL, NULL); 1710 MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 1711 NULL, NULL); 1712 MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL); 1713 MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL); 1714 MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL); 1715 MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL); 1716 MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL); 1717 MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL); 1718 MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL); 1719 MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1720 MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1721 MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1722 1723 /* display */ 1724 MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL); 1725 MMIO_D(_MMIO(0x602a0), D_ALL); 1726 1727 MMIO_D(_MMIO(0x65050), D_ALL); 1728 MMIO_D(_MMIO(0x650b4), D_ALL); 1729 1730 MMIO_D(_MMIO(0xc4040), D_ALL); 1731 MMIO_D(DERRMR, D_ALL); 1732 1733 MMIO_D(PIPEDSL(PIPE_A), D_ALL); 1734 MMIO_D(PIPEDSL(PIPE_B), D_ALL); 1735 MMIO_D(PIPEDSL(PIPE_C), D_ALL); 1736 MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL); 1737 1738 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write); 1739 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write); 1740 MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write); 1741 MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write); 1742 1743 MMIO_D(PIPESTAT(PIPE_A), D_ALL); 1744 MMIO_D(PIPESTAT(PIPE_B), D_ALL); 1745 MMIO_D(PIPESTAT(PIPE_C), D_ALL); 1746 MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL); 1747 1748 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL); 1749 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL); 1750 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL); 1751 MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL); 1752 1753 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL); 1754 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL); 1755 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL); 1756 MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL); 1757 1758 MMIO_D(CURCNTR(PIPE_A), D_ALL); 1759 MMIO_D(CURCNTR(PIPE_B), D_ALL); 1760 MMIO_D(CURCNTR(PIPE_C), D_ALL); 1761 1762 MMIO_D(CURPOS(PIPE_A), D_ALL); 1763 MMIO_D(CURPOS(PIPE_B), D_ALL); 1764 MMIO_D(CURPOS(PIPE_C), D_ALL); 1765 1766 MMIO_D(CURBASE(PIPE_A), D_ALL); 1767 MMIO_D(CURBASE(PIPE_B), D_ALL); 1768 MMIO_D(CURBASE(PIPE_C), D_ALL); 1769 1770 MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL); 1771 MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL); 1772 MMIO_D(CUR_FBC_CTL(PIPE_C), D_ALL); 1773 1774 MMIO_D(_MMIO(0x700ac), D_ALL); 1775 MMIO_D(_MMIO(0x710ac), D_ALL); 1776 MMIO_D(_MMIO(0x720ac), D_ALL); 1777 1778 MMIO_D(_MMIO(0x70090), D_ALL); 1779 MMIO_D(_MMIO(0x70094), D_ALL); 1780 MMIO_D(_MMIO(0x70098), D_ALL); 1781 MMIO_D(_MMIO(0x7009c), D_ALL); 1782 1783 MMIO_D(DSPCNTR(PIPE_A), D_ALL); 1784 MMIO_D(DSPADDR(PIPE_A), D_ALL); 1785 MMIO_D(DSPSTRIDE(PIPE_A), D_ALL); 1786 MMIO_D(DSPPOS(PIPE_A), D_ALL); 1787 MMIO_D(DSPSIZE(PIPE_A), D_ALL); 1788 MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write); 1789 MMIO_D(DSPOFFSET(PIPE_A), D_ALL); 1790 MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL); 1791 1792 MMIO_D(DSPCNTR(PIPE_B), D_ALL); 1793 MMIO_D(DSPADDR(PIPE_B), D_ALL); 1794 MMIO_D(DSPSTRIDE(PIPE_B), D_ALL); 1795 MMIO_D(DSPPOS(PIPE_B), D_ALL); 1796 MMIO_D(DSPSIZE(PIPE_B), D_ALL); 1797 MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write); 1798 MMIO_D(DSPOFFSET(PIPE_B), D_ALL); 1799 MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL); 1800 1801 MMIO_D(DSPCNTR(PIPE_C), D_ALL); 1802 MMIO_D(DSPADDR(PIPE_C), D_ALL); 1803 MMIO_D(DSPSTRIDE(PIPE_C), D_ALL); 1804 MMIO_D(DSPPOS(PIPE_C), D_ALL); 1805 MMIO_D(DSPSIZE(PIPE_C), D_ALL); 1806 MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write); 1807 MMIO_D(DSPOFFSET(PIPE_C), D_ALL); 1808 MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL); 1809 1810 MMIO_D(SPRCTL(PIPE_A), D_ALL); 1811 MMIO_D(SPRLINOFF(PIPE_A), D_ALL); 1812 MMIO_D(SPRSTRIDE(PIPE_A), D_ALL); 1813 MMIO_D(SPRPOS(PIPE_A), D_ALL); 1814 MMIO_D(SPRSIZE(PIPE_A), D_ALL); 1815 MMIO_D(SPRKEYVAL(PIPE_A), D_ALL); 1816 MMIO_D(SPRKEYMSK(PIPE_A), D_ALL); 1817 MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write); 1818 MMIO_D(SPRKEYMAX(PIPE_A), D_ALL); 1819 MMIO_D(SPROFFSET(PIPE_A), D_ALL); 1820 MMIO_D(SPRSCALE(PIPE_A), D_ALL); 1821 MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL); 1822 1823 MMIO_D(SPRCTL(PIPE_B), D_ALL); 1824 MMIO_D(SPRLINOFF(PIPE_B), D_ALL); 1825 MMIO_D(SPRSTRIDE(PIPE_B), D_ALL); 1826 MMIO_D(SPRPOS(PIPE_B), D_ALL); 1827 MMIO_D(SPRSIZE(PIPE_B), D_ALL); 1828 MMIO_D(SPRKEYVAL(PIPE_B), D_ALL); 1829 MMIO_D(SPRKEYMSK(PIPE_B), D_ALL); 1830 MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write); 1831 MMIO_D(SPRKEYMAX(PIPE_B), D_ALL); 1832 MMIO_D(SPROFFSET(PIPE_B), D_ALL); 1833 MMIO_D(SPRSCALE(PIPE_B), D_ALL); 1834 MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL); 1835 1836 MMIO_D(SPRCTL(PIPE_C), D_ALL); 1837 MMIO_D(SPRLINOFF(PIPE_C), D_ALL); 1838 MMIO_D(SPRSTRIDE(PIPE_C), D_ALL); 1839 MMIO_D(SPRPOS(PIPE_C), D_ALL); 1840 MMIO_D(SPRSIZE(PIPE_C), D_ALL); 1841 MMIO_D(SPRKEYVAL(PIPE_C), D_ALL); 1842 MMIO_D(SPRKEYMSK(PIPE_C), D_ALL); 1843 MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write); 1844 MMIO_D(SPRKEYMAX(PIPE_C), D_ALL); 1845 MMIO_D(SPROFFSET(PIPE_C), D_ALL); 1846 MMIO_D(SPRSCALE(PIPE_C), D_ALL); 1847 MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL); 1848 1849 MMIO_D(HTOTAL(TRANSCODER_A), D_ALL); 1850 MMIO_D(HBLANK(TRANSCODER_A), D_ALL); 1851 MMIO_D(HSYNC(TRANSCODER_A), D_ALL); 1852 MMIO_D(VTOTAL(TRANSCODER_A), D_ALL); 1853 MMIO_D(VBLANK(TRANSCODER_A), D_ALL); 1854 MMIO_D(VSYNC(TRANSCODER_A), D_ALL); 1855 MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL); 1856 MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL); 1857 MMIO_D(PIPESRC(TRANSCODER_A), D_ALL); 1858 1859 MMIO_D(HTOTAL(TRANSCODER_B), D_ALL); 1860 MMIO_D(HBLANK(TRANSCODER_B), D_ALL); 1861 MMIO_D(HSYNC(TRANSCODER_B), D_ALL); 1862 MMIO_D(VTOTAL(TRANSCODER_B), D_ALL); 1863 MMIO_D(VBLANK(TRANSCODER_B), D_ALL); 1864 MMIO_D(VSYNC(TRANSCODER_B), D_ALL); 1865 MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL); 1866 MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL); 1867 MMIO_D(PIPESRC(TRANSCODER_B), D_ALL); 1868 1869 MMIO_D(HTOTAL(TRANSCODER_C), D_ALL); 1870 MMIO_D(HBLANK(TRANSCODER_C), D_ALL); 1871 MMIO_D(HSYNC(TRANSCODER_C), D_ALL); 1872 MMIO_D(VTOTAL(TRANSCODER_C), D_ALL); 1873 MMIO_D(VBLANK(TRANSCODER_C), D_ALL); 1874 MMIO_D(VSYNC(TRANSCODER_C), D_ALL); 1875 MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL); 1876 MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL); 1877 MMIO_D(PIPESRC(TRANSCODER_C), D_ALL); 1878 1879 MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL); 1880 MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL); 1881 MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL); 1882 MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL); 1883 MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL); 1884 MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL); 1885 MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL); 1886 MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL); 1887 1888 MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL); 1889 MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL); 1890 MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL); 1891 MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL); 1892 MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL); 1893 MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL); 1894 MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL); 1895 MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL); 1896 1897 MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL); 1898 MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL); 1899 MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL); 1900 MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL); 1901 MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL); 1902 MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL); 1903 MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL); 1904 MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL); 1905 1906 MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL); 1907 MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL); 1908 MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL); 1909 MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL); 1910 MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL); 1911 MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL); 1912 MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL); 1913 MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL); 1914 1915 MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL); 1916 MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL); 1917 MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL); 1918 MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL); 1919 MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL); 1920 MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL); 1921 MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL); 1922 MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL); 1923 1924 MMIO_D(PF_CTL(PIPE_A), D_ALL); 1925 MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL); 1926 MMIO_D(PF_WIN_POS(PIPE_A), D_ALL); 1927 MMIO_D(PF_VSCALE(PIPE_A), D_ALL); 1928 MMIO_D(PF_HSCALE(PIPE_A), D_ALL); 1929 1930 MMIO_D(PF_CTL(PIPE_B), D_ALL); 1931 MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL); 1932 MMIO_D(PF_WIN_POS(PIPE_B), D_ALL); 1933 MMIO_D(PF_VSCALE(PIPE_B), D_ALL); 1934 MMIO_D(PF_HSCALE(PIPE_B), D_ALL); 1935 1936 MMIO_D(PF_CTL(PIPE_C), D_ALL); 1937 MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL); 1938 MMIO_D(PF_WIN_POS(PIPE_C), D_ALL); 1939 MMIO_D(PF_VSCALE(PIPE_C), D_ALL); 1940 MMIO_D(PF_HSCALE(PIPE_C), D_ALL); 1941 1942 MMIO_D(WM0_PIPEA_ILK, D_ALL); 1943 MMIO_D(WM0_PIPEB_ILK, D_ALL); 1944 MMIO_D(WM0_PIPEC_IVB, D_ALL); 1945 MMIO_D(WM1_LP_ILK, D_ALL); 1946 MMIO_D(WM2_LP_ILK, D_ALL); 1947 MMIO_D(WM3_LP_ILK, D_ALL); 1948 MMIO_D(WM1S_LP_ILK, D_ALL); 1949 MMIO_D(WM2S_LP_IVB, D_ALL); 1950 MMIO_D(WM3S_LP_IVB, D_ALL); 1951 1952 MMIO_D(BLC_PWM_CPU_CTL2, D_ALL); 1953 MMIO_D(BLC_PWM_CPU_CTL, D_ALL); 1954 MMIO_D(BLC_PWM_PCH_CTL1, D_ALL); 1955 MMIO_D(BLC_PWM_PCH_CTL2, D_ALL); 1956 1957 MMIO_D(_MMIO(0x48268), D_ALL); 1958 1959 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read, 1960 gmbus_mmio_write); 1961 MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL); 1962 MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL); 1963 1964 MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 1965 dp_aux_ch_ctl_mmio_write); 1966 MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 1967 dp_aux_ch_ctl_mmio_write); 1968 MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 1969 dp_aux_ch_ctl_mmio_write); 1970 1971 MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write); 1972 1973 MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write); 1974 MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write); 1975 1976 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write); 1977 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write); 1978 MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write); 1979 MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); 1980 MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); 1981 MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); 1982 MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); 1983 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); 1984 MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); 1985 1986 MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A), D_ALL); 1987 MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A), D_ALL); 1988 MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A), D_ALL); 1989 MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A), D_ALL); 1990 MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A), D_ALL); 1991 MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A), D_ALL); 1992 MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A), D_ALL); 1993 1994 MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B), D_ALL); 1995 MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B), D_ALL); 1996 MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B), D_ALL); 1997 MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B), D_ALL); 1998 MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B), D_ALL); 1999 MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B), D_ALL); 2000 MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B), D_ALL); 2001 2002 MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1), D_ALL); 2003 MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1), D_ALL); 2004 MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2), D_ALL); 2005 MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2), D_ALL); 2006 MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1), D_ALL); 2007 MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1), D_ALL); 2008 MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2), D_ALL); 2009 MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2), D_ALL); 2010 2011 MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL); 2012 MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL); 2013 MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL); 2014 2015 MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL); 2016 MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL); 2017 MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL); 2018 2019 MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL); 2020 MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL); 2021 MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL); 2022 2023 MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL); 2024 MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL); 2025 MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL); 2026 2027 MMIO_D(_MMIO(_FDI_RXA_MISC), D_ALL); 2028 MMIO_D(_MMIO(_FDI_RXB_MISC), D_ALL); 2029 MMIO_D(_MMIO(_FDI_RXA_TUSIZE1), D_ALL); 2030 MMIO_D(_MMIO(_FDI_RXA_TUSIZE2), D_ALL); 2031 MMIO_D(_MMIO(_FDI_RXB_TUSIZE1), D_ALL); 2032 MMIO_D(_MMIO(_FDI_RXB_TUSIZE2), D_ALL); 2033 2034 MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write); 2035 MMIO_D(PCH_PP_DIVISOR, D_ALL); 2036 MMIO_D(PCH_PP_STATUS, D_ALL); 2037 MMIO_D(PCH_LVDS, D_ALL); 2038 MMIO_D(_MMIO(_PCH_DPLL_A), D_ALL); 2039 MMIO_D(_MMIO(_PCH_DPLL_B), D_ALL); 2040 MMIO_D(_MMIO(_PCH_FPA0), D_ALL); 2041 MMIO_D(_MMIO(_PCH_FPA1), D_ALL); 2042 MMIO_D(_MMIO(_PCH_FPB0), D_ALL); 2043 MMIO_D(_MMIO(_PCH_FPB1), D_ALL); 2044 MMIO_D(PCH_DREF_CONTROL, D_ALL); 2045 MMIO_D(PCH_RAWCLK_FREQ, D_ALL); 2046 MMIO_D(PCH_DPLL_SEL, D_ALL); 2047 2048 MMIO_D(_MMIO(0x61208), D_ALL); 2049 MMIO_D(_MMIO(0x6120c), D_ALL); 2050 MMIO_D(PCH_PP_ON_DELAYS, D_ALL); 2051 MMIO_D(PCH_PP_OFF_DELAYS, D_ALL); 2052 2053 MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL); 2054 MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL); 2055 MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL); 2056 MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL); 2057 MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL); 2058 MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL); 2059 2060 MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0, 2061 PORTA_HOTPLUG_STATUS_MASK 2062 | PORTB_HOTPLUG_STATUS_MASK 2063 | PORTC_HOTPLUG_STATUS_MASK 2064 | PORTD_HOTPLUG_STATUS_MASK, 2065 NULL, NULL); 2066 2067 MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write); 2068 MMIO_D(FUSE_STRAP, D_ALL); 2069 MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL); 2070 2071 MMIO_D(DISP_ARB_CTL, D_ALL); 2072 MMIO_D(DISP_ARB_CTL2, D_ALL); 2073 2074 MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL); 2075 MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL); 2076 MMIO_D(ILK_DSPCLK_GATE_D, D_ALL); 2077 2078 MMIO_D(SOUTH_CHICKEN1, D_ALL); 2079 MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write); 2080 MMIO_D(_MMIO(_TRANSA_CHICKEN1), D_ALL); 2081 MMIO_D(_MMIO(_TRANSB_CHICKEN1), D_ALL); 2082 MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL); 2083 MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL); 2084 MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL); 2085 2086 MMIO_D(ILK_DPFC_CB_BASE, D_ALL); 2087 MMIO_D(ILK_DPFC_CONTROL, D_ALL); 2088 MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL); 2089 MMIO_D(ILK_DPFC_STATUS, D_ALL); 2090 MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL); 2091 MMIO_D(ILK_DPFC_CHICKEN, D_ALL); 2092 MMIO_D(ILK_FBC_RT_BASE, D_ALL); 2093 2094 MMIO_D(IPS_CTL, D_ALL); 2095 2096 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL); 2097 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL); 2098 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL); 2099 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL); 2100 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL); 2101 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL); 2102 MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL); 2103 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL); 2104 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL); 2105 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL); 2106 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL); 2107 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL); 2108 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL); 2109 2110 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL); 2111 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL); 2112 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL); 2113 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL); 2114 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL); 2115 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL); 2116 MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL); 2117 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL); 2118 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL); 2119 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL); 2120 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL); 2121 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL); 2122 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL); 2123 2124 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL); 2125 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL); 2126 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL); 2127 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL); 2128 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL); 2129 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL); 2130 MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL); 2131 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL); 2132 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL); 2133 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL); 2134 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL); 2135 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL); 2136 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL); 2137 2138 MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL); 2139 MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL); 2140 MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 2141 2142 MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL); 2143 MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL); 2144 MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 2145 2146 MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL); 2147 MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL); 2148 MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 2149 2150 MMIO_D(_MMIO(0x60110), D_ALL); 2151 MMIO_D(_MMIO(0x61110), D_ALL); 2152 MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL); 2153 MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL); 2154 MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL); 2155 MMIO_F(_MMIO(0x70440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2156 MMIO_F(_MMIO(0x71440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2157 MMIO_F(_MMIO(0x72440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2158 MMIO_F(_MMIO(0x7044c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2159 MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2160 MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2161 2162 MMIO_D(PIPE_WM_LINETIME(PIPE_A), D_ALL); 2163 MMIO_D(PIPE_WM_LINETIME(PIPE_B), D_ALL); 2164 MMIO_D(PIPE_WM_LINETIME(PIPE_C), D_ALL); 2165 MMIO_D(SPLL_CTL, D_ALL); 2166 MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL); 2167 MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL); 2168 MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL); 2169 MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL); 2170 MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL); 2171 MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL); 2172 MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL); 2173 MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL); 2174 MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL); 2175 MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL); 2176 2177 MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL); 2178 MMIO_D(_MMIO(0x46508), D_ALL); 2179 2180 MMIO_D(_MMIO(0x49080), D_ALL); 2181 MMIO_D(_MMIO(0x49180), D_ALL); 2182 MMIO_D(_MMIO(0x49280), D_ALL); 2183 2184 MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL); 2185 MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL); 2186 MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL); 2187 2188 MMIO_D(GAMMA_MODE(PIPE_A), D_ALL); 2189 MMIO_D(GAMMA_MODE(PIPE_B), D_ALL); 2190 MMIO_D(GAMMA_MODE(PIPE_C), D_ALL); 2191 2192 MMIO_D(PIPE_MULT(PIPE_A), D_ALL); 2193 MMIO_D(PIPE_MULT(PIPE_B), D_ALL); 2194 MMIO_D(PIPE_MULT(PIPE_C), D_ALL); 2195 2196 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL); 2197 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL); 2198 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL); 2199 2200 MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL); 2201 MMIO_D(SBI_ADDR, D_ALL); 2202 MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL); 2203 MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write); 2204 MMIO_D(PIXCLK_GATE, D_ALL); 2205 2206 MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL, 2207 dp_aux_ch_ctl_mmio_write); 2208 2209 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2210 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2211 MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2212 MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2213 MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2214 2215 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write); 2216 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write); 2217 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write); 2218 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write); 2219 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write); 2220 2221 MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write); 2222 MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write); 2223 MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write); 2224 MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write); 2225 MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL); 2226 2227 MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2228 MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2229 MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2230 MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2231 MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2232 2233 MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL); 2234 MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL); 2235 MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A), D_ALL); 2236 2237 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL); 2238 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL); 2239 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL); 2240 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL); 2241 2242 MMIO_D(_MMIO(_TRANSA_MSA_MISC), D_ALL); 2243 MMIO_D(_MMIO(_TRANSB_MSA_MISC), D_ALL); 2244 MMIO_D(_MMIO(_TRANSC_MSA_MISC), D_ALL); 2245 MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC), D_ALL); 2246 2247 MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL); 2248 MMIO_D(FORCEWAKE_ACK, D_ALL); 2249 MMIO_D(GEN6_GT_CORE_STATUS, D_ALL); 2250 MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL); 2251 MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL); 2252 MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL); 2253 MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write); 2254 MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL); 2255 MMIO_D(ECOBUS, D_ALL); 2256 MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL); 2257 MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL); 2258 MMIO_D(GEN6_RPNSWREQ, D_ALL); 2259 MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL); 2260 MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL); 2261 MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL); 2262 MMIO_D(GEN6_RPSTAT1, D_ALL); 2263 MMIO_D(GEN6_RP_CONTROL, D_ALL); 2264 MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL); 2265 MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL); 2266 MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL); 2267 MMIO_D(GEN6_RP_CUR_UP, D_ALL); 2268 MMIO_D(GEN6_RP_PREV_UP, D_ALL); 2269 MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL); 2270 MMIO_D(GEN6_RP_CUR_DOWN, D_ALL); 2271 MMIO_D(GEN6_RP_PREV_DOWN, D_ALL); 2272 MMIO_D(GEN6_RP_UP_EI, D_ALL); 2273 MMIO_D(GEN6_RP_DOWN_EI, D_ALL); 2274 MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL); 2275 MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL); 2276 MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL); 2277 MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL); 2278 MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL); 2279 MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL); 2280 MMIO_D(GEN6_RC_SLEEP, D_ALL); 2281 MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL); 2282 MMIO_D(GEN6_RC6_THRESHOLD, D_ALL); 2283 MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL); 2284 MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL); 2285 MMIO_D(GEN6_PMINTRMSK, D_ALL); 2286 /* 2287 * Use an arbitrary power well controlled by the PWR_WELL_CTL 2288 * register. 2289 */ 2290 MMIO_DH(HSW_PWR_WELL_CTL_BIOS(HSW_DISP_PW_GLOBAL), D_BDW, NULL, 2291 power_well_ctl_mmio_write); 2292 MMIO_DH(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL), D_BDW, NULL, 2293 power_well_ctl_mmio_write); 2294 MMIO_DH(HSW_PWR_WELL_CTL_KVMR, D_BDW, NULL, power_well_ctl_mmio_write); 2295 MMIO_DH(HSW_PWR_WELL_CTL_DEBUG(HSW_DISP_PW_GLOBAL), D_BDW, NULL, 2296 power_well_ctl_mmio_write); 2297 MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write); 2298 MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write); 2299 2300 MMIO_D(RSTDBYCTL, D_ALL); 2301 2302 MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write); 2303 MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write); 2304 MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write); 2305 2306 MMIO_D(TILECTL, D_ALL); 2307 2308 MMIO_D(GEN6_UCGCTL1, D_ALL); 2309 MMIO_D(GEN6_UCGCTL2, D_ALL); 2310 2311 MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL); 2312 2313 MMIO_D(GEN6_PCODE_DATA, D_ALL); 2314 MMIO_D(_MMIO(0x13812c), D_ALL); 2315 MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL); 2316 MMIO_D(HSW_EDRAM_CAP, D_ALL); 2317 MMIO_D(HSW_IDICR, D_ALL); 2318 MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL); 2319 2320 MMIO_D(_MMIO(0x3c), D_ALL); 2321 MMIO_D(_MMIO(0x860), D_ALL); 2322 MMIO_D(ECOSKPD, D_ALL); 2323 MMIO_D(_MMIO(0x121d0), D_ALL); 2324 MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL); 2325 MMIO_D(_MMIO(0x41d0), D_ALL); 2326 MMIO_D(GAC_ECO_BITS, D_ALL); 2327 MMIO_D(_MMIO(0x6200), D_ALL); 2328 MMIO_D(_MMIO(0x6204), D_ALL); 2329 MMIO_D(_MMIO(0x6208), D_ALL); 2330 MMIO_D(_MMIO(0x7118), D_ALL); 2331 MMIO_D(_MMIO(0x7180), D_ALL); 2332 MMIO_D(_MMIO(0x7408), D_ALL); 2333 MMIO_D(_MMIO(0x7c00), D_ALL); 2334 MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write); 2335 MMIO_D(_MMIO(0x911c), D_ALL); 2336 MMIO_D(_MMIO(0x9120), D_ALL); 2337 MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL); 2338 2339 MMIO_D(GAB_CTL, D_ALL); 2340 MMIO_D(_MMIO(0x48800), D_ALL); 2341 MMIO_D(_MMIO(0xce044), D_ALL); 2342 MMIO_D(_MMIO(0xe6500), D_ALL); 2343 MMIO_D(_MMIO(0xe6504), D_ALL); 2344 MMIO_D(_MMIO(0xe6600), D_ALL); 2345 MMIO_D(_MMIO(0xe6604), D_ALL); 2346 MMIO_D(_MMIO(0xe6700), D_ALL); 2347 MMIO_D(_MMIO(0xe6704), D_ALL); 2348 MMIO_D(_MMIO(0xe6800), D_ALL); 2349 MMIO_D(_MMIO(0xe6804), D_ALL); 2350 MMIO_D(PCH_GMBUS4, D_ALL); 2351 MMIO_D(PCH_GMBUS5, D_ALL); 2352 2353 MMIO_D(_MMIO(0x902c), D_ALL); 2354 MMIO_D(_MMIO(0xec008), D_ALL); 2355 MMIO_D(_MMIO(0xec00c), D_ALL); 2356 MMIO_D(_MMIO(0xec008 + 0x18), D_ALL); 2357 MMIO_D(_MMIO(0xec00c + 0x18), D_ALL); 2358 MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL); 2359 MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL); 2360 MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL); 2361 MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL); 2362 MMIO_D(_MMIO(0xec408), D_ALL); 2363 MMIO_D(_MMIO(0xec40c), D_ALL); 2364 MMIO_D(_MMIO(0xec408 + 0x18), D_ALL); 2365 MMIO_D(_MMIO(0xec40c + 0x18), D_ALL); 2366 MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL); 2367 MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL); 2368 MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL); 2369 MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL); 2370 MMIO_D(_MMIO(0xfc810), D_ALL); 2371 MMIO_D(_MMIO(0xfc81c), D_ALL); 2372 MMIO_D(_MMIO(0xfc828), D_ALL); 2373 MMIO_D(_MMIO(0xfc834), D_ALL); 2374 MMIO_D(_MMIO(0xfcc00), D_ALL); 2375 MMIO_D(_MMIO(0xfcc0c), D_ALL); 2376 MMIO_D(_MMIO(0xfcc18), D_ALL); 2377 MMIO_D(_MMIO(0xfcc24), D_ALL); 2378 MMIO_D(_MMIO(0xfd000), D_ALL); 2379 MMIO_D(_MMIO(0xfd00c), D_ALL); 2380 MMIO_D(_MMIO(0xfd018), D_ALL); 2381 MMIO_D(_MMIO(0xfd024), D_ALL); 2382 MMIO_D(_MMIO(0xfd034), D_ALL); 2383 2384 MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write); 2385 MMIO_D(_MMIO(0x2054), D_ALL); 2386 MMIO_D(_MMIO(0x12054), D_ALL); 2387 MMIO_D(_MMIO(0x22054), D_ALL); 2388 MMIO_D(_MMIO(0x1a054), D_ALL); 2389 2390 MMIO_D(_MMIO(0x44070), D_ALL); 2391 MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2392 MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL); 2393 MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL); 2394 MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL); 2395 MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL); 2396 2397 MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL); 2398 MMIO_D(_MMIO(0x2b00), D_BDW_PLUS); 2399 MMIO_D(_MMIO(0x2360), D_BDW_PLUS); 2400 MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2401 MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2402 MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2403 2404 MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2405 MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2406 MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL); 2407 2408 MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2409 MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2410 MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2411 MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2412 MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2413 MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2414 MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2415 MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2416 MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2417 MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2418 MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2419 MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2420 MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2421 MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2422 MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2423 MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2424 MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2425 2426 MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2427 MMIO_RING_GM_RDR(RING_BBADDR, D_ALL, NULL, NULL); 2428 MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL); 2429 MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL); 2430 MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL); 2431 MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL); 2432 MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL); 2433 MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2434 MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2435 MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2436 MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2437 return 0; 2438 } 2439 2440 static int init_broadwell_mmio_info(struct intel_gvt *gvt) 2441 { 2442 struct drm_i915_private *dev_priv = gvt->dev_priv; 2443 int ret; 2444 2445 MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2446 MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2447 MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2448 MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS); 2449 2450 MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2451 MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2452 MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2453 MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS); 2454 2455 MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2456 MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2457 MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2458 MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS); 2459 2460 MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2461 MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2462 MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2463 MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS); 2464 2465 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL, 2466 intel_vgpu_reg_imr_handler); 2467 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL, 2468 intel_vgpu_reg_ier_handler); 2469 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL, 2470 intel_vgpu_reg_iir_handler); 2471 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS); 2472 2473 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL, 2474 intel_vgpu_reg_imr_handler); 2475 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL, 2476 intel_vgpu_reg_ier_handler); 2477 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL, 2478 intel_vgpu_reg_iir_handler); 2479 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS); 2480 2481 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL, 2482 intel_vgpu_reg_imr_handler); 2483 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL, 2484 intel_vgpu_reg_ier_handler); 2485 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL, 2486 intel_vgpu_reg_iir_handler); 2487 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS); 2488 2489 MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2490 MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2491 MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2492 MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS); 2493 2494 MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2495 MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2496 MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2497 MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS); 2498 2499 MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2500 MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2501 MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2502 MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS); 2503 2504 MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL, 2505 intel_vgpu_reg_master_irq_handler); 2506 2507 MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, F_CMD_ACCESS, 2508 mmio_read_from_hw, NULL); 2509 2510 #define RING_REG(base) _MMIO((base) + 0xd0) 2511 MMIO_RING_F(RING_REG, 4, F_RO, 0, 2512 ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL, 2513 ring_reset_ctl_write); 2514 #undef RING_REG 2515 2516 #define RING_REG(base) _MMIO((base) + 0x230) 2517 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write); 2518 #undef RING_REG 2519 2520 #define RING_REG(base) _MMIO((base) + 0x234) 2521 MMIO_RING_F(RING_REG, 8, F_RO | F_CMD_ACCESS, 0, ~0, D_BDW_PLUS, 2522 NULL, NULL); 2523 #undef RING_REG 2524 2525 #define RING_REG(base) _MMIO((base) + 0x244) 2526 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2527 #undef RING_REG 2528 2529 #define RING_REG(base) _MMIO((base) + 0x370) 2530 MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL); 2531 #undef RING_REG 2532 2533 #define RING_REG(base) _MMIO((base) + 0x3a0) 2534 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2535 #undef RING_REG 2536 2537 MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS); 2538 MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS); 2539 MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS); 2540 MMIO_D(_MMIO(0x1c1d0), D_BDW_PLUS); 2541 MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS); 2542 MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS); 2543 MMIO_D(_MMIO(0x1c054), D_BDW_PLUS); 2544 2545 MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write); 2546 2547 MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS); 2548 MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS); 2549 2550 MMIO_D(GAMTARBMODE, D_BDW_PLUS); 2551 2552 #define RING_REG(base) _MMIO((base) + 0x270) 2553 MMIO_RING_F(RING_REG, 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL); 2554 #undef RING_REG 2555 2556 MMIO_RING_GM_RDR(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write); 2557 2558 MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2559 2560 MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS); 2561 MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS); 2562 MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS); 2563 2564 MMIO_D(WM_MISC, D_BDW); 2565 MMIO_D(_MMIO(BDW_EDP_PSR_BASE), D_BDW); 2566 2567 MMIO_D(_MMIO(0x6671c), D_BDW_PLUS); 2568 MMIO_D(_MMIO(0x66c00), D_BDW_PLUS); 2569 MMIO_D(_MMIO(0x66c04), D_BDW_PLUS); 2570 2571 MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS); 2572 2573 MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS); 2574 MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS); 2575 MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS); 2576 2577 MMIO_D(_MMIO(0xfdc), D_BDW_PLUS); 2578 MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2579 NULL, NULL); 2580 MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2581 NULL, NULL); 2582 MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2583 2584 MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL); 2585 MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL); 2586 MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2587 MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL); 2588 MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL); 2589 MMIO_D(_MMIO(0xb110), D_BDW); 2590 2591 MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, 2592 NULL, force_nonpriv_write); 2593 2594 MMIO_D(_MMIO(0x44484), D_BDW_PLUS); 2595 MMIO_D(_MMIO(0x4448c), D_BDW_PLUS); 2596 2597 MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL); 2598 MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS); 2599 2600 MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL); 2601 2602 MMIO_D(_MMIO(0x110000), D_BDW_PLUS); 2603 2604 MMIO_D(_MMIO(0x48400), D_BDW_PLUS); 2605 2606 MMIO_D(_MMIO(0x6e570), D_BDW_PLUS); 2607 MMIO_D(_MMIO(0x65f10), D_BDW_PLUS); 2608 2609 MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2610 MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2611 MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2612 MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2613 2614 MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL); 2615 2616 MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2617 MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2618 MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2619 MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2620 MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2621 MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2622 MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2623 MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2624 MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2625 return 0; 2626 } 2627 2628 static int init_skl_mmio_info(struct intel_gvt *gvt) 2629 { 2630 struct drm_i915_private *dev_priv = gvt->dev_priv; 2631 int ret; 2632 2633 MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2634 MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL); 2635 MMIO_DH(FORCEWAKE_BLITTER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2636 MMIO_DH(FORCEWAKE_ACK_BLITTER_GEN9, D_SKL_PLUS, NULL, NULL); 2637 MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2638 MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL); 2639 2640 MMIO_F(_MMIO(_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 2641 dp_aux_ch_ctl_mmio_write); 2642 MMIO_F(_MMIO(_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 2643 dp_aux_ch_ctl_mmio_write); 2644 MMIO_F(_MMIO(_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 2645 dp_aux_ch_ctl_mmio_write); 2646 2647 /* 2648 * Use an arbitrary power well controlled by the PWR_WELL_CTL 2649 * register. 2650 */ 2651 MMIO_D(HSW_PWR_WELL_CTL_BIOS(SKL_DISP_PW_MISC_IO), D_SKL_PLUS); 2652 MMIO_DH(HSW_PWR_WELL_CTL_DRIVER(SKL_DISP_PW_MISC_IO), D_SKL_PLUS, NULL, 2653 skl_power_well_ctl_write); 2654 2655 MMIO_D(_MMIO(0xa210), D_SKL_PLUS); 2656 MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS); 2657 MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS); 2658 MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2659 MMIO_DH(_MMIO(0x4ddc), D_SKL_PLUS, NULL, NULL); 2660 MMIO_DH(_MMIO(0x42080), D_SKL_PLUS, NULL, NULL); 2661 MMIO_D(_MMIO(0x45504), D_SKL_PLUS); 2662 MMIO_D(_MMIO(0x45520), D_SKL_PLUS); 2663 MMIO_D(_MMIO(0x46000), D_SKL_PLUS); 2664 MMIO_DH(_MMIO(0x46010), D_SKL | D_KBL, NULL, skl_lcpll_write); 2665 MMIO_DH(_MMIO(0x46014), D_SKL | D_KBL, NULL, skl_lcpll_write); 2666 MMIO_D(_MMIO(0x6C040), D_SKL | D_KBL); 2667 MMIO_D(_MMIO(0x6C048), D_SKL | D_KBL); 2668 MMIO_D(_MMIO(0x6C050), D_SKL | D_KBL); 2669 MMIO_D(_MMIO(0x6C044), D_SKL | D_KBL); 2670 MMIO_D(_MMIO(0x6C04C), D_SKL | D_KBL); 2671 MMIO_D(_MMIO(0x6C054), D_SKL | D_KBL); 2672 MMIO_D(_MMIO(0x6c058), D_SKL | D_KBL); 2673 MMIO_D(_MMIO(0x6c05c), D_SKL | D_KBL); 2674 MMIO_DH(_MMIO(0x6c060), D_SKL | D_KBL, dpll_status_read, NULL); 2675 2676 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); 2677 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); 2678 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); 2679 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); 2680 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); 2681 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); 2682 2683 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); 2684 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); 2685 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); 2686 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); 2687 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); 2688 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); 2689 2690 MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); 2691 MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); 2692 MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); 2693 MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); 2694 MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); 2695 MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); 2696 2697 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 2698 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 2699 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 2700 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); 2701 2702 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 2703 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 2704 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 2705 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); 2706 2707 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 2708 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 2709 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2710 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); 2711 2712 MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL); 2713 MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL); 2714 MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL); 2715 2716 MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2717 MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2718 MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2719 2720 MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2721 MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2722 MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2723 2724 MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2725 MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2726 MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2727 2728 MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2729 MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2730 MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2731 2732 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 2733 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 2734 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 2735 2736 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 2737 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 2738 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 2739 2740 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 2741 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 2742 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2743 2744 MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL); 2745 MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL); 2746 MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL); 2747 2748 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 2749 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 2750 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 2751 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); 2752 2753 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 2754 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 2755 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 2756 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); 2757 2758 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 2759 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 2760 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2761 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); 2762 2763 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL); 2764 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL); 2765 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL); 2766 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL); 2767 2768 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL); 2769 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL); 2770 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL); 2771 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL); 2772 2773 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL); 2774 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL); 2775 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL); 2776 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL); 2777 2778 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL); 2779 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL); 2780 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL); 2781 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL); 2782 2783 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL); 2784 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL); 2785 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL); 2786 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL); 2787 2788 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL); 2789 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL); 2790 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL); 2791 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL); 2792 2793 MMIO_D(_MMIO(0x70380), D_SKL_PLUS); 2794 MMIO_D(_MMIO(0x71380), D_SKL_PLUS); 2795 MMIO_D(_MMIO(0x72380), D_SKL_PLUS); 2796 MMIO_D(_MMIO(0x7239c), D_SKL_PLUS); 2797 MMIO_D(_MMIO(0x7039c), D_SKL_PLUS); 2798 2799 MMIO_D(_MMIO(0x8f074), D_SKL | D_KBL); 2800 MMIO_D(_MMIO(0x8f004), D_SKL | D_KBL); 2801 MMIO_D(_MMIO(0x8f034), D_SKL | D_KBL); 2802 2803 MMIO_D(_MMIO(0xb11c), D_SKL | D_KBL); 2804 2805 MMIO_D(_MMIO(0x51000), D_SKL | D_KBL); 2806 MMIO_D(_MMIO(0x6c00c), D_SKL_PLUS); 2807 2808 MMIO_F(_MMIO(0xc800), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL | D_KBL, NULL, NULL); 2809 MMIO_F(_MMIO(0xb020), 0x80, F_CMD_ACCESS, 0, 0, D_SKL | D_KBL, NULL, NULL); 2810 2811 MMIO_D(RPM_CONFIG0, D_SKL_PLUS); 2812 MMIO_D(_MMIO(0xd08), D_SKL_PLUS); 2813 MMIO_D(RC6_LOCATION, D_SKL_PLUS); 2814 MMIO_DFH(_MMIO(0x20e0), D_SKL_PLUS, F_MODE_MASK, NULL, NULL); 2815 MMIO_DFH(_MMIO(0x20ec), D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2816 2817 /* TRTT */ 2818 MMIO_DFH(_MMIO(0x4de0), D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL); 2819 MMIO_DFH(_MMIO(0x4de4), D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL); 2820 MMIO_DFH(_MMIO(0x4de8), D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL); 2821 MMIO_DFH(_MMIO(0x4dec), D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL); 2822 MMIO_DFH(_MMIO(0x4df0), D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL); 2823 MMIO_DFH(_MMIO(0x4df4), D_SKL | D_KBL, F_CMD_ACCESS, NULL, gen9_trtte_write); 2824 MMIO_DH(_MMIO(0x4dfc), D_SKL | D_KBL, NULL, gen9_trtt_chicken_write); 2825 2826 MMIO_D(_MMIO(0x45008), D_SKL | D_KBL); 2827 2828 MMIO_D(_MMIO(0x46430), D_SKL | D_KBL); 2829 2830 MMIO_D(_MMIO(0x46520), D_SKL | D_KBL); 2831 2832 MMIO_D(_MMIO(0xc403c), D_SKL | D_KBL); 2833 MMIO_D(_MMIO(0xb004), D_SKL_PLUS); 2834 MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write); 2835 2836 MMIO_D(_MMIO(0x65900), D_SKL_PLUS); 2837 MMIO_D(_MMIO(0x1082c0), D_SKL | D_KBL); 2838 MMIO_D(_MMIO(0x4068), D_SKL | D_KBL); 2839 MMIO_D(_MMIO(0x67054), D_SKL | D_KBL); 2840 MMIO_D(_MMIO(0x6e560), D_SKL | D_KBL); 2841 MMIO_D(_MMIO(0x6e554), D_SKL | D_KBL); 2842 MMIO_D(_MMIO(0x2b20), D_SKL | D_KBL); 2843 MMIO_D(_MMIO(0x65f00), D_SKL | D_KBL); 2844 MMIO_D(_MMIO(0x65f08), D_SKL | D_KBL); 2845 MMIO_D(_MMIO(0x320f0), D_SKL | D_KBL); 2846 2847 MMIO_D(_MMIO(0x70034), D_SKL_PLUS); 2848 MMIO_D(_MMIO(0x71034), D_SKL_PLUS); 2849 MMIO_D(_MMIO(0x72034), D_SKL_PLUS); 2850 2851 MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A)), D_SKL_PLUS); 2852 MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B)), D_SKL_PLUS); 2853 MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C)), D_SKL_PLUS); 2854 MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A)), D_SKL_PLUS); 2855 MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B)), D_SKL_PLUS); 2856 MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C)), D_SKL_PLUS); 2857 MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A)), D_SKL_PLUS); 2858 MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)), D_SKL_PLUS); 2859 MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)), D_SKL_PLUS); 2860 2861 MMIO_D(_MMIO(0x44500), D_SKL_PLUS); 2862 MMIO_DFH(GEN9_CSFE_CHICKEN1_RCS, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2863 MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL | D_KBL, F_MODE_MASK | F_CMD_ACCESS, 2864 NULL, NULL); 2865 2866 MMIO_D(_MMIO(0x4ab8), D_KBL); 2867 MMIO_D(_MMIO(0x2248), D_SKL_PLUS | D_KBL); 2868 2869 return 0; 2870 } 2871 2872 static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt, 2873 unsigned int offset) 2874 { 2875 unsigned long device = intel_gvt_get_device_type(gvt); 2876 struct gvt_mmio_block *block = gvt->mmio.mmio_block; 2877 int num = gvt->mmio.num_mmio_block; 2878 int i; 2879 2880 for (i = 0; i < num; i++, block++) { 2881 if (!(device & block->device)) 2882 continue; 2883 if (offset >= i915_mmio_reg_offset(block->offset) && 2884 offset < i915_mmio_reg_offset(block->offset) + block->size) 2885 return block; 2886 } 2887 return NULL; 2888 } 2889 2890 /** 2891 * intel_gvt_clean_mmio_info - clean up MMIO information table for GVT device 2892 * @gvt: GVT device 2893 * 2894 * This function is called at the driver unloading stage, to clean up the MMIO 2895 * information table of GVT device 2896 * 2897 */ 2898 void intel_gvt_clean_mmio_info(struct intel_gvt *gvt) 2899 { 2900 struct hlist_node *tmp; 2901 struct intel_gvt_mmio_info *e; 2902 int i; 2903 2904 hash_for_each_safe(gvt->mmio.mmio_info_table, i, tmp, e, node) 2905 kfree(e); 2906 2907 vfree(gvt->mmio.mmio_attribute); 2908 gvt->mmio.mmio_attribute = NULL; 2909 } 2910 2911 /* Special MMIO blocks. */ 2912 static struct gvt_mmio_block mmio_blocks[] = { 2913 {D_SKL_PLUS, _MMIO(CSR_MMIO_START_RANGE), 0x3000, NULL, NULL}, 2914 {D_ALL, _MMIO(MCHBAR_MIRROR_BASE_SNB), 0x40000, NULL, NULL}, 2915 {D_ALL, _MMIO(VGT_PVINFO_PAGE), VGT_PVINFO_SIZE, 2916 pvinfo_mmio_read, pvinfo_mmio_write}, 2917 {D_ALL, LGC_PALETTE(PIPE_A, 0), 1024, NULL, NULL}, 2918 {D_ALL, LGC_PALETTE(PIPE_B, 0), 1024, NULL, NULL}, 2919 {D_ALL, LGC_PALETTE(PIPE_C, 0), 1024, NULL, NULL}, 2920 }; 2921 2922 /** 2923 * intel_gvt_setup_mmio_info - setup MMIO information table for GVT device 2924 * @gvt: GVT device 2925 * 2926 * This function is called at the initialization stage, to setup the MMIO 2927 * information table for GVT device 2928 * 2929 * Returns: 2930 * zero on success, negative if failed. 2931 */ 2932 int intel_gvt_setup_mmio_info(struct intel_gvt *gvt) 2933 { 2934 struct intel_gvt_device_info *info = &gvt->device_info; 2935 struct drm_i915_private *dev_priv = gvt->dev_priv; 2936 int size = info->mmio_size / 4 * sizeof(*gvt->mmio.mmio_attribute); 2937 int ret; 2938 2939 gvt->mmio.mmio_attribute = vzalloc(size); 2940 if (!gvt->mmio.mmio_attribute) 2941 return -ENOMEM; 2942 2943 ret = init_generic_mmio_info(gvt); 2944 if (ret) 2945 goto err; 2946 2947 if (IS_BROADWELL(dev_priv)) { 2948 ret = init_broadwell_mmio_info(gvt); 2949 if (ret) 2950 goto err; 2951 } else if (IS_SKYLAKE(dev_priv) 2952 || IS_KABYLAKE(dev_priv)) { 2953 ret = init_broadwell_mmio_info(gvt); 2954 if (ret) 2955 goto err; 2956 ret = init_skl_mmio_info(gvt); 2957 if (ret) 2958 goto err; 2959 } 2960 2961 gvt->mmio.mmio_block = mmio_blocks; 2962 gvt->mmio.num_mmio_block = ARRAY_SIZE(mmio_blocks); 2963 2964 return 0; 2965 err: 2966 intel_gvt_clean_mmio_info(gvt); 2967 return ret; 2968 } 2969 2970 /** 2971 * intel_gvt_for_each_tracked_mmio - iterate each tracked mmio 2972 * @gvt: a GVT device 2973 * @handler: the handler 2974 * @data: private data given to handler 2975 * 2976 * Returns: 2977 * Zero on success, negative error code if failed. 2978 */ 2979 int intel_gvt_for_each_tracked_mmio(struct intel_gvt *gvt, 2980 int (*handler)(struct intel_gvt *gvt, u32 offset, void *data), 2981 void *data) 2982 { 2983 struct gvt_mmio_block *block = gvt->mmio.mmio_block; 2984 struct intel_gvt_mmio_info *e; 2985 int i, j, ret; 2986 2987 hash_for_each(gvt->mmio.mmio_info_table, i, e, node) { 2988 ret = handler(gvt, e->offset, data); 2989 if (ret) 2990 return ret; 2991 } 2992 2993 for (i = 0; i < gvt->mmio.num_mmio_block; i++, block++) { 2994 for (j = 0; j < block->size; j += 4) { 2995 ret = handler(gvt, 2996 i915_mmio_reg_offset(block->offset) + j, 2997 data); 2998 if (ret) 2999 return ret; 3000 } 3001 } 3002 return 0; 3003 } 3004 3005 /** 3006 * intel_vgpu_default_mmio_read - default MMIO read handler 3007 * @vgpu: a vGPU 3008 * @offset: access offset 3009 * @p_data: data return buffer 3010 * @bytes: access data length 3011 * 3012 * Returns: 3013 * Zero on success, negative error code if failed. 3014 */ 3015 int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 3016 void *p_data, unsigned int bytes) 3017 { 3018 read_vreg(vgpu, offset, p_data, bytes); 3019 return 0; 3020 } 3021 3022 /** 3023 * intel_t_default_mmio_write - default MMIO write handler 3024 * @vgpu: a vGPU 3025 * @offset: access offset 3026 * @p_data: write data buffer 3027 * @bytes: access data length 3028 * 3029 * Returns: 3030 * Zero on success, negative error code if failed. 3031 */ 3032 int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 3033 void *p_data, unsigned int bytes) 3034 { 3035 write_vreg(vgpu, offset, p_data, bytes); 3036 return 0; 3037 } 3038 3039 /** 3040 * intel_gvt_in_force_nonpriv_whitelist - if a mmio is in whitelist to be 3041 * force-nopriv register 3042 * 3043 * @gvt: a GVT device 3044 * @offset: register offset 3045 * 3046 * Returns: 3047 * True if the register is in force-nonpriv whitelist; 3048 * False if outside; 3049 */ 3050 bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt, 3051 unsigned int offset) 3052 { 3053 return in_whitelist(offset); 3054 } 3055 3056 /** 3057 * intel_vgpu_mmio_reg_rw - emulate tracked mmio registers 3058 * @vgpu: a vGPU 3059 * @offset: register offset 3060 * @pdata: data buffer 3061 * @bytes: data length 3062 * 3063 * Returns: 3064 * Zero on success, negative error code if failed. 3065 */ 3066 int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset, 3067 void *pdata, unsigned int bytes, bool is_read) 3068 { 3069 struct intel_gvt *gvt = vgpu->gvt; 3070 struct intel_gvt_mmio_info *mmio_info; 3071 struct gvt_mmio_block *mmio_block; 3072 gvt_mmio_func func; 3073 int ret; 3074 3075 if (WARN_ON(bytes > 8)) 3076 return -EINVAL; 3077 3078 /* 3079 * Handle special MMIO blocks. 3080 */ 3081 mmio_block = find_mmio_block(gvt, offset); 3082 if (mmio_block) { 3083 func = is_read ? mmio_block->read : mmio_block->write; 3084 if (func) 3085 return func(vgpu, offset, pdata, bytes); 3086 goto default_rw; 3087 } 3088 3089 /* 3090 * Normal tracked MMIOs. 3091 */ 3092 mmio_info = find_mmio_info(gvt, offset); 3093 if (!mmio_info) { 3094 if (!vgpu->mmio.disable_warn_untrack) 3095 gvt_vgpu_err("untracked MMIO %08x len %d\n", 3096 offset, bytes); 3097 goto default_rw; 3098 } 3099 3100 if (is_read) 3101 return mmio_info->read(vgpu, offset, pdata, bytes); 3102 else { 3103 u64 ro_mask = mmio_info->ro_mask; 3104 u32 old_vreg = 0, old_sreg = 0; 3105 u64 data = 0; 3106 3107 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) { 3108 old_vreg = vgpu_vreg(vgpu, offset); 3109 old_sreg = vgpu_sreg(vgpu, offset); 3110 } 3111 3112 if (likely(!ro_mask)) 3113 ret = mmio_info->write(vgpu, offset, pdata, bytes); 3114 else if (!~ro_mask) { 3115 gvt_vgpu_err("try to write RO reg %x\n", offset); 3116 return 0; 3117 } else { 3118 /* keep the RO bits in the virtual register */ 3119 memcpy(&data, pdata, bytes); 3120 data &= ~ro_mask; 3121 data |= vgpu_vreg(vgpu, offset) & ro_mask; 3122 ret = mmio_info->write(vgpu, offset, &data, bytes); 3123 } 3124 3125 /* higher 16bits of mode ctl regs are mask bits for change */ 3126 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) { 3127 u32 mask = vgpu_vreg(vgpu, offset) >> 16; 3128 3129 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask) 3130 | (vgpu_vreg(vgpu, offset) & mask); 3131 vgpu_sreg(vgpu, offset) = (old_sreg & ~mask) 3132 | (vgpu_sreg(vgpu, offset) & mask); 3133 } 3134 } 3135 3136 return ret; 3137 3138 default_rw: 3139 return is_read ? 3140 intel_vgpu_default_mmio_read(vgpu, offset, pdata, bytes) : 3141 intel_vgpu_default_mmio_write(vgpu, offset, pdata, bytes); 3142 } 3143