1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Kevin Tian <kevin.tian@intel.com> 25 * Eddie Dong <eddie.dong@intel.com> 26 * Zhiyuan Lv <zhiyuan.lv@intel.com> 27 * 28 * Contributors: 29 * Min He <min.he@intel.com> 30 * Tina Zhang <tina.zhang@intel.com> 31 * Pei Zhang <pei.zhang@intel.com> 32 * Niu Bing <bing.niu@intel.com> 33 * Ping Gao <ping.a.gao@intel.com> 34 * Zhi Wang <zhi.a.wang@intel.com> 35 * 36 37 */ 38 39 #include "i915_drv.h" 40 #include "gvt.h" 41 #include "i915_pvinfo.h" 42 43 /* XXX FIXME i915 has changed PP_XXX definition */ 44 #define PCH_PP_STATUS _MMIO(0xc7200) 45 #define PCH_PP_CONTROL _MMIO(0xc7204) 46 #define PCH_PP_ON_DELAYS _MMIO(0xc7208) 47 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c) 48 #define PCH_PP_DIVISOR _MMIO(0xc7210) 49 50 /* Register contains RO bits */ 51 #define F_RO (1 << 0) 52 /* Register contains graphics address */ 53 #define F_GMADR (1 << 1) 54 /* Mode mask registers with high 16 bits as the mask bits */ 55 #define F_MODE_MASK (1 << 2) 56 /* This reg can be accessed by GPU commands */ 57 #define F_CMD_ACCESS (1 << 3) 58 /* This reg has been accessed by a VM */ 59 #define F_ACCESSED (1 << 4) 60 /* This reg has been accessed through GPU commands */ 61 #define F_CMD_ACCESSED (1 << 5) 62 /* This reg could be accessed by unaligned address */ 63 #define F_UNALIGN (1 << 6) 64 65 unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt) 66 { 67 if (IS_BROADWELL(gvt->dev_priv)) 68 return D_BDW; 69 else if (IS_SKYLAKE(gvt->dev_priv)) 70 return D_SKL; 71 72 return 0; 73 } 74 75 bool intel_gvt_match_device(struct intel_gvt *gvt, 76 unsigned long device) 77 { 78 return intel_gvt_get_device_type(gvt) & device; 79 } 80 81 static void read_vreg(struct intel_vgpu *vgpu, unsigned int offset, 82 void *p_data, unsigned int bytes) 83 { 84 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); 85 } 86 87 static void write_vreg(struct intel_vgpu *vgpu, unsigned int offset, 88 void *p_data, unsigned int bytes) 89 { 90 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes); 91 } 92 93 static int new_mmio_info(struct intel_gvt *gvt, 94 u32 offset, u32 flags, u32 size, 95 u32 addr_mask, u32 ro_mask, u32 device, 96 int (*read)(struct intel_vgpu *, unsigned int, void *, unsigned int), 97 int (*write)(struct intel_vgpu *, unsigned int, void *, unsigned int)) 98 { 99 struct intel_gvt_mmio_info *info, *p; 100 u32 start, end, i; 101 102 if (!intel_gvt_match_device(gvt, device)) 103 return 0; 104 105 if (WARN_ON(!IS_ALIGNED(offset, 4))) 106 return -EINVAL; 107 108 start = offset; 109 end = offset + size; 110 111 for (i = start; i < end; i += 4) { 112 info = kzalloc(sizeof(*info), GFP_KERNEL); 113 if (!info) 114 return -ENOMEM; 115 116 info->offset = i; 117 p = intel_gvt_find_mmio_info(gvt, info->offset); 118 if (p) 119 gvt_err("dup mmio definition offset %x\n", 120 info->offset); 121 info->size = size; 122 info->length = (i + 4) < end ? 4 : (end - i); 123 info->addr_mask = addr_mask; 124 info->device = device; 125 info->read = read ? read : intel_vgpu_default_mmio_read; 126 info->write = write ? write : intel_vgpu_default_mmio_write; 127 gvt->mmio.mmio_attribute[info->offset / 4] = flags; 128 INIT_HLIST_NODE(&info->node); 129 hash_add(gvt->mmio.mmio_info_table, &info->node, info->offset); 130 } 131 return 0; 132 } 133 134 static int render_mmio_to_ring_id(struct intel_gvt *gvt, unsigned int reg) 135 { 136 enum intel_engine_id id; 137 struct intel_engine_cs *engine; 138 139 reg &= ~GENMASK(11, 0); 140 for_each_engine(engine, gvt->dev_priv, id) { 141 if (engine->mmio_base == reg) 142 return id; 143 } 144 return -1; 145 } 146 147 #define offset_to_fence_num(offset) \ 148 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3) 149 150 #define fence_num_to_offset(num) \ 151 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) 152 153 static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu, 154 unsigned int fence_num, void *p_data, unsigned int bytes) 155 { 156 if (fence_num >= vgpu_fence_sz(vgpu)) { 157 gvt_err("vgpu%d: found oob fence register access\n", 158 vgpu->id); 159 gvt_err("vgpu%d: total fence num %d access fence num %d\n", 160 vgpu->id, vgpu_fence_sz(vgpu), fence_num); 161 memset(p_data, 0, bytes); 162 } 163 return 0; 164 } 165 166 static int fence_mmio_read(struct intel_vgpu *vgpu, unsigned int off, 167 void *p_data, unsigned int bytes) 168 { 169 int ret; 170 171 ret = sanitize_fence_mmio_access(vgpu, offset_to_fence_num(off), 172 p_data, bytes); 173 if (ret) 174 return ret; 175 read_vreg(vgpu, off, p_data, bytes); 176 return 0; 177 } 178 179 static int fence_mmio_write(struct intel_vgpu *vgpu, unsigned int off, 180 void *p_data, unsigned int bytes) 181 { 182 unsigned int fence_num = offset_to_fence_num(off); 183 int ret; 184 185 ret = sanitize_fence_mmio_access(vgpu, fence_num, p_data, bytes); 186 if (ret) 187 return ret; 188 write_vreg(vgpu, off, p_data, bytes); 189 190 intel_vgpu_write_fence(vgpu, fence_num, 191 vgpu_vreg64(vgpu, fence_num_to_offset(fence_num))); 192 return 0; 193 } 194 195 #define CALC_MODE_MASK_REG(old, new) \ 196 (((new) & GENMASK(31, 16)) \ 197 | ((((old) & GENMASK(15, 0)) & ~((new) >> 16)) \ 198 | ((new) & ((new) >> 16)))) 199 200 static int mul_force_wake_write(struct intel_vgpu *vgpu, 201 unsigned int offset, void *p_data, unsigned int bytes) 202 { 203 u32 old, new; 204 uint32_t ack_reg_offset; 205 206 old = vgpu_vreg(vgpu, offset); 207 new = CALC_MODE_MASK_REG(old, *(u32 *)p_data); 208 209 if (IS_SKYLAKE(vgpu->gvt->dev_priv)) { 210 switch (offset) { 211 case FORCEWAKE_RENDER_GEN9_REG: 212 ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG; 213 break; 214 case FORCEWAKE_BLITTER_GEN9_REG: 215 ack_reg_offset = FORCEWAKE_ACK_BLITTER_GEN9_REG; 216 break; 217 case FORCEWAKE_MEDIA_GEN9_REG: 218 ack_reg_offset = FORCEWAKE_ACK_MEDIA_GEN9_REG; 219 break; 220 default: 221 /*should not hit here*/ 222 gvt_err("invalid forcewake offset 0x%x\n", offset); 223 return -EINVAL; 224 } 225 } else { 226 ack_reg_offset = FORCEWAKE_ACK_HSW_REG; 227 } 228 229 vgpu_vreg(vgpu, offset) = new; 230 vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0)); 231 return 0; 232 } 233 234 static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 235 void *p_data, unsigned int bytes) 236 { 237 unsigned int engine_mask = 0; 238 u32 data; 239 240 write_vreg(vgpu, offset, p_data, bytes); 241 data = vgpu_vreg(vgpu, offset); 242 243 if (data & GEN6_GRDOM_FULL) { 244 gvt_dbg_mmio("vgpu%d: request full GPU reset\n", vgpu->id); 245 engine_mask = ALL_ENGINES; 246 } else { 247 if (data & GEN6_GRDOM_RENDER) { 248 gvt_dbg_mmio("vgpu%d: request RCS reset\n", vgpu->id); 249 engine_mask |= (1 << RCS); 250 } 251 if (data & GEN6_GRDOM_MEDIA) { 252 gvt_dbg_mmio("vgpu%d: request VCS reset\n", vgpu->id); 253 engine_mask |= (1 << VCS); 254 } 255 if (data & GEN6_GRDOM_BLT) { 256 gvt_dbg_mmio("vgpu%d: request BCS Reset\n", vgpu->id); 257 engine_mask |= (1 << BCS); 258 } 259 if (data & GEN6_GRDOM_VECS) { 260 gvt_dbg_mmio("vgpu%d: request VECS Reset\n", vgpu->id); 261 engine_mask |= (1 << VECS); 262 } 263 if (data & GEN8_GRDOM_MEDIA2) { 264 gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id); 265 if (HAS_BSD2(vgpu->gvt->dev_priv)) 266 engine_mask |= (1 << VCS2); 267 } 268 } 269 270 intel_gvt_reset_vgpu_locked(vgpu, false, engine_mask); 271 272 return 0; 273 } 274 275 static int gmbus_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 276 void *p_data, unsigned int bytes) 277 { 278 return intel_gvt_i2c_handle_gmbus_read(vgpu, offset, p_data, bytes); 279 } 280 281 static int gmbus_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 282 void *p_data, unsigned int bytes) 283 { 284 return intel_gvt_i2c_handle_gmbus_write(vgpu, offset, p_data, bytes); 285 } 286 287 static int pch_pp_control_mmio_write(struct intel_vgpu *vgpu, 288 unsigned int offset, void *p_data, unsigned int bytes) 289 { 290 write_vreg(vgpu, offset, p_data, bytes); 291 292 if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) { 293 vgpu_vreg(vgpu, PCH_PP_STATUS) |= PP_ON; 294 vgpu_vreg(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE; 295 vgpu_vreg(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN; 296 vgpu_vreg(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE; 297 298 } else 299 vgpu_vreg(vgpu, PCH_PP_STATUS) &= 300 ~(PP_ON | PP_SEQUENCE_POWER_DOWN 301 | PP_CYCLE_DELAY_ACTIVE); 302 return 0; 303 } 304 305 static int transconf_mmio_write(struct intel_vgpu *vgpu, 306 unsigned int offset, void *p_data, unsigned int bytes) 307 { 308 write_vreg(vgpu, offset, p_data, bytes); 309 310 if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE) 311 vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE; 312 else 313 vgpu_vreg(vgpu, offset) &= ~TRANS_STATE_ENABLE; 314 return 0; 315 } 316 317 static int lcpll_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 318 void *p_data, unsigned int bytes) 319 { 320 write_vreg(vgpu, offset, p_data, bytes); 321 322 if (vgpu_vreg(vgpu, offset) & LCPLL_PLL_DISABLE) 323 vgpu_vreg(vgpu, offset) &= ~LCPLL_PLL_LOCK; 324 else 325 vgpu_vreg(vgpu, offset) |= LCPLL_PLL_LOCK; 326 327 if (vgpu_vreg(vgpu, offset) & LCPLL_CD_SOURCE_FCLK) 328 vgpu_vreg(vgpu, offset) |= LCPLL_CD_SOURCE_FCLK_DONE; 329 else 330 vgpu_vreg(vgpu, offset) &= ~LCPLL_CD_SOURCE_FCLK_DONE; 331 332 return 0; 333 } 334 335 static int dpy_reg_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 336 void *p_data, unsigned int bytes) 337 { 338 *(u32 *)p_data = (1 << 17); 339 return 0; 340 } 341 342 static int dpy_reg_mmio_read_2(struct intel_vgpu *vgpu, unsigned int offset, 343 void *p_data, unsigned int bytes) 344 { 345 *(u32 *)p_data = 3; 346 return 0; 347 } 348 349 static int dpy_reg_mmio_read_3(struct intel_vgpu *vgpu, unsigned int offset, 350 void *p_data, unsigned int bytes) 351 { 352 *(u32 *)p_data = (0x2f << 16); 353 return 0; 354 } 355 356 static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 357 void *p_data, unsigned int bytes) 358 { 359 u32 data; 360 361 write_vreg(vgpu, offset, p_data, bytes); 362 data = vgpu_vreg(vgpu, offset); 363 364 if (data & PIPECONF_ENABLE) 365 vgpu_vreg(vgpu, offset) |= I965_PIPECONF_ACTIVE; 366 else 367 vgpu_vreg(vgpu, offset) &= ~I965_PIPECONF_ACTIVE; 368 intel_gvt_check_vblank_emulation(vgpu->gvt); 369 return 0; 370 } 371 372 static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 373 void *p_data, unsigned int bytes) 374 { 375 write_vreg(vgpu, offset, p_data, bytes); 376 377 if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) { 378 vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE; 379 } else { 380 vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE; 381 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E))) 382 vgpu_vreg(vgpu, DP_TP_STATUS(PORT_E)) 383 &= ~DP_TP_STATUS_AUTOTRAIN_DONE; 384 } 385 return 0; 386 } 387 388 static int fdi_rx_iir_mmio_write(struct intel_vgpu *vgpu, 389 unsigned int offset, void *p_data, unsigned int bytes) 390 { 391 vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data; 392 return 0; 393 } 394 395 #define FDI_LINK_TRAIN_PATTERN1 0 396 #define FDI_LINK_TRAIN_PATTERN2 1 397 398 static int fdi_auto_training_started(struct intel_vgpu *vgpu) 399 { 400 u32 ddi_buf_ctl = vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_E)); 401 u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL); 402 u32 tx_ctl = vgpu_vreg(vgpu, DP_TP_CTL(PORT_E)); 403 404 if ((ddi_buf_ctl & DDI_BUF_CTL_ENABLE) && 405 (rx_ctl & FDI_RX_ENABLE) && 406 (rx_ctl & FDI_AUTO_TRAINING) && 407 (tx_ctl & DP_TP_CTL_ENABLE) && 408 (tx_ctl & DP_TP_CTL_FDI_AUTOTRAIN)) 409 return 1; 410 else 411 return 0; 412 } 413 414 static int check_fdi_rx_train_status(struct intel_vgpu *vgpu, 415 enum pipe pipe, unsigned int train_pattern) 416 { 417 i915_reg_t fdi_rx_imr, fdi_tx_ctl, fdi_rx_ctl; 418 unsigned int fdi_rx_check_bits, fdi_tx_check_bits; 419 unsigned int fdi_rx_train_bits, fdi_tx_train_bits; 420 unsigned int fdi_iir_check_bits; 421 422 fdi_rx_imr = FDI_RX_IMR(pipe); 423 fdi_tx_ctl = FDI_TX_CTL(pipe); 424 fdi_rx_ctl = FDI_RX_CTL(pipe); 425 426 if (train_pattern == FDI_LINK_TRAIN_PATTERN1) { 427 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_1_CPT; 428 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_1; 429 fdi_iir_check_bits = FDI_RX_BIT_LOCK; 430 } else if (train_pattern == FDI_LINK_TRAIN_PATTERN2) { 431 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_2_CPT; 432 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_2; 433 fdi_iir_check_bits = FDI_RX_SYMBOL_LOCK; 434 } else { 435 gvt_err("Invalid train pattern %d\n", train_pattern); 436 return -EINVAL; 437 } 438 439 fdi_rx_check_bits = FDI_RX_ENABLE | fdi_rx_train_bits; 440 fdi_tx_check_bits = FDI_TX_ENABLE | fdi_tx_train_bits; 441 442 /* If imr bit has been masked */ 443 if (vgpu_vreg(vgpu, fdi_rx_imr) & fdi_iir_check_bits) 444 return 0; 445 446 if (((vgpu_vreg(vgpu, fdi_tx_ctl) & fdi_tx_check_bits) 447 == fdi_tx_check_bits) 448 && ((vgpu_vreg(vgpu, fdi_rx_ctl) & fdi_rx_check_bits) 449 == fdi_rx_check_bits)) 450 return 1; 451 else 452 return 0; 453 } 454 455 #define INVALID_INDEX (~0U) 456 457 static unsigned int calc_index(unsigned int offset, unsigned int start, 458 unsigned int next, unsigned int end, i915_reg_t i915_end) 459 { 460 unsigned int range = next - start; 461 462 if (!end) 463 end = i915_mmio_reg_offset(i915_end); 464 if (offset < start || offset > end) 465 return INVALID_INDEX; 466 offset -= start; 467 return offset / range; 468 } 469 470 #define FDI_RX_CTL_TO_PIPE(offset) \ 471 calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, 0, FDI_RX_CTL(PIPE_C)) 472 473 #define FDI_TX_CTL_TO_PIPE(offset) \ 474 calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, 0, FDI_TX_CTL(PIPE_C)) 475 476 #define FDI_RX_IMR_TO_PIPE(offset) \ 477 calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, 0, FDI_RX_IMR(PIPE_C)) 478 479 static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu, 480 unsigned int offset, void *p_data, unsigned int bytes) 481 { 482 i915_reg_t fdi_rx_iir; 483 unsigned int index; 484 int ret; 485 486 if (FDI_RX_CTL_TO_PIPE(offset) != INVALID_INDEX) 487 index = FDI_RX_CTL_TO_PIPE(offset); 488 else if (FDI_TX_CTL_TO_PIPE(offset) != INVALID_INDEX) 489 index = FDI_TX_CTL_TO_PIPE(offset); 490 else if (FDI_RX_IMR_TO_PIPE(offset) != INVALID_INDEX) 491 index = FDI_RX_IMR_TO_PIPE(offset); 492 else { 493 gvt_err("Unsupport registers %x\n", offset); 494 return -EINVAL; 495 } 496 497 write_vreg(vgpu, offset, p_data, bytes); 498 499 fdi_rx_iir = FDI_RX_IIR(index); 500 501 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN1); 502 if (ret < 0) 503 return ret; 504 if (ret) 505 vgpu_vreg(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK; 506 507 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN2); 508 if (ret < 0) 509 return ret; 510 if (ret) 511 vgpu_vreg(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK; 512 513 if (offset == _FDI_RXA_CTL) 514 if (fdi_auto_training_started(vgpu)) 515 vgpu_vreg(vgpu, DP_TP_STATUS(PORT_E)) |= 516 DP_TP_STATUS_AUTOTRAIN_DONE; 517 return 0; 518 } 519 520 #define DP_TP_CTL_TO_PORT(offset) \ 521 calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, 0, DP_TP_CTL(PORT_E)) 522 523 static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 524 void *p_data, unsigned int bytes) 525 { 526 i915_reg_t status_reg; 527 unsigned int index; 528 u32 data; 529 530 write_vreg(vgpu, offset, p_data, bytes); 531 532 index = DP_TP_CTL_TO_PORT(offset); 533 data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8; 534 if (data == 0x2) { 535 status_reg = DP_TP_STATUS(index); 536 vgpu_vreg(vgpu, status_reg) |= (1 << 25); 537 } 538 return 0; 539 } 540 541 static int dp_tp_status_mmio_write(struct intel_vgpu *vgpu, 542 unsigned int offset, void *p_data, unsigned int bytes) 543 { 544 u32 reg_val; 545 u32 sticky_mask; 546 547 reg_val = *((u32 *)p_data); 548 sticky_mask = GENMASK(27, 26) | (1 << 24); 549 550 vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) | 551 (vgpu_vreg(vgpu, offset) & sticky_mask); 552 vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask); 553 return 0; 554 } 555 556 static int pch_adpa_mmio_write(struct intel_vgpu *vgpu, 557 unsigned int offset, void *p_data, unsigned int bytes) 558 { 559 u32 data; 560 561 write_vreg(vgpu, offset, p_data, bytes); 562 data = vgpu_vreg(vgpu, offset); 563 564 if (data & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) 565 vgpu_vreg(vgpu, offset) &= ~ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 566 return 0; 567 } 568 569 static int south_chicken2_mmio_write(struct intel_vgpu *vgpu, 570 unsigned int offset, void *p_data, unsigned int bytes) 571 { 572 u32 data; 573 574 write_vreg(vgpu, offset, p_data, bytes); 575 data = vgpu_vreg(vgpu, offset); 576 577 if (data & FDI_MPHY_IOSFSB_RESET_CTL) 578 vgpu_vreg(vgpu, offset) |= FDI_MPHY_IOSFSB_RESET_STATUS; 579 else 580 vgpu_vreg(vgpu, offset) &= ~FDI_MPHY_IOSFSB_RESET_STATUS; 581 return 0; 582 } 583 584 #define DSPSURF_TO_PIPE(offset) \ 585 calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C)) 586 587 static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 588 void *p_data, unsigned int bytes) 589 { 590 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 591 unsigned int index = DSPSURF_TO_PIPE(offset); 592 i915_reg_t surflive_reg = DSPSURFLIVE(index); 593 int flip_event[] = { 594 [PIPE_A] = PRIMARY_A_FLIP_DONE, 595 [PIPE_B] = PRIMARY_B_FLIP_DONE, 596 [PIPE_C] = PRIMARY_C_FLIP_DONE, 597 }; 598 599 write_vreg(vgpu, offset, p_data, bytes); 600 vgpu_vreg(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset); 601 602 set_bit(flip_event[index], vgpu->irq.flip_done_event[index]); 603 return 0; 604 } 605 606 #define SPRSURF_TO_PIPE(offset) \ 607 calc_index(offset, _SPRA_SURF, _SPRB_SURF, 0, SPRSURF(PIPE_C)) 608 609 static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 610 void *p_data, unsigned int bytes) 611 { 612 unsigned int index = SPRSURF_TO_PIPE(offset); 613 i915_reg_t surflive_reg = SPRSURFLIVE(index); 614 int flip_event[] = { 615 [PIPE_A] = SPRITE_A_FLIP_DONE, 616 [PIPE_B] = SPRITE_B_FLIP_DONE, 617 [PIPE_C] = SPRITE_C_FLIP_DONE, 618 }; 619 620 write_vreg(vgpu, offset, p_data, bytes); 621 vgpu_vreg(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset); 622 623 set_bit(flip_event[index], vgpu->irq.flip_done_event[index]); 624 return 0; 625 } 626 627 static int trigger_aux_channel_interrupt(struct intel_vgpu *vgpu, 628 unsigned int reg) 629 { 630 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 631 enum intel_gvt_event_type event; 632 633 if (reg == _DPA_AUX_CH_CTL) 634 event = AUX_CHANNEL_A; 635 else if (reg == _PCH_DPB_AUX_CH_CTL || reg == _DPB_AUX_CH_CTL) 636 event = AUX_CHANNEL_B; 637 else if (reg == _PCH_DPC_AUX_CH_CTL || reg == _DPC_AUX_CH_CTL) 638 event = AUX_CHANNEL_C; 639 else if (reg == _PCH_DPD_AUX_CH_CTL || reg == _DPD_AUX_CH_CTL) 640 event = AUX_CHANNEL_D; 641 else { 642 WARN_ON(true); 643 return -EINVAL; 644 } 645 646 intel_vgpu_trigger_virtual_event(vgpu, event); 647 return 0; 648 } 649 650 static int dp_aux_ch_ctl_trans_done(struct intel_vgpu *vgpu, u32 value, 651 unsigned int reg, int len, bool data_valid) 652 { 653 /* mark transaction done */ 654 value |= DP_AUX_CH_CTL_DONE; 655 value &= ~DP_AUX_CH_CTL_SEND_BUSY; 656 value &= ~DP_AUX_CH_CTL_RECEIVE_ERROR; 657 658 if (data_valid) 659 value &= ~DP_AUX_CH_CTL_TIME_OUT_ERROR; 660 else 661 value |= DP_AUX_CH_CTL_TIME_OUT_ERROR; 662 663 /* message size */ 664 value &= ~(0xf << 20); 665 value |= (len << 20); 666 vgpu_vreg(vgpu, reg) = value; 667 668 if (value & DP_AUX_CH_CTL_INTERRUPT) 669 return trigger_aux_channel_interrupt(vgpu, reg); 670 return 0; 671 } 672 673 static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd, 674 uint8_t t) 675 { 676 if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == DPCD_TRAINING_PATTERN_1) { 677 /* training pattern 1 for CR */ 678 /* set LANE0_CR_DONE, LANE1_CR_DONE */ 679 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_CR_DONE; 680 /* set LANE2_CR_DONE, LANE3_CR_DONE */ 681 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_CR_DONE; 682 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == 683 DPCD_TRAINING_PATTERN_2) { 684 /* training pattern 2 for EQ */ 685 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane0_1 */ 686 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_EQ_DONE; 687 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_SYMBOL_LOCKED; 688 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane2_3 */ 689 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_EQ_DONE; 690 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_SYMBOL_LOCKED; 691 /* set INTERLANE_ALIGN_DONE */ 692 dpcd->data[DPCD_LANE_ALIGN_STATUS_UPDATED] |= 693 DPCD_INTERLANE_ALIGN_DONE; 694 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == 695 DPCD_LINK_TRAINING_DISABLED) { 696 /* finish link training */ 697 /* set sink status as synchronized */ 698 dpcd->data[DPCD_SINK_STATUS] = DPCD_SINK_IN_SYNC; 699 } 700 } 701 702 #define _REG_HSW_DP_AUX_CH_CTL(dp) \ 703 ((dp) ? (_PCH_DPB_AUX_CH_CTL + ((dp)-1)*0x100) : 0x64010) 704 705 #define _REG_SKL_DP_AUX_CH_CTL(dp) (0x64010 + (dp) * 0x100) 706 707 #define OFFSET_TO_DP_AUX_PORT(offset) (((offset) & 0xF00) >> 8) 708 709 #define dpy_is_valid_port(port) \ 710 (((port) >= PORT_A) && ((port) < I915_MAX_PORTS)) 711 712 static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu, 713 unsigned int offset, void *p_data, unsigned int bytes) 714 { 715 struct intel_vgpu_display *display = &vgpu->display; 716 int msg, addr, ctrl, op, len; 717 int port_index = OFFSET_TO_DP_AUX_PORT(offset); 718 struct intel_vgpu_dpcd_data *dpcd = NULL; 719 struct intel_vgpu_port *port = NULL; 720 u32 data; 721 722 if (!dpy_is_valid_port(port_index)) { 723 gvt_err("GVT(%d): Unsupported DP port access!\n", vgpu->id); 724 return 0; 725 } 726 727 write_vreg(vgpu, offset, p_data, bytes); 728 data = vgpu_vreg(vgpu, offset); 729 730 if (IS_SKYLAKE(vgpu->gvt->dev_priv) && 731 offset != _REG_SKL_DP_AUX_CH_CTL(port_index)) { 732 /* SKL DPB/C/D aux ctl register changed */ 733 return 0; 734 } else if (IS_BROADWELL(vgpu->gvt->dev_priv) && 735 offset != _REG_HSW_DP_AUX_CH_CTL(port_index)) { 736 /* write to the data registers */ 737 return 0; 738 } 739 740 if (!(data & DP_AUX_CH_CTL_SEND_BUSY)) { 741 /* just want to clear the sticky bits */ 742 vgpu_vreg(vgpu, offset) = 0; 743 return 0; 744 } 745 746 port = &display->ports[port_index]; 747 dpcd = port->dpcd; 748 749 /* read out message from DATA1 register */ 750 msg = vgpu_vreg(vgpu, offset + 4); 751 addr = (msg >> 8) & 0xffff; 752 ctrl = (msg >> 24) & 0xff; 753 len = msg & 0xff; 754 op = ctrl >> 4; 755 756 if (op == GVT_AUX_NATIVE_WRITE) { 757 int t; 758 uint8_t buf[16]; 759 760 if ((addr + len + 1) >= DPCD_SIZE) { 761 /* 762 * Write request exceeds what we supported, 763 * DCPD spec: When a Source Device is writing a DPCD 764 * address not supported by the Sink Device, the Sink 765 * Device shall reply with AUX NACK and “M” equal to 766 * zero. 767 */ 768 769 /* NAK the write */ 770 vgpu_vreg(vgpu, offset + 4) = AUX_NATIVE_REPLY_NAK; 771 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 2, true); 772 return 0; 773 } 774 775 /* 776 * Write request format: (command + address) occupies 777 * 3 bytes, followed by (len + 1) bytes of data. 778 */ 779 if (WARN_ON((len + 4) > AUX_BURST_SIZE)) 780 return -EINVAL; 781 782 /* unpack data from vreg to buf */ 783 for (t = 0; t < 4; t++) { 784 u32 r = vgpu_vreg(vgpu, offset + 8 + t * 4); 785 786 buf[t * 4] = (r >> 24) & 0xff; 787 buf[t * 4 + 1] = (r >> 16) & 0xff; 788 buf[t * 4 + 2] = (r >> 8) & 0xff; 789 buf[t * 4 + 3] = r & 0xff; 790 } 791 792 /* write to virtual DPCD */ 793 if (dpcd && dpcd->data_valid) { 794 for (t = 0; t <= len; t++) { 795 int p = addr + t; 796 797 dpcd->data[p] = buf[t]; 798 /* check for link training */ 799 if (p == DPCD_TRAINING_PATTERN_SET) 800 dp_aux_ch_ctl_link_training(dpcd, 801 buf[t]); 802 } 803 } 804 805 /* ACK the write */ 806 vgpu_vreg(vgpu, offset + 4) = 0; 807 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 1, 808 dpcd && dpcd->data_valid); 809 return 0; 810 } 811 812 if (op == GVT_AUX_NATIVE_READ) { 813 int idx, i, ret = 0; 814 815 if ((addr + len + 1) >= DPCD_SIZE) { 816 /* 817 * read request exceeds what we supported 818 * DPCD spec: A Sink Device receiving a Native AUX CH 819 * read request for an unsupported DPCD address must 820 * reply with an AUX ACK and read data set equal to 821 * zero instead of replying with AUX NACK. 822 */ 823 824 /* ACK the READ*/ 825 vgpu_vreg(vgpu, offset + 4) = 0; 826 vgpu_vreg(vgpu, offset + 8) = 0; 827 vgpu_vreg(vgpu, offset + 12) = 0; 828 vgpu_vreg(vgpu, offset + 16) = 0; 829 vgpu_vreg(vgpu, offset + 20) = 0; 830 831 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2, 832 true); 833 return 0; 834 } 835 836 for (idx = 1; idx <= 5; idx++) { 837 /* clear the data registers */ 838 vgpu_vreg(vgpu, offset + 4 * idx) = 0; 839 } 840 841 /* 842 * Read reply format: ACK (1 byte) plus (len + 1) bytes of data. 843 */ 844 if (WARN_ON((len + 2) > AUX_BURST_SIZE)) 845 return -EINVAL; 846 847 /* read from virtual DPCD to vreg */ 848 /* first 4 bytes: [ACK][addr][addr+1][addr+2] */ 849 if (dpcd && dpcd->data_valid) { 850 for (i = 1; i <= (len + 1); i++) { 851 int t; 852 853 t = dpcd->data[addr + i - 1]; 854 t <<= (24 - 8 * (i % 4)); 855 ret |= t; 856 857 if ((i % 4 == 3) || (i == (len + 1))) { 858 vgpu_vreg(vgpu, offset + 859 (i / 4 + 1) * 4) = ret; 860 ret = 0; 861 } 862 } 863 } 864 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2, 865 dpcd && dpcd->data_valid); 866 return 0; 867 } 868 869 /* i2c transaction starts */ 870 intel_gvt_i2c_handle_aux_ch_write(vgpu, port_index, offset, p_data); 871 872 if (data & DP_AUX_CH_CTL_INTERRUPT) 873 trigger_aux_channel_interrupt(vgpu, offset); 874 return 0; 875 } 876 877 static int vga_control_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 878 void *p_data, unsigned int bytes) 879 { 880 bool vga_disable; 881 882 write_vreg(vgpu, offset, p_data, bytes); 883 vga_disable = vgpu_vreg(vgpu, offset) & VGA_DISP_DISABLE; 884 885 gvt_dbg_core("vgpu%d: %s VGA mode\n", vgpu->id, 886 vga_disable ? "Disable" : "Enable"); 887 return 0; 888 } 889 890 static u32 read_virtual_sbi_register(struct intel_vgpu *vgpu, 891 unsigned int sbi_offset) 892 { 893 struct intel_vgpu_display *display = &vgpu->display; 894 int num = display->sbi.number; 895 int i; 896 897 for (i = 0; i < num; ++i) 898 if (display->sbi.registers[i].offset == sbi_offset) 899 break; 900 901 if (i == num) 902 return 0; 903 904 return display->sbi.registers[i].value; 905 } 906 907 static void write_virtual_sbi_register(struct intel_vgpu *vgpu, 908 unsigned int offset, u32 value) 909 { 910 struct intel_vgpu_display *display = &vgpu->display; 911 int num = display->sbi.number; 912 int i; 913 914 for (i = 0; i < num; ++i) { 915 if (display->sbi.registers[i].offset == offset) 916 break; 917 } 918 919 if (i == num) { 920 if (num == SBI_REG_MAX) { 921 gvt_err("vgpu%d: SBI caching meets maximum limits\n", 922 vgpu->id); 923 return; 924 } 925 display->sbi.number++; 926 } 927 928 display->sbi.registers[i].offset = offset; 929 display->sbi.registers[i].value = value; 930 } 931 932 static int sbi_data_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 933 void *p_data, unsigned int bytes) 934 { 935 if (((vgpu_vreg(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> 936 SBI_OPCODE_SHIFT) == SBI_CMD_CRRD) { 937 unsigned int sbi_offset = (vgpu_vreg(vgpu, SBI_ADDR) & 938 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; 939 vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu, 940 sbi_offset); 941 } 942 read_vreg(vgpu, offset, p_data, bytes); 943 return 0; 944 } 945 946 static int sbi_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 947 void *p_data, unsigned int bytes) 948 { 949 u32 data; 950 951 write_vreg(vgpu, offset, p_data, bytes); 952 data = vgpu_vreg(vgpu, offset); 953 954 data &= ~(SBI_STAT_MASK << SBI_STAT_SHIFT); 955 data |= SBI_READY; 956 957 data &= ~(SBI_RESPONSE_MASK << SBI_RESPONSE_SHIFT); 958 data |= SBI_RESPONSE_SUCCESS; 959 960 vgpu_vreg(vgpu, offset) = data; 961 962 if (((vgpu_vreg(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> 963 SBI_OPCODE_SHIFT) == SBI_CMD_CRWR) { 964 unsigned int sbi_offset = (vgpu_vreg(vgpu, SBI_ADDR) & 965 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; 966 967 write_virtual_sbi_register(vgpu, sbi_offset, 968 vgpu_vreg(vgpu, SBI_DATA)); 969 } 970 return 0; 971 } 972 973 #define _vgtif_reg(x) \ 974 (VGT_PVINFO_PAGE + offsetof(struct vgt_if, x)) 975 976 static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 977 void *p_data, unsigned int bytes) 978 { 979 bool invalid_read = false; 980 981 read_vreg(vgpu, offset, p_data, bytes); 982 983 switch (offset) { 984 case _vgtif_reg(magic) ... _vgtif_reg(vgt_id): 985 if (offset + bytes > _vgtif_reg(vgt_id) + 4) 986 invalid_read = true; 987 break; 988 case _vgtif_reg(avail_rs.mappable_gmadr.base) ... 989 _vgtif_reg(avail_rs.fence_num): 990 if (offset + bytes > 991 _vgtif_reg(avail_rs.fence_num) + 4) 992 invalid_read = true; 993 break; 994 case 0x78010: /* vgt_caps */ 995 case 0x7881c: 996 break; 997 default: 998 invalid_read = true; 999 break; 1000 } 1001 if (invalid_read) 1002 gvt_err("invalid pvinfo read: [%x:%x] = %x\n", 1003 offset, bytes, *(u32 *)p_data); 1004 return 0; 1005 } 1006 1007 static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification) 1008 { 1009 int ret = 0; 1010 1011 switch (notification) { 1012 case VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE: 1013 ret = intel_vgpu_g2v_create_ppgtt_mm(vgpu, 3); 1014 break; 1015 case VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY: 1016 ret = intel_vgpu_g2v_destroy_ppgtt_mm(vgpu, 3); 1017 break; 1018 case VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE: 1019 ret = intel_vgpu_g2v_create_ppgtt_mm(vgpu, 4); 1020 break; 1021 case VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY: 1022 ret = intel_vgpu_g2v_destroy_ppgtt_mm(vgpu, 4); 1023 break; 1024 case VGT_G2V_EXECLIST_CONTEXT_CREATE: 1025 case VGT_G2V_EXECLIST_CONTEXT_DESTROY: 1026 case 1: /* Remove this in guest driver. */ 1027 break; 1028 default: 1029 gvt_err("Invalid PV notification %d\n", notification); 1030 } 1031 return ret; 1032 } 1033 1034 static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready) 1035 { 1036 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1037 struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj; 1038 char *env[3] = {NULL, NULL, NULL}; 1039 char vmid_str[20]; 1040 char display_ready_str[20]; 1041 1042 snprintf(display_ready_str, 20, "GVT_DISPLAY_READY=%d\n", ready); 1043 env[0] = display_ready_str; 1044 1045 snprintf(vmid_str, 20, "VMID=%d", vgpu->id); 1046 env[1] = vmid_str; 1047 1048 return kobject_uevent_env(kobj, KOBJ_ADD, env); 1049 } 1050 1051 static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1052 void *p_data, unsigned int bytes) 1053 { 1054 u32 data; 1055 int ret; 1056 1057 write_vreg(vgpu, offset, p_data, bytes); 1058 data = vgpu_vreg(vgpu, offset); 1059 1060 switch (offset) { 1061 case _vgtif_reg(display_ready): 1062 send_display_ready_uevent(vgpu, data ? 1 : 0); 1063 break; 1064 case _vgtif_reg(g2v_notify): 1065 ret = handle_g2v_notification(vgpu, data); 1066 break; 1067 /* add xhot and yhot to handled list to avoid error log */ 1068 case 0x78830: 1069 case 0x78834: 1070 case _vgtif_reg(pdp[0].lo): 1071 case _vgtif_reg(pdp[0].hi): 1072 case _vgtif_reg(pdp[1].lo): 1073 case _vgtif_reg(pdp[1].hi): 1074 case _vgtif_reg(pdp[2].lo): 1075 case _vgtif_reg(pdp[2].hi): 1076 case _vgtif_reg(pdp[3].lo): 1077 case _vgtif_reg(pdp[3].hi): 1078 case _vgtif_reg(execlist_context_descriptor_lo): 1079 case _vgtif_reg(execlist_context_descriptor_hi): 1080 break; 1081 default: 1082 gvt_err("invalid pvinfo write offset %x bytes %x data %x\n", 1083 offset, bytes, data); 1084 break; 1085 } 1086 return 0; 1087 } 1088 1089 static int pf_write(struct intel_vgpu *vgpu, 1090 unsigned int offset, void *p_data, unsigned int bytes) 1091 { 1092 u32 val = *(u32 *)p_data; 1093 1094 if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL || 1095 offset == _PS_1B_CTRL || offset == _PS_2B_CTRL || 1096 offset == _PS_1C_CTRL) && (val & PS_PLANE_SEL_MASK) != 0) { 1097 WARN_ONCE(true, "VM(%d): guest is trying to scaling a plane\n", 1098 vgpu->id); 1099 return 0; 1100 } 1101 1102 return intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes); 1103 } 1104 1105 static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu, 1106 unsigned int offset, void *p_data, unsigned int bytes) 1107 { 1108 write_vreg(vgpu, offset, p_data, bytes); 1109 1110 if (vgpu_vreg(vgpu, offset) & HSW_PWR_WELL_ENABLE_REQUEST) 1111 vgpu_vreg(vgpu, offset) |= HSW_PWR_WELL_STATE_ENABLED; 1112 else 1113 vgpu_vreg(vgpu, offset) &= ~HSW_PWR_WELL_STATE_ENABLED; 1114 return 0; 1115 } 1116 1117 static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu, 1118 unsigned int offset, void *p_data, unsigned int bytes) 1119 { 1120 write_vreg(vgpu, offset, p_data, bytes); 1121 1122 if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM) 1123 vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM; 1124 return 0; 1125 } 1126 1127 static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset, 1128 void *p_data, unsigned int bytes) 1129 { 1130 u32 mode; 1131 1132 write_vreg(vgpu, offset, p_data, bytes); 1133 mode = vgpu_vreg(vgpu, offset); 1134 1135 if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) { 1136 WARN_ONCE(1, "VM(%d): iGVT-g doesn't supporte GuC\n", 1137 vgpu->id); 1138 return 0; 1139 } 1140 1141 return 0; 1142 } 1143 1144 static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset, 1145 void *p_data, unsigned int bytes) 1146 { 1147 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1148 u32 trtte = *(u32 *)p_data; 1149 1150 if ((trtte & 1) && (trtte & (1 << 1)) == 0) { 1151 WARN(1, "VM(%d): Use physical address for TRTT!\n", 1152 vgpu->id); 1153 return -EINVAL; 1154 } 1155 write_vreg(vgpu, offset, p_data, bytes); 1156 /* TRTTE is not per-context */ 1157 I915_WRITE(_MMIO(offset), vgpu_vreg(vgpu, offset)); 1158 1159 return 0; 1160 } 1161 1162 static int gen9_trtt_chicken_write(struct intel_vgpu *vgpu, unsigned int offset, 1163 void *p_data, unsigned int bytes) 1164 { 1165 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1166 u32 val = *(u32 *)p_data; 1167 1168 if (val & 1) { 1169 /* unblock hw logic */ 1170 I915_WRITE(_MMIO(offset), val); 1171 } 1172 write_vreg(vgpu, offset, p_data, bytes); 1173 return 0; 1174 } 1175 1176 static int dpll_status_read(struct intel_vgpu *vgpu, unsigned int offset, 1177 void *p_data, unsigned int bytes) 1178 { 1179 u32 v = 0; 1180 1181 if (vgpu_vreg(vgpu, 0x46010) & (1 << 31)) 1182 v |= (1 << 0); 1183 1184 if (vgpu_vreg(vgpu, 0x46014) & (1 << 31)) 1185 v |= (1 << 8); 1186 1187 if (vgpu_vreg(vgpu, 0x46040) & (1 << 31)) 1188 v |= (1 << 16); 1189 1190 if (vgpu_vreg(vgpu, 0x46060) & (1 << 31)) 1191 v |= (1 << 24); 1192 1193 vgpu_vreg(vgpu, offset) = v; 1194 1195 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1196 } 1197 1198 static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset, 1199 void *p_data, unsigned int bytes) 1200 { 1201 u32 value = *(u32 *)p_data; 1202 u32 cmd = value & 0xff; 1203 u32 *data0 = &vgpu_vreg(vgpu, GEN6_PCODE_DATA); 1204 1205 switch (cmd) { 1206 case 0x6: 1207 /** 1208 * "Read memory latency" command on gen9. 1209 * Below memory latency values are read 1210 * from skylake platform. 1211 */ 1212 if (!*data0) 1213 *data0 = 0x1e1a1100; 1214 else 1215 *data0 = 0x61514b3d; 1216 break; 1217 case 0x5: 1218 *data0 |= 0x1; 1219 break; 1220 } 1221 1222 gvt_dbg_core("VM(%d) write %x to mailbox, return data0 %x\n", 1223 vgpu->id, value, *data0); 1224 1225 value &= ~(1 << 31); 1226 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes); 1227 } 1228 1229 static int skl_power_well_ctl_write(struct intel_vgpu *vgpu, 1230 unsigned int offset, void *p_data, unsigned int bytes) 1231 { 1232 u32 v = *(u32 *)p_data; 1233 1234 v &= (1 << 31) | (1 << 29) | (1 << 9) | 1235 (1 << 7) | (1 << 5) | (1 << 3) | (1 << 1); 1236 v |= (v >> 1); 1237 1238 return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes); 1239 } 1240 1241 static int skl_misc_ctl_write(struct intel_vgpu *vgpu, unsigned int offset, 1242 void *p_data, unsigned int bytes) 1243 { 1244 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1245 i915_reg_t reg = {.reg = offset}; 1246 1247 switch (offset) { 1248 case 0x4ddc: 1249 vgpu_vreg(vgpu, offset) = 0x8000003c; 1250 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl */ 1251 I915_WRITE(reg, vgpu_vreg(vgpu, offset)); 1252 break; 1253 case 0x42080: 1254 vgpu_vreg(vgpu, offset) = 0x8000; 1255 /* WaCompressedResourceDisplayNewHashMode:skl */ 1256 I915_WRITE(reg, vgpu_vreg(vgpu, offset)); 1257 break; 1258 default: 1259 return -EINVAL; 1260 } 1261 1262 return 0; 1263 } 1264 1265 static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset, 1266 void *p_data, unsigned int bytes) 1267 { 1268 u32 v = *(u32 *)p_data; 1269 1270 /* other bits are MBZ. */ 1271 v &= (1 << 31) | (1 << 30); 1272 v & (1 << 31) ? (v |= (1 << 30)) : (v &= ~(1 << 30)); 1273 1274 vgpu_vreg(vgpu, offset) = v; 1275 1276 return 0; 1277 } 1278 1279 static int ring_timestamp_mmio_read(struct intel_vgpu *vgpu, 1280 unsigned int offset, void *p_data, unsigned int bytes) 1281 { 1282 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1283 1284 vgpu_vreg(vgpu, offset) = I915_READ(_MMIO(offset)); 1285 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1286 } 1287 1288 static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1289 void *p_data, unsigned int bytes) 1290 { 1291 int ring_id = render_mmio_to_ring_id(vgpu->gvt, offset); 1292 struct intel_vgpu_execlist *execlist; 1293 u32 data = *(u32 *)p_data; 1294 int ret = 0; 1295 1296 if (WARN_ON(ring_id < 0 || ring_id > I915_NUM_ENGINES - 1)) 1297 return -EINVAL; 1298 1299 execlist = &vgpu->execlist[ring_id]; 1300 1301 execlist->elsp_dwords.data[execlist->elsp_dwords.index] = data; 1302 if (execlist->elsp_dwords.index == 3) { 1303 ret = intel_vgpu_submit_execlist(vgpu, ring_id); 1304 if(ret) 1305 gvt_err("fail submit workload on ring %d\n", ring_id); 1306 } 1307 1308 ++execlist->elsp_dwords.index; 1309 execlist->elsp_dwords.index &= 0x3; 1310 return ret; 1311 } 1312 1313 static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1314 void *p_data, unsigned int bytes) 1315 { 1316 u32 data = *(u32 *)p_data; 1317 int ring_id = render_mmio_to_ring_id(vgpu->gvt, offset); 1318 bool enable_execlist; 1319 1320 write_vreg(vgpu, offset, p_data, bytes); 1321 if ((data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)) 1322 || (data & _MASKED_BIT_DISABLE(GFX_RUN_LIST_ENABLE))) { 1323 enable_execlist = !!(data & GFX_RUN_LIST_ENABLE); 1324 1325 gvt_dbg_core("EXECLIST %s on ring %d\n", 1326 (enable_execlist ? "enabling" : "disabling"), 1327 ring_id); 1328 1329 if (enable_execlist) 1330 intel_vgpu_start_schedule(vgpu); 1331 } 1332 return 0; 1333 } 1334 1335 static int gvt_reg_tlb_control_handler(struct intel_vgpu *vgpu, 1336 unsigned int offset, void *p_data, unsigned int bytes) 1337 { 1338 unsigned int id = 0; 1339 1340 write_vreg(vgpu, offset, p_data, bytes); 1341 vgpu_vreg(vgpu, offset) = 0; 1342 1343 switch (offset) { 1344 case 0x4260: 1345 id = RCS; 1346 break; 1347 case 0x4264: 1348 id = VCS; 1349 break; 1350 case 0x4268: 1351 id = VCS2; 1352 break; 1353 case 0x426c: 1354 id = BCS; 1355 break; 1356 case 0x4270: 1357 id = VECS; 1358 break; 1359 default: 1360 return -EINVAL; 1361 } 1362 set_bit(id, (void *)vgpu->tlb_handle_pending); 1363 1364 return 0; 1365 } 1366 1367 static int ring_reset_ctl_write(struct intel_vgpu *vgpu, 1368 unsigned int offset, void *p_data, unsigned int bytes) 1369 { 1370 u32 data; 1371 1372 write_vreg(vgpu, offset, p_data, bytes); 1373 data = vgpu_vreg(vgpu, offset); 1374 1375 if (data & _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET)) 1376 data |= RESET_CTL_READY_TO_RESET; 1377 else if (data & _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET)) 1378 data &= ~RESET_CTL_READY_TO_RESET; 1379 1380 vgpu_vreg(vgpu, offset) = data; 1381 return 0; 1382 } 1383 1384 #define MMIO_F(reg, s, f, am, rm, d, r, w) do { \ 1385 ret = new_mmio_info(gvt, INTEL_GVT_MMIO_OFFSET(reg), \ 1386 f, s, am, rm, d, r, w); \ 1387 if (ret) \ 1388 return ret; \ 1389 } while (0) 1390 1391 #define MMIO_D(reg, d) \ 1392 MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL) 1393 1394 #define MMIO_DH(reg, d, r, w) \ 1395 MMIO_F(reg, 4, 0, 0, 0, d, r, w) 1396 1397 #define MMIO_DFH(reg, d, f, r, w) \ 1398 MMIO_F(reg, 4, f, 0, 0, d, r, w) 1399 1400 #define MMIO_GM(reg, d, r, w) \ 1401 MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w) 1402 1403 #define MMIO_RO(reg, d, f, rm, r, w) \ 1404 MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w) 1405 1406 #define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \ 1407 MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \ 1408 MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \ 1409 MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \ 1410 MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \ 1411 } while (0) 1412 1413 #define MMIO_RING_D(prefix, d) \ 1414 MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL) 1415 1416 #define MMIO_RING_DFH(prefix, d, f, r, w) \ 1417 MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w) 1418 1419 #define MMIO_RING_GM(prefix, d, r, w) \ 1420 MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w) 1421 1422 #define MMIO_RING_RO(prefix, d, f, rm, r, w) \ 1423 MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w) 1424 1425 static int init_generic_mmio_info(struct intel_gvt *gvt) 1426 { 1427 struct drm_i915_private *dev_priv = gvt->dev_priv; 1428 int ret; 1429 1430 MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler); 1431 1432 MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler); 1433 MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler); 1434 MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler); 1435 MMIO_D(SDEISR, D_ALL); 1436 1437 MMIO_RING_D(RING_HWSTAM, D_ALL); 1438 1439 MMIO_GM(RENDER_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1440 MMIO_GM(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1441 MMIO_GM(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1442 MMIO_GM(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1443 1444 #define RING_REG(base) (base + 0x28) 1445 MMIO_RING_D(RING_REG, D_ALL); 1446 #undef RING_REG 1447 1448 #define RING_REG(base) (base + 0x134) 1449 MMIO_RING_D(RING_REG, D_ALL); 1450 #undef RING_REG 1451 1452 MMIO_GM(0x2148, D_ALL, NULL, NULL); 1453 MMIO_GM(CCID, D_ALL, NULL, NULL); 1454 MMIO_GM(0x12198, D_ALL, NULL, NULL); 1455 MMIO_D(GEN7_CXT_SIZE, D_ALL); 1456 1457 MMIO_RING_D(RING_TAIL, D_ALL); 1458 MMIO_RING_D(RING_HEAD, D_ALL); 1459 MMIO_RING_D(RING_CTL, D_ALL); 1460 MMIO_RING_D(RING_ACTHD, D_ALL); 1461 MMIO_RING_GM(RING_START, D_ALL, NULL, NULL); 1462 1463 /* RING MODE */ 1464 #define RING_REG(base) (base + 0x29c) 1465 MMIO_RING_DFH(RING_REG, D_ALL, F_MODE_MASK, NULL, ring_mode_mmio_write); 1466 #undef RING_REG 1467 1468 MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK, NULL, NULL); 1469 MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK, NULL, NULL); 1470 MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS, 1471 ring_timestamp_mmio_read, NULL); 1472 MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS, 1473 ring_timestamp_mmio_read, NULL); 1474 1475 MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK, NULL, NULL); 1476 MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK, NULL, NULL); 1477 MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1478 1479 MMIO_DFH(0x20dc, D_ALL, F_MODE_MASK, NULL, NULL); 1480 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK, NULL, NULL); 1481 MMIO_DFH(0x2088, D_ALL, F_MODE_MASK, NULL, NULL); 1482 MMIO_DFH(0x20e4, D_ALL, F_MODE_MASK, NULL, NULL); 1483 MMIO_DFH(0x2470, D_ALL, F_MODE_MASK, NULL, NULL); 1484 MMIO_D(GAM_ECOCHK, D_ALL); 1485 MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK, NULL, NULL); 1486 MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1487 MMIO_D(0x9030, D_ALL); 1488 MMIO_D(0x20a0, D_ALL); 1489 MMIO_D(0x2420, D_ALL); 1490 MMIO_D(0x2430, D_ALL); 1491 MMIO_D(0x2434, D_ALL); 1492 MMIO_D(0x2438, D_ALL); 1493 MMIO_D(0x243c, D_ALL); 1494 MMIO_DFH(0x7018, D_ALL, F_MODE_MASK, NULL, NULL); 1495 MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1496 MMIO_DFH(0xe100, D_ALL, F_MODE_MASK, NULL, NULL); 1497 1498 /* display */ 1499 MMIO_F(0x60220, 0x20, 0, 0, 0, D_ALL, NULL, NULL); 1500 MMIO_D(0x602a0, D_ALL); 1501 1502 MMIO_D(0x65050, D_ALL); 1503 MMIO_D(0x650b4, D_ALL); 1504 1505 MMIO_D(0xc4040, D_ALL); 1506 MMIO_D(DERRMR, D_ALL); 1507 1508 MMIO_D(PIPEDSL(PIPE_A), D_ALL); 1509 MMIO_D(PIPEDSL(PIPE_B), D_ALL); 1510 MMIO_D(PIPEDSL(PIPE_C), D_ALL); 1511 MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL); 1512 1513 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write); 1514 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write); 1515 MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write); 1516 MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write); 1517 1518 MMIO_D(PIPESTAT(PIPE_A), D_ALL); 1519 MMIO_D(PIPESTAT(PIPE_B), D_ALL); 1520 MMIO_D(PIPESTAT(PIPE_C), D_ALL); 1521 MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL); 1522 1523 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL); 1524 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL); 1525 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL); 1526 MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL); 1527 1528 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL); 1529 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL); 1530 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL); 1531 MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL); 1532 1533 MMIO_D(CURCNTR(PIPE_A), D_ALL); 1534 MMIO_D(CURCNTR(PIPE_B), D_ALL); 1535 MMIO_D(CURCNTR(PIPE_C), D_ALL); 1536 1537 MMIO_D(CURPOS(PIPE_A), D_ALL); 1538 MMIO_D(CURPOS(PIPE_B), D_ALL); 1539 MMIO_D(CURPOS(PIPE_C), D_ALL); 1540 1541 MMIO_D(CURBASE(PIPE_A), D_ALL); 1542 MMIO_D(CURBASE(PIPE_B), D_ALL); 1543 MMIO_D(CURBASE(PIPE_C), D_ALL); 1544 1545 MMIO_D(0x700ac, D_ALL); 1546 MMIO_D(0x710ac, D_ALL); 1547 MMIO_D(0x720ac, D_ALL); 1548 1549 MMIO_D(0x70090, D_ALL); 1550 MMIO_D(0x70094, D_ALL); 1551 MMIO_D(0x70098, D_ALL); 1552 MMIO_D(0x7009c, D_ALL); 1553 1554 MMIO_D(DSPCNTR(PIPE_A), D_ALL); 1555 MMIO_D(DSPADDR(PIPE_A), D_ALL); 1556 MMIO_D(DSPSTRIDE(PIPE_A), D_ALL); 1557 MMIO_D(DSPPOS(PIPE_A), D_ALL); 1558 MMIO_D(DSPSIZE(PIPE_A), D_ALL); 1559 MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write); 1560 MMIO_D(DSPOFFSET(PIPE_A), D_ALL); 1561 MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL); 1562 1563 MMIO_D(DSPCNTR(PIPE_B), D_ALL); 1564 MMIO_D(DSPADDR(PIPE_B), D_ALL); 1565 MMIO_D(DSPSTRIDE(PIPE_B), D_ALL); 1566 MMIO_D(DSPPOS(PIPE_B), D_ALL); 1567 MMIO_D(DSPSIZE(PIPE_B), D_ALL); 1568 MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write); 1569 MMIO_D(DSPOFFSET(PIPE_B), D_ALL); 1570 MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL); 1571 1572 MMIO_D(DSPCNTR(PIPE_C), D_ALL); 1573 MMIO_D(DSPADDR(PIPE_C), D_ALL); 1574 MMIO_D(DSPSTRIDE(PIPE_C), D_ALL); 1575 MMIO_D(DSPPOS(PIPE_C), D_ALL); 1576 MMIO_D(DSPSIZE(PIPE_C), D_ALL); 1577 MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write); 1578 MMIO_D(DSPOFFSET(PIPE_C), D_ALL); 1579 MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL); 1580 1581 MMIO_D(SPRCTL(PIPE_A), D_ALL); 1582 MMIO_D(SPRLINOFF(PIPE_A), D_ALL); 1583 MMIO_D(SPRSTRIDE(PIPE_A), D_ALL); 1584 MMIO_D(SPRPOS(PIPE_A), D_ALL); 1585 MMIO_D(SPRSIZE(PIPE_A), D_ALL); 1586 MMIO_D(SPRKEYVAL(PIPE_A), D_ALL); 1587 MMIO_D(SPRKEYMSK(PIPE_A), D_ALL); 1588 MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write); 1589 MMIO_D(SPRKEYMAX(PIPE_A), D_ALL); 1590 MMIO_D(SPROFFSET(PIPE_A), D_ALL); 1591 MMIO_D(SPRSCALE(PIPE_A), D_ALL); 1592 MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL); 1593 1594 MMIO_D(SPRCTL(PIPE_B), D_ALL); 1595 MMIO_D(SPRLINOFF(PIPE_B), D_ALL); 1596 MMIO_D(SPRSTRIDE(PIPE_B), D_ALL); 1597 MMIO_D(SPRPOS(PIPE_B), D_ALL); 1598 MMIO_D(SPRSIZE(PIPE_B), D_ALL); 1599 MMIO_D(SPRKEYVAL(PIPE_B), D_ALL); 1600 MMIO_D(SPRKEYMSK(PIPE_B), D_ALL); 1601 MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write); 1602 MMIO_D(SPRKEYMAX(PIPE_B), D_ALL); 1603 MMIO_D(SPROFFSET(PIPE_B), D_ALL); 1604 MMIO_D(SPRSCALE(PIPE_B), D_ALL); 1605 MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL); 1606 1607 MMIO_D(SPRCTL(PIPE_C), D_ALL); 1608 MMIO_D(SPRLINOFF(PIPE_C), D_ALL); 1609 MMIO_D(SPRSTRIDE(PIPE_C), D_ALL); 1610 MMIO_D(SPRPOS(PIPE_C), D_ALL); 1611 MMIO_D(SPRSIZE(PIPE_C), D_ALL); 1612 MMIO_D(SPRKEYVAL(PIPE_C), D_ALL); 1613 MMIO_D(SPRKEYMSK(PIPE_C), D_ALL); 1614 MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write); 1615 MMIO_D(SPRKEYMAX(PIPE_C), D_ALL); 1616 MMIO_D(SPROFFSET(PIPE_C), D_ALL); 1617 MMIO_D(SPRSCALE(PIPE_C), D_ALL); 1618 MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL); 1619 1620 MMIO_F(LGC_PALETTE(PIPE_A, 0), 4 * 256, 0, 0, 0, D_ALL, NULL, NULL); 1621 MMIO_F(LGC_PALETTE(PIPE_B, 0), 4 * 256, 0, 0, 0, D_ALL, NULL, NULL); 1622 MMIO_F(LGC_PALETTE(PIPE_C, 0), 4 * 256, 0, 0, 0, D_ALL, NULL, NULL); 1623 1624 MMIO_D(HTOTAL(TRANSCODER_A), D_ALL); 1625 MMIO_D(HBLANK(TRANSCODER_A), D_ALL); 1626 MMIO_D(HSYNC(TRANSCODER_A), D_ALL); 1627 MMIO_D(VTOTAL(TRANSCODER_A), D_ALL); 1628 MMIO_D(VBLANK(TRANSCODER_A), D_ALL); 1629 MMIO_D(VSYNC(TRANSCODER_A), D_ALL); 1630 MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL); 1631 MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL); 1632 MMIO_D(PIPESRC(TRANSCODER_A), D_ALL); 1633 1634 MMIO_D(HTOTAL(TRANSCODER_B), D_ALL); 1635 MMIO_D(HBLANK(TRANSCODER_B), D_ALL); 1636 MMIO_D(HSYNC(TRANSCODER_B), D_ALL); 1637 MMIO_D(VTOTAL(TRANSCODER_B), D_ALL); 1638 MMIO_D(VBLANK(TRANSCODER_B), D_ALL); 1639 MMIO_D(VSYNC(TRANSCODER_B), D_ALL); 1640 MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL); 1641 MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL); 1642 MMIO_D(PIPESRC(TRANSCODER_B), D_ALL); 1643 1644 MMIO_D(HTOTAL(TRANSCODER_C), D_ALL); 1645 MMIO_D(HBLANK(TRANSCODER_C), D_ALL); 1646 MMIO_D(HSYNC(TRANSCODER_C), D_ALL); 1647 MMIO_D(VTOTAL(TRANSCODER_C), D_ALL); 1648 MMIO_D(VBLANK(TRANSCODER_C), D_ALL); 1649 MMIO_D(VSYNC(TRANSCODER_C), D_ALL); 1650 MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL); 1651 MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL); 1652 MMIO_D(PIPESRC(TRANSCODER_C), D_ALL); 1653 1654 MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL); 1655 MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL); 1656 MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL); 1657 MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL); 1658 MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL); 1659 MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL); 1660 MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL); 1661 MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL); 1662 1663 MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL); 1664 MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL); 1665 MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL); 1666 MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL); 1667 MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL); 1668 MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL); 1669 MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL); 1670 MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL); 1671 1672 MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL); 1673 MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL); 1674 MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL); 1675 MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL); 1676 MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL); 1677 MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL); 1678 MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL); 1679 MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL); 1680 1681 MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL); 1682 MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL); 1683 MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL); 1684 MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL); 1685 MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL); 1686 MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL); 1687 MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL); 1688 MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL); 1689 1690 MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL); 1691 MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL); 1692 MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL); 1693 MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL); 1694 MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL); 1695 MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL); 1696 MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL); 1697 MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL); 1698 1699 MMIO_D(PF_CTL(PIPE_A), D_ALL); 1700 MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL); 1701 MMIO_D(PF_WIN_POS(PIPE_A), D_ALL); 1702 MMIO_D(PF_VSCALE(PIPE_A), D_ALL); 1703 MMIO_D(PF_HSCALE(PIPE_A), D_ALL); 1704 1705 MMIO_D(PF_CTL(PIPE_B), D_ALL); 1706 MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL); 1707 MMIO_D(PF_WIN_POS(PIPE_B), D_ALL); 1708 MMIO_D(PF_VSCALE(PIPE_B), D_ALL); 1709 MMIO_D(PF_HSCALE(PIPE_B), D_ALL); 1710 1711 MMIO_D(PF_CTL(PIPE_C), D_ALL); 1712 MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL); 1713 MMIO_D(PF_WIN_POS(PIPE_C), D_ALL); 1714 MMIO_D(PF_VSCALE(PIPE_C), D_ALL); 1715 MMIO_D(PF_HSCALE(PIPE_C), D_ALL); 1716 1717 MMIO_D(WM0_PIPEA_ILK, D_ALL); 1718 MMIO_D(WM0_PIPEB_ILK, D_ALL); 1719 MMIO_D(WM0_PIPEC_IVB, D_ALL); 1720 MMIO_D(WM1_LP_ILK, D_ALL); 1721 MMIO_D(WM2_LP_ILK, D_ALL); 1722 MMIO_D(WM3_LP_ILK, D_ALL); 1723 MMIO_D(WM1S_LP_ILK, D_ALL); 1724 MMIO_D(WM2S_LP_IVB, D_ALL); 1725 MMIO_D(WM3S_LP_IVB, D_ALL); 1726 1727 MMIO_D(BLC_PWM_CPU_CTL2, D_ALL); 1728 MMIO_D(BLC_PWM_CPU_CTL, D_ALL); 1729 MMIO_D(BLC_PWM_PCH_CTL1, D_ALL); 1730 MMIO_D(BLC_PWM_PCH_CTL2, D_ALL); 1731 1732 MMIO_D(0x48268, D_ALL); 1733 1734 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read, 1735 gmbus_mmio_write); 1736 MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL); 1737 MMIO_F(0xe4f00, 0x28, 0, 0, 0, D_ALL, NULL, NULL); 1738 1739 MMIO_F(_PCH_DPB_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 1740 dp_aux_ch_ctl_mmio_write); 1741 MMIO_F(_PCH_DPC_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 1742 dp_aux_ch_ctl_mmio_write); 1743 MMIO_F(_PCH_DPD_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 1744 dp_aux_ch_ctl_mmio_write); 1745 1746 MMIO_RO(PCH_ADPA, D_ALL, 0, ADPA_CRT_HOTPLUG_MONITOR_MASK, NULL, pch_adpa_mmio_write); 1747 1748 MMIO_DH(_PCH_TRANSACONF, D_ALL, NULL, transconf_mmio_write); 1749 MMIO_DH(_PCH_TRANSBCONF, D_ALL, NULL, transconf_mmio_write); 1750 1751 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write); 1752 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write); 1753 MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write); 1754 MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); 1755 MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); 1756 MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); 1757 MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); 1758 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); 1759 MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); 1760 1761 MMIO_D(_PCH_TRANS_HTOTAL_A, D_ALL); 1762 MMIO_D(_PCH_TRANS_HBLANK_A, D_ALL); 1763 MMIO_D(_PCH_TRANS_HSYNC_A, D_ALL); 1764 MMIO_D(_PCH_TRANS_VTOTAL_A, D_ALL); 1765 MMIO_D(_PCH_TRANS_VBLANK_A, D_ALL); 1766 MMIO_D(_PCH_TRANS_VSYNC_A, D_ALL); 1767 MMIO_D(_PCH_TRANS_VSYNCSHIFT_A, D_ALL); 1768 1769 MMIO_D(_PCH_TRANS_HTOTAL_B, D_ALL); 1770 MMIO_D(_PCH_TRANS_HBLANK_B, D_ALL); 1771 MMIO_D(_PCH_TRANS_HSYNC_B, D_ALL); 1772 MMIO_D(_PCH_TRANS_VTOTAL_B, D_ALL); 1773 MMIO_D(_PCH_TRANS_VBLANK_B, D_ALL); 1774 MMIO_D(_PCH_TRANS_VSYNC_B, D_ALL); 1775 MMIO_D(_PCH_TRANS_VSYNCSHIFT_B, D_ALL); 1776 1777 MMIO_D(_PCH_TRANSA_DATA_M1, D_ALL); 1778 MMIO_D(_PCH_TRANSA_DATA_N1, D_ALL); 1779 MMIO_D(_PCH_TRANSA_DATA_M2, D_ALL); 1780 MMIO_D(_PCH_TRANSA_DATA_N2, D_ALL); 1781 MMIO_D(_PCH_TRANSA_LINK_M1, D_ALL); 1782 MMIO_D(_PCH_TRANSA_LINK_N1, D_ALL); 1783 MMIO_D(_PCH_TRANSA_LINK_M2, D_ALL); 1784 MMIO_D(_PCH_TRANSA_LINK_N2, D_ALL); 1785 1786 MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL); 1787 MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL); 1788 MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL); 1789 1790 MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL); 1791 MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL); 1792 MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL); 1793 1794 MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL); 1795 MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL); 1796 MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL); 1797 1798 MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL); 1799 MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL); 1800 MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL); 1801 1802 MMIO_D(_FDI_RXA_MISC, D_ALL); 1803 MMIO_D(_FDI_RXB_MISC, D_ALL); 1804 MMIO_D(_FDI_RXA_TUSIZE1, D_ALL); 1805 MMIO_D(_FDI_RXA_TUSIZE2, D_ALL); 1806 MMIO_D(_FDI_RXB_TUSIZE1, D_ALL); 1807 MMIO_D(_FDI_RXB_TUSIZE2, D_ALL); 1808 1809 MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write); 1810 MMIO_D(PCH_PP_DIVISOR, D_ALL); 1811 MMIO_D(PCH_PP_STATUS, D_ALL); 1812 MMIO_D(PCH_LVDS, D_ALL); 1813 MMIO_D(_PCH_DPLL_A, D_ALL); 1814 MMIO_D(_PCH_DPLL_B, D_ALL); 1815 MMIO_D(_PCH_FPA0, D_ALL); 1816 MMIO_D(_PCH_FPA1, D_ALL); 1817 MMIO_D(_PCH_FPB0, D_ALL); 1818 MMIO_D(_PCH_FPB1, D_ALL); 1819 MMIO_D(PCH_DREF_CONTROL, D_ALL); 1820 MMIO_D(PCH_RAWCLK_FREQ, D_ALL); 1821 MMIO_D(PCH_DPLL_SEL, D_ALL); 1822 1823 MMIO_D(0x61208, D_ALL); 1824 MMIO_D(0x6120c, D_ALL); 1825 MMIO_D(PCH_PP_ON_DELAYS, D_ALL); 1826 MMIO_D(PCH_PP_OFF_DELAYS, D_ALL); 1827 1828 MMIO_DH(0xe651c, D_ALL, dpy_reg_mmio_read, NULL); 1829 MMIO_DH(0xe661c, D_ALL, dpy_reg_mmio_read, NULL); 1830 MMIO_DH(0xe671c, D_ALL, dpy_reg_mmio_read, NULL); 1831 MMIO_DH(0xe681c, D_ALL, dpy_reg_mmio_read, NULL); 1832 MMIO_DH(0xe6c04, D_ALL, dpy_reg_mmio_read_2, NULL); 1833 MMIO_DH(0xe6e1c, D_ALL, dpy_reg_mmio_read_3, NULL); 1834 1835 MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0, 1836 PORTA_HOTPLUG_STATUS_MASK 1837 | PORTB_HOTPLUG_STATUS_MASK 1838 | PORTC_HOTPLUG_STATUS_MASK 1839 | PORTD_HOTPLUG_STATUS_MASK, 1840 NULL, NULL); 1841 1842 MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write); 1843 MMIO_D(FUSE_STRAP, D_ALL); 1844 MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL); 1845 1846 MMIO_D(DISP_ARB_CTL, D_ALL); 1847 MMIO_D(DISP_ARB_CTL2, D_ALL); 1848 1849 MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL); 1850 MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL); 1851 MMIO_D(ILK_DSPCLK_GATE_D, D_ALL); 1852 1853 MMIO_D(SOUTH_CHICKEN1, D_ALL); 1854 MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write); 1855 MMIO_D(_TRANSA_CHICKEN1, D_ALL); 1856 MMIO_D(_TRANSB_CHICKEN1, D_ALL); 1857 MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL); 1858 MMIO_D(_TRANSA_CHICKEN2, D_ALL); 1859 MMIO_D(_TRANSB_CHICKEN2, D_ALL); 1860 1861 MMIO_D(ILK_DPFC_CB_BASE, D_ALL); 1862 MMIO_D(ILK_DPFC_CONTROL, D_ALL); 1863 MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL); 1864 MMIO_D(ILK_DPFC_STATUS, D_ALL); 1865 MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL); 1866 MMIO_D(ILK_DPFC_CHICKEN, D_ALL); 1867 MMIO_D(ILK_FBC_RT_BASE, D_ALL); 1868 1869 MMIO_D(IPS_CTL, D_ALL); 1870 1871 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL); 1872 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL); 1873 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL); 1874 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL); 1875 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL); 1876 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL); 1877 MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL); 1878 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL); 1879 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL); 1880 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL); 1881 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL); 1882 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL); 1883 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL); 1884 1885 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL); 1886 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL); 1887 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL); 1888 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL); 1889 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL); 1890 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL); 1891 MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL); 1892 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL); 1893 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL); 1894 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL); 1895 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL); 1896 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL); 1897 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL); 1898 1899 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL); 1900 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL); 1901 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL); 1902 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL); 1903 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL); 1904 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL); 1905 MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL); 1906 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL); 1907 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL); 1908 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL); 1909 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL); 1910 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL); 1911 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL); 1912 1913 MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL); 1914 MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL); 1915 MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 1916 1917 MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL); 1918 MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL); 1919 MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 1920 1921 MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL); 1922 MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL); 1923 MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 1924 1925 MMIO_D(0x60110, D_ALL); 1926 MMIO_D(0x61110, D_ALL); 1927 MMIO_F(0x70400, 0x40, 0, 0, 0, D_ALL, NULL, NULL); 1928 MMIO_F(0x71400, 0x40, 0, 0, 0, D_ALL, NULL, NULL); 1929 MMIO_F(0x72400, 0x40, 0, 0, 0, D_ALL, NULL, NULL); 1930 MMIO_F(0x70440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 1931 MMIO_F(0x71440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 1932 MMIO_F(0x72440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 1933 MMIO_F(0x7044c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 1934 MMIO_F(0x7144c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 1935 MMIO_F(0x7244c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 1936 1937 MMIO_D(PIPE_WM_LINETIME(PIPE_A), D_ALL); 1938 MMIO_D(PIPE_WM_LINETIME(PIPE_B), D_ALL); 1939 MMIO_D(PIPE_WM_LINETIME(PIPE_C), D_ALL); 1940 MMIO_D(SPLL_CTL, D_ALL); 1941 MMIO_D(_WRPLL_CTL1, D_ALL); 1942 MMIO_D(_WRPLL_CTL2, D_ALL); 1943 MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL); 1944 MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL); 1945 MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL); 1946 MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL); 1947 MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL); 1948 MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL); 1949 MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL); 1950 MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL); 1951 1952 MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL); 1953 MMIO_D(0x46508, D_ALL); 1954 1955 MMIO_D(0x49080, D_ALL); 1956 MMIO_D(0x49180, D_ALL); 1957 MMIO_D(0x49280, D_ALL); 1958 1959 MMIO_F(0x49090, 0x14, 0, 0, 0, D_ALL, NULL, NULL); 1960 MMIO_F(0x49190, 0x14, 0, 0, 0, D_ALL, NULL, NULL); 1961 MMIO_F(0x49290, 0x14, 0, 0, 0, D_ALL, NULL, NULL); 1962 1963 MMIO_D(GAMMA_MODE(PIPE_A), D_ALL); 1964 MMIO_D(GAMMA_MODE(PIPE_B), D_ALL); 1965 MMIO_D(GAMMA_MODE(PIPE_C), D_ALL); 1966 1967 MMIO_D(PIPE_MULT(PIPE_A), D_ALL); 1968 MMIO_D(PIPE_MULT(PIPE_B), D_ALL); 1969 MMIO_D(PIPE_MULT(PIPE_C), D_ALL); 1970 1971 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL); 1972 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL); 1973 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL); 1974 1975 MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL); 1976 MMIO_D(SBI_ADDR, D_ALL); 1977 MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL); 1978 MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write); 1979 MMIO_D(PIXCLK_GATE, D_ALL); 1980 1981 MMIO_F(_DPA_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_ALL, NULL, 1982 dp_aux_ch_ctl_mmio_write); 1983 1984 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write); 1985 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write); 1986 MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write); 1987 MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write); 1988 MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write); 1989 1990 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write); 1991 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write); 1992 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write); 1993 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write); 1994 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write); 1995 1996 MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write); 1997 MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write); 1998 MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write); 1999 MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write); 2000 MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL); 2001 2002 MMIO_F(_DDI_BUF_TRANS_A, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2003 MMIO_F(0x64e60, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2004 MMIO_F(0x64eC0, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2005 MMIO_F(0x64f20, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2006 MMIO_F(0x64f80, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2007 2008 MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL); 2009 MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL); 2010 2011 MMIO_DH(_TRANS_DDI_FUNC_CTL_A, D_ALL, NULL, NULL); 2012 MMIO_DH(_TRANS_DDI_FUNC_CTL_B, D_ALL, NULL, NULL); 2013 MMIO_DH(_TRANS_DDI_FUNC_CTL_C, D_ALL, NULL, NULL); 2014 MMIO_DH(_TRANS_DDI_FUNC_CTL_EDP, D_ALL, NULL, NULL); 2015 2016 MMIO_D(_TRANSA_MSA_MISC, D_ALL); 2017 MMIO_D(_TRANSB_MSA_MISC, D_ALL); 2018 MMIO_D(_TRANSC_MSA_MISC, D_ALL); 2019 MMIO_D(_TRANS_EDP_MSA_MISC, D_ALL); 2020 2021 MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL); 2022 MMIO_D(FORCEWAKE_ACK, D_ALL); 2023 MMIO_D(GEN6_GT_CORE_STATUS, D_ALL); 2024 MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL); 2025 MMIO_D(GTFIFODBG, D_ALL); 2026 MMIO_D(GTFIFOCTL, D_ALL); 2027 MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write); 2028 MMIO_DH(FORCEWAKE_ACK_HSW, D_HSW | D_BDW, NULL, NULL); 2029 MMIO_D(ECOBUS, D_ALL); 2030 MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL); 2031 MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL); 2032 MMIO_D(GEN6_RPNSWREQ, D_ALL); 2033 MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL); 2034 MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL); 2035 MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL); 2036 MMIO_D(GEN6_RPSTAT1, D_ALL); 2037 MMIO_D(GEN6_RP_CONTROL, D_ALL); 2038 MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL); 2039 MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL); 2040 MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL); 2041 MMIO_D(GEN6_RP_CUR_UP, D_ALL); 2042 MMIO_D(GEN6_RP_PREV_UP, D_ALL); 2043 MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL); 2044 MMIO_D(GEN6_RP_CUR_DOWN, D_ALL); 2045 MMIO_D(GEN6_RP_PREV_DOWN, D_ALL); 2046 MMIO_D(GEN6_RP_UP_EI, D_ALL); 2047 MMIO_D(GEN6_RP_DOWN_EI, D_ALL); 2048 MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL); 2049 MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL); 2050 MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL); 2051 MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL); 2052 MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL); 2053 MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL); 2054 MMIO_D(GEN6_RC_SLEEP, D_ALL); 2055 MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL); 2056 MMIO_D(GEN6_RC6_THRESHOLD, D_ALL); 2057 MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL); 2058 MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL); 2059 MMIO_D(GEN6_PMINTRMSK, D_ALL); 2060 MMIO_DH(HSW_PWR_WELL_BIOS, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); 2061 MMIO_DH(HSW_PWR_WELL_DRIVER, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); 2062 MMIO_DH(HSW_PWR_WELL_KVMR, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); 2063 MMIO_DH(HSW_PWR_WELL_DEBUG, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); 2064 MMIO_DH(HSW_PWR_WELL_CTL5, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); 2065 MMIO_DH(HSW_PWR_WELL_CTL6, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); 2066 2067 MMIO_D(RSTDBYCTL, D_ALL); 2068 2069 MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write); 2070 MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write); 2071 MMIO_F(VGT_PVINFO_PAGE, VGT_PVINFO_SIZE, F_UNALIGN, 0, 0, D_ALL, pvinfo_mmio_read, pvinfo_mmio_write); 2072 MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write); 2073 2074 MMIO_F(MCHBAR_MIRROR_BASE_SNB, 0x40000, 0, 0, 0, D_ALL, NULL, NULL); 2075 2076 MMIO_D(TILECTL, D_ALL); 2077 2078 MMIO_D(GEN6_UCGCTL1, D_ALL); 2079 MMIO_D(GEN6_UCGCTL2, D_ALL); 2080 2081 MMIO_F(0x4f000, 0x90, 0, 0, 0, D_ALL, NULL, NULL); 2082 2083 MMIO_D(GEN6_PCODE_MAILBOX, D_PRE_SKL); 2084 MMIO_D(GEN6_PCODE_DATA, D_ALL); 2085 MMIO_D(0x13812c, D_ALL); 2086 MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL); 2087 MMIO_D(HSW_EDRAM_CAP, D_ALL); 2088 MMIO_D(HSW_IDICR, D_ALL); 2089 MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL); 2090 2091 MMIO_D(0x3c, D_ALL); 2092 MMIO_D(0x860, D_ALL); 2093 MMIO_D(ECOSKPD, D_ALL); 2094 MMIO_D(0x121d0, D_ALL); 2095 MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL); 2096 MMIO_D(0x41d0, D_ALL); 2097 MMIO_D(GAC_ECO_BITS, D_ALL); 2098 MMIO_D(0x6200, D_ALL); 2099 MMIO_D(0x6204, D_ALL); 2100 MMIO_D(0x6208, D_ALL); 2101 MMIO_D(0x7118, D_ALL); 2102 MMIO_D(0x7180, D_ALL); 2103 MMIO_D(0x7408, D_ALL); 2104 MMIO_D(0x7c00, D_ALL); 2105 MMIO_D(GEN6_MBCTL, D_ALL); 2106 MMIO_D(0x911c, D_ALL); 2107 MMIO_D(0x9120, D_ALL); 2108 MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL); 2109 2110 MMIO_D(GAB_CTL, D_ALL); 2111 MMIO_D(0x48800, D_ALL); 2112 MMIO_D(0xce044, D_ALL); 2113 MMIO_D(0xe6500, D_ALL); 2114 MMIO_D(0xe6504, D_ALL); 2115 MMIO_D(0xe6600, D_ALL); 2116 MMIO_D(0xe6604, D_ALL); 2117 MMIO_D(0xe6700, D_ALL); 2118 MMIO_D(0xe6704, D_ALL); 2119 MMIO_D(0xe6800, D_ALL); 2120 MMIO_D(0xe6804, D_ALL); 2121 MMIO_D(PCH_GMBUS4, D_ALL); 2122 MMIO_D(PCH_GMBUS5, D_ALL); 2123 2124 MMIO_D(0x902c, D_ALL); 2125 MMIO_D(0xec008, D_ALL); 2126 MMIO_D(0xec00c, D_ALL); 2127 MMIO_D(0xec008 + 0x18, D_ALL); 2128 MMIO_D(0xec00c + 0x18, D_ALL); 2129 MMIO_D(0xec008 + 0x18 * 2, D_ALL); 2130 MMIO_D(0xec00c + 0x18 * 2, D_ALL); 2131 MMIO_D(0xec008 + 0x18 * 3, D_ALL); 2132 MMIO_D(0xec00c + 0x18 * 3, D_ALL); 2133 MMIO_D(0xec408, D_ALL); 2134 MMIO_D(0xec40c, D_ALL); 2135 MMIO_D(0xec408 + 0x18, D_ALL); 2136 MMIO_D(0xec40c + 0x18, D_ALL); 2137 MMIO_D(0xec408 + 0x18 * 2, D_ALL); 2138 MMIO_D(0xec40c + 0x18 * 2, D_ALL); 2139 MMIO_D(0xec408 + 0x18 * 3, D_ALL); 2140 MMIO_D(0xec40c + 0x18 * 3, D_ALL); 2141 MMIO_D(0xfc810, D_ALL); 2142 MMIO_D(0xfc81c, D_ALL); 2143 MMIO_D(0xfc828, D_ALL); 2144 MMIO_D(0xfc834, D_ALL); 2145 MMIO_D(0xfcc00, D_ALL); 2146 MMIO_D(0xfcc0c, D_ALL); 2147 MMIO_D(0xfcc18, D_ALL); 2148 MMIO_D(0xfcc24, D_ALL); 2149 MMIO_D(0xfd000, D_ALL); 2150 MMIO_D(0xfd00c, D_ALL); 2151 MMIO_D(0xfd018, D_ALL); 2152 MMIO_D(0xfd024, D_ALL); 2153 MMIO_D(0xfd034, D_ALL); 2154 2155 MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write); 2156 MMIO_D(0x2054, D_ALL); 2157 MMIO_D(0x12054, D_ALL); 2158 MMIO_D(0x22054, D_ALL); 2159 MMIO_D(0x1a054, D_ALL); 2160 2161 MMIO_D(0x44070, D_ALL); 2162 2163 MMIO_D(0x215c, D_HSW_PLUS); 2164 MMIO_DFH(0x2178, D_ALL, F_CMD_ACCESS, NULL, NULL); 2165 MMIO_DFH(0x217c, D_ALL, F_CMD_ACCESS, NULL, NULL); 2166 MMIO_DFH(0x12178, D_ALL, F_CMD_ACCESS, NULL, NULL); 2167 MMIO_DFH(0x1217c, D_ALL, F_CMD_ACCESS, NULL, NULL); 2168 2169 MMIO_F(0x2290, 8, 0, 0, 0, D_HSW_PLUS, NULL, NULL); 2170 MMIO_D(GEN7_OACONTROL, D_HSW); 2171 MMIO_D(0x2b00, D_BDW_PLUS); 2172 MMIO_D(0x2360, D_BDW_PLUS); 2173 MMIO_F(0x5200, 32, 0, 0, 0, D_ALL, NULL, NULL); 2174 MMIO_F(0x5240, 32, 0, 0, 0, D_ALL, NULL, NULL); 2175 MMIO_F(0x5280, 16, 0, 0, 0, D_ALL, NULL, NULL); 2176 2177 MMIO_DFH(0x1c17c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2178 MMIO_DFH(0x1c178, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2179 MMIO_D(BCS_SWCTRL, D_ALL); 2180 2181 MMIO_F(HS_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2182 MMIO_F(DS_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2183 MMIO_F(IA_VERTICES_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2184 MMIO_F(IA_PRIMITIVES_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2185 MMIO_F(VS_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2186 MMIO_F(GS_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2187 MMIO_F(GS_PRIMITIVES_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2188 MMIO_F(CL_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2189 MMIO_F(CL_PRIMITIVES_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2190 MMIO_F(PS_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2191 MMIO_F(PS_DEPTH_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL); 2192 MMIO_DH(0x4260, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2193 MMIO_DH(0x4264, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2194 MMIO_DH(0x4268, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2195 MMIO_DH(0x426c, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2196 MMIO_DH(0x4270, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2197 MMIO_DFH(0x4094, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2198 2199 return 0; 2200 } 2201 2202 static int init_broadwell_mmio_info(struct intel_gvt *gvt) 2203 { 2204 struct drm_i915_private *dev_priv = gvt->dev_priv; 2205 int ret; 2206 2207 MMIO_DH(RING_IMR(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, 2208 intel_vgpu_reg_imr_handler); 2209 2210 MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2211 MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2212 MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2213 MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS); 2214 2215 MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2216 MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2217 MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2218 MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS); 2219 2220 MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2221 MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2222 MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2223 MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS); 2224 2225 MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2226 MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2227 MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2228 MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS); 2229 2230 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL, 2231 intel_vgpu_reg_imr_handler); 2232 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL, 2233 intel_vgpu_reg_ier_handler); 2234 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL, 2235 intel_vgpu_reg_iir_handler); 2236 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS); 2237 2238 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL, 2239 intel_vgpu_reg_imr_handler); 2240 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL, 2241 intel_vgpu_reg_ier_handler); 2242 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL, 2243 intel_vgpu_reg_iir_handler); 2244 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS); 2245 2246 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL, 2247 intel_vgpu_reg_imr_handler); 2248 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL, 2249 intel_vgpu_reg_ier_handler); 2250 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL, 2251 intel_vgpu_reg_iir_handler); 2252 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS); 2253 2254 MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2255 MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2256 MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2257 MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS); 2258 2259 MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2260 MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2261 MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2262 MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS); 2263 2264 MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2265 MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2266 MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2267 MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS); 2268 2269 MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL, 2270 intel_vgpu_reg_master_irq_handler); 2271 2272 MMIO_D(RING_HWSTAM(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2273 MMIO_D(0x1c134, D_BDW_PLUS); 2274 2275 MMIO_D(RING_TAIL(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2276 MMIO_D(RING_HEAD(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2277 MMIO_GM(RING_START(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, NULL); 2278 MMIO_D(RING_CTL(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2279 MMIO_D(RING_ACTHD(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2280 MMIO_D(RING_ACTHD_UDW(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2281 MMIO_DFH(0x1c29c, D_BDW_PLUS, F_MODE_MASK, NULL, ring_mode_mmio_write); 2282 MMIO_DFH(RING_MI_MODE(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_MODE_MASK, 2283 NULL, NULL); 2284 MMIO_DFH(RING_INSTPM(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_MODE_MASK, 2285 NULL, NULL); 2286 MMIO_DFH(RING_TIMESTAMP(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS, 2287 ring_timestamp_mmio_read, NULL); 2288 2289 MMIO_RING_D(RING_ACTHD_UDW, D_BDW_PLUS); 2290 2291 #define RING_REG(base) (base + 0xd0) 2292 MMIO_RING_F(RING_REG, 4, F_RO, 0, 2293 ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL, 2294 ring_reset_ctl_write); 2295 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 4, F_RO, 0, 2296 ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL, 2297 ring_reset_ctl_write); 2298 #undef RING_REG 2299 2300 #define RING_REG(base) (base + 0x230) 2301 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write); 2302 MMIO_DH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, elsp_mmio_write); 2303 #undef RING_REG 2304 2305 #define RING_REG(base) (base + 0x234) 2306 MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL); 2307 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 4, F_RO, 0, ~0LL, D_BDW_PLUS, NULL, NULL); 2308 #undef RING_REG 2309 2310 #define RING_REG(base) (base + 0x244) 2311 MMIO_RING_D(RING_REG, D_BDW_PLUS); 2312 MMIO_D(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS); 2313 #undef RING_REG 2314 2315 #define RING_REG(base) (base + 0x370) 2316 MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL); 2317 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 48, F_RO, 0, ~0, D_BDW_PLUS, 2318 NULL, NULL); 2319 #undef RING_REG 2320 2321 #define RING_REG(base) (base + 0x3a0) 2322 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2323 MMIO_DFH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2324 #undef RING_REG 2325 2326 MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS); 2327 MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS); 2328 MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS); 2329 MMIO_D(0x1c1d0, D_BDW_PLUS); 2330 MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS); 2331 MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS); 2332 MMIO_D(0x1c054, D_BDW_PLUS); 2333 2334 MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS); 2335 MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS); 2336 2337 MMIO_D(GAMTARBMODE, D_BDW_PLUS); 2338 2339 #define RING_REG(base) (base + 0x270) 2340 MMIO_RING_F(RING_REG, 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL); 2341 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL); 2342 #undef RING_REG 2343 2344 MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, NULL); 2345 MMIO_GM(0x1c080, D_BDW_PLUS, NULL, NULL); 2346 2347 MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2348 2349 MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW); 2350 MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW); 2351 MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW); 2352 2353 MMIO_D(WM_MISC, D_BDW); 2354 MMIO_D(BDW_EDP_PSR_BASE, D_BDW); 2355 2356 MMIO_D(0x66c00, D_BDW_PLUS); 2357 MMIO_D(0x66c04, D_BDW_PLUS); 2358 2359 MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS); 2360 2361 MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS); 2362 MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS); 2363 MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS); 2364 2365 MMIO_D(0xfdc, D_BDW); 2366 MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2367 MMIO_D(GEN7_ROW_CHICKEN2, D_BDW_PLUS); 2368 MMIO_D(GEN8_UCGCTL6, D_BDW_PLUS); 2369 2370 MMIO_D(0xb1f0, D_BDW); 2371 MMIO_D(0xb1c0, D_BDW); 2372 MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2373 MMIO_D(0xb100, D_BDW); 2374 MMIO_D(0xb10c, D_BDW); 2375 MMIO_D(0xb110, D_BDW); 2376 2377 MMIO_DFH(0x24d0, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2378 MMIO_DFH(0x24d4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2379 MMIO_DFH(0x24d8, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2380 MMIO_DFH(0x24dc, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2381 2382 MMIO_D(0x83a4, D_BDW); 2383 MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS); 2384 2385 MMIO_D(0x8430, D_BDW); 2386 2387 MMIO_D(0x110000, D_BDW_PLUS); 2388 2389 MMIO_D(0x48400, D_BDW_PLUS); 2390 2391 MMIO_D(0x6e570, D_BDW_PLUS); 2392 MMIO_D(0x65f10, D_BDW_PLUS); 2393 2394 MMIO_DFH(0xe194, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2395 MMIO_DFH(0xe188, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2396 MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2397 MMIO_DFH(0x2580, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2398 2399 MMIO_D(0x2248, D_BDW); 2400 2401 return 0; 2402 } 2403 2404 static int init_skl_mmio_info(struct intel_gvt *gvt) 2405 { 2406 struct drm_i915_private *dev_priv = gvt->dev_priv; 2407 int ret; 2408 2409 MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2410 MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL); 2411 MMIO_DH(FORCEWAKE_BLITTER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2412 MMIO_DH(FORCEWAKE_ACK_BLITTER_GEN9, D_SKL_PLUS, NULL, NULL); 2413 MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2414 MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL); 2415 2416 MMIO_F(_DPB_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL, NULL, dp_aux_ch_ctl_mmio_write); 2417 MMIO_F(_DPC_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL, NULL, dp_aux_ch_ctl_mmio_write); 2418 MMIO_F(_DPD_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL, NULL, dp_aux_ch_ctl_mmio_write); 2419 2420 MMIO_D(HSW_PWR_WELL_BIOS, D_SKL); 2421 MMIO_DH(HSW_PWR_WELL_DRIVER, D_SKL, NULL, skl_power_well_ctl_write); 2422 2423 MMIO_DH(GEN6_PCODE_MAILBOX, D_SKL, NULL, mailbox_write); 2424 MMIO_D(0xa210, D_SKL_PLUS); 2425 MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS); 2426 MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS); 2427 MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2428 MMIO_DH(0x4ddc, D_SKL, NULL, skl_misc_ctl_write); 2429 MMIO_DH(0x42080, D_SKL, NULL, skl_misc_ctl_write); 2430 MMIO_D(0x45504, D_SKL); 2431 MMIO_D(0x45520, D_SKL); 2432 MMIO_D(0x46000, D_SKL); 2433 MMIO_DH(0x46010, D_SKL, NULL, skl_lcpll_write); 2434 MMIO_DH(0x46014, D_SKL, NULL, skl_lcpll_write); 2435 MMIO_D(0x6C040, D_SKL); 2436 MMIO_D(0x6C048, D_SKL); 2437 MMIO_D(0x6C050, D_SKL); 2438 MMIO_D(0x6C044, D_SKL); 2439 MMIO_D(0x6C04C, D_SKL); 2440 MMIO_D(0x6C054, D_SKL); 2441 MMIO_D(0x6c058, D_SKL); 2442 MMIO_D(0x6c05c, D_SKL); 2443 MMIO_DH(0X6c060, D_SKL, dpll_status_read, NULL); 2444 2445 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL, NULL, pf_write); 2446 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL, NULL, pf_write); 2447 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL, NULL, pf_write); 2448 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL, NULL, pf_write); 2449 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL, NULL, pf_write); 2450 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL, NULL, pf_write); 2451 2452 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL, NULL, pf_write); 2453 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL, NULL, pf_write); 2454 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL, NULL, pf_write); 2455 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL, NULL, pf_write); 2456 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL, NULL, pf_write); 2457 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL, NULL, pf_write); 2458 2459 MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL, NULL, pf_write); 2460 MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL, NULL, pf_write); 2461 MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL, NULL, pf_write); 2462 MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL, NULL, pf_write); 2463 MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL, NULL, pf_write); 2464 MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL, NULL, pf_write); 2465 2466 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL, NULL, NULL); 2467 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL, NULL, NULL); 2468 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL, NULL, NULL); 2469 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL, NULL, NULL); 2470 2471 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL, NULL, NULL); 2472 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL, NULL, NULL); 2473 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL, NULL, NULL); 2474 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL, NULL, NULL); 2475 2476 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL, NULL, NULL); 2477 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL, NULL, NULL); 2478 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL, NULL, NULL); 2479 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL, NULL, NULL); 2480 2481 MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL, NULL, NULL); 2482 MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL, NULL, NULL); 2483 MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL, NULL, NULL); 2484 2485 MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2486 MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2487 MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2488 2489 MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2490 MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2491 MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2492 2493 MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2494 MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2495 MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2496 2497 MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2498 MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2499 MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2500 2501 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL, NULL, NULL); 2502 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL, NULL, NULL); 2503 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL, NULL, NULL); 2504 2505 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL, NULL, NULL); 2506 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL, NULL, NULL); 2507 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL, NULL, NULL); 2508 2509 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL, NULL, NULL); 2510 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL, NULL, NULL); 2511 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL, NULL, NULL); 2512 2513 MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL, NULL, NULL); 2514 MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL, NULL, NULL); 2515 MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL, NULL, NULL); 2516 2517 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL, NULL, NULL); 2518 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL, NULL, NULL); 2519 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL, NULL, NULL); 2520 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL, NULL, NULL); 2521 2522 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL, NULL, NULL); 2523 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL, NULL, NULL); 2524 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL, NULL, NULL); 2525 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL, NULL, NULL); 2526 2527 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL, NULL, NULL); 2528 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL, NULL, NULL); 2529 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL, NULL, NULL); 2530 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL, NULL, NULL); 2531 2532 MMIO_DH(_REG_701C0(PIPE_A, 1), D_SKL, NULL, NULL); 2533 MMIO_DH(_REG_701C0(PIPE_A, 2), D_SKL, NULL, NULL); 2534 MMIO_DH(_REG_701C0(PIPE_A, 3), D_SKL, NULL, NULL); 2535 MMIO_DH(_REG_701C0(PIPE_A, 4), D_SKL, NULL, NULL); 2536 2537 MMIO_DH(_REG_701C0(PIPE_B, 1), D_SKL, NULL, NULL); 2538 MMIO_DH(_REG_701C0(PIPE_B, 2), D_SKL, NULL, NULL); 2539 MMIO_DH(_REG_701C0(PIPE_B, 3), D_SKL, NULL, NULL); 2540 MMIO_DH(_REG_701C0(PIPE_B, 4), D_SKL, NULL, NULL); 2541 2542 MMIO_DH(_REG_701C0(PIPE_C, 1), D_SKL, NULL, NULL); 2543 MMIO_DH(_REG_701C0(PIPE_C, 2), D_SKL, NULL, NULL); 2544 MMIO_DH(_REG_701C0(PIPE_C, 3), D_SKL, NULL, NULL); 2545 MMIO_DH(_REG_701C0(PIPE_C, 4), D_SKL, NULL, NULL); 2546 2547 MMIO_DH(_REG_701C4(PIPE_A, 1), D_SKL, NULL, NULL); 2548 MMIO_DH(_REG_701C4(PIPE_A, 2), D_SKL, NULL, NULL); 2549 MMIO_DH(_REG_701C4(PIPE_A, 3), D_SKL, NULL, NULL); 2550 MMIO_DH(_REG_701C4(PIPE_A, 4), D_SKL, NULL, NULL); 2551 2552 MMIO_DH(_REG_701C4(PIPE_B, 1), D_SKL, NULL, NULL); 2553 MMIO_DH(_REG_701C4(PIPE_B, 2), D_SKL, NULL, NULL); 2554 MMIO_DH(_REG_701C4(PIPE_B, 3), D_SKL, NULL, NULL); 2555 MMIO_DH(_REG_701C4(PIPE_B, 4), D_SKL, NULL, NULL); 2556 2557 MMIO_DH(_REG_701C4(PIPE_C, 1), D_SKL, NULL, NULL); 2558 MMIO_DH(_REG_701C4(PIPE_C, 2), D_SKL, NULL, NULL); 2559 MMIO_DH(_REG_701C4(PIPE_C, 3), D_SKL, NULL, NULL); 2560 MMIO_DH(_REG_701C4(PIPE_C, 4), D_SKL, NULL, NULL); 2561 2562 MMIO_D(0x70380, D_SKL); 2563 MMIO_D(0x71380, D_SKL); 2564 MMIO_D(0x72380, D_SKL); 2565 MMIO_D(0x7039c, D_SKL); 2566 2567 MMIO_F(0x80000, 0x3000, 0, 0, 0, D_SKL, NULL, NULL); 2568 MMIO_D(0x8f074, D_SKL); 2569 MMIO_D(0x8f004, D_SKL); 2570 MMIO_D(0x8f034, D_SKL); 2571 2572 MMIO_D(0xb11c, D_SKL); 2573 2574 MMIO_D(0x51000, D_SKL); 2575 MMIO_D(0x6c00c, D_SKL); 2576 2577 MMIO_F(0xc800, 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL, NULL, NULL); 2578 MMIO_F(0xb020, 0x80, F_CMD_ACCESS, 0, 0, D_SKL, NULL, NULL); 2579 2580 MMIO_D(0xd08, D_SKL); 2581 MMIO_D(0x20e0, D_SKL); 2582 MMIO_D(0x20ec, D_SKL); 2583 2584 /* TRTT */ 2585 MMIO_D(0x4de0, D_SKL); 2586 MMIO_D(0x4de4, D_SKL); 2587 MMIO_D(0x4de8, D_SKL); 2588 MMIO_D(0x4dec, D_SKL); 2589 MMIO_D(0x4df0, D_SKL); 2590 MMIO_DH(0x4df4, D_SKL, NULL, gen9_trtte_write); 2591 MMIO_DH(0x4dfc, D_SKL, NULL, gen9_trtt_chicken_write); 2592 2593 MMIO_D(0x45008, D_SKL); 2594 2595 MMIO_D(0x46430, D_SKL); 2596 2597 MMIO_D(0x46520, D_SKL); 2598 2599 MMIO_D(0xc403c, D_SKL); 2600 MMIO_D(0xb004, D_SKL); 2601 MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write); 2602 2603 MMIO_D(0x65900, D_SKL); 2604 MMIO_D(0x1082c0, D_SKL); 2605 MMIO_D(0x4068, D_SKL); 2606 MMIO_D(0x67054, D_SKL); 2607 MMIO_D(0x6e560, D_SKL); 2608 MMIO_D(0x6e554, D_SKL); 2609 MMIO_D(0x2b20, D_SKL); 2610 MMIO_D(0x65f00, D_SKL); 2611 MMIO_D(0x65f08, D_SKL); 2612 MMIO_D(0x320f0, D_SKL); 2613 2614 MMIO_D(_REG_VCS2_EXCC, D_SKL); 2615 MMIO_D(0x70034, D_SKL); 2616 MMIO_D(0x71034, D_SKL); 2617 MMIO_D(0x72034, D_SKL); 2618 2619 MMIO_D(_PLANE_KEYVAL_1(PIPE_A), D_SKL); 2620 MMIO_D(_PLANE_KEYVAL_1(PIPE_B), D_SKL); 2621 MMIO_D(_PLANE_KEYVAL_1(PIPE_C), D_SKL); 2622 MMIO_D(_PLANE_KEYMSK_1(PIPE_A), D_SKL); 2623 MMIO_D(_PLANE_KEYMSK_1(PIPE_B), D_SKL); 2624 MMIO_D(_PLANE_KEYMSK_1(PIPE_C), D_SKL); 2625 2626 MMIO_D(0x44500, D_SKL); 2627 return 0; 2628 } 2629 2630 /** 2631 * intel_gvt_find_mmio_info - find MMIO information entry by aligned offset 2632 * @gvt: GVT device 2633 * @offset: register offset 2634 * 2635 * This function is used to find the MMIO information entry from hash table 2636 * 2637 * Returns: 2638 * pointer to MMIO information entry, NULL if not exists 2639 */ 2640 struct intel_gvt_mmio_info *intel_gvt_find_mmio_info(struct intel_gvt *gvt, 2641 unsigned int offset) 2642 { 2643 struct intel_gvt_mmio_info *e; 2644 2645 WARN_ON(!IS_ALIGNED(offset, 4)); 2646 2647 hash_for_each_possible(gvt->mmio.mmio_info_table, e, node, offset) { 2648 if (e->offset == offset) 2649 return e; 2650 } 2651 return NULL; 2652 } 2653 2654 /** 2655 * intel_gvt_clean_mmio_info - clean up MMIO information table for GVT device 2656 * @gvt: GVT device 2657 * 2658 * This function is called at the driver unloading stage, to clean up the MMIO 2659 * information table of GVT device 2660 * 2661 */ 2662 void intel_gvt_clean_mmio_info(struct intel_gvt *gvt) 2663 { 2664 struct hlist_node *tmp; 2665 struct intel_gvt_mmio_info *e; 2666 int i; 2667 2668 hash_for_each_safe(gvt->mmio.mmio_info_table, i, tmp, e, node) 2669 kfree(e); 2670 2671 vfree(gvt->mmio.mmio_attribute); 2672 gvt->mmio.mmio_attribute = NULL; 2673 } 2674 2675 /** 2676 * intel_gvt_setup_mmio_info - setup MMIO information table for GVT device 2677 * @gvt: GVT device 2678 * 2679 * This function is called at the initialization stage, to setup the MMIO 2680 * information table for GVT device 2681 * 2682 * Returns: 2683 * zero on success, negative if failed. 2684 */ 2685 int intel_gvt_setup_mmio_info(struct intel_gvt *gvt) 2686 { 2687 struct intel_gvt_device_info *info = &gvt->device_info; 2688 struct drm_i915_private *dev_priv = gvt->dev_priv; 2689 int ret; 2690 2691 gvt->mmio.mmio_attribute = vzalloc(info->mmio_size); 2692 if (!gvt->mmio.mmio_attribute) 2693 return -ENOMEM; 2694 2695 ret = init_generic_mmio_info(gvt); 2696 if (ret) 2697 goto err; 2698 2699 if (IS_BROADWELL(dev_priv)) { 2700 ret = init_broadwell_mmio_info(gvt); 2701 if (ret) 2702 goto err; 2703 } else if (IS_SKYLAKE(dev_priv)) { 2704 ret = init_broadwell_mmio_info(gvt); 2705 if (ret) 2706 goto err; 2707 ret = init_skl_mmio_info(gvt); 2708 if (ret) 2709 goto err; 2710 } 2711 return 0; 2712 err: 2713 intel_gvt_clean_mmio_info(gvt); 2714 return ret; 2715 } 2716 2717 /** 2718 * intel_gvt_mmio_set_accessed - mark a MMIO has been accessed 2719 * @gvt: a GVT device 2720 * @offset: register offset 2721 * 2722 */ 2723 void intel_gvt_mmio_set_accessed(struct intel_gvt *gvt, unsigned int offset) 2724 { 2725 gvt->mmio.mmio_attribute[offset >> 2] |= 2726 F_ACCESSED; 2727 } 2728 2729 /** 2730 * intel_gvt_mmio_is_cmd_accessed - mark a MMIO could be accessed by command 2731 * @gvt: a GVT device 2732 * @offset: register offset 2733 * 2734 */ 2735 bool intel_gvt_mmio_is_cmd_access(struct intel_gvt *gvt, 2736 unsigned int offset) 2737 { 2738 return gvt->mmio.mmio_attribute[offset >> 2] & 2739 F_CMD_ACCESS; 2740 } 2741 2742 /** 2743 * intel_gvt_mmio_is_unalign - mark a MMIO could be accessed unaligned 2744 * @gvt: a GVT device 2745 * @offset: register offset 2746 * 2747 */ 2748 bool intel_gvt_mmio_is_unalign(struct intel_gvt *gvt, 2749 unsigned int offset) 2750 { 2751 return gvt->mmio.mmio_attribute[offset >> 2] & 2752 F_UNALIGN; 2753 } 2754 2755 /** 2756 * intel_gvt_mmio_set_cmd_accessed - mark a MMIO has been accessed by command 2757 * @gvt: a GVT device 2758 * @offset: register offset 2759 * 2760 */ 2761 void intel_gvt_mmio_set_cmd_accessed(struct intel_gvt *gvt, 2762 unsigned int offset) 2763 { 2764 gvt->mmio.mmio_attribute[offset >> 2] |= 2765 F_CMD_ACCESSED; 2766 } 2767 2768 /** 2769 * intel_gvt_mmio_has_mode_mask - if a MMIO has a mode mask 2770 * @gvt: a GVT device 2771 * @offset: register offset 2772 * 2773 * Returns: 2774 * True if a MMIO has a mode mask in its higher 16 bits, false if it isn't. 2775 * 2776 */ 2777 bool intel_gvt_mmio_has_mode_mask(struct intel_gvt *gvt, unsigned int offset) 2778 { 2779 return gvt->mmio.mmio_attribute[offset >> 2] & 2780 F_MODE_MASK; 2781 } 2782 2783 /** 2784 * intel_vgpu_default_mmio_read - default MMIO read handler 2785 * @vgpu: a vGPU 2786 * @offset: access offset 2787 * @p_data: data return buffer 2788 * @bytes: access data length 2789 * 2790 * Returns: 2791 * Zero on success, negative error code if failed. 2792 */ 2793 int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 2794 void *p_data, unsigned int bytes) 2795 { 2796 read_vreg(vgpu, offset, p_data, bytes); 2797 return 0; 2798 } 2799 2800 /** 2801 * intel_t_default_mmio_write - default MMIO write handler 2802 * @vgpu: a vGPU 2803 * @offset: access offset 2804 * @p_data: write data buffer 2805 * @bytes: access data length 2806 * 2807 * Returns: 2808 * Zero on success, negative error code if failed. 2809 */ 2810 int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 2811 void *p_data, unsigned int bytes) 2812 { 2813 write_vreg(vgpu, offset, p_data, bytes); 2814 return 0; 2815 } 2816