1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Kevin Tian <kevin.tian@intel.com> 25 * Eddie Dong <eddie.dong@intel.com> 26 * Zhiyuan Lv <zhiyuan.lv@intel.com> 27 * 28 * Contributors: 29 * Min He <min.he@intel.com> 30 * Tina Zhang <tina.zhang@intel.com> 31 * Pei Zhang <pei.zhang@intel.com> 32 * Niu Bing <bing.niu@intel.com> 33 * Ping Gao <ping.a.gao@intel.com> 34 * Zhi Wang <zhi.a.wang@intel.com> 35 * 36 37 */ 38 39 #include "i915_drv.h" 40 #include "gvt.h" 41 #include "i915_pvinfo.h" 42 43 /* XXX FIXME i915 has changed PP_XXX definition */ 44 #define PCH_PP_STATUS _MMIO(0xc7200) 45 #define PCH_PP_CONTROL _MMIO(0xc7204) 46 #define PCH_PP_ON_DELAYS _MMIO(0xc7208) 47 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c) 48 #define PCH_PP_DIVISOR _MMIO(0xc7210) 49 50 unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt) 51 { 52 struct drm_i915_private *i915 = gvt->gt->i915; 53 54 if (IS_BROADWELL(i915)) 55 return D_BDW; 56 else if (IS_SKYLAKE(i915)) 57 return D_SKL; 58 else if (IS_KABYLAKE(i915)) 59 return D_KBL; 60 else if (IS_BROXTON(i915)) 61 return D_BXT; 62 else if (IS_COFFEELAKE(i915)) 63 return D_CFL; 64 65 return 0; 66 } 67 68 bool intel_gvt_match_device(struct intel_gvt *gvt, 69 unsigned long device) 70 { 71 return intel_gvt_get_device_type(gvt) & device; 72 } 73 74 static void read_vreg(struct intel_vgpu *vgpu, unsigned int offset, 75 void *p_data, unsigned int bytes) 76 { 77 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); 78 } 79 80 static void write_vreg(struct intel_vgpu *vgpu, unsigned int offset, 81 void *p_data, unsigned int bytes) 82 { 83 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes); 84 } 85 86 static struct intel_gvt_mmio_info *find_mmio_info(struct intel_gvt *gvt, 87 unsigned int offset) 88 { 89 struct intel_gvt_mmio_info *e; 90 91 hash_for_each_possible(gvt->mmio.mmio_info_table, e, node, offset) { 92 if (e->offset == offset) 93 return e; 94 } 95 return NULL; 96 } 97 98 static int new_mmio_info(struct intel_gvt *gvt, 99 u32 offset, u8 flags, u32 size, 100 u32 addr_mask, u32 ro_mask, u32 device, 101 gvt_mmio_func read, gvt_mmio_func write) 102 { 103 struct intel_gvt_mmio_info *info, *p; 104 u32 start, end, i; 105 106 if (!intel_gvt_match_device(gvt, device)) 107 return 0; 108 109 if (WARN_ON(!IS_ALIGNED(offset, 4))) 110 return -EINVAL; 111 112 start = offset; 113 end = offset + size; 114 115 for (i = start; i < end; i += 4) { 116 info = kzalloc(sizeof(*info), GFP_KERNEL); 117 if (!info) 118 return -ENOMEM; 119 120 info->offset = i; 121 p = find_mmio_info(gvt, info->offset); 122 if (p) { 123 WARN(1, "dup mmio definition offset %x\n", 124 info->offset); 125 kfree(info); 126 127 /* We return -EEXIST here to make GVT-g load fail. 128 * So duplicated MMIO can be found as soon as 129 * possible. 130 */ 131 return -EEXIST; 132 } 133 134 info->ro_mask = ro_mask; 135 info->device = device; 136 info->read = read ? read : intel_vgpu_default_mmio_read; 137 info->write = write ? write : intel_vgpu_default_mmio_write; 138 gvt->mmio.mmio_attribute[info->offset / 4] = flags; 139 INIT_HLIST_NODE(&info->node); 140 hash_add(gvt->mmio.mmio_info_table, &info->node, info->offset); 141 gvt->mmio.num_tracked_mmio++; 142 } 143 return 0; 144 } 145 146 /** 147 * intel_gvt_render_mmio_to_engine - convert a mmio offset into the engine 148 * @gvt: a GVT device 149 * @offset: register offset 150 * 151 * Returns: 152 * The engine containing the offset within its mmio page. 153 */ 154 const struct intel_engine_cs * 155 intel_gvt_render_mmio_to_engine(struct intel_gvt *gvt, unsigned int offset) 156 { 157 struct intel_engine_cs *engine; 158 enum intel_engine_id id; 159 160 offset &= ~GENMASK(11, 0); 161 for_each_engine(engine, gvt->gt, id) 162 if (engine->mmio_base == offset) 163 return engine; 164 165 return NULL; 166 } 167 168 #define offset_to_fence_num(offset) \ 169 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3) 170 171 #define fence_num_to_offset(num) \ 172 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) 173 174 175 void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason) 176 { 177 switch (reason) { 178 case GVT_FAILSAFE_UNSUPPORTED_GUEST: 179 pr_err("Detected your guest driver doesn't support GVT-g.\n"); 180 break; 181 case GVT_FAILSAFE_INSUFFICIENT_RESOURCE: 182 pr_err("Graphics resource is not enough for the guest\n"); 183 break; 184 case GVT_FAILSAFE_GUEST_ERR: 185 pr_err("GVT Internal error for the guest\n"); 186 break; 187 default: 188 break; 189 } 190 pr_err("Now vgpu %d will enter failsafe mode.\n", vgpu->id); 191 vgpu->failsafe = true; 192 } 193 194 static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu, 195 unsigned int fence_num, void *p_data, unsigned int bytes) 196 { 197 unsigned int max_fence = vgpu_fence_sz(vgpu); 198 199 if (fence_num >= max_fence) { 200 gvt_vgpu_err("access oob fence reg %d/%d\n", 201 fence_num, max_fence); 202 203 /* When guest access oob fence regs without access 204 * pv_info first, we treat guest not supporting GVT, 205 * and we will let vgpu enter failsafe mode. 206 */ 207 if (!vgpu->pv_notified) 208 enter_failsafe_mode(vgpu, 209 GVT_FAILSAFE_UNSUPPORTED_GUEST); 210 211 memset(p_data, 0, bytes); 212 return -EINVAL; 213 } 214 return 0; 215 } 216 217 static int gamw_echo_dev_rw_ia_write(struct intel_vgpu *vgpu, 218 unsigned int offset, void *p_data, unsigned int bytes) 219 { 220 u32 ips = (*(u32 *)p_data) & GAMW_ECO_ENABLE_64K_IPS_FIELD; 221 222 if (INTEL_GEN(vgpu->gvt->gt->i915) <= 10) { 223 if (ips == GAMW_ECO_ENABLE_64K_IPS_FIELD) 224 gvt_dbg_core("vgpu%d: ips enabled\n", vgpu->id); 225 else if (!ips) 226 gvt_dbg_core("vgpu%d: ips disabled\n", vgpu->id); 227 else { 228 /* All engines must be enabled together for vGPU, 229 * since we don't know which engine the ppgtt will 230 * bind to when shadowing. 231 */ 232 gvt_vgpu_err("Unsupported IPS setting %x, cannot enable 64K gtt.\n", 233 ips); 234 return -EINVAL; 235 } 236 } 237 238 write_vreg(vgpu, offset, p_data, bytes); 239 return 0; 240 } 241 242 static int fence_mmio_read(struct intel_vgpu *vgpu, unsigned int off, 243 void *p_data, unsigned int bytes) 244 { 245 int ret; 246 247 ret = sanitize_fence_mmio_access(vgpu, offset_to_fence_num(off), 248 p_data, bytes); 249 if (ret) 250 return ret; 251 read_vreg(vgpu, off, p_data, bytes); 252 return 0; 253 } 254 255 static int fence_mmio_write(struct intel_vgpu *vgpu, unsigned int off, 256 void *p_data, unsigned int bytes) 257 { 258 struct intel_gvt *gvt = vgpu->gvt; 259 unsigned int fence_num = offset_to_fence_num(off); 260 int ret; 261 262 ret = sanitize_fence_mmio_access(vgpu, fence_num, p_data, bytes); 263 if (ret) 264 return ret; 265 write_vreg(vgpu, off, p_data, bytes); 266 267 mmio_hw_access_pre(gvt->gt); 268 intel_vgpu_write_fence(vgpu, fence_num, 269 vgpu_vreg64(vgpu, fence_num_to_offset(fence_num))); 270 mmio_hw_access_post(gvt->gt); 271 return 0; 272 } 273 274 #define CALC_MODE_MASK_REG(old, new) \ 275 (((new) & GENMASK(31, 16)) \ 276 | ((((old) & GENMASK(15, 0)) & ~((new) >> 16)) \ 277 | ((new) & ((new) >> 16)))) 278 279 static int mul_force_wake_write(struct intel_vgpu *vgpu, 280 unsigned int offset, void *p_data, unsigned int bytes) 281 { 282 u32 old, new; 283 u32 ack_reg_offset; 284 285 old = vgpu_vreg(vgpu, offset); 286 new = CALC_MODE_MASK_REG(old, *(u32 *)p_data); 287 288 if (INTEL_GEN(vgpu->gvt->gt->i915) >= 9) { 289 switch (offset) { 290 case FORCEWAKE_RENDER_GEN9_REG: 291 ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG; 292 break; 293 case FORCEWAKE_BLITTER_GEN9_REG: 294 ack_reg_offset = FORCEWAKE_ACK_BLITTER_GEN9_REG; 295 break; 296 case FORCEWAKE_MEDIA_GEN9_REG: 297 ack_reg_offset = FORCEWAKE_ACK_MEDIA_GEN9_REG; 298 break; 299 default: 300 /*should not hit here*/ 301 gvt_vgpu_err("invalid forcewake offset 0x%x\n", offset); 302 return -EINVAL; 303 } 304 } else { 305 ack_reg_offset = FORCEWAKE_ACK_HSW_REG; 306 } 307 308 vgpu_vreg(vgpu, offset) = new; 309 vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0)); 310 return 0; 311 } 312 313 static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 314 void *p_data, unsigned int bytes) 315 { 316 intel_engine_mask_t engine_mask = 0; 317 u32 data; 318 319 write_vreg(vgpu, offset, p_data, bytes); 320 data = vgpu_vreg(vgpu, offset); 321 322 if (data & GEN6_GRDOM_FULL) { 323 gvt_dbg_mmio("vgpu%d: request full GPU reset\n", vgpu->id); 324 engine_mask = ALL_ENGINES; 325 } else { 326 if (data & GEN6_GRDOM_RENDER) { 327 gvt_dbg_mmio("vgpu%d: request RCS reset\n", vgpu->id); 328 engine_mask |= BIT(RCS0); 329 } 330 if (data & GEN6_GRDOM_MEDIA) { 331 gvt_dbg_mmio("vgpu%d: request VCS reset\n", vgpu->id); 332 engine_mask |= BIT(VCS0); 333 } 334 if (data & GEN6_GRDOM_BLT) { 335 gvt_dbg_mmio("vgpu%d: request BCS Reset\n", vgpu->id); 336 engine_mask |= BIT(BCS0); 337 } 338 if (data & GEN6_GRDOM_VECS) { 339 gvt_dbg_mmio("vgpu%d: request VECS Reset\n", vgpu->id); 340 engine_mask |= BIT(VECS0); 341 } 342 if (data & GEN8_GRDOM_MEDIA2) { 343 gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id); 344 engine_mask |= BIT(VCS1); 345 } 346 if (data & GEN9_GRDOM_GUC) { 347 gvt_dbg_mmio("vgpu%d: request GUC Reset\n", vgpu->id); 348 vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET; 349 } 350 engine_mask &= INTEL_INFO(vgpu->gvt->gt->i915)->engine_mask; 351 } 352 353 /* vgpu_lock already hold by emulate mmio r/w */ 354 intel_gvt_reset_vgpu_locked(vgpu, false, engine_mask); 355 356 /* sw will wait for the device to ack the reset request */ 357 vgpu_vreg(vgpu, offset) = 0; 358 359 return 0; 360 } 361 362 static int gmbus_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 363 void *p_data, unsigned int bytes) 364 { 365 return intel_gvt_i2c_handle_gmbus_read(vgpu, offset, p_data, bytes); 366 } 367 368 static int gmbus_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 369 void *p_data, unsigned int bytes) 370 { 371 return intel_gvt_i2c_handle_gmbus_write(vgpu, offset, p_data, bytes); 372 } 373 374 static int pch_pp_control_mmio_write(struct intel_vgpu *vgpu, 375 unsigned int offset, void *p_data, unsigned int bytes) 376 { 377 write_vreg(vgpu, offset, p_data, bytes); 378 379 if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) { 380 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_ON; 381 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE; 382 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN; 383 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE; 384 385 } else 386 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= 387 ~(PP_ON | PP_SEQUENCE_POWER_DOWN 388 | PP_CYCLE_DELAY_ACTIVE); 389 return 0; 390 } 391 392 static int transconf_mmio_write(struct intel_vgpu *vgpu, 393 unsigned int offset, void *p_data, unsigned int bytes) 394 { 395 write_vreg(vgpu, offset, p_data, bytes); 396 397 if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE) 398 vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE; 399 else 400 vgpu_vreg(vgpu, offset) &= ~TRANS_STATE_ENABLE; 401 return 0; 402 } 403 404 static int lcpll_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 405 void *p_data, unsigned int bytes) 406 { 407 write_vreg(vgpu, offset, p_data, bytes); 408 409 if (vgpu_vreg(vgpu, offset) & LCPLL_PLL_DISABLE) 410 vgpu_vreg(vgpu, offset) &= ~LCPLL_PLL_LOCK; 411 else 412 vgpu_vreg(vgpu, offset) |= LCPLL_PLL_LOCK; 413 414 if (vgpu_vreg(vgpu, offset) & LCPLL_CD_SOURCE_FCLK) 415 vgpu_vreg(vgpu, offset) |= LCPLL_CD_SOURCE_FCLK_DONE; 416 else 417 vgpu_vreg(vgpu, offset) &= ~LCPLL_CD_SOURCE_FCLK_DONE; 418 419 return 0; 420 } 421 422 static int dpy_reg_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 423 void *p_data, unsigned int bytes) 424 { 425 switch (offset) { 426 case 0xe651c: 427 case 0xe661c: 428 case 0xe671c: 429 case 0xe681c: 430 vgpu_vreg(vgpu, offset) = 1 << 17; 431 break; 432 case 0xe6c04: 433 vgpu_vreg(vgpu, offset) = 0x3; 434 break; 435 case 0xe6e1c: 436 vgpu_vreg(vgpu, offset) = 0x2f << 16; 437 break; 438 default: 439 return -EINVAL; 440 } 441 442 read_vreg(vgpu, offset, p_data, bytes); 443 return 0; 444 } 445 446 static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 447 void *p_data, unsigned int bytes) 448 { 449 u32 data; 450 451 write_vreg(vgpu, offset, p_data, bytes); 452 data = vgpu_vreg(vgpu, offset); 453 454 if (data & PIPECONF_ENABLE) 455 vgpu_vreg(vgpu, offset) |= I965_PIPECONF_ACTIVE; 456 else 457 vgpu_vreg(vgpu, offset) &= ~I965_PIPECONF_ACTIVE; 458 /* vgpu_lock already hold by emulate mmio r/w */ 459 mutex_unlock(&vgpu->vgpu_lock); 460 intel_gvt_check_vblank_emulation(vgpu->gvt); 461 mutex_lock(&vgpu->vgpu_lock); 462 return 0; 463 } 464 465 /* ascendingly sorted */ 466 static i915_reg_t force_nonpriv_white_list[] = { 467 GEN9_CS_DEBUG_MODE1, //_MMIO(0x20ec) 468 GEN9_CTX_PREEMPT_REG,//_MMIO(0x2248) 469 PS_INVOCATION_COUNT,//_MMIO(0x2348) 470 GEN8_CS_CHICKEN1,//_MMIO(0x2580) 471 _MMIO(0x2690), 472 _MMIO(0x2694), 473 _MMIO(0x2698), 474 _MMIO(0x2754), 475 _MMIO(0x28a0), 476 _MMIO(0x4de0), 477 _MMIO(0x4de4), 478 _MMIO(0x4dfc), 479 GEN7_COMMON_SLICE_CHICKEN1,//_MMIO(0x7010) 480 _MMIO(0x7014), 481 HDC_CHICKEN0,//_MMIO(0x7300) 482 GEN8_HDC_CHICKEN1,//_MMIO(0x7304) 483 _MMIO(0x7700), 484 _MMIO(0x7704), 485 _MMIO(0x7708), 486 _MMIO(0x770c), 487 _MMIO(0x83a8), 488 _MMIO(0xb110), 489 GEN8_L3SQCREG4,//_MMIO(0xb118) 490 _MMIO(0xe100), 491 _MMIO(0xe18c), 492 _MMIO(0xe48c), 493 _MMIO(0xe5f4), 494 }; 495 496 /* a simple bsearch */ 497 static inline bool in_whitelist(u32 reg) 498 { 499 int left = 0, right = ARRAY_SIZE(force_nonpriv_white_list); 500 i915_reg_t *array = force_nonpriv_white_list; 501 502 while (left < right) { 503 int mid = (left + right)/2; 504 505 if (reg > array[mid].reg) 506 left = mid + 1; 507 else if (reg < array[mid].reg) 508 right = mid; 509 else 510 return true; 511 } 512 return false; 513 } 514 515 static int force_nonpriv_write(struct intel_vgpu *vgpu, 516 unsigned int offset, void *p_data, unsigned int bytes) 517 { 518 u32 reg_nonpriv = (*(u32 *)p_data) & REG_GENMASK(25, 2); 519 const struct intel_engine_cs *engine = 520 intel_gvt_render_mmio_to_engine(vgpu->gvt, offset); 521 522 if (bytes != 4 || !IS_ALIGNED(offset, bytes) || !engine) { 523 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV offset %x(%dB)\n", 524 vgpu->id, offset, bytes); 525 return -EINVAL; 526 } 527 528 if (!in_whitelist(reg_nonpriv) && 529 reg_nonpriv != i915_mmio_reg_offset(RING_NOPID(engine->mmio_base))) { 530 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x at offset %x\n", 531 vgpu->id, reg_nonpriv, offset); 532 } else 533 intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes); 534 535 return 0; 536 } 537 538 static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 539 void *p_data, unsigned int bytes) 540 { 541 write_vreg(vgpu, offset, p_data, bytes); 542 543 if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) { 544 vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE; 545 } else { 546 vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE; 547 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E))) 548 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) 549 &= ~DP_TP_STATUS_AUTOTRAIN_DONE; 550 } 551 return 0; 552 } 553 554 static int fdi_rx_iir_mmio_write(struct intel_vgpu *vgpu, 555 unsigned int offset, void *p_data, unsigned int bytes) 556 { 557 vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data; 558 return 0; 559 } 560 561 #define FDI_LINK_TRAIN_PATTERN1 0 562 #define FDI_LINK_TRAIN_PATTERN2 1 563 564 static int fdi_auto_training_started(struct intel_vgpu *vgpu) 565 { 566 u32 ddi_buf_ctl = vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_E)); 567 u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL); 568 u32 tx_ctl = vgpu_vreg_t(vgpu, DP_TP_CTL(PORT_E)); 569 570 if ((ddi_buf_ctl & DDI_BUF_CTL_ENABLE) && 571 (rx_ctl & FDI_RX_ENABLE) && 572 (rx_ctl & FDI_AUTO_TRAINING) && 573 (tx_ctl & DP_TP_CTL_ENABLE) && 574 (tx_ctl & DP_TP_CTL_FDI_AUTOTRAIN)) 575 return 1; 576 else 577 return 0; 578 } 579 580 static int check_fdi_rx_train_status(struct intel_vgpu *vgpu, 581 enum pipe pipe, unsigned int train_pattern) 582 { 583 i915_reg_t fdi_rx_imr, fdi_tx_ctl, fdi_rx_ctl; 584 unsigned int fdi_rx_check_bits, fdi_tx_check_bits; 585 unsigned int fdi_rx_train_bits, fdi_tx_train_bits; 586 unsigned int fdi_iir_check_bits; 587 588 fdi_rx_imr = FDI_RX_IMR(pipe); 589 fdi_tx_ctl = FDI_TX_CTL(pipe); 590 fdi_rx_ctl = FDI_RX_CTL(pipe); 591 592 if (train_pattern == FDI_LINK_TRAIN_PATTERN1) { 593 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_1_CPT; 594 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_1; 595 fdi_iir_check_bits = FDI_RX_BIT_LOCK; 596 } else if (train_pattern == FDI_LINK_TRAIN_PATTERN2) { 597 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_2_CPT; 598 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_2; 599 fdi_iir_check_bits = FDI_RX_SYMBOL_LOCK; 600 } else { 601 gvt_vgpu_err("Invalid train pattern %d\n", train_pattern); 602 return -EINVAL; 603 } 604 605 fdi_rx_check_bits = FDI_RX_ENABLE | fdi_rx_train_bits; 606 fdi_tx_check_bits = FDI_TX_ENABLE | fdi_tx_train_bits; 607 608 /* If imr bit has been masked */ 609 if (vgpu_vreg_t(vgpu, fdi_rx_imr) & fdi_iir_check_bits) 610 return 0; 611 612 if (((vgpu_vreg_t(vgpu, fdi_tx_ctl) & fdi_tx_check_bits) 613 == fdi_tx_check_bits) 614 && ((vgpu_vreg_t(vgpu, fdi_rx_ctl) & fdi_rx_check_bits) 615 == fdi_rx_check_bits)) 616 return 1; 617 else 618 return 0; 619 } 620 621 #define INVALID_INDEX (~0U) 622 623 static unsigned int calc_index(unsigned int offset, unsigned int start, 624 unsigned int next, unsigned int end, i915_reg_t i915_end) 625 { 626 unsigned int range = next - start; 627 628 if (!end) 629 end = i915_mmio_reg_offset(i915_end); 630 if (offset < start || offset > end) 631 return INVALID_INDEX; 632 offset -= start; 633 return offset / range; 634 } 635 636 #define FDI_RX_CTL_TO_PIPE(offset) \ 637 calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, 0, FDI_RX_CTL(PIPE_C)) 638 639 #define FDI_TX_CTL_TO_PIPE(offset) \ 640 calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, 0, FDI_TX_CTL(PIPE_C)) 641 642 #define FDI_RX_IMR_TO_PIPE(offset) \ 643 calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, 0, FDI_RX_IMR(PIPE_C)) 644 645 static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu, 646 unsigned int offset, void *p_data, unsigned int bytes) 647 { 648 i915_reg_t fdi_rx_iir; 649 unsigned int index; 650 int ret; 651 652 if (FDI_RX_CTL_TO_PIPE(offset) != INVALID_INDEX) 653 index = FDI_RX_CTL_TO_PIPE(offset); 654 else if (FDI_TX_CTL_TO_PIPE(offset) != INVALID_INDEX) 655 index = FDI_TX_CTL_TO_PIPE(offset); 656 else if (FDI_RX_IMR_TO_PIPE(offset) != INVALID_INDEX) 657 index = FDI_RX_IMR_TO_PIPE(offset); 658 else { 659 gvt_vgpu_err("Unsupport registers %x\n", offset); 660 return -EINVAL; 661 } 662 663 write_vreg(vgpu, offset, p_data, bytes); 664 665 fdi_rx_iir = FDI_RX_IIR(index); 666 667 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN1); 668 if (ret < 0) 669 return ret; 670 if (ret) 671 vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK; 672 673 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN2); 674 if (ret < 0) 675 return ret; 676 if (ret) 677 vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK; 678 679 if (offset == _FDI_RXA_CTL) 680 if (fdi_auto_training_started(vgpu)) 681 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) |= 682 DP_TP_STATUS_AUTOTRAIN_DONE; 683 return 0; 684 } 685 686 #define DP_TP_CTL_TO_PORT(offset) \ 687 calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, 0, DP_TP_CTL(PORT_E)) 688 689 static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 690 void *p_data, unsigned int bytes) 691 { 692 i915_reg_t status_reg; 693 unsigned int index; 694 u32 data; 695 696 write_vreg(vgpu, offset, p_data, bytes); 697 698 index = DP_TP_CTL_TO_PORT(offset); 699 data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8; 700 if (data == 0x2) { 701 status_reg = DP_TP_STATUS(index); 702 vgpu_vreg_t(vgpu, status_reg) |= (1 << 25); 703 } 704 return 0; 705 } 706 707 static int dp_tp_status_mmio_write(struct intel_vgpu *vgpu, 708 unsigned int offset, void *p_data, unsigned int bytes) 709 { 710 u32 reg_val; 711 u32 sticky_mask; 712 713 reg_val = *((u32 *)p_data); 714 sticky_mask = GENMASK(27, 26) | (1 << 24); 715 716 vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) | 717 (vgpu_vreg(vgpu, offset) & sticky_mask); 718 vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask); 719 return 0; 720 } 721 722 static int pch_adpa_mmio_write(struct intel_vgpu *vgpu, 723 unsigned int offset, void *p_data, unsigned int bytes) 724 { 725 u32 data; 726 727 write_vreg(vgpu, offset, p_data, bytes); 728 data = vgpu_vreg(vgpu, offset); 729 730 if (data & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) 731 vgpu_vreg(vgpu, offset) &= ~ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 732 return 0; 733 } 734 735 static int south_chicken2_mmio_write(struct intel_vgpu *vgpu, 736 unsigned int offset, void *p_data, unsigned int bytes) 737 { 738 u32 data; 739 740 write_vreg(vgpu, offset, p_data, bytes); 741 data = vgpu_vreg(vgpu, offset); 742 743 if (data & FDI_MPHY_IOSFSB_RESET_CTL) 744 vgpu_vreg(vgpu, offset) |= FDI_MPHY_IOSFSB_RESET_STATUS; 745 else 746 vgpu_vreg(vgpu, offset) &= ~FDI_MPHY_IOSFSB_RESET_STATUS; 747 return 0; 748 } 749 750 #define DSPSURF_TO_PIPE(offset) \ 751 calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C)) 752 753 static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 754 void *p_data, unsigned int bytes) 755 { 756 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 757 u32 pipe = DSPSURF_TO_PIPE(offset); 758 int event = SKL_FLIP_EVENT(pipe, PLANE_PRIMARY); 759 760 write_vreg(vgpu, offset, p_data, bytes); 761 vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); 762 763 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++; 764 765 if (vgpu_vreg_t(vgpu, DSPCNTR(pipe)) & PLANE_CTL_ASYNC_FLIP) 766 intel_vgpu_trigger_virtual_event(vgpu, event); 767 else 768 set_bit(event, vgpu->irq.flip_done_event[pipe]); 769 770 return 0; 771 } 772 773 #define SPRSURF_TO_PIPE(offset) \ 774 calc_index(offset, _SPRA_SURF, _SPRB_SURF, 0, SPRSURF(PIPE_C)) 775 776 static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 777 void *p_data, unsigned int bytes) 778 { 779 u32 pipe = SPRSURF_TO_PIPE(offset); 780 int event = SKL_FLIP_EVENT(pipe, PLANE_SPRITE0); 781 782 write_vreg(vgpu, offset, p_data, bytes); 783 vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); 784 785 if (vgpu_vreg_t(vgpu, SPRCTL(pipe)) & PLANE_CTL_ASYNC_FLIP) 786 intel_vgpu_trigger_virtual_event(vgpu, event); 787 else 788 set_bit(event, vgpu->irq.flip_done_event[pipe]); 789 790 return 0; 791 } 792 793 static int reg50080_mmio_write(struct intel_vgpu *vgpu, 794 unsigned int offset, void *p_data, 795 unsigned int bytes) 796 { 797 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 798 enum pipe pipe = REG_50080_TO_PIPE(offset); 799 enum plane_id plane = REG_50080_TO_PLANE(offset); 800 int event = SKL_FLIP_EVENT(pipe, plane); 801 802 write_vreg(vgpu, offset, p_data, bytes); 803 if (plane == PLANE_PRIMARY) { 804 vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); 805 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++; 806 } else { 807 vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); 808 } 809 810 if ((vgpu_vreg(vgpu, offset) & REG50080_FLIP_TYPE_MASK) == REG50080_FLIP_TYPE_ASYNC) 811 intel_vgpu_trigger_virtual_event(vgpu, event); 812 else 813 set_bit(event, vgpu->irq.flip_done_event[pipe]); 814 815 return 0; 816 } 817 818 static int trigger_aux_channel_interrupt(struct intel_vgpu *vgpu, 819 unsigned int reg) 820 { 821 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 822 enum intel_gvt_event_type event; 823 824 if (reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_A))) 825 event = AUX_CHANNEL_A; 826 else if (reg == _PCH_DPB_AUX_CH_CTL || 827 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_B))) 828 event = AUX_CHANNEL_B; 829 else if (reg == _PCH_DPC_AUX_CH_CTL || 830 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_C))) 831 event = AUX_CHANNEL_C; 832 else if (reg == _PCH_DPD_AUX_CH_CTL || 833 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_D))) 834 event = AUX_CHANNEL_D; 835 else { 836 drm_WARN_ON(&dev_priv->drm, true); 837 return -EINVAL; 838 } 839 840 intel_vgpu_trigger_virtual_event(vgpu, event); 841 return 0; 842 } 843 844 static int dp_aux_ch_ctl_trans_done(struct intel_vgpu *vgpu, u32 value, 845 unsigned int reg, int len, bool data_valid) 846 { 847 /* mark transaction done */ 848 value |= DP_AUX_CH_CTL_DONE; 849 value &= ~DP_AUX_CH_CTL_SEND_BUSY; 850 value &= ~DP_AUX_CH_CTL_RECEIVE_ERROR; 851 852 if (data_valid) 853 value &= ~DP_AUX_CH_CTL_TIME_OUT_ERROR; 854 else 855 value |= DP_AUX_CH_CTL_TIME_OUT_ERROR; 856 857 /* message size */ 858 value &= ~(0xf << 20); 859 value |= (len << 20); 860 vgpu_vreg(vgpu, reg) = value; 861 862 if (value & DP_AUX_CH_CTL_INTERRUPT) 863 return trigger_aux_channel_interrupt(vgpu, reg); 864 return 0; 865 } 866 867 static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd, 868 u8 t) 869 { 870 if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == DPCD_TRAINING_PATTERN_1) { 871 /* training pattern 1 for CR */ 872 /* set LANE0_CR_DONE, LANE1_CR_DONE */ 873 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_CR_DONE; 874 /* set LANE2_CR_DONE, LANE3_CR_DONE */ 875 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_CR_DONE; 876 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == 877 DPCD_TRAINING_PATTERN_2) { 878 /* training pattern 2 for EQ */ 879 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane0_1 */ 880 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_EQ_DONE; 881 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_SYMBOL_LOCKED; 882 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane2_3 */ 883 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_EQ_DONE; 884 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_SYMBOL_LOCKED; 885 /* set INTERLANE_ALIGN_DONE */ 886 dpcd->data[DPCD_LANE_ALIGN_STATUS_UPDATED] |= 887 DPCD_INTERLANE_ALIGN_DONE; 888 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == 889 DPCD_LINK_TRAINING_DISABLED) { 890 /* finish link training */ 891 /* set sink status as synchronized */ 892 dpcd->data[DPCD_SINK_STATUS] = DPCD_SINK_IN_SYNC; 893 } 894 } 895 896 #define _REG_HSW_DP_AUX_CH_CTL(dp) \ 897 ((dp) ? (_PCH_DPB_AUX_CH_CTL + ((dp)-1)*0x100) : 0x64010) 898 899 #define _REG_SKL_DP_AUX_CH_CTL(dp) (0x64010 + (dp) * 0x100) 900 901 #define OFFSET_TO_DP_AUX_PORT(offset) (((offset) & 0xF00) >> 8) 902 903 #define dpy_is_valid_port(port) \ 904 (((port) >= PORT_A) && ((port) < I915_MAX_PORTS)) 905 906 static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu, 907 unsigned int offset, void *p_data, unsigned int bytes) 908 { 909 struct intel_vgpu_display *display = &vgpu->display; 910 int msg, addr, ctrl, op, len; 911 int port_index = OFFSET_TO_DP_AUX_PORT(offset); 912 struct intel_vgpu_dpcd_data *dpcd = NULL; 913 struct intel_vgpu_port *port = NULL; 914 u32 data; 915 916 if (!dpy_is_valid_port(port_index)) { 917 gvt_vgpu_err("Unsupported DP port access!\n"); 918 return 0; 919 } 920 921 write_vreg(vgpu, offset, p_data, bytes); 922 data = vgpu_vreg(vgpu, offset); 923 924 if ((INTEL_GEN(vgpu->gvt->gt->i915) >= 9) 925 && offset != _REG_SKL_DP_AUX_CH_CTL(port_index)) { 926 /* SKL DPB/C/D aux ctl register changed */ 927 return 0; 928 } else if (IS_BROADWELL(vgpu->gvt->gt->i915) && 929 offset != _REG_HSW_DP_AUX_CH_CTL(port_index)) { 930 /* write to the data registers */ 931 return 0; 932 } 933 934 if (!(data & DP_AUX_CH_CTL_SEND_BUSY)) { 935 /* just want to clear the sticky bits */ 936 vgpu_vreg(vgpu, offset) = 0; 937 return 0; 938 } 939 940 port = &display->ports[port_index]; 941 dpcd = port->dpcd; 942 943 /* read out message from DATA1 register */ 944 msg = vgpu_vreg(vgpu, offset + 4); 945 addr = (msg >> 8) & 0xffff; 946 ctrl = (msg >> 24) & 0xff; 947 len = msg & 0xff; 948 op = ctrl >> 4; 949 950 if (op == GVT_AUX_NATIVE_WRITE) { 951 int t; 952 u8 buf[16]; 953 954 if ((addr + len + 1) >= DPCD_SIZE) { 955 /* 956 * Write request exceeds what we supported, 957 * DCPD spec: When a Source Device is writing a DPCD 958 * address not supported by the Sink Device, the Sink 959 * Device shall reply with AUX NACK and “M” equal to 960 * zero. 961 */ 962 963 /* NAK the write */ 964 vgpu_vreg(vgpu, offset + 4) = AUX_NATIVE_REPLY_NAK; 965 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 2, true); 966 return 0; 967 } 968 969 /* 970 * Write request format: Headr (command + address + size) occupies 971 * 4 bytes, followed by (len + 1) bytes of data. See details at 972 * intel_dp_aux_transfer(). 973 */ 974 if ((len + 1 + 4) > AUX_BURST_SIZE) { 975 gvt_vgpu_err("dp_aux_header: len %d is too large\n", len); 976 return -EINVAL; 977 } 978 979 /* unpack data from vreg to buf */ 980 for (t = 0; t < 4; t++) { 981 u32 r = vgpu_vreg(vgpu, offset + 8 + t * 4); 982 983 buf[t * 4] = (r >> 24) & 0xff; 984 buf[t * 4 + 1] = (r >> 16) & 0xff; 985 buf[t * 4 + 2] = (r >> 8) & 0xff; 986 buf[t * 4 + 3] = r & 0xff; 987 } 988 989 /* write to virtual DPCD */ 990 if (dpcd && dpcd->data_valid) { 991 for (t = 0; t <= len; t++) { 992 int p = addr + t; 993 994 dpcd->data[p] = buf[t]; 995 /* check for link training */ 996 if (p == DPCD_TRAINING_PATTERN_SET) 997 dp_aux_ch_ctl_link_training(dpcd, 998 buf[t]); 999 } 1000 } 1001 1002 /* ACK the write */ 1003 vgpu_vreg(vgpu, offset + 4) = 0; 1004 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 1, 1005 dpcd && dpcd->data_valid); 1006 return 0; 1007 } 1008 1009 if (op == GVT_AUX_NATIVE_READ) { 1010 int idx, i, ret = 0; 1011 1012 if ((addr + len + 1) >= DPCD_SIZE) { 1013 /* 1014 * read request exceeds what we supported 1015 * DPCD spec: A Sink Device receiving a Native AUX CH 1016 * read request for an unsupported DPCD address must 1017 * reply with an AUX ACK and read data set equal to 1018 * zero instead of replying with AUX NACK. 1019 */ 1020 1021 /* ACK the READ*/ 1022 vgpu_vreg(vgpu, offset + 4) = 0; 1023 vgpu_vreg(vgpu, offset + 8) = 0; 1024 vgpu_vreg(vgpu, offset + 12) = 0; 1025 vgpu_vreg(vgpu, offset + 16) = 0; 1026 vgpu_vreg(vgpu, offset + 20) = 0; 1027 1028 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2, 1029 true); 1030 return 0; 1031 } 1032 1033 for (idx = 1; idx <= 5; idx++) { 1034 /* clear the data registers */ 1035 vgpu_vreg(vgpu, offset + 4 * idx) = 0; 1036 } 1037 1038 /* 1039 * Read reply format: ACK (1 byte) plus (len + 1) bytes of data. 1040 */ 1041 if ((len + 2) > AUX_BURST_SIZE) { 1042 gvt_vgpu_err("dp_aux_header: len %d is too large\n", len); 1043 return -EINVAL; 1044 } 1045 1046 /* read from virtual DPCD to vreg */ 1047 /* first 4 bytes: [ACK][addr][addr+1][addr+2] */ 1048 if (dpcd && dpcd->data_valid) { 1049 for (i = 1; i <= (len + 1); i++) { 1050 int t; 1051 1052 t = dpcd->data[addr + i - 1]; 1053 t <<= (24 - 8 * (i % 4)); 1054 ret |= t; 1055 1056 if ((i % 4 == 3) || (i == (len + 1))) { 1057 vgpu_vreg(vgpu, offset + 1058 (i / 4 + 1) * 4) = ret; 1059 ret = 0; 1060 } 1061 } 1062 } 1063 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2, 1064 dpcd && dpcd->data_valid); 1065 return 0; 1066 } 1067 1068 /* i2c transaction starts */ 1069 intel_gvt_i2c_handle_aux_ch_write(vgpu, port_index, offset, p_data); 1070 1071 if (data & DP_AUX_CH_CTL_INTERRUPT) 1072 trigger_aux_channel_interrupt(vgpu, offset); 1073 return 0; 1074 } 1075 1076 static int mbctl_write(struct intel_vgpu *vgpu, unsigned int offset, 1077 void *p_data, unsigned int bytes) 1078 { 1079 *(u32 *)p_data &= (~GEN6_MBCTL_ENABLE_BOOT_FETCH); 1080 write_vreg(vgpu, offset, p_data, bytes); 1081 return 0; 1082 } 1083 1084 static int vga_control_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1085 void *p_data, unsigned int bytes) 1086 { 1087 bool vga_disable; 1088 1089 write_vreg(vgpu, offset, p_data, bytes); 1090 vga_disable = vgpu_vreg(vgpu, offset) & VGA_DISP_DISABLE; 1091 1092 gvt_dbg_core("vgpu%d: %s VGA mode\n", vgpu->id, 1093 vga_disable ? "Disable" : "Enable"); 1094 return 0; 1095 } 1096 1097 static u32 read_virtual_sbi_register(struct intel_vgpu *vgpu, 1098 unsigned int sbi_offset) 1099 { 1100 struct intel_vgpu_display *display = &vgpu->display; 1101 int num = display->sbi.number; 1102 int i; 1103 1104 for (i = 0; i < num; ++i) 1105 if (display->sbi.registers[i].offset == sbi_offset) 1106 break; 1107 1108 if (i == num) 1109 return 0; 1110 1111 return display->sbi.registers[i].value; 1112 } 1113 1114 static void write_virtual_sbi_register(struct intel_vgpu *vgpu, 1115 unsigned int offset, u32 value) 1116 { 1117 struct intel_vgpu_display *display = &vgpu->display; 1118 int num = display->sbi.number; 1119 int i; 1120 1121 for (i = 0; i < num; ++i) { 1122 if (display->sbi.registers[i].offset == offset) 1123 break; 1124 } 1125 1126 if (i == num) { 1127 if (num == SBI_REG_MAX) { 1128 gvt_vgpu_err("SBI caching meets maximum limits\n"); 1129 return; 1130 } 1131 display->sbi.number++; 1132 } 1133 1134 display->sbi.registers[i].offset = offset; 1135 display->sbi.registers[i].value = value; 1136 } 1137 1138 static int sbi_data_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 1139 void *p_data, unsigned int bytes) 1140 { 1141 if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> 1142 SBI_OPCODE_SHIFT) == SBI_CMD_CRRD) { 1143 unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) & 1144 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; 1145 vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu, 1146 sbi_offset); 1147 } 1148 read_vreg(vgpu, offset, p_data, bytes); 1149 return 0; 1150 } 1151 1152 static int sbi_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1153 void *p_data, unsigned int bytes) 1154 { 1155 u32 data; 1156 1157 write_vreg(vgpu, offset, p_data, bytes); 1158 data = vgpu_vreg(vgpu, offset); 1159 1160 data &= ~(SBI_STAT_MASK << SBI_STAT_SHIFT); 1161 data |= SBI_READY; 1162 1163 data &= ~(SBI_RESPONSE_MASK << SBI_RESPONSE_SHIFT); 1164 data |= SBI_RESPONSE_SUCCESS; 1165 1166 vgpu_vreg(vgpu, offset) = data; 1167 1168 if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> 1169 SBI_OPCODE_SHIFT) == SBI_CMD_CRWR) { 1170 unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) & 1171 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; 1172 1173 write_virtual_sbi_register(vgpu, sbi_offset, 1174 vgpu_vreg_t(vgpu, SBI_DATA)); 1175 } 1176 return 0; 1177 } 1178 1179 #define _vgtif_reg(x) \ 1180 (VGT_PVINFO_PAGE + offsetof(struct vgt_if, x)) 1181 1182 static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 1183 void *p_data, unsigned int bytes) 1184 { 1185 bool invalid_read = false; 1186 1187 read_vreg(vgpu, offset, p_data, bytes); 1188 1189 switch (offset) { 1190 case _vgtif_reg(magic) ... _vgtif_reg(vgt_id): 1191 if (offset + bytes > _vgtif_reg(vgt_id) + 4) 1192 invalid_read = true; 1193 break; 1194 case _vgtif_reg(avail_rs.mappable_gmadr.base) ... 1195 _vgtif_reg(avail_rs.fence_num): 1196 if (offset + bytes > 1197 _vgtif_reg(avail_rs.fence_num) + 4) 1198 invalid_read = true; 1199 break; 1200 case 0x78010: /* vgt_caps */ 1201 case 0x7881c: 1202 break; 1203 default: 1204 invalid_read = true; 1205 break; 1206 } 1207 if (invalid_read) 1208 gvt_vgpu_err("invalid pvinfo read: [%x:%x] = %x\n", 1209 offset, bytes, *(u32 *)p_data); 1210 vgpu->pv_notified = true; 1211 return 0; 1212 } 1213 1214 static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification) 1215 { 1216 enum intel_gvt_gtt_type root_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY; 1217 struct intel_vgpu_mm *mm; 1218 u64 *pdps; 1219 1220 pdps = (u64 *)&vgpu_vreg64_t(vgpu, vgtif_reg(pdp[0])); 1221 1222 switch (notification) { 1223 case VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE: 1224 root_entry_type = GTT_TYPE_PPGTT_ROOT_L3_ENTRY; 1225 /* fall through */ 1226 case VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE: 1227 mm = intel_vgpu_get_ppgtt_mm(vgpu, root_entry_type, pdps); 1228 return PTR_ERR_OR_ZERO(mm); 1229 case VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY: 1230 case VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY: 1231 return intel_vgpu_put_ppgtt_mm(vgpu, pdps); 1232 case VGT_G2V_EXECLIST_CONTEXT_CREATE: 1233 case VGT_G2V_EXECLIST_CONTEXT_DESTROY: 1234 case 1: /* Remove this in guest driver. */ 1235 break; 1236 default: 1237 gvt_vgpu_err("Invalid PV notification %d\n", notification); 1238 } 1239 return 0; 1240 } 1241 1242 static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready) 1243 { 1244 struct kobject *kobj = &vgpu->gvt->gt->i915->drm.primary->kdev->kobj; 1245 char *env[3] = {NULL, NULL, NULL}; 1246 char vmid_str[20]; 1247 char display_ready_str[20]; 1248 1249 snprintf(display_ready_str, 20, "GVT_DISPLAY_READY=%d", ready); 1250 env[0] = display_ready_str; 1251 1252 snprintf(vmid_str, 20, "VMID=%d", vgpu->id); 1253 env[1] = vmid_str; 1254 1255 return kobject_uevent_env(kobj, KOBJ_ADD, env); 1256 } 1257 1258 static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1259 void *p_data, unsigned int bytes) 1260 { 1261 u32 data = *(u32 *)p_data; 1262 bool invalid_write = false; 1263 1264 switch (offset) { 1265 case _vgtif_reg(display_ready): 1266 send_display_ready_uevent(vgpu, data ? 1 : 0); 1267 break; 1268 case _vgtif_reg(g2v_notify): 1269 handle_g2v_notification(vgpu, data); 1270 break; 1271 /* add xhot and yhot to handled list to avoid error log */ 1272 case _vgtif_reg(cursor_x_hot): 1273 case _vgtif_reg(cursor_y_hot): 1274 case _vgtif_reg(pdp[0].lo): 1275 case _vgtif_reg(pdp[0].hi): 1276 case _vgtif_reg(pdp[1].lo): 1277 case _vgtif_reg(pdp[1].hi): 1278 case _vgtif_reg(pdp[2].lo): 1279 case _vgtif_reg(pdp[2].hi): 1280 case _vgtif_reg(pdp[3].lo): 1281 case _vgtif_reg(pdp[3].hi): 1282 case _vgtif_reg(execlist_context_descriptor_lo): 1283 case _vgtif_reg(execlist_context_descriptor_hi): 1284 break; 1285 case _vgtif_reg(rsv5[0])..._vgtif_reg(rsv5[3]): 1286 invalid_write = true; 1287 enter_failsafe_mode(vgpu, GVT_FAILSAFE_INSUFFICIENT_RESOURCE); 1288 break; 1289 default: 1290 invalid_write = true; 1291 gvt_vgpu_err("invalid pvinfo write offset %x bytes %x data %x\n", 1292 offset, bytes, data); 1293 break; 1294 } 1295 1296 if (!invalid_write) 1297 write_vreg(vgpu, offset, p_data, bytes); 1298 1299 return 0; 1300 } 1301 1302 static int pf_write(struct intel_vgpu *vgpu, 1303 unsigned int offset, void *p_data, unsigned int bytes) 1304 { 1305 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 1306 u32 val = *(u32 *)p_data; 1307 1308 if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL || 1309 offset == _PS_1B_CTRL || offset == _PS_2B_CTRL || 1310 offset == _PS_1C_CTRL) && (val & PS_PLANE_SEL_MASK) != 0) { 1311 drm_WARN_ONCE(&i915->drm, true, 1312 "VM(%d): guest is trying to scaling a plane\n", 1313 vgpu->id); 1314 return 0; 1315 } 1316 1317 return intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes); 1318 } 1319 1320 static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu, 1321 unsigned int offset, void *p_data, unsigned int bytes) 1322 { 1323 write_vreg(vgpu, offset, p_data, bytes); 1324 1325 if (vgpu_vreg(vgpu, offset) & 1326 HSW_PWR_WELL_CTL_REQ(HSW_PW_CTL_IDX_GLOBAL)) 1327 vgpu_vreg(vgpu, offset) |= 1328 HSW_PWR_WELL_CTL_STATE(HSW_PW_CTL_IDX_GLOBAL); 1329 else 1330 vgpu_vreg(vgpu, offset) &= 1331 ~HSW_PWR_WELL_CTL_STATE(HSW_PW_CTL_IDX_GLOBAL); 1332 return 0; 1333 } 1334 1335 static int gen9_dbuf_ctl_mmio_write(struct intel_vgpu *vgpu, 1336 unsigned int offset, void *p_data, unsigned int bytes) 1337 { 1338 write_vreg(vgpu, offset, p_data, bytes); 1339 1340 if (vgpu_vreg(vgpu, offset) & DBUF_POWER_REQUEST) 1341 vgpu_vreg(vgpu, offset) |= DBUF_POWER_STATE; 1342 else 1343 vgpu_vreg(vgpu, offset) &= ~DBUF_POWER_STATE; 1344 1345 return 0; 1346 } 1347 1348 static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu, 1349 unsigned int offset, void *p_data, unsigned int bytes) 1350 { 1351 write_vreg(vgpu, offset, p_data, bytes); 1352 1353 if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM) 1354 vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM; 1355 return 0; 1356 } 1357 1358 static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset, 1359 void *p_data, unsigned int bytes) 1360 { 1361 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 1362 u32 mode; 1363 1364 write_vreg(vgpu, offset, p_data, bytes); 1365 mode = vgpu_vreg(vgpu, offset); 1366 1367 if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) { 1368 drm_WARN_ONCE(&i915->drm, 1, 1369 "VM(%d): iGVT-g doesn't support GuC\n", 1370 vgpu->id); 1371 return 0; 1372 } 1373 1374 return 0; 1375 } 1376 1377 static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset, 1378 void *p_data, unsigned int bytes) 1379 { 1380 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 1381 u32 trtte = *(u32 *)p_data; 1382 1383 if ((trtte & 1) && (trtte & (1 << 1)) == 0) { 1384 drm_WARN(&i915->drm, 1, 1385 "VM(%d): Use physical address for TRTT!\n", 1386 vgpu->id); 1387 return -EINVAL; 1388 } 1389 write_vreg(vgpu, offset, p_data, bytes); 1390 1391 return 0; 1392 } 1393 1394 static int gen9_trtt_chicken_write(struct intel_vgpu *vgpu, unsigned int offset, 1395 void *p_data, unsigned int bytes) 1396 { 1397 write_vreg(vgpu, offset, p_data, bytes); 1398 return 0; 1399 } 1400 1401 static int dpll_status_read(struct intel_vgpu *vgpu, unsigned int offset, 1402 void *p_data, unsigned int bytes) 1403 { 1404 u32 v = 0; 1405 1406 if (vgpu_vreg(vgpu, 0x46010) & (1 << 31)) 1407 v |= (1 << 0); 1408 1409 if (vgpu_vreg(vgpu, 0x46014) & (1 << 31)) 1410 v |= (1 << 8); 1411 1412 if (vgpu_vreg(vgpu, 0x46040) & (1 << 31)) 1413 v |= (1 << 16); 1414 1415 if (vgpu_vreg(vgpu, 0x46060) & (1 << 31)) 1416 v |= (1 << 24); 1417 1418 vgpu_vreg(vgpu, offset) = v; 1419 1420 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1421 } 1422 1423 static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset, 1424 void *p_data, unsigned int bytes) 1425 { 1426 u32 value = *(u32 *)p_data; 1427 u32 cmd = value & 0xff; 1428 u32 *data0 = &vgpu_vreg_t(vgpu, GEN6_PCODE_DATA); 1429 1430 switch (cmd) { 1431 case GEN9_PCODE_READ_MEM_LATENCY: 1432 if (IS_SKYLAKE(vgpu->gvt->gt->i915) || 1433 IS_KABYLAKE(vgpu->gvt->gt->i915) || 1434 IS_COFFEELAKE(vgpu->gvt->gt->i915)) { 1435 /** 1436 * "Read memory latency" command on gen9. 1437 * Below memory latency values are read 1438 * from skylake platform. 1439 */ 1440 if (!*data0) 1441 *data0 = 0x1e1a1100; 1442 else 1443 *data0 = 0x61514b3d; 1444 } else if (IS_BROXTON(vgpu->gvt->gt->i915)) { 1445 /** 1446 * "Read memory latency" command on gen9. 1447 * Below memory latency values are read 1448 * from Broxton MRB. 1449 */ 1450 if (!*data0) 1451 *data0 = 0x16080707; 1452 else 1453 *data0 = 0x16161616; 1454 } 1455 break; 1456 case SKL_PCODE_CDCLK_CONTROL: 1457 if (IS_SKYLAKE(vgpu->gvt->gt->i915) || 1458 IS_KABYLAKE(vgpu->gvt->gt->i915) || 1459 IS_COFFEELAKE(vgpu->gvt->gt->i915)) 1460 *data0 = SKL_CDCLK_READY_FOR_CHANGE; 1461 break; 1462 case GEN6_PCODE_READ_RC6VIDS: 1463 *data0 |= 0x1; 1464 break; 1465 } 1466 1467 gvt_dbg_core("VM(%d) write %x to mailbox, return data0 %x\n", 1468 vgpu->id, value, *data0); 1469 /** 1470 * PCODE_READY clear means ready for pcode read/write, 1471 * PCODE_ERROR_MASK clear means no error happened. In GVT-g we 1472 * always emulate as pcode read/write success and ready for access 1473 * anytime, since we don't touch real physical registers here. 1474 */ 1475 value &= ~(GEN6_PCODE_READY | GEN6_PCODE_ERROR_MASK); 1476 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes); 1477 } 1478 1479 static int hws_pga_write(struct intel_vgpu *vgpu, unsigned int offset, 1480 void *p_data, unsigned int bytes) 1481 { 1482 u32 value = *(u32 *)p_data; 1483 const struct intel_engine_cs *engine = 1484 intel_gvt_render_mmio_to_engine(vgpu->gvt, offset); 1485 1486 if (!intel_gvt_ggtt_validate_range(vgpu, value, I915_GTT_PAGE_SIZE)) { 1487 gvt_vgpu_err("write invalid HWSP address, reg:0x%x, value:0x%x\n", 1488 offset, value); 1489 return -EINVAL; 1490 } 1491 1492 /* 1493 * Need to emulate all the HWSP register write to ensure host can 1494 * update the VM CSB status correctly. Here listed registers can 1495 * support BDW, SKL or other platforms with same HWSP registers. 1496 */ 1497 if (unlikely(!engine)) { 1498 gvt_vgpu_err("access unknown hardware status page register:0x%x\n", 1499 offset); 1500 return -EINVAL; 1501 } 1502 vgpu->hws_pga[engine->id] = value; 1503 gvt_dbg_mmio("VM(%d) write: 0x%x to HWSP: 0x%x\n", 1504 vgpu->id, value, offset); 1505 1506 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes); 1507 } 1508 1509 static int skl_power_well_ctl_write(struct intel_vgpu *vgpu, 1510 unsigned int offset, void *p_data, unsigned int bytes) 1511 { 1512 u32 v = *(u32 *)p_data; 1513 1514 if (IS_BROXTON(vgpu->gvt->gt->i915)) 1515 v &= (1 << 31) | (1 << 29); 1516 else 1517 v &= (1 << 31) | (1 << 29) | (1 << 9) | 1518 (1 << 7) | (1 << 5) | (1 << 3) | (1 << 1); 1519 v |= (v >> 1); 1520 1521 return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes); 1522 } 1523 1524 static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset, 1525 void *p_data, unsigned int bytes) 1526 { 1527 u32 v = *(u32 *)p_data; 1528 1529 /* other bits are MBZ. */ 1530 v &= (1 << 31) | (1 << 30); 1531 v & (1 << 31) ? (v |= (1 << 30)) : (v &= ~(1 << 30)); 1532 1533 vgpu_vreg(vgpu, offset) = v; 1534 1535 return 0; 1536 } 1537 1538 static int bxt_de_pll_enable_write(struct intel_vgpu *vgpu, 1539 unsigned int offset, void *p_data, unsigned int bytes) 1540 { 1541 u32 v = *(u32 *)p_data; 1542 1543 if (v & BXT_DE_PLL_PLL_ENABLE) 1544 v |= BXT_DE_PLL_LOCK; 1545 1546 vgpu_vreg(vgpu, offset) = v; 1547 1548 return 0; 1549 } 1550 1551 static int bxt_port_pll_enable_write(struct intel_vgpu *vgpu, 1552 unsigned int offset, void *p_data, unsigned int bytes) 1553 { 1554 u32 v = *(u32 *)p_data; 1555 1556 if (v & PORT_PLL_ENABLE) 1557 v |= PORT_PLL_LOCK; 1558 1559 vgpu_vreg(vgpu, offset) = v; 1560 1561 return 0; 1562 } 1563 1564 static int bxt_phy_ctl_family_write(struct intel_vgpu *vgpu, 1565 unsigned int offset, void *p_data, unsigned int bytes) 1566 { 1567 u32 v = *(u32 *)p_data; 1568 u32 data = v & COMMON_RESET_DIS ? BXT_PHY_LANE_ENABLED : 0; 1569 1570 switch (offset) { 1571 case _PHY_CTL_FAMILY_EDP: 1572 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_A) = data; 1573 break; 1574 case _PHY_CTL_FAMILY_DDI: 1575 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_B) = data; 1576 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_C) = data; 1577 break; 1578 } 1579 1580 vgpu_vreg(vgpu, offset) = v; 1581 1582 return 0; 1583 } 1584 1585 static int bxt_port_tx_dw3_read(struct intel_vgpu *vgpu, 1586 unsigned int offset, void *p_data, unsigned int bytes) 1587 { 1588 u32 v = vgpu_vreg(vgpu, offset); 1589 1590 v &= ~UNIQUE_TRANGE_EN_METHOD; 1591 1592 vgpu_vreg(vgpu, offset) = v; 1593 1594 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1595 } 1596 1597 static int bxt_pcs_dw12_grp_write(struct intel_vgpu *vgpu, 1598 unsigned int offset, void *p_data, unsigned int bytes) 1599 { 1600 u32 v = *(u32 *)p_data; 1601 1602 if (offset == _PORT_PCS_DW12_GRP_A || offset == _PORT_PCS_DW12_GRP_B) { 1603 vgpu_vreg(vgpu, offset - 0x600) = v; 1604 vgpu_vreg(vgpu, offset - 0x800) = v; 1605 } else { 1606 vgpu_vreg(vgpu, offset - 0x400) = v; 1607 vgpu_vreg(vgpu, offset - 0x600) = v; 1608 } 1609 1610 vgpu_vreg(vgpu, offset) = v; 1611 1612 return 0; 1613 } 1614 1615 static int bxt_gt_disp_pwron_write(struct intel_vgpu *vgpu, 1616 unsigned int offset, void *p_data, unsigned int bytes) 1617 { 1618 u32 v = *(u32 *)p_data; 1619 1620 if (v & BIT(0)) { 1621 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &= 1622 ~PHY_RESERVED; 1623 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |= 1624 PHY_POWER_GOOD; 1625 } 1626 1627 if (v & BIT(1)) { 1628 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &= 1629 ~PHY_RESERVED; 1630 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |= 1631 PHY_POWER_GOOD; 1632 } 1633 1634 1635 vgpu_vreg(vgpu, offset) = v; 1636 1637 return 0; 1638 } 1639 1640 static int edp_psr_imr_iir_write(struct intel_vgpu *vgpu, 1641 unsigned int offset, void *p_data, unsigned int bytes) 1642 { 1643 vgpu_vreg(vgpu, offset) = 0; 1644 return 0; 1645 } 1646 1647 static int guc_status_read(struct intel_vgpu *vgpu, 1648 unsigned int offset, void *p_data, 1649 unsigned int bytes) 1650 { 1651 /* keep MIA_IN_RESET before clearing */ 1652 read_vreg(vgpu, offset, p_data, bytes); 1653 vgpu_vreg(vgpu, offset) &= ~GS_MIA_IN_RESET; 1654 return 0; 1655 } 1656 1657 static int mmio_read_from_hw(struct intel_vgpu *vgpu, 1658 unsigned int offset, void *p_data, unsigned int bytes) 1659 { 1660 struct intel_gvt *gvt = vgpu->gvt; 1661 const struct intel_engine_cs *engine = 1662 intel_gvt_render_mmio_to_engine(gvt, offset); 1663 1664 /** 1665 * Read HW reg in following case 1666 * a. the offset isn't a ring mmio 1667 * b. the offset's ring is running on hw. 1668 * c. the offset is ring time stamp mmio 1669 */ 1670 1671 if (!engine || 1672 vgpu == gvt->scheduler.engine_owner[engine->id] || 1673 offset == i915_mmio_reg_offset(RING_TIMESTAMP(engine->mmio_base)) || 1674 offset == i915_mmio_reg_offset(RING_TIMESTAMP_UDW(engine->mmio_base))) { 1675 mmio_hw_access_pre(gvt->gt); 1676 vgpu_vreg(vgpu, offset) = 1677 intel_uncore_read(gvt->gt->uncore, _MMIO(offset)); 1678 mmio_hw_access_post(gvt->gt); 1679 } 1680 1681 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1682 } 1683 1684 static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1685 void *p_data, unsigned int bytes) 1686 { 1687 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 1688 const struct intel_engine_cs *engine = intel_gvt_render_mmio_to_engine(vgpu->gvt, offset); 1689 struct intel_vgpu_execlist *execlist; 1690 u32 data = *(u32 *)p_data; 1691 int ret = 0; 1692 1693 if (drm_WARN_ON(&i915->drm, !engine)) 1694 return -EINVAL; 1695 1696 execlist = &vgpu->submission.execlist[engine->id]; 1697 1698 execlist->elsp_dwords.data[3 - execlist->elsp_dwords.index] = data; 1699 if (execlist->elsp_dwords.index == 3) { 1700 ret = intel_vgpu_submit_execlist(vgpu, engine); 1701 if(ret) 1702 gvt_vgpu_err("fail submit workload on ring %s\n", 1703 engine->name); 1704 } 1705 1706 ++execlist->elsp_dwords.index; 1707 execlist->elsp_dwords.index &= 0x3; 1708 return ret; 1709 } 1710 1711 static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1712 void *p_data, unsigned int bytes) 1713 { 1714 u32 data = *(u32 *)p_data; 1715 const struct intel_engine_cs *engine = 1716 intel_gvt_render_mmio_to_engine(vgpu->gvt, offset); 1717 bool enable_execlist; 1718 int ret; 1719 1720 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(1); 1721 if (IS_COFFEELAKE(vgpu->gvt->gt->i915)) 1722 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(2); 1723 write_vreg(vgpu, offset, p_data, bytes); 1724 1725 if (data & _MASKED_BIT_ENABLE(1)) { 1726 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); 1727 return 0; 1728 } 1729 1730 if (IS_COFFEELAKE(vgpu->gvt->gt->i915) && 1731 data & _MASKED_BIT_ENABLE(2)) { 1732 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); 1733 return 0; 1734 } 1735 1736 /* when PPGTT mode enabled, we will check if guest has called 1737 * pvinfo, if not, we will treat this guest as non-gvtg-aware 1738 * guest, and stop emulating its cfg space, mmio, gtt, etc. 1739 */ 1740 if (((data & _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)) || 1741 (data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE))) 1742 && !vgpu->pv_notified) { 1743 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); 1744 return 0; 1745 } 1746 if ((data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)) 1747 || (data & _MASKED_BIT_DISABLE(GFX_RUN_LIST_ENABLE))) { 1748 enable_execlist = !!(data & GFX_RUN_LIST_ENABLE); 1749 1750 gvt_dbg_core("EXECLIST %s on ring %s\n", 1751 (enable_execlist ? "enabling" : "disabling"), 1752 engine->name); 1753 1754 if (!enable_execlist) 1755 return 0; 1756 1757 ret = intel_vgpu_select_submission_ops(vgpu, 1758 engine->mask, 1759 INTEL_VGPU_EXECLIST_SUBMISSION); 1760 if (ret) 1761 return ret; 1762 1763 intel_vgpu_start_schedule(vgpu); 1764 } 1765 return 0; 1766 } 1767 1768 static int gvt_reg_tlb_control_handler(struct intel_vgpu *vgpu, 1769 unsigned int offset, void *p_data, unsigned int bytes) 1770 { 1771 unsigned int id = 0; 1772 1773 write_vreg(vgpu, offset, p_data, bytes); 1774 vgpu_vreg(vgpu, offset) = 0; 1775 1776 switch (offset) { 1777 case 0x4260: 1778 id = RCS0; 1779 break; 1780 case 0x4264: 1781 id = VCS0; 1782 break; 1783 case 0x4268: 1784 id = VCS1; 1785 break; 1786 case 0x426c: 1787 id = BCS0; 1788 break; 1789 case 0x4270: 1790 id = VECS0; 1791 break; 1792 default: 1793 return -EINVAL; 1794 } 1795 set_bit(id, (void *)vgpu->submission.tlb_handle_pending); 1796 1797 return 0; 1798 } 1799 1800 static int ring_reset_ctl_write(struct intel_vgpu *vgpu, 1801 unsigned int offset, void *p_data, unsigned int bytes) 1802 { 1803 u32 data; 1804 1805 write_vreg(vgpu, offset, p_data, bytes); 1806 data = vgpu_vreg(vgpu, offset); 1807 1808 if (data & _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET)) 1809 data |= RESET_CTL_READY_TO_RESET; 1810 else if (data & _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET)) 1811 data &= ~RESET_CTL_READY_TO_RESET; 1812 1813 vgpu_vreg(vgpu, offset) = data; 1814 return 0; 1815 } 1816 1817 static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu, 1818 unsigned int offset, void *p_data, 1819 unsigned int bytes) 1820 { 1821 u32 data = *(u32 *)p_data; 1822 1823 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(0x18); 1824 write_vreg(vgpu, offset, p_data, bytes); 1825 1826 if (data & _MASKED_BIT_ENABLE(0x10) || data & _MASKED_BIT_ENABLE(0x8)) 1827 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); 1828 1829 return 0; 1830 } 1831 1832 #define MMIO_F(reg, s, f, am, rm, d, r, w) do { \ 1833 ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \ 1834 f, s, am, rm, d, r, w); \ 1835 if (ret) \ 1836 return ret; \ 1837 } while (0) 1838 1839 #define MMIO_D(reg, d) \ 1840 MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL) 1841 1842 #define MMIO_DH(reg, d, r, w) \ 1843 MMIO_F(reg, 4, 0, 0, 0, d, r, w) 1844 1845 #define MMIO_DFH(reg, d, f, r, w) \ 1846 MMIO_F(reg, 4, f, 0, 0, d, r, w) 1847 1848 #define MMIO_GM(reg, d, r, w) \ 1849 MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w) 1850 1851 #define MMIO_GM_RDR(reg, d, r, w) \ 1852 MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w) 1853 1854 #define MMIO_RO(reg, d, f, rm, r, w) \ 1855 MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w) 1856 1857 #define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \ 1858 MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \ 1859 MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \ 1860 MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \ 1861 MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \ 1862 if (HAS_ENGINE(dev_priv, VCS1)) \ 1863 MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \ 1864 } while (0) 1865 1866 #define MMIO_RING_D(prefix, d) \ 1867 MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL) 1868 1869 #define MMIO_RING_DFH(prefix, d, f, r, w) \ 1870 MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w) 1871 1872 #define MMIO_RING_GM(prefix, d, r, w) \ 1873 MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w) 1874 1875 #define MMIO_RING_GM_RDR(prefix, d, r, w) \ 1876 MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w) 1877 1878 #define MMIO_RING_RO(prefix, d, f, rm, r, w) \ 1879 MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w) 1880 1881 static int init_generic_mmio_info(struct intel_gvt *gvt) 1882 { 1883 struct drm_i915_private *dev_priv = gvt->gt->i915; 1884 int ret; 1885 1886 MMIO_RING_DFH(RING_IMR, D_ALL, F_CMD_ACCESS, NULL, 1887 intel_vgpu_reg_imr_handler); 1888 1889 MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler); 1890 MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler); 1891 MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler); 1892 MMIO_D(SDEISR, D_ALL); 1893 1894 MMIO_RING_DFH(RING_HWSTAM, D_ALL, F_CMD_ACCESS, NULL, NULL); 1895 1896 MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL, 1897 gamw_echo_dev_rw_ia_write); 1898 1899 MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1900 MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1901 MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1902 1903 #define RING_REG(base) _MMIO((base) + 0x28) 1904 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL); 1905 #undef RING_REG 1906 1907 #define RING_REG(base) _MMIO((base) + 0x134) 1908 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL); 1909 #undef RING_REG 1910 1911 #define RING_REG(base) _MMIO((base) + 0x6c) 1912 MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL); 1913 #undef RING_REG 1914 MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL); 1915 1916 MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL); 1917 MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL); 1918 MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL); 1919 MMIO_D(GEN7_CXT_SIZE, D_ALL); 1920 1921 MMIO_RING_DFH(RING_TAIL, D_ALL, F_CMD_ACCESS, NULL, NULL); 1922 MMIO_RING_DFH(RING_HEAD, D_ALL, F_CMD_ACCESS, NULL, NULL); 1923 MMIO_RING_DFH(RING_CTL, D_ALL, F_CMD_ACCESS, NULL, NULL); 1924 MMIO_RING_DFH(RING_ACTHD, D_ALL, F_CMD_ACCESS, mmio_read_from_hw, NULL); 1925 MMIO_RING_GM_RDR(RING_START, D_ALL, NULL, NULL); 1926 1927 /* RING MODE */ 1928 #define RING_REG(base) _MMIO((base) + 0x29c) 1929 MMIO_RING_DFH(RING_REG, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, 1930 ring_mode_mmio_write); 1931 #undef RING_REG 1932 1933 MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 1934 NULL, NULL); 1935 MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 1936 NULL, NULL); 1937 MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS, 1938 mmio_read_from_hw, NULL); 1939 MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS, 1940 mmio_read_from_hw, NULL); 1941 1942 MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1943 MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 1944 NULL, NULL); 1945 MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1946 MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1947 MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1948 1949 MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1950 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1951 MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1952 MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL, 1953 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1954 MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1955 MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL); 1956 MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 1957 NULL, NULL); 1958 MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 1959 NULL, NULL); 1960 MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL); 1961 MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL); 1962 MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL); 1963 MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL); 1964 MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL); 1965 MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL); 1966 MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL); 1967 MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1968 MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1969 MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1970 1971 /* display */ 1972 MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL); 1973 MMIO_D(_MMIO(0x602a0), D_ALL); 1974 1975 MMIO_D(_MMIO(0x65050), D_ALL); 1976 MMIO_D(_MMIO(0x650b4), D_ALL); 1977 1978 MMIO_D(_MMIO(0xc4040), D_ALL); 1979 MMIO_D(DERRMR, D_ALL); 1980 1981 MMIO_D(PIPEDSL(PIPE_A), D_ALL); 1982 MMIO_D(PIPEDSL(PIPE_B), D_ALL); 1983 MMIO_D(PIPEDSL(PIPE_C), D_ALL); 1984 MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL); 1985 1986 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write); 1987 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write); 1988 MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write); 1989 MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write); 1990 1991 MMIO_D(PIPESTAT(PIPE_A), D_ALL); 1992 MMIO_D(PIPESTAT(PIPE_B), D_ALL); 1993 MMIO_D(PIPESTAT(PIPE_C), D_ALL); 1994 MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL); 1995 1996 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL); 1997 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL); 1998 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL); 1999 MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL); 2000 2001 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL); 2002 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL); 2003 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL); 2004 MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL); 2005 2006 MMIO_D(CURCNTR(PIPE_A), D_ALL); 2007 MMIO_D(CURCNTR(PIPE_B), D_ALL); 2008 MMIO_D(CURCNTR(PIPE_C), D_ALL); 2009 2010 MMIO_D(CURPOS(PIPE_A), D_ALL); 2011 MMIO_D(CURPOS(PIPE_B), D_ALL); 2012 MMIO_D(CURPOS(PIPE_C), D_ALL); 2013 2014 MMIO_D(CURBASE(PIPE_A), D_ALL); 2015 MMIO_D(CURBASE(PIPE_B), D_ALL); 2016 MMIO_D(CURBASE(PIPE_C), D_ALL); 2017 2018 MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL); 2019 MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL); 2020 MMIO_D(CUR_FBC_CTL(PIPE_C), D_ALL); 2021 2022 MMIO_D(_MMIO(0x700ac), D_ALL); 2023 MMIO_D(_MMIO(0x710ac), D_ALL); 2024 MMIO_D(_MMIO(0x720ac), D_ALL); 2025 2026 MMIO_D(_MMIO(0x70090), D_ALL); 2027 MMIO_D(_MMIO(0x70094), D_ALL); 2028 MMIO_D(_MMIO(0x70098), D_ALL); 2029 MMIO_D(_MMIO(0x7009c), D_ALL); 2030 2031 MMIO_D(DSPCNTR(PIPE_A), D_ALL); 2032 MMIO_D(DSPADDR(PIPE_A), D_ALL); 2033 MMIO_D(DSPSTRIDE(PIPE_A), D_ALL); 2034 MMIO_D(DSPPOS(PIPE_A), D_ALL); 2035 MMIO_D(DSPSIZE(PIPE_A), D_ALL); 2036 MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write); 2037 MMIO_D(DSPOFFSET(PIPE_A), D_ALL); 2038 MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL); 2039 MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL, 2040 reg50080_mmio_write); 2041 2042 MMIO_D(DSPCNTR(PIPE_B), D_ALL); 2043 MMIO_D(DSPADDR(PIPE_B), D_ALL); 2044 MMIO_D(DSPSTRIDE(PIPE_B), D_ALL); 2045 MMIO_D(DSPPOS(PIPE_B), D_ALL); 2046 MMIO_D(DSPSIZE(PIPE_B), D_ALL); 2047 MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write); 2048 MMIO_D(DSPOFFSET(PIPE_B), D_ALL); 2049 MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL); 2050 MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL, 2051 reg50080_mmio_write); 2052 2053 MMIO_D(DSPCNTR(PIPE_C), D_ALL); 2054 MMIO_D(DSPADDR(PIPE_C), D_ALL); 2055 MMIO_D(DSPSTRIDE(PIPE_C), D_ALL); 2056 MMIO_D(DSPPOS(PIPE_C), D_ALL); 2057 MMIO_D(DSPSIZE(PIPE_C), D_ALL); 2058 MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write); 2059 MMIO_D(DSPOFFSET(PIPE_C), D_ALL); 2060 MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL); 2061 MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL, 2062 reg50080_mmio_write); 2063 2064 MMIO_D(SPRCTL(PIPE_A), D_ALL); 2065 MMIO_D(SPRLINOFF(PIPE_A), D_ALL); 2066 MMIO_D(SPRSTRIDE(PIPE_A), D_ALL); 2067 MMIO_D(SPRPOS(PIPE_A), D_ALL); 2068 MMIO_D(SPRSIZE(PIPE_A), D_ALL); 2069 MMIO_D(SPRKEYVAL(PIPE_A), D_ALL); 2070 MMIO_D(SPRKEYMSK(PIPE_A), D_ALL); 2071 MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write); 2072 MMIO_D(SPRKEYMAX(PIPE_A), D_ALL); 2073 MMIO_D(SPROFFSET(PIPE_A), D_ALL); 2074 MMIO_D(SPRSCALE(PIPE_A), D_ALL); 2075 MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL); 2076 MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL, 2077 reg50080_mmio_write); 2078 2079 MMIO_D(SPRCTL(PIPE_B), D_ALL); 2080 MMIO_D(SPRLINOFF(PIPE_B), D_ALL); 2081 MMIO_D(SPRSTRIDE(PIPE_B), D_ALL); 2082 MMIO_D(SPRPOS(PIPE_B), D_ALL); 2083 MMIO_D(SPRSIZE(PIPE_B), D_ALL); 2084 MMIO_D(SPRKEYVAL(PIPE_B), D_ALL); 2085 MMIO_D(SPRKEYMSK(PIPE_B), D_ALL); 2086 MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write); 2087 MMIO_D(SPRKEYMAX(PIPE_B), D_ALL); 2088 MMIO_D(SPROFFSET(PIPE_B), D_ALL); 2089 MMIO_D(SPRSCALE(PIPE_B), D_ALL); 2090 MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL); 2091 MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL, 2092 reg50080_mmio_write); 2093 2094 MMIO_D(SPRCTL(PIPE_C), D_ALL); 2095 MMIO_D(SPRLINOFF(PIPE_C), D_ALL); 2096 MMIO_D(SPRSTRIDE(PIPE_C), D_ALL); 2097 MMIO_D(SPRPOS(PIPE_C), D_ALL); 2098 MMIO_D(SPRSIZE(PIPE_C), D_ALL); 2099 MMIO_D(SPRKEYVAL(PIPE_C), D_ALL); 2100 MMIO_D(SPRKEYMSK(PIPE_C), D_ALL); 2101 MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write); 2102 MMIO_D(SPRKEYMAX(PIPE_C), D_ALL); 2103 MMIO_D(SPROFFSET(PIPE_C), D_ALL); 2104 MMIO_D(SPRSCALE(PIPE_C), D_ALL); 2105 MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL); 2106 MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL, 2107 reg50080_mmio_write); 2108 2109 MMIO_D(HTOTAL(TRANSCODER_A), D_ALL); 2110 MMIO_D(HBLANK(TRANSCODER_A), D_ALL); 2111 MMIO_D(HSYNC(TRANSCODER_A), D_ALL); 2112 MMIO_D(VTOTAL(TRANSCODER_A), D_ALL); 2113 MMIO_D(VBLANK(TRANSCODER_A), D_ALL); 2114 MMIO_D(VSYNC(TRANSCODER_A), D_ALL); 2115 MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL); 2116 MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL); 2117 MMIO_D(PIPESRC(TRANSCODER_A), D_ALL); 2118 2119 MMIO_D(HTOTAL(TRANSCODER_B), D_ALL); 2120 MMIO_D(HBLANK(TRANSCODER_B), D_ALL); 2121 MMIO_D(HSYNC(TRANSCODER_B), D_ALL); 2122 MMIO_D(VTOTAL(TRANSCODER_B), D_ALL); 2123 MMIO_D(VBLANK(TRANSCODER_B), D_ALL); 2124 MMIO_D(VSYNC(TRANSCODER_B), D_ALL); 2125 MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL); 2126 MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL); 2127 MMIO_D(PIPESRC(TRANSCODER_B), D_ALL); 2128 2129 MMIO_D(HTOTAL(TRANSCODER_C), D_ALL); 2130 MMIO_D(HBLANK(TRANSCODER_C), D_ALL); 2131 MMIO_D(HSYNC(TRANSCODER_C), D_ALL); 2132 MMIO_D(VTOTAL(TRANSCODER_C), D_ALL); 2133 MMIO_D(VBLANK(TRANSCODER_C), D_ALL); 2134 MMIO_D(VSYNC(TRANSCODER_C), D_ALL); 2135 MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL); 2136 MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL); 2137 MMIO_D(PIPESRC(TRANSCODER_C), D_ALL); 2138 2139 MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL); 2140 MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL); 2141 MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL); 2142 MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL); 2143 MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL); 2144 MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL); 2145 MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL); 2146 MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL); 2147 2148 MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL); 2149 MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL); 2150 MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL); 2151 MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL); 2152 MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL); 2153 MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL); 2154 MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL); 2155 MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL); 2156 2157 MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL); 2158 MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL); 2159 MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL); 2160 MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL); 2161 MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL); 2162 MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL); 2163 MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL); 2164 MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL); 2165 2166 MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL); 2167 MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL); 2168 MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL); 2169 MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL); 2170 MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL); 2171 MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL); 2172 MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL); 2173 MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL); 2174 2175 MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL); 2176 MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL); 2177 MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL); 2178 MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL); 2179 MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL); 2180 MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL); 2181 MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL); 2182 MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL); 2183 2184 MMIO_D(PF_CTL(PIPE_A), D_ALL); 2185 MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL); 2186 MMIO_D(PF_WIN_POS(PIPE_A), D_ALL); 2187 MMIO_D(PF_VSCALE(PIPE_A), D_ALL); 2188 MMIO_D(PF_HSCALE(PIPE_A), D_ALL); 2189 2190 MMIO_D(PF_CTL(PIPE_B), D_ALL); 2191 MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL); 2192 MMIO_D(PF_WIN_POS(PIPE_B), D_ALL); 2193 MMIO_D(PF_VSCALE(PIPE_B), D_ALL); 2194 MMIO_D(PF_HSCALE(PIPE_B), D_ALL); 2195 2196 MMIO_D(PF_CTL(PIPE_C), D_ALL); 2197 MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL); 2198 MMIO_D(PF_WIN_POS(PIPE_C), D_ALL); 2199 MMIO_D(PF_VSCALE(PIPE_C), D_ALL); 2200 MMIO_D(PF_HSCALE(PIPE_C), D_ALL); 2201 2202 MMIO_D(WM0_PIPEA_ILK, D_ALL); 2203 MMIO_D(WM0_PIPEB_ILK, D_ALL); 2204 MMIO_D(WM0_PIPEC_IVB, D_ALL); 2205 MMIO_D(WM1_LP_ILK, D_ALL); 2206 MMIO_D(WM2_LP_ILK, D_ALL); 2207 MMIO_D(WM3_LP_ILK, D_ALL); 2208 MMIO_D(WM1S_LP_ILK, D_ALL); 2209 MMIO_D(WM2S_LP_IVB, D_ALL); 2210 MMIO_D(WM3S_LP_IVB, D_ALL); 2211 2212 MMIO_D(BLC_PWM_CPU_CTL2, D_ALL); 2213 MMIO_D(BLC_PWM_CPU_CTL, D_ALL); 2214 MMIO_D(BLC_PWM_PCH_CTL1, D_ALL); 2215 MMIO_D(BLC_PWM_PCH_CTL2, D_ALL); 2216 2217 MMIO_D(_MMIO(0x48268), D_ALL); 2218 2219 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read, 2220 gmbus_mmio_write); 2221 MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL); 2222 MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL); 2223 2224 MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 2225 dp_aux_ch_ctl_mmio_write); 2226 MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 2227 dp_aux_ch_ctl_mmio_write); 2228 MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 2229 dp_aux_ch_ctl_mmio_write); 2230 2231 MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write); 2232 2233 MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write); 2234 MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write); 2235 2236 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write); 2237 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write); 2238 MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write); 2239 MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); 2240 MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); 2241 MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); 2242 MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); 2243 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); 2244 MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); 2245 2246 MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A), D_ALL); 2247 MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A), D_ALL); 2248 MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A), D_ALL); 2249 MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A), D_ALL); 2250 MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A), D_ALL); 2251 MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A), D_ALL); 2252 MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A), D_ALL); 2253 2254 MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B), D_ALL); 2255 MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B), D_ALL); 2256 MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B), D_ALL); 2257 MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B), D_ALL); 2258 MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B), D_ALL); 2259 MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B), D_ALL); 2260 MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B), D_ALL); 2261 2262 MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1), D_ALL); 2263 MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1), D_ALL); 2264 MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2), D_ALL); 2265 MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2), D_ALL); 2266 MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1), D_ALL); 2267 MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1), D_ALL); 2268 MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2), D_ALL); 2269 MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2), D_ALL); 2270 2271 MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL); 2272 MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL); 2273 MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL); 2274 2275 MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL); 2276 MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL); 2277 MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL); 2278 2279 MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL); 2280 MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL); 2281 MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL); 2282 2283 MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL); 2284 MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL); 2285 MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL); 2286 2287 MMIO_D(_MMIO(_FDI_RXA_MISC), D_ALL); 2288 MMIO_D(_MMIO(_FDI_RXB_MISC), D_ALL); 2289 MMIO_D(_MMIO(_FDI_RXA_TUSIZE1), D_ALL); 2290 MMIO_D(_MMIO(_FDI_RXA_TUSIZE2), D_ALL); 2291 MMIO_D(_MMIO(_FDI_RXB_TUSIZE1), D_ALL); 2292 MMIO_D(_MMIO(_FDI_RXB_TUSIZE2), D_ALL); 2293 2294 MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write); 2295 MMIO_D(PCH_PP_DIVISOR, D_ALL); 2296 MMIO_D(PCH_PP_STATUS, D_ALL); 2297 MMIO_D(PCH_LVDS, D_ALL); 2298 MMIO_D(_MMIO(_PCH_DPLL_A), D_ALL); 2299 MMIO_D(_MMIO(_PCH_DPLL_B), D_ALL); 2300 MMIO_D(_MMIO(_PCH_FPA0), D_ALL); 2301 MMIO_D(_MMIO(_PCH_FPA1), D_ALL); 2302 MMIO_D(_MMIO(_PCH_FPB0), D_ALL); 2303 MMIO_D(_MMIO(_PCH_FPB1), D_ALL); 2304 MMIO_D(PCH_DREF_CONTROL, D_ALL); 2305 MMIO_D(PCH_RAWCLK_FREQ, D_ALL); 2306 MMIO_D(PCH_DPLL_SEL, D_ALL); 2307 2308 MMIO_D(_MMIO(0x61208), D_ALL); 2309 MMIO_D(_MMIO(0x6120c), D_ALL); 2310 MMIO_D(PCH_PP_ON_DELAYS, D_ALL); 2311 MMIO_D(PCH_PP_OFF_DELAYS, D_ALL); 2312 2313 MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL); 2314 MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL); 2315 MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL); 2316 MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL); 2317 MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL); 2318 MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL); 2319 2320 MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0, 2321 PORTA_HOTPLUG_STATUS_MASK 2322 | PORTB_HOTPLUG_STATUS_MASK 2323 | PORTC_HOTPLUG_STATUS_MASK 2324 | PORTD_HOTPLUG_STATUS_MASK, 2325 NULL, NULL); 2326 2327 MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write); 2328 MMIO_D(FUSE_STRAP, D_ALL); 2329 MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL); 2330 2331 MMIO_D(DISP_ARB_CTL, D_ALL); 2332 MMIO_D(DISP_ARB_CTL2, D_ALL); 2333 2334 MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL); 2335 MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL); 2336 MMIO_D(ILK_DSPCLK_GATE_D, D_ALL); 2337 2338 MMIO_D(SOUTH_CHICKEN1, D_ALL); 2339 MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write); 2340 MMIO_D(_MMIO(_TRANSA_CHICKEN1), D_ALL); 2341 MMIO_D(_MMIO(_TRANSB_CHICKEN1), D_ALL); 2342 MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL); 2343 MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL); 2344 MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL); 2345 2346 MMIO_D(ILK_DPFC_CB_BASE, D_ALL); 2347 MMIO_D(ILK_DPFC_CONTROL, D_ALL); 2348 MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL); 2349 MMIO_D(ILK_DPFC_STATUS, D_ALL); 2350 MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL); 2351 MMIO_D(ILK_DPFC_CHICKEN, D_ALL); 2352 MMIO_D(ILK_FBC_RT_BASE, D_ALL); 2353 2354 MMIO_D(IPS_CTL, D_ALL); 2355 2356 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL); 2357 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL); 2358 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL); 2359 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL); 2360 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL); 2361 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL); 2362 MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL); 2363 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL); 2364 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL); 2365 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL); 2366 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL); 2367 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL); 2368 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL); 2369 2370 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL); 2371 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL); 2372 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL); 2373 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL); 2374 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL); 2375 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL); 2376 MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL); 2377 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL); 2378 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL); 2379 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL); 2380 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL); 2381 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL); 2382 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL); 2383 2384 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL); 2385 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL); 2386 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL); 2387 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL); 2388 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL); 2389 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL); 2390 MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL); 2391 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL); 2392 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL); 2393 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL); 2394 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL); 2395 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL); 2396 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL); 2397 2398 MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL); 2399 MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL); 2400 MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 2401 2402 MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL); 2403 MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL); 2404 MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 2405 2406 MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL); 2407 MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL); 2408 MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 2409 2410 MMIO_D(_MMIO(0x60110), D_ALL); 2411 MMIO_D(_MMIO(0x61110), D_ALL); 2412 MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL); 2413 MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL); 2414 MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL); 2415 MMIO_F(_MMIO(0x70440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2416 MMIO_F(_MMIO(0x71440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2417 MMIO_F(_MMIO(0x72440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2418 MMIO_F(_MMIO(0x7044c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2419 MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2420 MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2421 2422 MMIO_D(WM_LINETIME(PIPE_A), D_ALL); 2423 MMIO_D(WM_LINETIME(PIPE_B), D_ALL); 2424 MMIO_D(WM_LINETIME(PIPE_C), D_ALL); 2425 MMIO_D(SPLL_CTL, D_ALL); 2426 MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL); 2427 MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL); 2428 MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL); 2429 MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL); 2430 MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL); 2431 MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL); 2432 MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL); 2433 MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL); 2434 MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL); 2435 MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL); 2436 2437 MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL); 2438 MMIO_D(_MMIO(0x46508), D_ALL); 2439 2440 MMIO_D(_MMIO(0x49080), D_ALL); 2441 MMIO_D(_MMIO(0x49180), D_ALL); 2442 MMIO_D(_MMIO(0x49280), D_ALL); 2443 2444 MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL); 2445 MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL); 2446 MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL); 2447 2448 MMIO_D(GAMMA_MODE(PIPE_A), D_ALL); 2449 MMIO_D(GAMMA_MODE(PIPE_B), D_ALL); 2450 MMIO_D(GAMMA_MODE(PIPE_C), D_ALL); 2451 2452 MMIO_D(PIPE_MULT(PIPE_A), D_ALL); 2453 MMIO_D(PIPE_MULT(PIPE_B), D_ALL); 2454 MMIO_D(PIPE_MULT(PIPE_C), D_ALL); 2455 2456 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL); 2457 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL); 2458 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL); 2459 2460 MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL); 2461 MMIO_D(SBI_ADDR, D_ALL); 2462 MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL); 2463 MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write); 2464 MMIO_D(PIXCLK_GATE, D_ALL); 2465 2466 MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL, 2467 dp_aux_ch_ctl_mmio_write); 2468 2469 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2470 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2471 MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2472 MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2473 MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2474 2475 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write); 2476 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write); 2477 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write); 2478 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write); 2479 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write); 2480 2481 MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write); 2482 MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write); 2483 MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write); 2484 MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write); 2485 MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL); 2486 2487 MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2488 MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2489 MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2490 MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2491 MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2492 2493 MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL); 2494 MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL); 2495 MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A), D_ALL); 2496 2497 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL); 2498 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL); 2499 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL); 2500 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL); 2501 2502 MMIO_D(_MMIO(_TRANSA_MSA_MISC), D_ALL); 2503 MMIO_D(_MMIO(_TRANSB_MSA_MISC), D_ALL); 2504 MMIO_D(_MMIO(_TRANSC_MSA_MISC), D_ALL); 2505 MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC), D_ALL); 2506 2507 MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL); 2508 MMIO_D(FORCEWAKE_ACK, D_ALL); 2509 MMIO_D(GEN6_GT_CORE_STATUS, D_ALL); 2510 MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL); 2511 MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL); 2512 MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL); 2513 MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write); 2514 MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL); 2515 MMIO_D(ECOBUS, D_ALL); 2516 MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL); 2517 MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL); 2518 MMIO_D(GEN6_RPNSWREQ, D_ALL); 2519 MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL); 2520 MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL); 2521 MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL); 2522 MMIO_D(GEN6_RPSTAT1, D_ALL); 2523 MMIO_D(GEN6_RP_CONTROL, D_ALL); 2524 MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL); 2525 MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL); 2526 MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL); 2527 MMIO_D(GEN6_RP_CUR_UP, D_ALL); 2528 MMIO_D(GEN6_RP_PREV_UP, D_ALL); 2529 MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL); 2530 MMIO_D(GEN6_RP_CUR_DOWN, D_ALL); 2531 MMIO_D(GEN6_RP_PREV_DOWN, D_ALL); 2532 MMIO_D(GEN6_RP_UP_EI, D_ALL); 2533 MMIO_D(GEN6_RP_DOWN_EI, D_ALL); 2534 MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL); 2535 MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL); 2536 MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL); 2537 MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL); 2538 MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL); 2539 MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL); 2540 MMIO_D(GEN6_RC_SLEEP, D_ALL); 2541 MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL); 2542 MMIO_D(GEN6_RC6_THRESHOLD, D_ALL); 2543 MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL); 2544 MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL); 2545 MMIO_D(GEN6_PMINTRMSK, D_ALL); 2546 MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write); 2547 MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write); 2548 MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write); 2549 MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write); 2550 MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write); 2551 MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write); 2552 2553 MMIO_D(RSTDBYCTL, D_ALL); 2554 2555 MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write); 2556 MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write); 2557 MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write); 2558 2559 MMIO_D(TILECTL, D_ALL); 2560 2561 MMIO_D(GEN6_UCGCTL1, D_ALL); 2562 MMIO_D(GEN6_UCGCTL2, D_ALL); 2563 2564 MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL); 2565 2566 MMIO_D(GEN6_PCODE_DATA, D_ALL); 2567 MMIO_D(_MMIO(0x13812c), D_ALL); 2568 MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL); 2569 MMIO_D(HSW_EDRAM_CAP, D_ALL); 2570 MMIO_D(HSW_IDICR, D_ALL); 2571 MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL); 2572 2573 MMIO_D(_MMIO(0x3c), D_ALL); 2574 MMIO_D(_MMIO(0x860), D_ALL); 2575 MMIO_D(ECOSKPD, D_ALL); 2576 MMIO_D(_MMIO(0x121d0), D_ALL); 2577 MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL); 2578 MMIO_D(_MMIO(0x41d0), D_ALL); 2579 MMIO_D(GAC_ECO_BITS, D_ALL); 2580 MMIO_D(_MMIO(0x6200), D_ALL); 2581 MMIO_D(_MMIO(0x6204), D_ALL); 2582 MMIO_D(_MMIO(0x6208), D_ALL); 2583 MMIO_D(_MMIO(0x7118), D_ALL); 2584 MMIO_D(_MMIO(0x7180), D_ALL); 2585 MMIO_D(_MMIO(0x7408), D_ALL); 2586 MMIO_D(_MMIO(0x7c00), D_ALL); 2587 MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write); 2588 MMIO_D(_MMIO(0x911c), D_ALL); 2589 MMIO_D(_MMIO(0x9120), D_ALL); 2590 MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL); 2591 2592 MMIO_D(GAB_CTL, D_ALL); 2593 MMIO_D(_MMIO(0x48800), D_ALL); 2594 MMIO_D(_MMIO(0xce044), D_ALL); 2595 MMIO_D(_MMIO(0xe6500), D_ALL); 2596 MMIO_D(_MMIO(0xe6504), D_ALL); 2597 MMIO_D(_MMIO(0xe6600), D_ALL); 2598 MMIO_D(_MMIO(0xe6604), D_ALL); 2599 MMIO_D(_MMIO(0xe6700), D_ALL); 2600 MMIO_D(_MMIO(0xe6704), D_ALL); 2601 MMIO_D(_MMIO(0xe6800), D_ALL); 2602 MMIO_D(_MMIO(0xe6804), D_ALL); 2603 MMIO_D(PCH_GMBUS4, D_ALL); 2604 MMIO_D(PCH_GMBUS5, D_ALL); 2605 2606 MMIO_D(_MMIO(0x902c), D_ALL); 2607 MMIO_D(_MMIO(0xec008), D_ALL); 2608 MMIO_D(_MMIO(0xec00c), D_ALL); 2609 MMIO_D(_MMIO(0xec008 + 0x18), D_ALL); 2610 MMIO_D(_MMIO(0xec00c + 0x18), D_ALL); 2611 MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL); 2612 MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL); 2613 MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL); 2614 MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL); 2615 MMIO_D(_MMIO(0xec408), D_ALL); 2616 MMIO_D(_MMIO(0xec40c), D_ALL); 2617 MMIO_D(_MMIO(0xec408 + 0x18), D_ALL); 2618 MMIO_D(_MMIO(0xec40c + 0x18), D_ALL); 2619 MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL); 2620 MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL); 2621 MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL); 2622 MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL); 2623 MMIO_D(_MMIO(0xfc810), D_ALL); 2624 MMIO_D(_MMIO(0xfc81c), D_ALL); 2625 MMIO_D(_MMIO(0xfc828), D_ALL); 2626 MMIO_D(_MMIO(0xfc834), D_ALL); 2627 MMIO_D(_MMIO(0xfcc00), D_ALL); 2628 MMIO_D(_MMIO(0xfcc0c), D_ALL); 2629 MMIO_D(_MMIO(0xfcc18), D_ALL); 2630 MMIO_D(_MMIO(0xfcc24), D_ALL); 2631 MMIO_D(_MMIO(0xfd000), D_ALL); 2632 MMIO_D(_MMIO(0xfd00c), D_ALL); 2633 MMIO_D(_MMIO(0xfd018), D_ALL); 2634 MMIO_D(_MMIO(0xfd024), D_ALL); 2635 MMIO_D(_MMIO(0xfd034), D_ALL); 2636 2637 MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write); 2638 MMIO_D(_MMIO(0x2054), D_ALL); 2639 MMIO_D(_MMIO(0x12054), D_ALL); 2640 MMIO_D(_MMIO(0x22054), D_ALL); 2641 MMIO_D(_MMIO(0x1a054), D_ALL); 2642 2643 MMIO_D(_MMIO(0x44070), D_ALL); 2644 MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2645 MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL); 2646 MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL); 2647 MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL); 2648 MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL); 2649 2650 MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL); 2651 MMIO_D(_MMIO(0x2b00), D_BDW_PLUS); 2652 MMIO_D(_MMIO(0x2360), D_BDW_PLUS); 2653 MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2654 MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2655 MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2656 2657 MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2658 MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2659 MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL); 2660 2661 MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2662 MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2663 MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2664 MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2665 MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2666 MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2667 MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2668 MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2669 MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2670 MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2671 MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2672 MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2673 MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2674 MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2675 MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2676 MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2677 MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2678 2679 MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2680 MMIO_RING_GM_RDR(RING_BBADDR, D_ALL, NULL, NULL); 2681 MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL); 2682 MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL); 2683 MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL); 2684 MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL); 2685 MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL); 2686 MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2687 MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2688 MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2689 MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2690 2691 MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write); 2692 MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write); 2693 MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL); 2694 2695 return 0; 2696 } 2697 2698 static int init_bdw_mmio_info(struct intel_gvt *gvt) 2699 { 2700 struct drm_i915_private *dev_priv = gvt->gt->i915; 2701 int ret; 2702 2703 MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2704 MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2705 MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2706 MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS); 2707 2708 MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2709 MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2710 MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2711 MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS); 2712 2713 MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2714 MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2715 MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2716 MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS); 2717 2718 MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2719 MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2720 MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2721 MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS); 2722 2723 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL, 2724 intel_vgpu_reg_imr_handler); 2725 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL, 2726 intel_vgpu_reg_ier_handler); 2727 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL, 2728 intel_vgpu_reg_iir_handler); 2729 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS); 2730 2731 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL, 2732 intel_vgpu_reg_imr_handler); 2733 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL, 2734 intel_vgpu_reg_ier_handler); 2735 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL, 2736 intel_vgpu_reg_iir_handler); 2737 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS); 2738 2739 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL, 2740 intel_vgpu_reg_imr_handler); 2741 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL, 2742 intel_vgpu_reg_ier_handler); 2743 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL, 2744 intel_vgpu_reg_iir_handler); 2745 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS); 2746 2747 MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2748 MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2749 MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2750 MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS); 2751 2752 MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2753 MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2754 MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2755 MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS); 2756 2757 MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2758 MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2759 MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2760 MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS); 2761 2762 MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL, 2763 intel_vgpu_reg_master_irq_handler); 2764 2765 MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, F_CMD_ACCESS, 2766 mmio_read_from_hw, NULL); 2767 2768 #define RING_REG(base) _MMIO((base) + 0xd0) 2769 MMIO_RING_F(RING_REG, 4, F_RO, 0, 2770 ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL, 2771 ring_reset_ctl_write); 2772 #undef RING_REG 2773 2774 #define RING_REG(base) _MMIO((base) + 0x230) 2775 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write); 2776 #undef RING_REG 2777 2778 #define RING_REG(base) _MMIO((base) + 0x234) 2779 MMIO_RING_F(RING_REG, 8, F_RO | F_CMD_ACCESS, 0, ~0, D_BDW_PLUS, 2780 NULL, NULL); 2781 #undef RING_REG 2782 2783 #define RING_REG(base) _MMIO((base) + 0x244) 2784 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2785 #undef RING_REG 2786 2787 #define RING_REG(base) _MMIO((base) + 0x370) 2788 MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL); 2789 #undef RING_REG 2790 2791 #define RING_REG(base) _MMIO((base) + 0x3a0) 2792 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2793 #undef RING_REG 2794 2795 MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS); 2796 MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS); 2797 MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS); 2798 MMIO_D(_MMIO(0x1c1d0), D_BDW_PLUS); 2799 MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS); 2800 MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS); 2801 MMIO_D(_MMIO(0x1c054), D_BDW_PLUS); 2802 2803 MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write); 2804 2805 MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS); 2806 MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS); 2807 2808 MMIO_D(GAMTARBMODE, D_BDW_PLUS); 2809 2810 #define RING_REG(base) _MMIO((base) + 0x270) 2811 MMIO_RING_F(RING_REG, 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL); 2812 #undef RING_REG 2813 2814 MMIO_RING_GM_RDR(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write); 2815 2816 MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2817 2818 MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS); 2819 MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS); 2820 MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS); 2821 2822 MMIO_D(WM_MISC, D_BDW); 2823 MMIO_D(_MMIO(_SRD_CTL_EDP), D_BDW); 2824 2825 MMIO_D(_MMIO(0x6671c), D_BDW_PLUS); 2826 MMIO_D(_MMIO(0x66c00), D_BDW_PLUS); 2827 MMIO_D(_MMIO(0x66c04), D_BDW_PLUS); 2828 2829 MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS); 2830 2831 MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS); 2832 MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS); 2833 MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS); 2834 2835 MMIO_D(_MMIO(0xfdc), D_BDW_PLUS); 2836 MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2837 NULL, NULL); 2838 MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2839 NULL, NULL); 2840 MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2841 2842 MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL); 2843 MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL); 2844 MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2845 MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL); 2846 MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL); 2847 MMIO_D(_MMIO(0xb110), D_BDW); 2848 2849 MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, 2850 NULL, force_nonpriv_write); 2851 2852 MMIO_D(_MMIO(0x44484), D_BDW_PLUS); 2853 MMIO_D(_MMIO(0x4448c), D_BDW_PLUS); 2854 2855 MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL); 2856 MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS); 2857 2858 MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL); 2859 2860 MMIO_D(_MMIO(0x110000), D_BDW_PLUS); 2861 2862 MMIO_D(_MMIO(0x48400), D_BDW_PLUS); 2863 2864 MMIO_D(_MMIO(0x6e570), D_BDW_PLUS); 2865 MMIO_D(_MMIO(0x65f10), D_BDW_PLUS); 2866 2867 MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2868 MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2869 MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2870 MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2871 2872 MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL); 2873 2874 MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2875 MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2876 MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2877 MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2878 MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2879 MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2880 MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2881 MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2882 MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2883 MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2884 return 0; 2885 } 2886 2887 static int init_skl_mmio_info(struct intel_gvt *gvt) 2888 { 2889 struct drm_i915_private *dev_priv = gvt->gt->i915; 2890 int ret; 2891 2892 MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2893 MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL); 2894 MMIO_DH(FORCEWAKE_BLITTER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2895 MMIO_DH(FORCEWAKE_ACK_BLITTER_GEN9, D_SKL_PLUS, NULL, NULL); 2896 MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2897 MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL); 2898 2899 MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 2900 dp_aux_ch_ctl_mmio_write); 2901 MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 2902 dp_aux_ch_ctl_mmio_write); 2903 MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 2904 dp_aux_ch_ctl_mmio_write); 2905 2906 MMIO_D(HSW_PWR_WELL_CTL1, D_SKL_PLUS); 2907 MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write); 2908 2909 MMIO_DH(DBUF_CTL_S(0), D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write); 2910 2911 MMIO_D(GEN9_PG_ENABLE, D_SKL_PLUS); 2912 MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS); 2913 MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS); 2914 MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2915 MMIO_DH(MMCD_MISC_CTRL, D_SKL_PLUS, NULL, NULL); 2916 MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL); 2917 MMIO_D(DC_STATE_EN, D_SKL_PLUS); 2918 MMIO_D(DC_STATE_DEBUG, D_SKL_PLUS); 2919 MMIO_D(CDCLK_CTL, D_SKL_PLUS); 2920 MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write); 2921 MMIO_DH(LCPLL2_CTL, D_SKL_PLUS, NULL, skl_lcpll_write); 2922 MMIO_D(_MMIO(_DPLL1_CFGCR1), D_SKL_PLUS); 2923 MMIO_D(_MMIO(_DPLL2_CFGCR1), D_SKL_PLUS); 2924 MMIO_D(_MMIO(_DPLL3_CFGCR1), D_SKL_PLUS); 2925 MMIO_D(_MMIO(_DPLL1_CFGCR2), D_SKL_PLUS); 2926 MMIO_D(_MMIO(_DPLL2_CFGCR2), D_SKL_PLUS); 2927 MMIO_D(_MMIO(_DPLL3_CFGCR2), D_SKL_PLUS); 2928 MMIO_D(DPLL_CTRL1, D_SKL_PLUS); 2929 MMIO_D(DPLL_CTRL2, D_SKL_PLUS); 2930 MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL); 2931 2932 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); 2933 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); 2934 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); 2935 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); 2936 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); 2937 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); 2938 2939 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); 2940 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); 2941 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); 2942 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); 2943 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); 2944 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); 2945 2946 MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); 2947 MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); 2948 MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); 2949 MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); 2950 MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); 2951 MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); 2952 2953 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 2954 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 2955 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 2956 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); 2957 2958 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 2959 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 2960 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 2961 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); 2962 2963 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 2964 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 2965 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2966 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); 2967 2968 MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL); 2969 MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL); 2970 MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL); 2971 2972 MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2973 MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2974 MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2975 2976 MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2977 MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2978 MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2979 2980 MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2981 MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2982 MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2983 2984 MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2985 MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2986 MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2987 2988 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 2989 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 2990 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 2991 2992 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 2993 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 2994 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 2995 2996 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 2997 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 2998 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2999 3000 MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL); 3001 MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL); 3002 MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL); 3003 3004 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 3005 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 3006 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 3007 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); 3008 3009 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 3010 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 3011 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 3012 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); 3013 3014 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 3015 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 3016 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 3017 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); 3018 3019 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL); 3020 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL); 3021 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL); 3022 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL); 3023 3024 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL); 3025 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL); 3026 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL); 3027 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL); 3028 3029 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL); 3030 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL); 3031 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL); 3032 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL); 3033 3034 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL); 3035 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL); 3036 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL); 3037 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL); 3038 3039 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL); 3040 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL); 3041 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL); 3042 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL); 3043 3044 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL); 3045 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL); 3046 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL); 3047 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL); 3048 3049 MMIO_D(_MMIO(_PLANE_CTL_3_A), D_SKL_PLUS); 3050 MMIO_D(_MMIO(_PLANE_CTL_3_B), D_SKL_PLUS); 3051 MMIO_D(_MMIO(0x72380), D_SKL_PLUS); 3052 MMIO_D(_MMIO(0x7239c), D_SKL_PLUS); 3053 MMIO_D(_MMIO(_PLANE_SURF_3_A), D_SKL_PLUS); 3054 3055 MMIO_D(CSR_SSP_BASE, D_SKL_PLUS); 3056 MMIO_D(CSR_HTP_SKL, D_SKL_PLUS); 3057 MMIO_D(CSR_LAST_WRITE, D_SKL_PLUS); 3058 3059 MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 3060 3061 MMIO_D(SKL_DFSM, D_SKL_PLUS); 3062 MMIO_D(DISPIO_CR_TX_BMU_CR0, D_SKL_PLUS); 3063 3064 MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS, 3065 NULL, NULL); 3066 MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS, 3067 NULL, NULL); 3068 3069 MMIO_D(RPM_CONFIG0, D_SKL_PLUS); 3070 MMIO_D(_MMIO(0xd08), D_SKL_PLUS); 3071 MMIO_D(RC6_LOCATION, D_SKL_PLUS); 3072 MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS, 3073 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 3074 MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, 3075 NULL, NULL); 3076 3077 /* TRTT */ 3078 MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 3079 MMIO_DFH(TRVATTL3PTRDW(1), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 3080 MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 3081 MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 3082 MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 3083 MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS, 3084 NULL, gen9_trtte_write); 3085 MMIO_DH(_MMIO(0x4dfc), D_SKL_PLUS, NULL, gen9_trtt_chicken_write); 3086 3087 MMIO_D(_MMIO(0x46430), D_SKL_PLUS); 3088 3089 MMIO_D(_MMIO(0x46520), D_SKL_PLUS); 3090 3091 MMIO_D(_MMIO(0xc403c), D_SKL_PLUS); 3092 MMIO_DFH(GEN8_GARBCNTL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 3093 MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write); 3094 3095 MMIO_D(_MMIO(0x65900), D_SKL_PLUS); 3096 MMIO_D(GEN6_STOLEN_RESERVED, D_SKL_PLUS); 3097 MMIO_D(_MMIO(0x4068), D_SKL_PLUS); 3098 MMIO_D(_MMIO(0x67054), D_SKL_PLUS); 3099 MMIO_D(_MMIO(0x6e560), D_SKL_PLUS); 3100 MMIO_D(_MMIO(0x6e554), D_SKL_PLUS); 3101 MMIO_D(_MMIO(0x2b20), D_SKL_PLUS); 3102 MMIO_D(_MMIO(0x65f00), D_SKL_PLUS); 3103 MMIO_D(_MMIO(0x65f08), D_SKL_PLUS); 3104 MMIO_D(_MMIO(0x320f0), D_SKL_PLUS); 3105 3106 MMIO_D(_MMIO(0x70034), D_SKL_PLUS); 3107 MMIO_D(_MMIO(0x71034), D_SKL_PLUS); 3108 MMIO_D(_MMIO(0x72034), D_SKL_PLUS); 3109 3110 MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A)), D_SKL_PLUS); 3111 MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B)), D_SKL_PLUS); 3112 MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C)), D_SKL_PLUS); 3113 MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A)), D_SKL_PLUS); 3114 MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B)), D_SKL_PLUS); 3115 MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C)), D_SKL_PLUS); 3116 MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A)), D_SKL_PLUS); 3117 MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)), D_SKL_PLUS); 3118 MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)), D_SKL_PLUS); 3119 3120 MMIO_D(_MMIO(0x44500), D_SKL_PLUS); 3121 #define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4) 3122 MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, 3123 NULL, csfe_chicken1_mmio_write); 3124 #undef CSFE_CHICKEN1_REG 3125 MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, 3126 NULL, NULL); 3127 MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, 3128 NULL, NULL); 3129 3130 MMIO_D(GAMT_CHKN_BIT_REG, D_KBL); 3131 MMIO_D(GEN9_CTX_PREEMPT_REG, D_KBL | D_SKL); 3132 3133 return 0; 3134 } 3135 3136 static int init_bxt_mmio_info(struct intel_gvt *gvt) 3137 { 3138 struct drm_i915_private *dev_priv = gvt->gt->i915; 3139 int ret; 3140 3141 MMIO_F(_MMIO(0x80000), 0x3000, 0, 0, 0, D_BXT, NULL, NULL); 3142 3143 MMIO_D(GEN7_SAMPLER_INSTDONE, D_BXT); 3144 MMIO_D(GEN7_ROW_INSTDONE, D_BXT); 3145 MMIO_D(GEN8_FAULT_TLB_DATA0, D_BXT); 3146 MMIO_D(GEN8_FAULT_TLB_DATA1, D_BXT); 3147 MMIO_D(ERROR_GEN6, D_BXT); 3148 MMIO_D(DONE_REG, D_BXT); 3149 MMIO_D(EIR, D_BXT); 3150 MMIO_D(PGTBL_ER, D_BXT); 3151 MMIO_D(_MMIO(0x4194), D_BXT); 3152 MMIO_D(_MMIO(0x4294), D_BXT); 3153 MMIO_D(_MMIO(0x4494), D_BXT); 3154 3155 MMIO_RING_D(RING_PSMI_CTL, D_BXT); 3156 MMIO_RING_D(RING_DMA_FADD, D_BXT); 3157 MMIO_RING_D(RING_DMA_FADD_UDW, D_BXT); 3158 MMIO_RING_D(RING_IPEHR, D_BXT); 3159 MMIO_RING_D(RING_INSTPS, D_BXT); 3160 MMIO_RING_D(RING_BBADDR_UDW, D_BXT); 3161 MMIO_RING_D(RING_BBSTATE, D_BXT); 3162 MMIO_RING_D(RING_IPEIR, D_BXT); 3163 3164 MMIO_F(SOFT_SCRATCH(0), 16 * 4, 0, 0, 0, D_BXT, NULL, NULL); 3165 3166 MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write); 3167 MMIO_D(BXT_RP_STATE_CAP, D_BXT); 3168 MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT, 3169 NULL, bxt_phy_ctl_family_write); 3170 MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT, 3171 NULL, bxt_phy_ctl_family_write); 3172 MMIO_D(BXT_PHY_CTL(PORT_A), D_BXT); 3173 MMIO_D(BXT_PHY_CTL(PORT_B), D_BXT); 3174 MMIO_D(BXT_PHY_CTL(PORT_C), D_BXT); 3175 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT, 3176 NULL, bxt_port_pll_enable_write); 3177 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT, 3178 NULL, bxt_port_pll_enable_write); 3179 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL, 3180 bxt_port_pll_enable_write); 3181 3182 MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY0), D_BXT); 3183 MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY0), D_BXT); 3184 MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY0), D_BXT); 3185 MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY0), D_BXT); 3186 MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY0), D_BXT); 3187 MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY0), D_BXT); 3188 MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY0), D_BXT); 3189 MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY0), D_BXT); 3190 MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY0), D_BXT); 3191 3192 MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY1), D_BXT); 3193 MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY1), D_BXT); 3194 MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY1), D_BXT); 3195 MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY1), D_BXT); 3196 MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY1), D_BXT); 3197 MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY1), D_BXT); 3198 MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY1), D_BXT); 3199 MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY1), D_BXT); 3200 MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY1), D_BXT); 3201 3202 MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH0), D_BXT); 3203 MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH0), D_BXT); 3204 MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH0), D_BXT); 3205 MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH0), D_BXT); 3206 MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH0), D_BXT); 3207 MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH0), D_BXT); 3208 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT, 3209 NULL, bxt_pcs_dw12_grp_write); 3210 MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH0), D_BXT); 3211 MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH0), D_BXT); 3212 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT, 3213 bxt_port_tx_dw3_read, NULL); 3214 MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH0), D_BXT); 3215 MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH0), D_BXT); 3216 MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH0), D_BXT); 3217 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT); 3218 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 1), D_BXT); 3219 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 2), D_BXT); 3220 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 3), D_BXT); 3221 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 0), D_BXT); 3222 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 1), D_BXT); 3223 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 2), D_BXT); 3224 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 3), D_BXT); 3225 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 6), D_BXT); 3226 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 8), D_BXT); 3227 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 9), D_BXT); 3228 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 10), D_BXT); 3229 3230 MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH1), D_BXT); 3231 MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH1), D_BXT); 3232 MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH1), D_BXT); 3233 MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH1), D_BXT); 3234 MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH1), D_BXT); 3235 MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH1), D_BXT); 3236 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT, 3237 NULL, bxt_pcs_dw12_grp_write); 3238 MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH1), D_BXT); 3239 MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH1), D_BXT); 3240 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT, 3241 bxt_port_tx_dw3_read, NULL); 3242 MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH1), D_BXT); 3243 MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH1), D_BXT); 3244 MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH1), D_BXT); 3245 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT); 3246 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 1), D_BXT); 3247 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 2), D_BXT); 3248 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 3), D_BXT); 3249 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 0), D_BXT); 3250 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 1), D_BXT); 3251 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 2), D_BXT); 3252 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 3), D_BXT); 3253 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 6), D_BXT); 3254 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 8), D_BXT); 3255 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 9), D_BXT); 3256 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 10), D_BXT); 3257 3258 MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY1, DPIO_CH0), D_BXT); 3259 MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY1, DPIO_CH0), D_BXT); 3260 MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY1, DPIO_CH0), D_BXT); 3261 MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY1, DPIO_CH0), D_BXT); 3262 MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY1, DPIO_CH0), D_BXT); 3263 MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY1, DPIO_CH0), D_BXT); 3264 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT, 3265 NULL, bxt_pcs_dw12_grp_write); 3266 MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY1, DPIO_CH0), D_BXT); 3267 MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY1, DPIO_CH0), D_BXT); 3268 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT, 3269 bxt_port_tx_dw3_read, NULL); 3270 MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY1, DPIO_CH0), D_BXT); 3271 MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY1, DPIO_CH0), D_BXT); 3272 MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY1, DPIO_CH0), D_BXT); 3273 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT); 3274 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 1), D_BXT); 3275 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 2), D_BXT); 3276 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 3), D_BXT); 3277 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 0), D_BXT); 3278 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 1), D_BXT); 3279 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 2), D_BXT); 3280 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 3), D_BXT); 3281 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 6), D_BXT); 3282 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 8), D_BXT); 3283 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 9), D_BXT); 3284 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 10), D_BXT); 3285 3286 MMIO_D(BXT_DE_PLL_CTL, D_BXT); 3287 MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write); 3288 MMIO_D(BXT_DSI_PLL_CTL, D_BXT); 3289 MMIO_D(BXT_DSI_PLL_ENABLE, D_BXT); 3290 3291 MMIO_D(GEN9_CLKGATE_DIS_0, D_BXT); 3292 MMIO_D(GEN9_CLKGATE_DIS_4, D_BXT); 3293 3294 MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_A), D_BXT); 3295 MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT); 3296 MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C), D_BXT); 3297 3298 MMIO_D(RC6_CTX_BASE, D_BXT); 3299 3300 MMIO_D(GEN8_PUSHBUS_CONTROL, D_BXT); 3301 MMIO_D(GEN8_PUSHBUS_ENABLE, D_BXT); 3302 MMIO_D(GEN8_PUSHBUS_SHIFT, D_BXT); 3303 MMIO_D(GEN6_GFXPAUSE, D_BXT); 3304 MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL); 3305 3306 MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL); 3307 3308 return 0; 3309 } 3310 3311 static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt, 3312 unsigned int offset) 3313 { 3314 unsigned long device = intel_gvt_get_device_type(gvt); 3315 struct gvt_mmio_block *block = gvt->mmio.mmio_block; 3316 int num = gvt->mmio.num_mmio_block; 3317 int i; 3318 3319 for (i = 0; i < num; i++, block++) { 3320 if (!(device & block->device)) 3321 continue; 3322 if (offset >= i915_mmio_reg_offset(block->offset) && 3323 offset < i915_mmio_reg_offset(block->offset) + block->size) 3324 return block; 3325 } 3326 return NULL; 3327 } 3328 3329 /** 3330 * intel_gvt_clean_mmio_info - clean up MMIO information table for GVT device 3331 * @gvt: GVT device 3332 * 3333 * This function is called at the driver unloading stage, to clean up the MMIO 3334 * information table of GVT device 3335 * 3336 */ 3337 void intel_gvt_clean_mmio_info(struct intel_gvt *gvt) 3338 { 3339 struct hlist_node *tmp; 3340 struct intel_gvt_mmio_info *e; 3341 int i; 3342 3343 hash_for_each_safe(gvt->mmio.mmio_info_table, i, tmp, e, node) 3344 kfree(e); 3345 3346 vfree(gvt->mmio.mmio_attribute); 3347 gvt->mmio.mmio_attribute = NULL; 3348 } 3349 3350 /* Special MMIO blocks. */ 3351 static struct gvt_mmio_block mmio_blocks[] = { 3352 {D_SKL_PLUS, _MMIO(CSR_MMIO_START_RANGE), 0x3000, NULL, NULL}, 3353 {D_ALL, _MMIO(MCHBAR_MIRROR_BASE_SNB), 0x40000, NULL, NULL}, 3354 {D_ALL, _MMIO(VGT_PVINFO_PAGE), VGT_PVINFO_SIZE, 3355 pvinfo_mmio_read, pvinfo_mmio_write}, 3356 {D_ALL, LGC_PALETTE(PIPE_A, 0), 1024, NULL, NULL}, 3357 {D_ALL, LGC_PALETTE(PIPE_B, 0), 1024, NULL, NULL}, 3358 {D_ALL, LGC_PALETTE(PIPE_C, 0), 1024, NULL, NULL}, 3359 }; 3360 3361 /** 3362 * intel_gvt_setup_mmio_info - setup MMIO information table for GVT device 3363 * @gvt: GVT device 3364 * 3365 * This function is called at the initialization stage, to setup the MMIO 3366 * information table for GVT device 3367 * 3368 * Returns: 3369 * zero on success, negative if failed. 3370 */ 3371 int intel_gvt_setup_mmio_info(struct intel_gvt *gvt) 3372 { 3373 struct intel_gvt_device_info *info = &gvt->device_info; 3374 struct drm_i915_private *i915 = gvt->gt->i915; 3375 int size = info->mmio_size / 4 * sizeof(*gvt->mmio.mmio_attribute); 3376 int ret; 3377 3378 gvt->mmio.mmio_attribute = vzalloc(size); 3379 if (!gvt->mmio.mmio_attribute) 3380 return -ENOMEM; 3381 3382 ret = init_generic_mmio_info(gvt); 3383 if (ret) 3384 goto err; 3385 3386 if (IS_BROADWELL(i915)) { 3387 ret = init_bdw_mmio_info(gvt); 3388 if (ret) 3389 goto err; 3390 } else if (IS_SKYLAKE(i915) || 3391 IS_KABYLAKE(i915) || 3392 IS_COFFEELAKE(i915)) { 3393 ret = init_bdw_mmio_info(gvt); 3394 if (ret) 3395 goto err; 3396 ret = init_skl_mmio_info(gvt); 3397 if (ret) 3398 goto err; 3399 } else if (IS_BROXTON(i915)) { 3400 ret = init_bdw_mmio_info(gvt); 3401 if (ret) 3402 goto err; 3403 ret = init_skl_mmio_info(gvt); 3404 if (ret) 3405 goto err; 3406 ret = init_bxt_mmio_info(gvt); 3407 if (ret) 3408 goto err; 3409 } 3410 3411 gvt->mmio.mmio_block = mmio_blocks; 3412 gvt->mmio.num_mmio_block = ARRAY_SIZE(mmio_blocks); 3413 3414 return 0; 3415 err: 3416 intel_gvt_clean_mmio_info(gvt); 3417 return ret; 3418 } 3419 3420 /** 3421 * intel_gvt_for_each_tracked_mmio - iterate each tracked mmio 3422 * @gvt: a GVT device 3423 * @handler: the handler 3424 * @data: private data given to handler 3425 * 3426 * Returns: 3427 * Zero on success, negative error code if failed. 3428 */ 3429 int intel_gvt_for_each_tracked_mmio(struct intel_gvt *gvt, 3430 int (*handler)(struct intel_gvt *gvt, u32 offset, void *data), 3431 void *data) 3432 { 3433 struct gvt_mmio_block *block = gvt->mmio.mmio_block; 3434 struct intel_gvt_mmio_info *e; 3435 int i, j, ret; 3436 3437 hash_for_each(gvt->mmio.mmio_info_table, i, e, node) { 3438 ret = handler(gvt, e->offset, data); 3439 if (ret) 3440 return ret; 3441 } 3442 3443 for (i = 0; i < gvt->mmio.num_mmio_block; i++, block++) { 3444 /* pvinfo data doesn't come from hw mmio */ 3445 if (i915_mmio_reg_offset(block->offset) == VGT_PVINFO_PAGE) 3446 continue; 3447 3448 for (j = 0; j < block->size; j += 4) { 3449 ret = handler(gvt, 3450 i915_mmio_reg_offset(block->offset) + j, 3451 data); 3452 if (ret) 3453 return ret; 3454 } 3455 } 3456 return 0; 3457 } 3458 3459 /** 3460 * intel_vgpu_default_mmio_read - default MMIO read handler 3461 * @vgpu: a vGPU 3462 * @offset: access offset 3463 * @p_data: data return buffer 3464 * @bytes: access data length 3465 * 3466 * Returns: 3467 * Zero on success, negative error code if failed. 3468 */ 3469 int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 3470 void *p_data, unsigned int bytes) 3471 { 3472 read_vreg(vgpu, offset, p_data, bytes); 3473 return 0; 3474 } 3475 3476 /** 3477 * intel_t_default_mmio_write - default MMIO write handler 3478 * @vgpu: a vGPU 3479 * @offset: access offset 3480 * @p_data: write data buffer 3481 * @bytes: access data length 3482 * 3483 * Returns: 3484 * Zero on success, negative error code if failed. 3485 */ 3486 int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 3487 void *p_data, unsigned int bytes) 3488 { 3489 write_vreg(vgpu, offset, p_data, bytes); 3490 return 0; 3491 } 3492 3493 /** 3494 * intel_vgpu_mask_mmio_write - write mask register 3495 * @vgpu: a vGPU 3496 * @offset: access offset 3497 * @p_data: write data buffer 3498 * @bytes: access data length 3499 * 3500 * Returns: 3501 * Zero on success, negative error code if failed. 3502 */ 3503 int intel_vgpu_mask_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 3504 void *p_data, unsigned int bytes) 3505 { 3506 u32 mask, old_vreg; 3507 3508 old_vreg = vgpu_vreg(vgpu, offset); 3509 write_vreg(vgpu, offset, p_data, bytes); 3510 mask = vgpu_vreg(vgpu, offset) >> 16; 3511 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask) | 3512 (vgpu_vreg(vgpu, offset) & mask); 3513 3514 return 0; 3515 } 3516 3517 /** 3518 * intel_gvt_in_force_nonpriv_whitelist - if a mmio is in whitelist to be 3519 * force-nopriv register 3520 * 3521 * @gvt: a GVT device 3522 * @offset: register offset 3523 * 3524 * Returns: 3525 * True if the register is in force-nonpriv whitelist; 3526 * False if outside; 3527 */ 3528 bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt, 3529 unsigned int offset) 3530 { 3531 return in_whitelist(offset); 3532 } 3533 3534 /** 3535 * intel_vgpu_mmio_reg_rw - emulate tracked mmio registers 3536 * @vgpu: a vGPU 3537 * @offset: register offset 3538 * @pdata: data buffer 3539 * @bytes: data length 3540 * @is_read: read or write 3541 * 3542 * Returns: 3543 * Zero on success, negative error code if failed. 3544 */ 3545 int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset, 3546 void *pdata, unsigned int bytes, bool is_read) 3547 { 3548 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 3549 struct intel_gvt *gvt = vgpu->gvt; 3550 struct intel_gvt_mmio_info *mmio_info; 3551 struct gvt_mmio_block *mmio_block; 3552 gvt_mmio_func func; 3553 int ret; 3554 3555 if (drm_WARN_ON(&i915->drm, bytes > 8)) 3556 return -EINVAL; 3557 3558 /* 3559 * Handle special MMIO blocks. 3560 */ 3561 mmio_block = find_mmio_block(gvt, offset); 3562 if (mmio_block) { 3563 func = is_read ? mmio_block->read : mmio_block->write; 3564 if (func) 3565 return func(vgpu, offset, pdata, bytes); 3566 goto default_rw; 3567 } 3568 3569 /* 3570 * Normal tracked MMIOs. 3571 */ 3572 mmio_info = find_mmio_info(gvt, offset); 3573 if (!mmio_info) { 3574 gvt_dbg_mmio("untracked MMIO %08x len %d\n", offset, bytes); 3575 goto default_rw; 3576 } 3577 3578 if (is_read) 3579 return mmio_info->read(vgpu, offset, pdata, bytes); 3580 else { 3581 u64 ro_mask = mmio_info->ro_mask; 3582 u32 old_vreg = 0; 3583 u64 data = 0; 3584 3585 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) { 3586 old_vreg = vgpu_vreg(vgpu, offset); 3587 } 3588 3589 if (likely(!ro_mask)) 3590 ret = mmio_info->write(vgpu, offset, pdata, bytes); 3591 else if (!~ro_mask) { 3592 gvt_vgpu_err("try to write RO reg %x\n", offset); 3593 return 0; 3594 } else { 3595 /* keep the RO bits in the virtual register */ 3596 memcpy(&data, pdata, bytes); 3597 data &= ~ro_mask; 3598 data |= vgpu_vreg(vgpu, offset) & ro_mask; 3599 ret = mmio_info->write(vgpu, offset, &data, bytes); 3600 } 3601 3602 /* higher 16bits of mode ctl regs are mask bits for change */ 3603 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) { 3604 u32 mask = vgpu_vreg(vgpu, offset) >> 16; 3605 3606 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask) 3607 | (vgpu_vreg(vgpu, offset) & mask); 3608 } 3609 } 3610 3611 return ret; 3612 3613 default_rw: 3614 return is_read ? 3615 intel_vgpu_default_mmio_read(vgpu, offset, pdata, bytes) : 3616 intel_vgpu_default_mmio_write(vgpu, offset, pdata, bytes); 3617 } 3618