1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Kevin Tian <kevin.tian@intel.com> 25 * Eddie Dong <eddie.dong@intel.com> 26 * Zhiyuan Lv <zhiyuan.lv@intel.com> 27 * 28 * Contributors: 29 * Min He <min.he@intel.com> 30 * Tina Zhang <tina.zhang@intel.com> 31 * Pei Zhang <pei.zhang@intel.com> 32 * Niu Bing <bing.niu@intel.com> 33 * Ping Gao <ping.a.gao@intel.com> 34 * Zhi Wang <zhi.a.wang@intel.com> 35 * 36 37 */ 38 39 #include "i915_drv.h" 40 #include "gvt.h" 41 #include "i915_pvinfo.h" 42 43 /* XXX FIXME i915 has changed PP_XXX definition */ 44 #define PCH_PP_STATUS _MMIO(0xc7200) 45 #define PCH_PP_CONTROL _MMIO(0xc7204) 46 #define PCH_PP_ON_DELAYS _MMIO(0xc7208) 47 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c) 48 #define PCH_PP_DIVISOR _MMIO(0xc7210) 49 50 unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt) 51 { 52 if (IS_BROADWELL(gvt->dev_priv)) 53 return D_BDW; 54 else if (IS_SKYLAKE(gvt->dev_priv)) 55 return D_SKL; 56 else if (IS_KABYLAKE(gvt->dev_priv)) 57 return D_KBL; 58 else if (IS_BROXTON(gvt->dev_priv)) 59 return D_BXT; 60 61 return 0; 62 } 63 64 bool intel_gvt_match_device(struct intel_gvt *gvt, 65 unsigned long device) 66 { 67 return intel_gvt_get_device_type(gvt) & device; 68 } 69 70 static void read_vreg(struct intel_vgpu *vgpu, unsigned int offset, 71 void *p_data, unsigned int bytes) 72 { 73 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); 74 } 75 76 static void write_vreg(struct intel_vgpu *vgpu, unsigned int offset, 77 void *p_data, unsigned int bytes) 78 { 79 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes); 80 } 81 82 static struct intel_gvt_mmio_info *find_mmio_info(struct intel_gvt *gvt, 83 unsigned int offset) 84 { 85 struct intel_gvt_mmio_info *e; 86 87 hash_for_each_possible(gvt->mmio.mmio_info_table, e, node, offset) { 88 if (e->offset == offset) 89 return e; 90 } 91 return NULL; 92 } 93 94 static int new_mmio_info(struct intel_gvt *gvt, 95 u32 offset, u8 flags, u32 size, 96 u32 addr_mask, u32 ro_mask, u32 device, 97 gvt_mmio_func read, gvt_mmio_func write) 98 { 99 struct intel_gvt_mmio_info *info, *p; 100 u32 start, end, i; 101 102 if (!intel_gvt_match_device(gvt, device)) 103 return 0; 104 105 if (WARN_ON(!IS_ALIGNED(offset, 4))) 106 return -EINVAL; 107 108 start = offset; 109 end = offset + size; 110 111 for (i = start; i < end; i += 4) { 112 info = kzalloc(sizeof(*info), GFP_KERNEL); 113 if (!info) 114 return -ENOMEM; 115 116 info->offset = i; 117 p = find_mmio_info(gvt, info->offset); 118 if (p) { 119 WARN(1, "dup mmio definition offset %x\n", 120 info->offset); 121 kfree(info); 122 123 /* We return -EEXIST here to make GVT-g load fail. 124 * So duplicated MMIO can be found as soon as 125 * possible. 126 */ 127 return -EEXIST; 128 } 129 130 info->ro_mask = ro_mask; 131 info->device = device; 132 info->read = read ? read : intel_vgpu_default_mmio_read; 133 info->write = write ? write : intel_vgpu_default_mmio_write; 134 gvt->mmio.mmio_attribute[info->offset / 4] = flags; 135 INIT_HLIST_NODE(&info->node); 136 hash_add(gvt->mmio.mmio_info_table, &info->node, info->offset); 137 gvt->mmio.num_tracked_mmio++; 138 } 139 return 0; 140 } 141 142 /** 143 * intel_gvt_render_mmio_to_ring_id - convert a mmio offset into ring id 144 * @gvt: a GVT device 145 * @offset: register offset 146 * 147 * Returns: 148 * Ring ID on success, negative error code if failed. 149 */ 150 int intel_gvt_render_mmio_to_ring_id(struct intel_gvt *gvt, 151 unsigned int offset) 152 { 153 enum intel_engine_id id; 154 struct intel_engine_cs *engine; 155 156 offset &= ~GENMASK(11, 0); 157 for_each_engine(engine, gvt->dev_priv, id) { 158 if (engine->mmio_base == offset) 159 return id; 160 } 161 return -ENODEV; 162 } 163 164 #define offset_to_fence_num(offset) \ 165 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3) 166 167 #define fence_num_to_offset(num) \ 168 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) 169 170 171 void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason) 172 { 173 switch (reason) { 174 case GVT_FAILSAFE_UNSUPPORTED_GUEST: 175 pr_err("Detected your guest driver doesn't support GVT-g.\n"); 176 break; 177 case GVT_FAILSAFE_INSUFFICIENT_RESOURCE: 178 pr_err("Graphics resource is not enough for the guest\n"); 179 break; 180 case GVT_FAILSAFE_GUEST_ERR: 181 pr_err("GVT Internal error for the guest\n"); 182 break; 183 default: 184 break; 185 } 186 pr_err("Now vgpu %d will enter failsafe mode.\n", vgpu->id); 187 vgpu->failsafe = true; 188 } 189 190 static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu, 191 unsigned int fence_num, void *p_data, unsigned int bytes) 192 { 193 unsigned int max_fence = vgpu_fence_sz(vgpu); 194 195 if (fence_num >= max_fence) { 196 gvt_vgpu_err("access oob fence reg %d/%d\n", 197 fence_num, max_fence); 198 199 /* When guest access oob fence regs without access 200 * pv_info first, we treat guest not supporting GVT, 201 * and we will let vgpu enter failsafe mode. 202 */ 203 if (!vgpu->pv_notified) 204 enter_failsafe_mode(vgpu, 205 GVT_FAILSAFE_UNSUPPORTED_GUEST); 206 207 memset(p_data, 0, bytes); 208 return -EINVAL; 209 } 210 return 0; 211 } 212 213 static int gamw_echo_dev_rw_ia_write(struct intel_vgpu *vgpu, 214 unsigned int offset, void *p_data, unsigned int bytes) 215 { 216 u32 ips = (*(u32 *)p_data) & GAMW_ECO_ENABLE_64K_IPS_FIELD; 217 218 if (INTEL_GEN(vgpu->gvt->dev_priv) <= 10) { 219 if (ips == GAMW_ECO_ENABLE_64K_IPS_FIELD) 220 gvt_dbg_core("vgpu%d: ips enabled\n", vgpu->id); 221 else if (!ips) 222 gvt_dbg_core("vgpu%d: ips disabled\n", vgpu->id); 223 else { 224 /* All engines must be enabled together for vGPU, 225 * since we don't know which engine the ppgtt will 226 * bind to when shadowing. 227 */ 228 gvt_vgpu_err("Unsupported IPS setting %x, cannot enable 64K gtt.\n", 229 ips); 230 return -EINVAL; 231 } 232 } 233 234 write_vreg(vgpu, offset, p_data, bytes); 235 return 0; 236 } 237 238 static int fence_mmio_read(struct intel_vgpu *vgpu, unsigned int off, 239 void *p_data, unsigned int bytes) 240 { 241 int ret; 242 243 ret = sanitize_fence_mmio_access(vgpu, offset_to_fence_num(off), 244 p_data, bytes); 245 if (ret) 246 return ret; 247 read_vreg(vgpu, off, p_data, bytes); 248 return 0; 249 } 250 251 static int fence_mmio_write(struct intel_vgpu *vgpu, unsigned int off, 252 void *p_data, unsigned int bytes) 253 { 254 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 255 unsigned int fence_num = offset_to_fence_num(off); 256 int ret; 257 258 ret = sanitize_fence_mmio_access(vgpu, fence_num, p_data, bytes); 259 if (ret) 260 return ret; 261 write_vreg(vgpu, off, p_data, bytes); 262 263 mmio_hw_access_pre(dev_priv); 264 intel_vgpu_write_fence(vgpu, fence_num, 265 vgpu_vreg64(vgpu, fence_num_to_offset(fence_num))); 266 mmio_hw_access_post(dev_priv); 267 return 0; 268 } 269 270 #define CALC_MODE_MASK_REG(old, new) \ 271 (((new) & GENMASK(31, 16)) \ 272 | ((((old) & GENMASK(15, 0)) & ~((new) >> 16)) \ 273 | ((new) & ((new) >> 16)))) 274 275 static int mul_force_wake_write(struct intel_vgpu *vgpu, 276 unsigned int offset, void *p_data, unsigned int bytes) 277 { 278 u32 old, new; 279 uint32_t ack_reg_offset; 280 281 old = vgpu_vreg(vgpu, offset); 282 new = CALC_MODE_MASK_REG(old, *(u32 *)p_data); 283 284 if (IS_SKYLAKE(vgpu->gvt->dev_priv) 285 || IS_KABYLAKE(vgpu->gvt->dev_priv) 286 || IS_BROXTON(vgpu->gvt->dev_priv)) { 287 switch (offset) { 288 case FORCEWAKE_RENDER_GEN9_REG: 289 ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG; 290 break; 291 case FORCEWAKE_BLITTER_GEN9_REG: 292 ack_reg_offset = FORCEWAKE_ACK_BLITTER_GEN9_REG; 293 break; 294 case FORCEWAKE_MEDIA_GEN9_REG: 295 ack_reg_offset = FORCEWAKE_ACK_MEDIA_GEN9_REG; 296 break; 297 default: 298 /*should not hit here*/ 299 gvt_vgpu_err("invalid forcewake offset 0x%x\n", offset); 300 return -EINVAL; 301 } 302 } else { 303 ack_reg_offset = FORCEWAKE_ACK_HSW_REG; 304 } 305 306 vgpu_vreg(vgpu, offset) = new; 307 vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0)); 308 return 0; 309 } 310 311 static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 312 void *p_data, unsigned int bytes) 313 { 314 unsigned int engine_mask = 0; 315 u32 data; 316 317 write_vreg(vgpu, offset, p_data, bytes); 318 data = vgpu_vreg(vgpu, offset); 319 320 if (data & GEN6_GRDOM_FULL) { 321 gvt_dbg_mmio("vgpu%d: request full GPU reset\n", vgpu->id); 322 engine_mask = ALL_ENGINES; 323 } else { 324 if (data & GEN6_GRDOM_RENDER) { 325 gvt_dbg_mmio("vgpu%d: request RCS reset\n", vgpu->id); 326 engine_mask |= (1 << RCS); 327 } 328 if (data & GEN6_GRDOM_MEDIA) { 329 gvt_dbg_mmio("vgpu%d: request VCS reset\n", vgpu->id); 330 engine_mask |= (1 << VCS); 331 } 332 if (data & GEN6_GRDOM_BLT) { 333 gvt_dbg_mmio("vgpu%d: request BCS Reset\n", vgpu->id); 334 engine_mask |= (1 << BCS); 335 } 336 if (data & GEN6_GRDOM_VECS) { 337 gvt_dbg_mmio("vgpu%d: request VECS Reset\n", vgpu->id); 338 engine_mask |= (1 << VECS); 339 } 340 if (data & GEN8_GRDOM_MEDIA2) { 341 gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id); 342 if (HAS_BSD2(vgpu->gvt->dev_priv)) 343 engine_mask |= (1 << VCS2); 344 } 345 } 346 347 /* vgpu_lock already hold by emulate mmio r/w */ 348 intel_gvt_reset_vgpu_locked(vgpu, false, engine_mask); 349 350 /* sw will wait for the device to ack the reset request */ 351 vgpu_vreg(vgpu, offset) = 0; 352 353 return 0; 354 } 355 356 static int gmbus_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 357 void *p_data, unsigned int bytes) 358 { 359 return intel_gvt_i2c_handle_gmbus_read(vgpu, offset, p_data, bytes); 360 } 361 362 static int gmbus_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 363 void *p_data, unsigned int bytes) 364 { 365 return intel_gvt_i2c_handle_gmbus_write(vgpu, offset, p_data, bytes); 366 } 367 368 static int pch_pp_control_mmio_write(struct intel_vgpu *vgpu, 369 unsigned int offset, void *p_data, unsigned int bytes) 370 { 371 write_vreg(vgpu, offset, p_data, bytes); 372 373 if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) { 374 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_ON; 375 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE; 376 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN; 377 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE; 378 379 } else 380 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= 381 ~(PP_ON | PP_SEQUENCE_POWER_DOWN 382 | PP_CYCLE_DELAY_ACTIVE); 383 return 0; 384 } 385 386 static int transconf_mmio_write(struct intel_vgpu *vgpu, 387 unsigned int offset, void *p_data, unsigned int bytes) 388 { 389 write_vreg(vgpu, offset, p_data, bytes); 390 391 if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE) 392 vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE; 393 else 394 vgpu_vreg(vgpu, offset) &= ~TRANS_STATE_ENABLE; 395 return 0; 396 } 397 398 static int lcpll_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 399 void *p_data, unsigned int bytes) 400 { 401 write_vreg(vgpu, offset, p_data, bytes); 402 403 if (vgpu_vreg(vgpu, offset) & LCPLL_PLL_DISABLE) 404 vgpu_vreg(vgpu, offset) &= ~LCPLL_PLL_LOCK; 405 else 406 vgpu_vreg(vgpu, offset) |= LCPLL_PLL_LOCK; 407 408 if (vgpu_vreg(vgpu, offset) & LCPLL_CD_SOURCE_FCLK) 409 vgpu_vreg(vgpu, offset) |= LCPLL_CD_SOURCE_FCLK_DONE; 410 else 411 vgpu_vreg(vgpu, offset) &= ~LCPLL_CD_SOURCE_FCLK_DONE; 412 413 return 0; 414 } 415 416 static int dpy_reg_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 417 void *p_data, unsigned int bytes) 418 { 419 switch (offset) { 420 case 0xe651c: 421 case 0xe661c: 422 case 0xe671c: 423 case 0xe681c: 424 vgpu_vreg(vgpu, offset) = 1 << 17; 425 break; 426 case 0xe6c04: 427 vgpu_vreg(vgpu, offset) = 0x3; 428 break; 429 case 0xe6e1c: 430 vgpu_vreg(vgpu, offset) = 0x2f << 16; 431 break; 432 default: 433 return -EINVAL; 434 } 435 436 read_vreg(vgpu, offset, p_data, bytes); 437 return 0; 438 } 439 440 static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 441 void *p_data, unsigned int bytes) 442 { 443 u32 data; 444 445 write_vreg(vgpu, offset, p_data, bytes); 446 data = vgpu_vreg(vgpu, offset); 447 448 if (data & PIPECONF_ENABLE) 449 vgpu_vreg(vgpu, offset) |= I965_PIPECONF_ACTIVE; 450 else 451 vgpu_vreg(vgpu, offset) &= ~I965_PIPECONF_ACTIVE; 452 /* vgpu_lock already hold by emulate mmio r/w */ 453 mutex_unlock(&vgpu->vgpu_lock); 454 intel_gvt_check_vblank_emulation(vgpu->gvt); 455 mutex_lock(&vgpu->vgpu_lock); 456 return 0; 457 } 458 459 /* ascendingly sorted */ 460 static i915_reg_t force_nonpriv_white_list[] = { 461 GEN9_CS_DEBUG_MODE1, //_MMIO(0x20ec) 462 GEN9_CTX_PREEMPT_REG,//_MMIO(0x2248) 463 GEN8_CS_CHICKEN1,//_MMIO(0x2580) 464 _MMIO(0x2690), 465 _MMIO(0x2694), 466 _MMIO(0x2698), 467 _MMIO(0x4de0), 468 _MMIO(0x4de4), 469 _MMIO(0x4dfc), 470 GEN7_COMMON_SLICE_CHICKEN1,//_MMIO(0x7010) 471 _MMIO(0x7014), 472 HDC_CHICKEN0,//_MMIO(0x7300) 473 GEN8_HDC_CHICKEN1,//_MMIO(0x7304) 474 _MMIO(0x7700), 475 _MMIO(0x7704), 476 _MMIO(0x7708), 477 _MMIO(0x770c), 478 _MMIO(0xb110), 479 GEN8_L3SQCREG4,//_MMIO(0xb118) 480 _MMIO(0xe100), 481 _MMIO(0xe18c), 482 _MMIO(0xe48c), 483 _MMIO(0xe5f4), 484 }; 485 486 /* a simple bsearch */ 487 static inline bool in_whitelist(unsigned int reg) 488 { 489 int left = 0, right = ARRAY_SIZE(force_nonpriv_white_list); 490 i915_reg_t *array = force_nonpriv_white_list; 491 492 while (left < right) { 493 int mid = (left + right)/2; 494 495 if (reg > array[mid].reg) 496 left = mid + 1; 497 else if (reg < array[mid].reg) 498 right = mid; 499 else 500 return true; 501 } 502 return false; 503 } 504 505 static int force_nonpriv_write(struct intel_vgpu *vgpu, 506 unsigned int offset, void *p_data, unsigned int bytes) 507 { 508 u32 reg_nonpriv = *(u32 *)p_data; 509 int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset); 510 u32 ring_base; 511 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 512 int ret = -EINVAL; 513 514 if ((bytes != 4) || ((offset & (bytes - 1)) != 0) || ring_id < 0) { 515 gvt_err("vgpu(%d) ring %d Invalid FORCE_NONPRIV offset %x(%dB)\n", 516 vgpu->id, ring_id, offset, bytes); 517 return ret; 518 } 519 520 ring_base = dev_priv->engine[ring_id]->mmio_base; 521 522 if (in_whitelist(reg_nonpriv) || 523 reg_nonpriv == i915_mmio_reg_offset(RING_NOPID(ring_base))) { 524 ret = intel_vgpu_default_mmio_write(vgpu, offset, p_data, 525 bytes); 526 } else 527 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x at offset %x\n", 528 vgpu->id, reg_nonpriv, offset); 529 530 return 0; 531 } 532 533 static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 534 void *p_data, unsigned int bytes) 535 { 536 write_vreg(vgpu, offset, p_data, bytes); 537 538 if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) { 539 vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE; 540 } else { 541 vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE; 542 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E))) 543 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) 544 &= ~DP_TP_STATUS_AUTOTRAIN_DONE; 545 } 546 return 0; 547 } 548 549 static int fdi_rx_iir_mmio_write(struct intel_vgpu *vgpu, 550 unsigned int offset, void *p_data, unsigned int bytes) 551 { 552 vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data; 553 return 0; 554 } 555 556 #define FDI_LINK_TRAIN_PATTERN1 0 557 #define FDI_LINK_TRAIN_PATTERN2 1 558 559 static int fdi_auto_training_started(struct intel_vgpu *vgpu) 560 { 561 u32 ddi_buf_ctl = vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_E)); 562 u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL); 563 u32 tx_ctl = vgpu_vreg_t(vgpu, DP_TP_CTL(PORT_E)); 564 565 if ((ddi_buf_ctl & DDI_BUF_CTL_ENABLE) && 566 (rx_ctl & FDI_RX_ENABLE) && 567 (rx_ctl & FDI_AUTO_TRAINING) && 568 (tx_ctl & DP_TP_CTL_ENABLE) && 569 (tx_ctl & DP_TP_CTL_FDI_AUTOTRAIN)) 570 return 1; 571 else 572 return 0; 573 } 574 575 static int check_fdi_rx_train_status(struct intel_vgpu *vgpu, 576 enum pipe pipe, unsigned int train_pattern) 577 { 578 i915_reg_t fdi_rx_imr, fdi_tx_ctl, fdi_rx_ctl; 579 unsigned int fdi_rx_check_bits, fdi_tx_check_bits; 580 unsigned int fdi_rx_train_bits, fdi_tx_train_bits; 581 unsigned int fdi_iir_check_bits; 582 583 fdi_rx_imr = FDI_RX_IMR(pipe); 584 fdi_tx_ctl = FDI_TX_CTL(pipe); 585 fdi_rx_ctl = FDI_RX_CTL(pipe); 586 587 if (train_pattern == FDI_LINK_TRAIN_PATTERN1) { 588 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_1_CPT; 589 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_1; 590 fdi_iir_check_bits = FDI_RX_BIT_LOCK; 591 } else if (train_pattern == FDI_LINK_TRAIN_PATTERN2) { 592 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_2_CPT; 593 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_2; 594 fdi_iir_check_bits = FDI_RX_SYMBOL_LOCK; 595 } else { 596 gvt_vgpu_err("Invalid train pattern %d\n", train_pattern); 597 return -EINVAL; 598 } 599 600 fdi_rx_check_bits = FDI_RX_ENABLE | fdi_rx_train_bits; 601 fdi_tx_check_bits = FDI_TX_ENABLE | fdi_tx_train_bits; 602 603 /* If imr bit has been masked */ 604 if (vgpu_vreg_t(vgpu, fdi_rx_imr) & fdi_iir_check_bits) 605 return 0; 606 607 if (((vgpu_vreg_t(vgpu, fdi_tx_ctl) & fdi_tx_check_bits) 608 == fdi_tx_check_bits) 609 && ((vgpu_vreg_t(vgpu, fdi_rx_ctl) & fdi_rx_check_bits) 610 == fdi_rx_check_bits)) 611 return 1; 612 else 613 return 0; 614 } 615 616 #define INVALID_INDEX (~0U) 617 618 static unsigned int calc_index(unsigned int offset, unsigned int start, 619 unsigned int next, unsigned int end, i915_reg_t i915_end) 620 { 621 unsigned int range = next - start; 622 623 if (!end) 624 end = i915_mmio_reg_offset(i915_end); 625 if (offset < start || offset > end) 626 return INVALID_INDEX; 627 offset -= start; 628 return offset / range; 629 } 630 631 #define FDI_RX_CTL_TO_PIPE(offset) \ 632 calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, 0, FDI_RX_CTL(PIPE_C)) 633 634 #define FDI_TX_CTL_TO_PIPE(offset) \ 635 calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, 0, FDI_TX_CTL(PIPE_C)) 636 637 #define FDI_RX_IMR_TO_PIPE(offset) \ 638 calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, 0, FDI_RX_IMR(PIPE_C)) 639 640 static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu, 641 unsigned int offset, void *p_data, unsigned int bytes) 642 { 643 i915_reg_t fdi_rx_iir; 644 unsigned int index; 645 int ret; 646 647 if (FDI_RX_CTL_TO_PIPE(offset) != INVALID_INDEX) 648 index = FDI_RX_CTL_TO_PIPE(offset); 649 else if (FDI_TX_CTL_TO_PIPE(offset) != INVALID_INDEX) 650 index = FDI_TX_CTL_TO_PIPE(offset); 651 else if (FDI_RX_IMR_TO_PIPE(offset) != INVALID_INDEX) 652 index = FDI_RX_IMR_TO_PIPE(offset); 653 else { 654 gvt_vgpu_err("Unsupport registers %x\n", offset); 655 return -EINVAL; 656 } 657 658 write_vreg(vgpu, offset, p_data, bytes); 659 660 fdi_rx_iir = FDI_RX_IIR(index); 661 662 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN1); 663 if (ret < 0) 664 return ret; 665 if (ret) 666 vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK; 667 668 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN2); 669 if (ret < 0) 670 return ret; 671 if (ret) 672 vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK; 673 674 if (offset == _FDI_RXA_CTL) 675 if (fdi_auto_training_started(vgpu)) 676 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) |= 677 DP_TP_STATUS_AUTOTRAIN_DONE; 678 return 0; 679 } 680 681 #define DP_TP_CTL_TO_PORT(offset) \ 682 calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, 0, DP_TP_CTL(PORT_E)) 683 684 static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 685 void *p_data, unsigned int bytes) 686 { 687 i915_reg_t status_reg; 688 unsigned int index; 689 u32 data; 690 691 write_vreg(vgpu, offset, p_data, bytes); 692 693 index = DP_TP_CTL_TO_PORT(offset); 694 data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8; 695 if (data == 0x2) { 696 status_reg = DP_TP_STATUS(index); 697 vgpu_vreg_t(vgpu, status_reg) |= (1 << 25); 698 } 699 return 0; 700 } 701 702 static int dp_tp_status_mmio_write(struct intel_vgpu *vgpu, 703 unsigned int offset, void *p_data, unsigned int bytes) 704 { 705 u32 reg_val; 706 u32 sticky_mask; 707 708 reg_val = *((u32 *)p_data); 709 sticky_mask = GENMASK(27, 26) | (1 << 24); 710 711 vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) | 712 (vgpu_vreg(vgpu, offset) & sticky_mask); 713 vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask); 714 return 0; 715 } 716 717 static int pch_adpa_mmio_write(struct intel_vgpu *vgpu, 718 unsigned int offset, void *p_data, unsigned int bytes) 719 { 720 u32 data; 721 722 write_vreg(vgpu, offset, p_data, bytes); 723 data = vgpu_vreg(vgpu, offset); 724 725 if (data & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) 726 vgpu_vreg(vgpu, offset) &= ~ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 727 return 0; 728 } 729 730 static int south_chicken2_mmio_write(struct intel_vgpu *vgpu, 731 unsigned int offset, void *p_data, unsigned int bytes) 732 { 733 u32 data; 734 735 write_vreg(vgpu, offset, p_data, bytes); 736 data = vgpu_vreg(vgpu, offset); 737 738 if (data & FDI_MPHY_IOSFSB_RESET_CTL) 739 vgpu_vreg(vgpu, offset) |= FDI_MPHY_IOSFSB_RESET_STATUS; 740 else 741 vgpu_vreg(vgpu, offset) &= ~FDI_MPHY_IOSFSB_RESET_STATUS; 742 return 0; 743 } 744 745 #define DSPSURF_TO_PIPE(offset) \ 746 calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C)) 747 748 static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 749 void *p_data, unsigned int bytes) 750 { 751 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 752 unsigned int index = DSPSURF_TO_PIPE(offset); 753 i915_reg_t surflive_reg = DSPSURFLIVE(index); 754 int flip_event[] = { 755 [PIPE_A] = PRIMARY_A_FLIP_DONE, 756 [PIPE_B] = PRIMARY_B_FLIP_DONE, 757 [PIPE_C] = PRIMARY_C_FLIP_DONE, 758 }; 759 760 write_vreg(vgpu, offset, p_data, bytes); 761 vgpu_vreg_t(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset); 762 763 set_bit(flip_event[index], vgpu->irq.flip_done_event[index]); 764 return 0; 765 } 766 767 #define SPRSURF_TO_PIPE(offset) \ 768 calc_index(offset, _SPRA_SURF, _SPRB_SURF, 0, SPRSURF(PIPE_C)) 769 770 static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 771 void *p_data, unsigned int bytes) 772 { 773 unsigned int index = SPRSURF_TO_PIPE(offset); 774 i915_reg_t surflive_reg = SPRSURFLIVE(index); 775 int flip_event[] = { 776 [PIPE_A] = SPRITE_A_FLIP_DONE, 777 [PIPE_B] = SPRITE_B_FLIP_DONE, 778 [PIPE_C] = SPRITE_C_FLIP_DONE, 779 }; 780 781 write_vreg(vgpu, offset, p_data, bytes); 782 vgpu_vreg_t(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset); 783 784 set_bit(flip_event[index], vgpu->irq.flip_done_event[index]); 785 return 0; 786 } 787 788 static int trigger_aux_channel_interrupt(struct intel_vgpu *vgpu, 789 unsigned int reg) 790 { 791 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 792 enum intel_gvt_event_type event; 793 794 if (reg == _DPA_AUX_CH_CTL) 795 event = AUX_CHANNEL_A; 796 else if (reg == _PCH_DPB_AUX_CH_CTL || reg == _DPB_AUX_CH_CTL) 797 event = AUX_CHANNEL_B; 798 else if (reg == _PCH_DPC_AUX_CH_CTL || reg == _DPC_AUX_CH_CTL) 799 event = AUX_CHANNEL_C; 800 else if (reg == _PCH_DPD_AUX_CH_CTL || reg == _DPD_AUX_CH_CTL) 801 event = AUX_CHANNEL_D; 802 else { 803 WARN_ON(true); 804 return -EINVAL; 805 } 806 807 intel_vgpu_trigger_virtual_event(vgpu, event); 808 return 0; 809 } 810 811 static int dp_aux_ch_ctl_trans_done(struct intel_vgpu *vgpu, u32 value, 812 unsigned int reg, int len, bool data_valid) 813 { 814 /* mark transaction done */ 815 value |= DP_AUX_CH_CTL_DONE; 816 value &= ~DP_AUX_CH_CTL_SEND_BUSY; 817 value &= ~DP_AUX_CH_CTL_RECEIVE_ERROR; 818 819 if (data_valid) 820 value &= ~DP_AUX_CH_CTL_TIME_OUT_ERROR; 821 else 822 value |= DP_AUX_CH_CTL_TIME_OUT_ERROR; 823 824 /* message size */ 825 value &= ~(0xf << 20); 826 value |= (len << 20); 827 vgpu_vreg(vgpu, reg) = value; 828 829 if (value & DP_AUX_CH_CTL_INTERRUPT) 830 return trigger_aux_channel_interrupt(vgpu, reg); 831 return 0; 832 } 833 834 static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd, 835 uint8_t t) 836 { 837 if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == DPCD_TRAINING_PATTERN_1) { 838 /* training pattern 1 for CR */ 839 /* set LANE0_CR_DONE, LANE1_CR_DONE */ 840 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_CR_DONE; 841 /* set LANE2_CR_DONE, LANE3_CR_DONE */ 842 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_CR_DONE; 843 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == 844 DPCD_TRAINING_PATTERN_2) { 845 /* training pattern 2 for EQ */ 846 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane0_1 */ 847 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_EQ_DONE; 848 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_SYMBOL_LOCKED; 849 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane2_3 */ 850 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_EQ_DONE; 851 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_SYMBOL_LOCKED; 852 /* set INTERLANE_ALIGN_DONE */ 853 dpcd->data[DPCD_LANE_ALIGN_STATUS_UPDATED] |= 854 DPCD_INTERLANE_ALIGN_DONE; 855 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == 856 DPCD_LINK_TRAINING_DISABLED) { 857 /* finish link training */ 858 /* set sink status as synchronized */ 859 dpcd->data[DPCD_SINK_STATUS] = DPCD_SINK_IN_SYNC; 860 } 861 } 862 863 #define _REG_HSW_DP_AUX_CH_CTL(dp) \ 864 ((dp) ? (_PCH_DPB_AUX_CH_CTL + ((dp)-1)*0x100) : 0x64010) 865 866 #define _REG_SKL_DP_AUX_CH_CTL(dp) (0x64010 + (dp) * 0x100) 867 868 #define OFFSET_TO_DP_AUX_PORT(offset) (((offset) & 0xF00) >> 8) 869 870 #define dpy_is_valid_port(port) \ 871 (((port) >= PORT_A) && ((port) < I915_MAX_PORTS)) 872 873 static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu, 874 unsigned int offset, void *p_data, unsigned int bytes) 875 { 876 struct intel_vgpu_display *display = &vgpu->display; 877 int msg, addr, ctrl, op, len; 878 int port_index = OFFSET_TO_DP_AUX_PORT(offset); 879 struct intel_vgpu_dpcd_data *dpcd = NULL; 880 struct intel_vgpu_port *port = NULL; 881 u32 data; 882 883 if (!dpy_is_valid_port(port_index)) { 884 gvt_vgpu_err("Unsupported DP port access!\n"); 885 return 0; 886 } 887 888 write_vreg(vgpu, offset, p_data, bytes); 889 data = vgpu_vreg(vgpu, offset); 890 891 if ((IS_SKYLAKE(vgpu->gvt->dev_priv) 892 || IS_KABYLAKE(vgpu->gvt->dev_priv) 893 || IS_BROXTON(vgpu->gvt->dev_priv)) 894 && offset != _REG_SKL_DP_AUX_CH_CTL(port_index)) { 895 /* SKL DPB/C/D aux ctl register changed */ 896 return 0; 897 } else if (IS_BROADWELL(vgpu->gvt->dev_priv) && 898 offset != _REG_HSW_DP_AUX_CH_CTL(port_index)) { 899 /* write to the data registers */ 900 return 0; 901 } 902 903 if (!(data & DP_AUX_CH_CTL_SEND_BUSY)) { 904 /* just want to clear the sticky bits */ 905 vgpu_vreg(vgpu, offset) = 0; 906 return 0; 907 } 908 909 port = &display->ports[port_index]; 910 dpcd = port->dpcd; 911 912 /* read out message from DATA1 register */ 913 msg = vgpu_vreg(vgpu, offset + 4); 914 addr = (msg >> 8) & 0xffff; 915 ctrl = (msg >> 24) & 0xff; 916 len = msg & 0xff; 917 op = ctrl >> 4; 918 919 if (op == GVT_AUX_NATIVE_WRITE) { 920 int t; 921 uint8_t buf[16]; 922 923 if ((addr + len + 1) >= DPCD_SIZE) { 924 /* 925 * Write request exceeds what we supported, 926 * DCPD spec: When a Source Device is writing a DPCD 927 * address not supported by the Sink Device, the Sink 928 * Device shall reply with AUX NACK and “M” equal to 929 * zero. 930 */ 931 932 /* NAK the write */ 933 vgpu_vreg(vgpu, offset + 4) = AUX_NATIVE_REPLY_NAK; 934 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 2, true); 935 return 0; 936 } 937 938 /* 939 * Write request format: Headr (command + address + size) occupies 940 * 4 bytes, followed by (len + 1) bytes of data. See details at 941 * intel_dp_aux_transfer(). 942 */ 943 if ((len + 1 + 4) > AUX_BURST_SIZE) { 944 gvt_vgpu_err("dp_aux_header: len %d is too large\n", len); 945 return -EINVAL; 946 } 947 948 /* unpack data from vreg to buf */ 949 for (t = 0; t < 4; t++) { 950 u32 r = vgpu_vreg(vgpu, offset + 8 + t * 4); 951 952 buf[t * 4] = (r >> 24) & 0xff; 953 buf[t * 4 + 1] = (r >> 16) & 0xff; 954 buf[t * 4 + 2] = (r >> 8) & 0xff; 955 buf[t * 4 + 3] = r & 0xff; 956 } 957 958 /* write to virtual DPCD */ 959 if (dpcd && dpcd->data_valid) { 960 for (t = 0; t <= len; t++) { 961 int p = addr + t; 962 963 dpcd->data[p] = buf[t]; 964 /* check for link training */ 965 if (p == DPCD_TRAINING_PATTERN_SET) 966 dp_aux_ch_ctl_link_training(dpcd, 967 buf[t]); 968 } 969 } 970 971 /* ACK the write */ 972 vgpu_vreg(vgpu, offset + 4) = 0; 973 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 1, 974 dpcd && dpcd->data_valid); 975 return 0; 976 } 977 978 if (op == GVT_AUX_NATIVE_READ) { 979 int idx, i, ret = 0; 980 981 if ((addr + len + 1) >= DPCD_SIZE) { 982 /* 983 * read request exceeds what we supported 984 * DPCD spec: A Sink Device receiving a Native AUX CH 985 * read request for an unsupported DPCD address must 986 * reply with an AUX ACK and read data set equal to 987 * zero instead of replying with AUX NACK. 988 */ 989 990 /* ACK the READ*/ 991 vgpu_vreg(vgpu, offset + 4) = 0; 992 vgpu_vreg(vgpu, offset + 8) = 0; 993 vgpu_vreg(vgpu, offset + 12) = 0; 994 vgpu_vreg(vgpu, offset + 16) = 0; 995 vgpu_vreg(vgpu, offset + 20) = 0; 996 997 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2, 998 true); 999 return 0; 1000 } 1001 1002 for (idx = 1; idx <= 5; idx++) { 1003 /* clear the data registers */ 1004 vgpu_vreg(vgpu, offset + 4 * idx) = 0; 1005 } 1006 1007 /* 1008 * Read reply format: ACK (1 byte) plus (len + 1) bytes of data. 1009 */ 1010 if ((len + 2) > AUX_BURST_SIZE) { 1011 gvt_vgpu_err("dp_aux_header: len %d is too large\n", len); 1012 return -EINVAL; 1013 } 1014 1015 /* read from virtual DPCD to vreg */ 1016 /* first 4 bytes: [ACK][addr][addr+1][addr+2] */ 1017 if (dpcd && dpcd->data_valid) { 1018 for (i = 1; i <= (len + 1); i++) { 1019 int t; 1020 1021 t = dpcd->data[addr + i - 1]; 1022 t <<= (24 - 8 * (i % 4)); 1023 ret |= t; 1024 1025 if ((i % 4 == 3) || (i == (len + 1))) { 1026 vgpu_vreg(vgpu, offset + 1027 (i / 4 + 1) * 4) = ret; 1028 ret = 0; 1029 } 1030 } 1031 } 1032 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2, 1033 dpcd && dpcd->data_valid); 1034 return 0; 1035 } 1036 1037 /* i2c transaction starts */ 1038 intel_gvt_i2c_handle_aux_ch_write(vgpu, port_index, offset, p_data); 1039 1040 if (data & DP_AUX_CH_CTL_INTERRUPT) 1041 trigger_aux_channel_interrupt(vgpu, offset); 1042 return 0; 1043 } 1044 1045 static int mbctl_write(struct intel_vgpu *vgpu, unsigned int offset, 1046 void *p_data, unsigned int bytes) 1047 { 1048 *(u32 *)p_data &= (~GEN6_MBCTL_ENABLE_BOOT_FETCH); 1049 write_vreg(vgpu, offset, p_data, bytes); 1050 return 0; 1051 } 1052 1053 static int vga_control_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1054 void *p_data, unsigned int bytes) 1055 { 1056 bool vga_disable; 1057 1058 write_vreg(vgpu, offset, p_data, bytes); 1059 vga_disable = vgpu_vreg(vgpu, offset) & VGA_DISP_DISABLE; 1060 1061 gvt_dbg_core("vgpu%d: %s VGA mode\n", vgpu->id, 1062 vga_disable ? "Disable" : "Enable"); 1063 return 0; 1064 } 1065 1066 static u32 read_virtual_sbi_register(struct intel_vgpu *vgpu, 1067 unsigned int sbi_offset) 1068 { 1069 struct intel_vgpu_display *display = &vgpu->display; 1070 int num = display->sbi.number; 1071 int i; 1072 1073 for (i = 0; i < num; ++i) 1074 if (display->sbi.registers[i].offset == sbi_offset) 1075 break; 1076 1077 if (i == num) 1078 return 0; 1079 1080 return display->sbi.registers[i].value; 1081 } 1082 1083 static void write_virtual_sbi_register(struct intel_vgpu *vgpu, 1084 unsigned int offset, u32 value) 1085 { 1086 struct intel_vgpu_display *display = &vgpu->display; 1087 int num = display->sbi.number; 1088 int i; 1089 1090 for (i = 0; i < num; ++i) { 1091 if (display->sbi.registers[i].offset == offset) 1092 break; 1093 } 1094 1095 if (i == num) { 1096 if (num == SBI_REG_MAX) { 1097 gvt_vgpu_err("SBI caching meets maximum limits\n"); 1098 return; 1099 } 1100 display->sbi.number++; 1101 } 1102 1103 display->sbi.registers[i].offset = offset; 1104 display->sbi.registers[i].value = value; 1105 } 1106 1107 static int sbi_data_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 1108 void *p_data, unsigned int bytes) 1109 { 1110 if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> 1111 SBI_OPCODE_SHIFT) == SBI_CMD_CRRD) { 1112 unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) & 1113 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; 1114 vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu, 1115 sbi_offset); 1116 } 1117 read_vreg(vgpu, offset, p_data, bytes); 1118 return 0; 1119 } 1120 1121 static int sbi_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1122 void *p_data, unsigned int bytes) 1123 { 1124 u32 data; 1125 1126 write_vreg(vgpu, offset, p_data, bytes); 1127 data = vgpu_vreg(vgpu, offset); 1128 1129 data &= ~(SBI_STAT_MASK << SBI_STAT_SHIFT); 1130 data |= SBI_READY; 1131 1132 data &= ~(SBI_RESPONSE_MASK << SBI_RESPONSE_SHIFT); 1133 data |= SBI_RESPONSE_SUCCESS; 1134 1135 vgpu_vreg(vgpu, offset) = data; 1136 1137 if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> 1138 SBI_OPCODE_SHIFT) == SBI_CMD_CRWR) { 1139 unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) & 1140 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; 1141 1142 write_virtual_sbi_register(vgpu, sbi_offset, 1143 vgpu_vreg_t(vgpu, SBI_DATA)); 1144 } 1145 return 0; 1146 } 1147 1148 #define _vgtif_reg(x) \ 1149 (VGT_PVINFO_PAGE + offsetof(struct vgt_if, x)) 1150 1151 static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 1152 void *p_data, unsigned int bytes) 1153 { 1154 bool invalid_read = false; 1155 1156 read_vreg(vgpu, offset, p_data, bytes); 1157 1158 switch (offset) { 1159 case _vgtif_reg(magic) ... _vgtif_reg(vgt_id): 1160 if (offset + bytes > _vgtif_reg(vgt_id) + 4) 1161 invalid_read = true; 1162 break; 1163 case _vgtif_reg(avail_rs.mappable_gmadr.base) ... 1164 _vgtif_reg(avail_rs.fence_num): 1165 if (offset + bytes > 1166 _vgtif_reg(avail_rs.fence_num) + 4) 1167 invalid_read = true; 1168 break; 1169 case 0x78010: /* vgt_caps */ 1170 case 0x7881c: 1171 break; 1172 default: 1173 invalid_read = true; 1174 break; 1175 } 1176 if (invalid_read) 1177 gvt_vgpu_err("invalid pvinfo read: [%x:%x] = %x\n", 1178 offset, bytes, *(u32 *)p_data); 1179 vgpu->pv_notified = true; 1180 return 0; 1181 } 1182 1183 static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification) 1184 { 1185 intel_gvt_gtt_type_t root_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY; 1186 struct intel_vgpu_mm *mm; 1187 u64 *pdps; 1188 1189 pdps = (u64 *)&vgpu_vreg64_t(vgpu, vgtif_reg(pdp[0])); 1190 1191 switch (notification) { 1192 case VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE: 1193 root_entry_type = GTT_TYPE_PPGTT_ROOT_L3_ENTRY; 1194 /* fall through */ 1195 case VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE: 1196 mm = intel_vgpu_get_ppgtt_mm(vgpu, root_entry_type, pdps); 1197 return PTR_ERR_OR_ZERO(mm); 1198 case VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY: 1199 case VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY: 1200 return intel_vgpu_put_ppgtt_mm(vgpu, pdps); 1201 case VGT_G2V_EXECLIST_CONTEXT_CREATE: 1202 case VGT_G2V_EXECLIST_CONTEXT_DESTROY: 1203 case 1: /* Remove this in guest driver. */ 1204 break; 1205 default: 1206 gvt_vgpu_err("Invalid PV notification %d\n", notification); 1207 } 1208 return 0; 1209 } 1210 1211 static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready) 1212 { 1213 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1214 struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj; 1215 char *env[3] = {NULL, NULL, NULL}; 1216 char vmid_str[20]; 1217 char display_ready_str[20]; 1218 1219 snprintf(display_ready_str, 20, "GVT_DISPLAY_READY=%d", ready); 1220 env[0] = display_ready_str; 1221 1222 snprintf(vmid_str, 20, "VMID=%d", vgpu->id); 1223 env[1] = vmid_str; 1224 1225 return kobject_uevent_env(kobj, KOBJ_ADD, env); 1226 } 1227 1228 static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1229 void *p_data, unsigned int bytes) 1230 { 1231 u32 data; 1232 int ret; 1233 1234 write_vreg(vgpu, offset, p_data, bytes); 1235 data = vgpu_vreg(vgpu, offset); 1236 1237 switch (offset) { 1238 case _vgtif_reg(display_ready): 1239 send_display_ready_uevent(vgpu, data ? 1 : 0); 1240 break; 1241 case _vgtif_reg(g2v_notify): 1242 ret = handle_g2v_notification(vgpu, data); 1243 break; 1244 /* add xhot and yhot to handled list to avoid error log */ 1245 case _vgtif_reg(cursor_x_hot): 1246 case _vgtif_reg(cursor_y_hot): 1247 case _vgtif_reg(pdp[0].lo): 1248 case _vgtif_reg(pdp[0].hi): 1249 case _vgtif_reg(pdp[1].lo): 1250 case _vgtif_reg(pdp[1].hi): 1251 case _vgtif_reg(pdp[2].lo): 1252 case _vgtif_reg(pdp[2].hi): 1253 case _vgtif_reg(pdp[3].lo): 1254 case _vgtif_reg(pdp[3].hi): 1255 case _vgtif_reg(execlist_context_descriptor_lo): 1256 case _vgtif_reg(execlist_context_descriptor_hi): 1257 break; 1258 case _vgtif_reg(rsv5[0])..._vgtif_reg(rsv5[3]): 1259 enter_failsafe_mode(vgpu, GVT_FAILSAFE_INSUFFICIENT_RESOURCE); 1260 break; 1261 default: 1262 gvt_vgpu_err("invalid pvinfo write offset %x bytes %x data %x\n", 1263 offset, bytes, data); 1264 break; 1265 } 1266 return 0; 1267 } 1268 1269 static int pf_write(struct intel_vgpu *vgpu, 1270 unsigned int offset, void *p_data, unsigned int bytes) 1271 { 1272 u32 val = *(u32 *)p_data; 1273 1274 if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL || 1275 offset == _PS_1B_CTRL || offset == _PS_2B_CTRL || 1276 offset == _PS_1C_CTRL) && (val & PS_PLANE_SEL_MASK) != 0) { 1277 WARN_ONCE(true, "VM(%d): guest is trying to scaling a plane\n", 1278 vgpu->id); 1279 return 0; 1280 } 1281 1282 return intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes); 1283 } 1284 1285 static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu, 1286 unsigned int offset, void *p_data, unsigned int bytes) 1287 { 1288 write_vreg(vgpu, offset, p_data, bytes); 1289 1290 if (vgpu_vreg(vgpu, offset) & 1291 HSW_PWR_WELL_CTL_REQ(HSW_PW_CTL_IDX_GLOBAL)) 1292 vgpu_vreg(vgpu, offset) |= 1293 HSW_PWR_WELL_CTL_STATE(HSW_PW_CTL_IDX_GLOBAL); 1294 else 1295 vgpu_vreg(vgpu, offset) &= 1296 ~HSW_PWR_WELL_CTL_STATE(HSW_PW_CTL_IDX_GLOBAL); 1297 return 0; 1298 } 1299 1300 static int gen9_dbuf_ctl_mmio_write(struct intel_vgpu *vgpu, 1301 unsigned int offset, void *p_data, unsigned int bytes) 1302 { 1303 write_vreg(vgpu, offset, p_data, bytes); 1304 1305 if (vgpu_vreg(vgpu, offset) & DBUF_POWER_REQUEST) 1306 vgpu_vreg(vgpu, offset) |= DBUF_POWER_STATE; 1307 else 1308 vgpu_vreg(vgpu, offset) &= ~DBUF_POWER_STATE; 1309 1310 return 0; 1311 } 1312 1313 static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu, 1314 unsigned int offset, void *p_data, unsigned int bytes) 1315 { 1316 write_vreg(vgpu, offset, p_data, bytes); 1317 1318 if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM) 1319 vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM; 1320 return 0; 1321 } 1322 1323 static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset, 1324 void *p_data, unsigned int bytes) 1325 { 1326 u32 mode; 1327 1328 write_vreg(vgpu, offset, p_data, bytes); 1329 mode = vgpu_vreg(vgpu, offset); 1330 1331 if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) { 1332 WARN_ONCE(1, "VM(%d): iGVT-g doesn't support GuC\n", 1333 vgpu->id); 1334 return 0; 1335 } 1336 1337 return 0; 1338 } 1339 1340 static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset, 1341 void *p_data, unsigned int bytes) 1342 { 1343 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1344 u32 trtte = *(u32 *)p_data; 1345 1346 if ((trtte & 1) && (trtte & (1 << 1)) == 0) { 1347 WARN(1, "VM(%d): Use physical address for TRTT!\n", 1348 vgpu->id); 1349 return -EINVAL; 1350 } 1351 write_vreg(vgpu, offset, p_data, bytes); 1352 /* TRTTE is not per-context */ 1353 1354 mmio_hw_access_pre(dev_priv); 1355 I915_WRITE(_MMIO(offset), vgpu_vreg(vgpu, offset)); 1356 mmio_hw_access_post(dev_priv); 1357 1358 return 0; 1359 } 1360 1361 static int gen9_trtt_chicken_write(struct intel_vgpu *vgpu, unsigned int offset, 1362 void *p_data, unsigned int bytes) 1363 { 1364 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1365 u32 val = *(u32 *)p_data; 1366 1367 if (val & 1) { 1368 /* unblock hw logic */ 1369 mmio_hw_access_pre(dev_priv); 1370 I915_WRITE(_MMIO(offset), val); 1371 mmio_hw_access_post(dev_priv); 1372 } 1373 write_vreg(vgpu, offset, p_data, bytes); 1374 return 0; 1375 } 1376 1377 static int dpll_status_read(struct intel_vgpu *vgpu, unsigned int offset, 1378 void *p_data, unsigned int bytes) 1379 { 1380 u32 v = 0; 1381 1382 if (vgpu_vreg(vgpu, 0x46010) & (1 << 31)) 1383 v |= (1 << 0); 1384 1385 if (vgpu_vreg(vgpu, 0x46014) & (1 << 31)) 1386 v |= (1 << 8); 1387 1388 if (vgpu_vreg(vgpu, 0x46040) & (1 << 31)) 1389 v |= (1 << 16); 1390 1391 if (vgpu_vreg(vgpu, 0x46060) & (1 << 31)) 1392 v |= (1 << 24); 1393 1394 vgpu_vreg(vgpu, offset) = v; 1395 1396 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1397 } 1398 1399 static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset, 1400 void *p_data, unsigned int bytes) 1401 { 1402 u32 value = *(u32 *)p_data; 1403 u32 cmd = value & 0xff; 1404 u32 *data0 = &vgpu_vreg_t(vgpu, GEN6_PCODE_DATA); 1405 1406 switch (cmd) { 1407 case GEN9_PCODE_READ_MEM_LATENCY: 1408 if (IS_SKYLAKE(vgpu->gvt->dev_priv) 1409 || IS_KABYLAKE(vgpu->gvt->dev_priv)) { 1410 /** 1411 * "Read memory latency" command on gen9. 1412 * Below memory latency values are read 1413 * from skylake platform. 1414 */ 1415 if (!*data0) 1416 *data0 = 0x1e1a1100; 1417 else 1418 *data0 = 0x61514b3d; 1419 } else if (IS_BROXTON(vgpu->gvt->dev_priv)) { 1420 /** 1421 * "Read memory latency" command on gen9. 1422 * Below memory latency values are read 1423 * from Broxton MRB. 1424 */ 1425 if (!*data0) 1426 *data0 = 0x16080707; 1427 else 1428 *data0 = 0x16161616; 1429 } 1430 break; 1431 case SKL_PCODE_CDCLK_CONTROL: 1432 if (IS_SKYLAKE(vgpu->gvt->dev_priv) 1433 || IS_KABYLAKE(vgpu->gvt->dev_priv)) 1434 *data0 = SKL_CDCLK_READY_FOR_CHANGE; 1435 break; 1436 case GEN6_PCODE_READ_RC6VIDS: 1437 *data0 |= 0x1; 1438 break; 1439 } 1440 1441 gvt_dbg_core("VM(%d) write %x to mailbox, return data0 %x\n", 1442 vgpu->id, value, *data0); 1443 /** 1444 * PCODE_READY clear means ready for pcode read/write, 1445 * PCODE_ERROR_MASK clear means no error happened. In GVT-g we 1446 * always emulate as pcode read/write success and ready for access 1447 * anytime, since we don't touch real physical registers here. 1448 */ 1449 value &= ~(GEN6_PCODE_READY | GEN6_PCODE_ERROR_MASK); 1450 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes); 1451 } 1452 1453 static int hws_pga_write(struct intel_vgpu *vgpu, unsigned int offset, 1454 void *p_data, unsigned int bytes) 1455 { 1456 u32 value = *(u32 *)p_data; 1457 int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset); 1458 1459 if (!intel_gvt_ggtt_validate_range(vgpu, value, I915_GTT_PAGE_SIZE)) { 1460 gvt_vgpu_err("write invalid HWSP address, reg:0x%x, value:0x%x\n", 1461 offset, value); 1462 return -EINVAL; 1463 } 1464 /* 1465 * Need to emulate all the HWSP register write to ensure host can 1466 * update the VM CSB status correctly. Here listed registers can 1467 * support BDW, SKL or other platforms with same HWSP registers. 1468 */ 1469 if (unlikely(ring_id < 0 || ring_id >= I915_NUM_ENGINES)) { 1470 gvt_vgpu_err("access unknown hardware status page register:0x%x\n", 1471 offset); 1472 return -EINVAL; 1473 } 1474 vgpu->hws_pga[ring_id] = value; 1475 gvt_dbg_mmio("VM(%d) write: 0x%x to HWSP: 0x%x\n", 1476 vgpu->id, value, offset); 1477 1478 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes); 1479 } 1480 1481 static int skl_power_well_ctl_write(struct intel_vgpu *vgpu, 1482 unsigned int offset, void *p_data, unsigned int bytes) 1483 { 1484 u32 v = *(u32 *)p_data; 1485 1486 if (IS_BROXTON(vgpu->gvt->dev_priv)) 1487 v &= (1 << 31) | (1 << 29); 1488 else 1489 v &= (1 << 31) | (1 << 29) | (1 << 9) | 1490 (1 << 7) | (1 << 5) | (1 << 3) | (1 << 1); 1491 v |= (v >> 1); 1492 1493 return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes); 1494 } 1495 1496 static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset, 1497 void *p_data, unsigned int bytes) 1498 { 1499 u32 v = *(u32 *)p_data; 1500 1501 /* other bits are MBZ. */ 1502 v &= (1 << 31) | (1 << 30); 1503 v & (1 << 31) ? (v |= (1 << 30)) : (v &= ~(1 << 30)); 1504 1505 vgpu_vreg(vgpu, offset) = v; 1506 1507 return 0; 1508 } 1509 1510 static int bxt_de_pll_enable_write(struct intel_vgpu *vgpu, 1511 unsigned int offset, void *p_data, unsigned int bytes) 1512 { 1513 u32 v = *(u32 *)p_data; 1514 1515 if (v & BXT_DE_PLL_PLL_ENABLE) 1516 v |= BXT_DE_PLL_LOCK; 1517 1518 vgpu_vreg(vgpu, offset) = v; 1519 1520 return 0; 1521 } 1522 1523 static int bxt_port_pll_enable_write(struct intel_vgpu *vgpu, 1524 unsigned int offset, void *p_data, unsigned int bytes) 1525 { 1526 u32 v = *(u32 *)p_data; 1527 1528 if (v & PORT_PLL_ENABLE) 1529 v |= PORT_PLL_LOCK; 1530 1531 vgpu_vreg(vgpu, offset) = v; 1532 1533 return 0; 1534 } 1535 1536 static int bxt_phy_ctl_family_write(struct intel_vgpu *vgpu, 1537 unsigned int offset, void *p_data, unsigned int bytes) 1538 { 1539 u32 v = *(u32 *)p_data; 1540 u32 data = v & COMMON_RESET_DIS ? BXT_PHY_LANE_ENABLED : 0; 1541 1542 switch (offset) { 1543 case _PHY_CTL_FAMILY_EDP: 1544 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_A) = data; 1545 break; 1546 case _PHY_CTL_FAMILY_DDI: 1547 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_B) = data; 1548 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_C) = data; 1549 break; 1550 } 1551 1552 vgpu_vreg(vgpu, offset) = v; 1553 1554 return 0; 1555 } 1556 1557 static int bxt_port_tx_dw3_read(struct intel_vgpu *vgpu, 1558 unsigned int offset, void *p_data, unsigned int bytes) 1559 { 1560 u32 v = vgpu_vreg(vgpu, offset); 1561 1562 v &= ~UNIQUE_TRANGE_EN_METHOD; 1563 1564 vgpu_vreg(vgpu, offset) = v; 1565 1566 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1567 } 1568 1569 static int bxt_pcs_dw12_grp_write(struct intel_vgpu *vgpu, 1570 unsigned int offset, void *p_data, unsigned int bytes) 1571 { 1572 u32 v = *(u32 *)p_data; 1573 1574 if (offset == _PORT_PCS_DW12_GRP_A || offset == _PORT_PCS_DW12_GRP_B) { 1575 vgpu_vreg(vgpu, offset - 0x600) = v; 1576 vgpu_vreg(vgpu, offset - 0x800) = v; 1577 } else { 1578 vgpu_vreg(vgpu, offset - 0x400) = v; 1579 vgpu_vreg(vgpu, offset - 0x600) = v; 1580 } 1581 1582 vgpu_vreg(vgpu, offset) = v; 1583 1584 return 0; 1585 } 1586 1587 static int bxt_gt_disp_pwron_write(struct intel_vgpu *vgpu, 1588 unsigned int offset, void *p_data, unsigned int bytes) 1589 { 1590 u32 v = *(u32 *)p_data; 1591 1592 if (v & BIT(0)) { 1593 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &= 1594 ~PHY_RESERVED; 1595 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |= 1596 PHY_POWER_GOOD; 1597 } 1598 1599 if (v & BIT(1)) { 1600 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &= 1601 ~PHY_RESERVED; 1602 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |= 1603 PHY_POWER_GOOD; 1604 } 1605 1606 1607 vgpu_vreg(vgpu, offset) = v; 1608 1609 return 0; 1610 } 1611 1612 static int bxt_edp_psr_imr_iir_write(struct intel_vgpu *vgpu, 1613 unsigned int offset, void *p_data, unsigned int bytes) 1614 { 1615 vgpu_vreg(vgpu, offset) = 0; 1616 return 0; 1617 } 1618 1619 static int mmio_read_from_hw(struct intel_vgpu *vgpu, 1620 unsigned int offset, void *p_data, unsigned int bytes) 1621 { 1622 struct intel_gvt *gvt = vgpu->gvt; 1623 struct drm_i915_private *dev_priv = gvt->dev_priv; 1624 int ring_id; 1625 u32 ring_base; 1626 1627 ring_id = intel_gvt_render_mmio_to_ring_id(gvt, offset); 1628 /** 1629 * Read HW reg in following case 1630 * a. the offset isn't a ring mmio 1631 * b. the offset's ring is running on hw. 1632 * c. the offset is ring time stamp mmio 1633 */ 1634 if (ring_id >= 0) 1635 ring_base = dev_priv->engine[ring_id]->mmio_base; 1636 1637 if (ring_id < 0 || vgpu == gvt->scheduler.engine_owner[ring_id] || 1638 offset == i915_mmio_reg_offset(RING_TIMESTAMP(ring_base)) || 1639 offset == i915_mmio_reg_offset(RING_TIMESTAMP_UDW(ring_base))) { 1640 mmio_hw_access_pre(dev_priv); 1641 vgpu_vreg(vgpu, offset) = I915_READ(_MMIO(offset)); 1642 mmio_hw_access_post(dev_priv); 1643 } 1644 1645 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1646 } 1647 1648 static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1649 void *p_data, unsigned int bytes) 1650 { 1651 int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset); 1652 struct intel_vgpu_execlist *execlist; 1653 u32 data = *(u32 *)p_data; 1654 int ret = 0; 1655 1656 if (WARN_ON(ring_id < 0 || ring_id >= I915_NUM_ENGINES)) 1657 return -EINVAL; 1658 1659 execlist = &vgpu->submission.execlist[ring_id]; 1660 1661 execlist->elsp_dwords.data[3 - execlist->elsp_dwords.index] = data; 1662 if (execlist->elsp_dwords.index == 3) { 1663 ret = intel_vgpu_submit_execlist(vgpu, ring_id); 1664 if(ret) 1665 gvt_vgpu_err("fail submit workload on ring %d\n", 1666 ring_id); 1667 } 1668 1669 ++execlist->elsp_dwords.index; 1670 execlist->elsp_dwords.index &= 0x3; 1671 return ret; 1672 } 1673 1674 static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1675 void *p_data, unsigned int bytes) 1676 { 1677 u32 data = *(u32 *)p_data; 1678 int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset); 1679 bool enable_execlist; 1680 int ret; 1681 1682 write_vreg(vgpu, offset, p_data, bytes); 1683 1684 /* when PPGTT mode enabled, we will check if guest has called 1685 * pvinfo, if not, we will treat this guest as non-gvtg-aware 1686 * guest, and stop emulating its cfg space, mmio, gtt, etc. 1687 */ 1688 if (((data & _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)) || 1689 (data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE))) 1690 && !vgpu->pv_notified) { 1691 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); 1692 return 0; 1693 } 1694 if ((data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)) 1695 || (data & _MASKED_BIT_DISABLE(GFX_RUN_LIST_ENABLE))) { 1696 enable_execlist = !!(data & GFX_RUN_LIST_ENABLE); 1697 1698 gvt_dbg_core("EXECLIST %s on ring %d\n", 1699 (enable_execlist ? "enabling" : "disabling"), 1700 ring_id); 1701 1702 if (!enable_execlist) 1703 return 0; 1704 1705 ret = intel_vgpu_select_submission_ops(vgpu, 1706 ENGINE_MASK(ring_id), 1707 INTEL_VGPU_EXECLIST_SUBMISSION); 1708 if (ret) 1709 return ret; 1710 1711 intel_vgpu_start_schedule(vgpu); 1712 } 1713 return 0; 1714 } 1715 1716 static int gvt_reg_tlb_control_handler(struct intel_vgpu *vgpu, 1717 unsigned int offset, void *p_data, unsigned int bytes) 1718 { 1719 unsigned int id = 0; 1720 1721 write_vreg(vgpu, offset, p_data, bytes); 1722 vgpu_vreg(vgpu, offset) = 0; 1723 1724 switch (offset) { 1725 case 0x4260: 1726 id = RCS; 1727 break; 1728 case 0x4264: 1729 id = VCS; 1730 break; 1731 case 0x4268: 1732 id = VCS2; 1733 break; 1734 case 0x426c: 1735 id = BCS; 1736 break; 1737 case 0x4270: 1738 id = VECS; 1739 break; 1740 default: 1741 return -EINVAL; 1742 } 1743 set_bit(id, (void *)vgpu->submission.tlb_handle_pending); 1744 1745 return 0; 1746 } 1747 1748 static int ring_reset_ctl_write(struct intel_vgpu *vgpu, 1749 unsigned int offset, void *p_data, unsigned int bytes) 1750 { 1751 u32 data; 1752 1753 write_vreg(vgpu, offset, p_data, bytes); 1754 data = vgpu_vreg(vgpu, offset); 1755 1756 if (data & _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET)) 1757 data |= RESET_CTL_READY_TO_RESET; 1758 else if (data & _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET)) 1759 data &= ~RESET_CTL_READY_TO_RESET; 1760 1761 vgpu_vreg(vgpu, offset) = data; 1762 return 0; 1763 } 1764 1765 #define MMIO_F(reg, s, f, am, rm, d, r, w) do { \ 1766 ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \ 1767 f, s, am, rm, d, r, w); \ 1768 if (ret) \ 1769 return ret; \ 1770 } while (0) 1771 1772 #define MMIO_D(reg, d) \ 1773 MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL) 1774 1775 #define MMIO_DH(reg, d, r, w) \ 1776 MMIO_F(reg, 4, 0, 0, 0, d, r, w) 1777 1778 #define MMIO_DFH(reg, d, f, r, w) \ 1779 MMIO_F(reg, 4, f, 0, 0, d, r, w) 1780 1781 #define MMIO_GM(reg, d, r, w) \ 1782 MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w) 1783 1784 #define MMIO_GM_RDR(reg, d, r, w) \ 1785 MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w) 1786 1787 #define MMIO_RO(reg, d, f, rm, r, w) \ 1788 MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w) 1789 1790 #define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \ 1791 MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \ 1792 MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \ 1793 MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \ 1794 MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \ 1795 if (HAS_BSD2(dev_priv)) \ 1796 MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \ 1797 } while (0) 1798 1799 #define MMIO_RING_D(prefix, d) \ 1800 MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL) 1801 1802 #define MMIO_RING_DFH(prefix, d, f, r, w) \ 1803 MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w) 1804 1805 #define MMIO_RING_GM(prefix, d, r, w) \ 1806 MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w) 1807 1808 #define MMIO_RING_GM_RDR(prefix, d, r, w) \ 1809 MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w) 1810 1811 #define MMIO_RING_RO(prefix, d, f, rm, r, w) \ 1812 MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w) 1813 1814 static int init_generic_mmio_info(struct intel_gvt *gvt) 1815 { 1816 struct drm_i915_private *dev_priv = gvt->dev_priv; 1817 int ret; 1818 1819 MMIO_RING_DFH(RING_IMR, D_ALL, F_CMD_ACCESS, NULL, 1820 intel_vgpu_reg_imr_handler); 1821 1822 MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler); 1823 MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler); 1824 MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler); 1825 MMIO_D(SDEISR, D_ALL); 1826 1827 MMIO_RING_DFH(RING_HWSTAM, D_ALL, F_CMD_ACCESS, NULL, NULL); 1828 1829 MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL, 1830 gamw_echo_dev_rw_ia_write); 1831 1832 MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1833 MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1834 MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1835 1836 #define RING_REG(base) _MMIO((base) + 0x28) 1837 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL); 1838 #undef RING_REG 1839 1840 #define RING_REG(base) _MMIO((base) + 0x134) 1841 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL); 1842 #undef RING_REG 1843 1844 #define RING_REG(base) _MMIO((base) + 0x6c) 1845 MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL); 1846 #undef RING_REG 1847 MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL); 1848 1849 MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL); 1850 MMIO_GM_RDR(CCID, D_ALL, NULL, NULL); 1851 MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL); 1852 MMIO_D(GEN7_CXT_SIZE, D_ALL); 1853 1854 MMIO_RING_DFH(RING_TAIL, D_ALL, F_CMD_ACCESS, NULL, NULL); 1855 MMIO_RING_DFH(RING_HEAD, D_ALL, F_CMD_ACCESS, NULL, NULL); 1856 MMIO_RING_DFH(RING_CTL, D_ALL, F_CMD_ACCESS, NULL, NULL); 1857 MMIO_RING_DFH(RING_ACTHD, D_ALL, F_CMD_ACCESS, mmio_read_from_hw, NULL); 1858 MMIO_RING_GM_RDR(RING_START, D_ALL, NULL, NULL); 1859 1860 /* RING MODE */ 1861 #define RING_REG(base) _MMIO((base) + 0x29c) 1862 MMIO_RING_DFH(RING_REG, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, 1863 ring_mode_mmio_write); 1864 #undef RING_REG 1865 1866 MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 1867 NULL, NULL); 1868 MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 1869 NULL, NULL); 1870 MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS, 1871 mmio_read_from_hw, NULL); 1872 MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS, 1873 mmio_read_from_hw, NULL); 1874 1875 MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1876 MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 1877 NULL, NULL); 1878 MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1879 MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1880 MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1881 1882 MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1883 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1884 MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1885 MMIO_DFH(_MMIO(0x20e4), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1886 MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1887 MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL); 1888 MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 1889 NULL, NULL); 1890 MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 1891 NULL, NULL); 1892 MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL); 1893 MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL); 1894 MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL); 1895 MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL); 1896 MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL); 1897 MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL); 1898 MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL); 1899 MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1900 MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1901 MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1902 1903 /* display */ 1904 MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL); 1905 MMIO_D(_MMIO(0x602a0), D_ALL); 1906 1907 MMIO_D(_MMIO(0x65050), D_ALL); 1908 MMIO_D(_MMIO(0x650b4), D_ALL); 1909 1910 MMIO_D(_MMIO(0xc4040), D_ALL); 1911 MMIO_D(DERRMR, D_ALL); 1912 1913 MMIO_D(PIPEDSL(PIPE_A), D_ALL); 1914 MMIO_D(PIPEDSL(PIPE_B), D_ALL); 1915 MMIO_D(PIPEDSL(PIPE_C), D_ALL); 1916 MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL); 1917 1918 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write); 1919 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write); 1920 MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write); 1921 MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write); 1922 1923 MMIO_D(PIPESTAT(PIPE_A), D_ALL); 1924 MMIO_D(PIPESTAT(PIPE_B), D_ALL); 1925 MMIO_D(PIPESTAT(PIPE_C), D_ALL); 1926 MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL); 1927 1928 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL); 1929 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL); 1930 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL); 1931 MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL); 1932 1933 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL); 1934 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL); 1935 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL); 1936 MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL); 1937 1938 MMIO_D(CURCNTR(PIPE_A), D_ALL); 1939 MMIO_D(CURCNTR(PIPE_B), D_ALL); 1940 MMIO_D(CURCNTR(PIPE_C), D_ALL); 1941 1942 MMIO_D(CURPOS(PIPE_A), D_ALL); 1943 MMIO_D(CURPOS(PIPE_B), D_ALL); 1944 MMIO_D(CURPOS(PIPE_C), D_ALL); 1945 1946 MMIO_D(CURBASE(PIPE_A), D_ALL); 1947 MMIO_D(CURBASE(PIPE_B), D_ALL); 1948 MMIO_D(CURBASE(PIPE_C), D_ALL); 1949 1950 MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL); 1951 MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL); 1952 MMIO_D(CUR_FBC_CTL(PIPE_C), D_ALL); 1953 1954 MMIO_D(_MMIO(0x700ac), D_ALL); 1955 MMIO_D(_MMIO(0x710ac), D_ALL); 1956 MMIO_D(_MMIO(0x720ac), D_ALL); 1957 1958 MMIO_D(_MMIO(0x70090), D_ALL); 1959 MMIO_D(_MMIO(0x70094), D_ALL); 1960 MMIO_D(_MMIO(0x70098), D_ALL); 1961 MMIO_D(_MMIO(0x7009c), D_ALL); 1962 1963 MMIO_D(DSPCNTR(PIPE_A), D_ALL); 1964 MMIO_D(DSPADDR(PIPE_A), D_ALL); 1965 MMIO_D(DSPSTRIDE(PIPE_A), D_ALL); 1966 MMIO_D(DSPPOS(PIPE_A), D_ALL); 1967 MMIO_D(DSPSIZE(PIPE_A), D_ALL); 1968 MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write); 1969 MMIO_D(DSPOFFSET(PIPE_A), D_ALL); 1970 MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL); 1971 1972 MMIO_D(DSPCNTR(PIPE_B), D_ALL); 1973 MMIO_D(DSPADDR(PIPE_B), D_ALL); 1974 MMIO_D(DSPSTRIDE(PIPE_B), D_ALL); 1975 MMIO_D(DSPPOS(PIPE_B), D_ALL); 1976 MMIO_D(DSPSIZE(PIPE_B), D_ALL); 1977 MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write); 1978 MMIO_D(DSPOFFSET(PIPE_B), D_ALL); 1979 MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL); 1980 1981 MMIO_D(DSPCNTR(PIPE_C), D_ALL); 1982 MMIO_D(DSPADDR(PIPE_C), D_ALL); 1983 MMIO_D(DSPSTRIDE(PIPE_C), D_ALL); 1984 MMIO_D(DSPPOS(PIPE_C), D_ALL); 1985 MMIO_D(DSPSIZE(PIPE_C), D_ALL); 1986 MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write); 1987 MMIO_D(DSPOFFSET(PIPE_C), D_ALL); 1988 MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL); 1989 1990 MMIO_D(SPRCTL(PIPE_A), D_ALL); 1991 MMIO_D(SPRLINOFF(PIPE_A), D_ALL); 1992 MMIO_D(SPRSTRIDE(PIPE_A), D_ALL); 1993 MMIO_D(SPRPOS(PIPE_A), D_ALL); 1994 MMIO_D(SPRSIZE(PIPE_A), D_ALL); 1995 MMIO_D(SPRKEYVAL(PIPE_A), D_ALL); 1996 MMIO_D(SPRKEYMSK(PIPE_A), D_ALL); 1997 MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write); 1998 MMIO_D(SPRKEYMAX(PIPE_A), D_ALL); 1999 MMIO_D(SPROFFSET(PIPE_A), D_ALL); 2000 MMIO_D(SPRSCALE(PIPE_A), D_ALL); 2001 MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL); 2002 2003 MMIO_D(SPRCTL(PIPE_B), D_ALL); 2004 MMIO_D(SPRLINOFF(PIPE_B), D_ALL); 2005 MMIO_D(SPRSTRIDE(PIPE_B), D_ALL); 2006 MMIO_D(SPRPOS(PIPE_B), D_ALL); 2007 MMIO_D(SPRSIZE(PIPE_B), D_ALL); 2008 MMIO_D(SPRKEYVAL(PIPE_B), D_ALL); 2009 MMIO_D(SPRKEYMSK(PIPE_B), D_ALL); 2010 MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write); 2011 MMIO_D(SPRKEYMAX(PIPE_B), D_ALL); 2012 MMIO_D(SPROFFSET(PIPE_B), D_ALL); 2013 MMIO_D(SPRSCALE(PIPE_B), D_ALL); 2014 MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL); 2015 2016 MMIO_D(SPRCTL(PIPE_C), D_ALL); 2017 MMIO_D(SPRLINOFF(PIPE_C), D_ALL); 2018 MMIO_D(SPRSTRIDE(PIPE_C), D_ALL); 2019 MMIO_D(SPRPOS(PIPE_C), D_ALL); 2020 MMIO_D(SPRSIZE(PIPE_C), D_ALL); 2021 MMIO_D(SPRKEYVAL(PIPE_C), D_ALL); 2022 MMIO_D(SPRKEYMSK(PIPE_C), D_ALL); 2023 MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write); 2024 MMIO_D(SPRKEYMAX(PIPE_C), D_ALL); 2025 MMIO_D(SPROFFSET(PIPE_C), D_ALL); 2026 MMIO_D(SPRSCALE(PIPE_C), D_ALL); 2027 MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL); 2028 2029 MMIO_D(HTOTAL(TRANSCODER_A), D_ALL); 2030 MMIO_D(HBLANK(TRANSCODER_A), D_ALL); 2031 MMIO_D(HSYNC(TRANSCODER_A), D_ALL); 2032 MMIO_D(VTOTAL(TRANSCODER_A), D_ALL); 2033 MMIO_D(VBLANK(TRANSCODER_A), D_ALL); 2034 MMIO_D(VSYNC(TRANSCODER_A), D_ALL); 2035 MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL); 2036 MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL); 2037 MMIO_D(PIPESRC(TRANSCODER_A), D_ALL); 2038 2039 MMIO_D(HTOTAL(TRANSCODER_B), D_ALL); 2040 MMIO_D(HBLANK(TRANSCODER_B), D_ALL); 2041 MMIO_D(HSYNC(TRANSCODER_B), D_ALL); 2042 MMIO_D(VTOTAL(TRANSCODER_B), D_ALL); 2043 MMIO_D(VBLANK(TRANSCODER_B), D_ALL); 2044 MMIO_D(VSYNC(TRANSCODER_B), D_ALL); 2045 MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL); 2046 MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL); 2047 MMIO_D(PIPESRC(TRANSCODER_B), D_ALL); 2048 2049 MMIO_D(HTOTAL(TRANSCODER_C), D_ALL); 2050 MMIO_D(HBLANK(TRANSCODER_C), D_ALL); 2051 MMIO_D(HSYNC(TRANSCODER_C), D_ALL); 2052 MMIO_D(VTOTAL(TRANSCODER_C), D_ALL); 2053 MMIO_D(VBLANK(TRANSCODER_C), D_ALL); 2054 MMIO_D(VSYNC(TRANSCODER_C), D_ALL); 2055 MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL); 2056 MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL); 2057 MMIO_D(PIPESRC(TRANSCODER_C), D_ALL); 2058 2059 MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL); 2060 MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL); 2061 MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL); 2062 MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL); 2063 MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL); 2064 MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL); 2065 MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL); 2066 MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL); 2067 2068 MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL); 2069 MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL); 2070 MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL); 2071 MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL); 2072 MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL); 2073 MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL); 2074 MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL); 2075 MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL); 2076 2077 MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL); 2078 MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL); 2079 MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL); 2080 MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL); 2081 MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL); 2082 MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL); 2083 MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL); 2084 MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL); 2085 2086 MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL); 2087 MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL); 2088 MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL); 2089 MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL); 2090 MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL); 2091 MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL); 2092 MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL); 2093 MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL); 2094 2095 MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL); 2096 MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL); 2097 MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL); 2098 MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL); 2099 MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL); 2100 MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL); 2101 MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL); 2102 MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL); 2103 2104 MMIO_D(PF_CTL(PIPE_A), D_ALL); 2105 MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL); 2106 MMIO_D(PF_WIN_POS(PIPE_A), D_ALL); 2107 MMIO_D(PF_VSCALE(PIPE_A), D_ALL); 2108 MMIO_D(PF_HSCALE(PIPE_A), D_ALL); 2109 2110 MMIO_D(PF_CTL(PIPE_B), D_ALL); 2111 MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL); 2112 MMIO_D(PF_WIN_POS(PIPE_B), D_ALL); 2113 MMIO_D(PF_VSCALE(PIPE_B), D_ALL); 2114 MMIO_D(PF_HSCALE(PIPE_B), D_ALL); 2115 2116 MMIO_D(PF_CTL(PIPE_C), D_ALL); 2117 MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL); 2118 MMIO_D(PF_WIN_POS(PIPE_C), D_ALL); 2119 MMIO_D(PF_VSCALE(PIPE_C), D_ALL); 2120 MMIO_D(PF_HSCALE(PIPE_C), D_ALL); 2121 2122 MMIO_D(WM0_PIPEA_ILK, D_ALL); 2123 MMIO_D(WM0_PIPEB_ILK, D_ALL); 2124 MMIO_D(WM0_PIPEC_IVB, D_ALL); 2125 MMIO_D(WM1_LP_ILK, D_ALL); 2126 MMIO_D(WM2_LP_ILK, D_ALL); 2127 MMIO_D(WM3_LP_ILK, D_ALL); 2128 MMIO_D(WM1S_LP_ILK, D_ALL); 2129 MMIO_D(WM2S_LP_IVB, D_ALL); 2130 MMIO_D(WM3S_LP_IVB, D_ALL); 2131 2132 MMIO_D(BLC_PWM_CPU_CTL2, D_ALL); 2133 MMIO_D(BLC_PWM_CPU_CTL, D_ALL); 2134 MMIO_D(BLC_PWM_PCH_CTL1, D_ALL); 2135 MMIO_D(BLC_PWM_PCH_CTL2, D_ALL); 2136 2137 MMIO_D(_MMIO(0x48268), D_ALL); 2138 2139 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read, 2140 gmbus_mmio_write); 2141 MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL); 2142 MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL); 2143 2144 MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 2145 dp_aux_ch_ctl_mmio_write); 2146 MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 2147 dp_aux_ch_ctl_mmio_write); 2148 MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 2149 dp_aux_ch_ctl_mmio_write); 2150 2151 MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write); 2152 2153 MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write); 2154 MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write); 2155 2156 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write); 2157 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write); 2158 MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write); 2159 MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); 2160 MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); 2161 MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); 2162 MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); 2163 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); 2164 MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); 2165 2166 MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A), D_ALL); 2167 MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A), D_ALL); 2168 MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A), D_ALL); 2169 MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A), D_ALL); 2170 MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A), D_ALL); 2171 MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A), D_ALL); 2172 MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A), D_ALL); 2173 2174 MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B), D_ALL); 2175 MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B), D_ALL); 2176 MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B), D_ALL); 2177 MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B), D_ALL); 2178 MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B), D_ALL); 2179 MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B), D_ALL); 2180 MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B), D_ALL); 2181 2182 MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1), D_ALL); 2183 MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1), D_ALL); 2184 MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2), D_ALL); 2185 MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2), D_ALL); 2186 MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1), D_ALL); 2187 MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1), D_ALL); 2188 MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2), D_ALL); 2189 MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2), D_ALL); 2190 2191 MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL); 2192 MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL); 2193 MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL); 2194 2195 MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL); 2196 MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL); 2197 MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL); 2198 2199 MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL); 2200 MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL); 2201 MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL); 2202 2203 MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL); 2204 MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL); 2205 MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL); 2206 2207 MMIO_D(_MMIO(_FDI_RXA_MISC), D_ALL); 2208 MMIO_D(_MMIO(_FDI_RXB_MISC), D_ALL); 2209 MMIO_D(_MMIO(_FDI_RXA_TUSIZE1), D_ALL); 2210 MMIO_D(_MMIO(_FDI_RXA_TUSIZE2), D_ALL); 2211 MMIO_D(_MMIO(_FDI_RXB_TUSIZE1), D_ALL); 2212 MMIO_D(_MMIO(_FDI_RXB_TUSIZE2), D_ALL); 2213 2214 MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write); 2215 MMIO_D(PCH_PP_DIVISOR, D_ALL); 2216 MMIO_D(PCH_PP_STATUS, D_ALL); 2217 MMIO_D(PCH_LVDS, D_ALL); 2218 MMIO_D(_MMIO(_PCH_DPLL_A), D_ALL); 2219 MMIO_D(_MMIO(_PCH_DPLL_B), D_ALL); 2220 MMIO_D(_MMIO(_PCH_FPA0), D_ALL); 2221 MMIO_D(_MMIO(_PCH_FPA1), D_ALL); 2222 MMIO_D(_MMIO(_PCH_FPB0), D_ALL); 2223 MMIO_D(_MMIO(_PCH_FPB1), D_ALL); 2224 MMIO_D(PCH_DREF_CONTROL, D_ALL); 2225 MMIO_D(PCH_RAWCLK_FREQ, D_ALL); 2226 MMIO_D(PCH_DPLL_SEL, D_ALL); 2227 2228 MMIO_D(_MMIO(0x61208), D_ALL); 2229 MMIO_D(_MMIO(0x6120c), D_ALL); 2230 MMIO_D(PCH_PP_ON_DELAYS, D_ALL); 2231 MMIO_D(PCH_PP_OFF_DELAYS, D_ALL); 2232 2233 MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL); 2234 MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL); 2235 MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL); 2236 MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL); 2237 MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL); 2238 MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL); 2239 2240 MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0, 2241 PORTA_HOTPLUG_STATUS_MASK 2242 | PORTB_HOTPLUG_STATUS_MASK 2243 | PORTC_HOTPLUG_STATUS_MASK 2244 | PORTD_HOTPLUG_STATUS_MASK, 2245 NULL, NULL); 2246 2247 MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write); 2248 MMIO_D(FUSE_STRAP, D_ALL); 2249 MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL); 2250 2251 MMIO_D(DISP_ARB_CTL, D_ALL); 2252 MMIO_D(DISP_ARB_CTL2, D_ALL); 2253 2254 MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL); 2255 MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL); 2256 MMIO_D(ILK_DSPCLK_GATE_D, D_ALL); 2257 2258 MMIO_D(SOUTH_CHICKEN1, D_ALL); 2259 MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write); 2260 MMIO_D(_MMIO(_TRANSA_CHICKEN1), D_ALL); 2261 MMIO_D(_MMIO(_TRANSB_CHICKEN1), D_ALL); 2262 MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL); 2263 MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL); 2264 MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL); 2265 2266 MMIO_D(ILK_DPFC_CB_BASE, D_ALL); 2267 MMIO_D(ILK_DPFC_CONTROL, D_ALL); 2268 MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL); 2269 MMIO_D(ILK_DPFC_STATUS, D_ALL); 2270 MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL); 2271 MMIO_D(ILK_DPFC_CHICKEN, D_ALL); 2272 MMIO_D(ILK_FBC_RT_BASE, D_ALL); 2273 2274 MMIO_D(IPS_CTL, D_ALL); 2275 2276 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL); 2277 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL); 2278 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL); 2279 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL); 2280 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL); 2281 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL); 2282 MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL); 2283 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL); 2284 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL); 2285 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL); 2286 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL); 2287 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL); 2288 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL); 2289 2290 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL); 2291 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL); 2292 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL); 2293 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL); 2294 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL); 2295 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL); 2296 MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL); 2297 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL); 2298 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL); 2299 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL); 2300 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL); 2301 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL); 2302 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL); 2303 2304 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL); 2305 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL); 2306 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL); 2307 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL); 2308 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL); 2309 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL); 2310 MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL); 2311 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL); 2312 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL); 2313 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL); 2314 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL); 2315 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL); 2316 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL); 2317 2318 MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL); 2319 MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL); 2320 MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 2321 2322 MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL); 2323 MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL); 2324 MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 2325 2326 MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL); 2327 MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL); 2328 MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 2329 2330 MMIO_D(_MMIO(0x60110), D_ALL); 2331 MMIO_D(_MMIO(0x61110), D_ALL); 2332 MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL); 2333 MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL); 2334 MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL); 2335 MMIO_F(_MMIO(0x70440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2336 MMIO_F(_MMIO(0x71440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2337 MMIO_F(_MMIO(0x72440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2338 MMIO_F(_MMIO(0x7044c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2339 MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2340 MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2341 2342 MMIO_D(PIPE_WM_LINETIME(PIPE_A), D_ALL); 2343 MMIO_D(PIPE_WM_LINETIME(PIPE_B), D_ALL); 2344 MMIO_D(PIPE_WM_LINETIME(PIPE_C), D_ALL); 2345 MMIO_D(SPLL_CTL, D_ALL); 2346 MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL); 2347 MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL); 2348 MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL); 2349 MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL); 2350 MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL); 2351 MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL); 2352 MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL); 2353 MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL); 2354 MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL); 2355 MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL); 2356 2357 MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL); 2358 MMIO_D(_MMIO(0x46508), D_ALL); 2359 2360 MMIO_D(_MMIO(0x49080), D_ALL); 2361 MMIO_D(_MMIO(0x49180), D_ALL); 2362 MMIO_D(_MMIO(0x49280), D_ALL); 2363 2364 MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL); 2365 MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL); 2366 MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL); 2367 2368 MMIO_D(GAMMA_MODE(PIPE_A), D_ALL); 2369 MMIO_D(GAMMA_MODE(PIPE_B), D_ALL); 2370 MMIO_D(GAMMA_MODE(PIPE_C), D_ALL); 2371 2372 MMIO_D(PIPE_MULT(PIPE_A), D_ALL); 2373 MMIO_D(PIPE_MULT(PIPE_B), D_ALL); 2374 MMIO_D(PIPE_MULT(PIPE_C), D_ALL); 2375 2376 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL); 2377 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL); 2378 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL); 2379 2380 MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL); 2381 MMIO_D(SBI_ADDR, D_ALL); 2382 MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL); 2383 MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write); 2384 MMIO_D(PIXCLK_GATE, D_ALL); 2385 2386 MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL, 2387 dp_aux_ch_ctl_mmio_write); 2388 2389 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2390 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2391 MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2392 MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2393 MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2394 2395 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write); 2396 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write); 2397 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write); 2398 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write); 2399 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write); 2400 2401 MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write); 2402 MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write); 2403 MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write); 2404 MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write); 2405 MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL); 2406 2407 MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2408 MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2409 MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2410 MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2411 MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2412 2413 MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL); 2414 MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL); 2415 MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A), D_ALL); 2416 2417 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL); 2418 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL); 2419 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL); 2420 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL); 2421 2422 MMIO_D(_MMIO(_TRANSA_MSA_MISC), D_ALL); 2423 MMIO_D(_MMIO(_TRANSB_MSA_MISC), D_ALL); 2424 MMIO_D(_MMIO(_TRANSC_MSA_MISC), D_ALL); 2425 MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC), D_ALL); 2426 2427 MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL); 2428 MMIO_D(FORCEWAKE_ACK, D_ALL); 2429 MMIO_D(GEN6_GT_CORE_STATUS, D_ALL); 2430 MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL); 2431 MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL); 2432 MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL); 2433 MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write); 2434 MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL); 2435 MMIO_D(ECOBUS, D_ALL); 2436 MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL); 2437 MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL); 2438 MMIO_D(GEN6_RPNSWREQ, D_ALL); 2439 MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL); 2440 MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL); 2441 MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL); 2442 MMIO_D(GEN6_RPSTAT1, D_ALL); 2443 MMIO_D(GEN6_RP_CONTROL, D_ALL); 2444 MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL); 2445 MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL); 2446 MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL); 2447 MMIO_D(GEN6_RP_CUR_UP, D_ALL); 2448 MMIO_D(GEN6_RP_PREV_UP, D_ALL); 2449 MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL); 2450 MMIO_D(GEN6_RP_CUR_DOWN, D_ALL); 2451 MMIO_D(GEN6_RP_PREV_DOWN, D_ALL); 2452 MMIO_D(GEN6_RP_UP_EI, D_ALL); 2453 MMIO_D(GEN6_RP_DOWN_EI, D_ALL); 2454 MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL); 2455 MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL); 2456 MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL); 2457 MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL); 2458 MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL); 2459 MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL); 2460 MMIO_D(GEN6_RC_SLEEP, D_ALL); 2461 MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL); 2462 MMIO_D(GEN6_RC6_THRESHOLD, D_ALL); 2463 MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL); 2464 MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL); 2465 MMIO_D(GEN6_PMINTRMSK, D_ALL); 2466 MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write); 2467 MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write); 2468 MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write); 2469 MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write); 2470 MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write); 2471 MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write); 2472 2473 MMIO_D(RSTDBYCTL, D_ALL); 2474 2475 MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write); 2476 MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write); 2477 MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write); 2478 2479 MMIO_D(TILECTL, D_ALL); 2480 2481 MMIO_D(GEN6_UCGCTL1, D_ALL); 2482 MMIO_D(GEN6_UCGCTL2, D_ALL); 2483 2484 MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL); 2485 2486 MMIO_D(GEN6_PCODE_DATA, D_ALL); 2487 MMIO_D(_MMIO(0x13812c), D_ALL); 2488 MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL); 2489 MMIO_D(HSW_EDRAM_CAP, D_ALL); 2490 MMIO_D(HSW_IDICR, D_ALL); 2491 MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL); 2492 2493 MMIO_D(_MMIO(0x3c), D_ALL); 2494 MMIO_D(_MMIO(0x860), D_ALL); 2495 MMIO_D(ECOSKPD, D_ALL); 2496 MMIO_D(_MMIO(0x121d0), D_ALL); 2497 MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL); 2498 MMIO_D(_MMIO(0x41d0), D_ALL); 2499 MMIO_D(GAC_ECO_BITS, D_ALL); 2500 MMIO_D(_MMIO(0x6200), D_ALL); 2501 MMIO_D(_MMIO(0x6204), D_ALL); 2502 MMIO_D(_MMIO(0x6208), D_ALL); 2503 MMIO_D(_MMIO(0x7118), D_ALL); 2504 MMIO_D(_MMIO(0x7180), D_ALL); 2505 MMIO_D(_MMIO(0x7408), D_ALL); 2506 MMIO_D(_MMIO(0x7c00), D_ALL); 2507 MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write); 2508 MMIO_D(_MMIO(0x911c), D_ALL); 2509 MMIO_D(_MMIO(0x9120), D_ALL); 2510 MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL); 2511 2512 MMIO_D(GAB_CTL, D_ALL); 2513 MMIO_D(_MMIO(0x48800), D_ALL); 2514 MMIO_D(_MMIO(0xce044), D_ALL); 2515 MMIO_D(_MMIO(0xe6500), D_ALL); 2516 MMIO_D(_MMIO(0xe6504), D_ALL); 2517 MMIO_D(_MMIO(0xe6600), D_ALL); 2518 MMIO_D(_MMIO(0xe6604), D_ALL); 2519 MMIO_D(_MMIO(0xe6700), D_ALL); 2520 MMIO_D(_MMIO(0xe6704), D_ALL); 2521 MMIO_D(_MMIO(0xe6800), D_ALL); 2522 MMIO_D(_MMIO(0xe6804), D_ALL); 2523 MMIO_D(PCH_GMBUS4, D_ALL); 2524 MMIO_D(PCH_GMBUS5, D_ALL); 2525 2526 MMIO_D(_MMIO(0x902c), D_ALL); 2527 MMIO_D(_MMIO(0xec008), D_ALL); 2528 MMIO_D(_MMIO(0xec00c), D_ALL); 2529 MMIO_D(_MMIO(0xec008 + 0x18), D_ALL); 2530 MMIO_D(_MMIO(0xec00c + 0x18), D_ALL); 2531 MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL); 2532 MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL); 2533 MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL); 2534 MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL); 2535 MMIO_D(_MMIO(0xec408), D_ALL); 2536 MMIO_D(_MMIO(0xec40c), D_ALL); 2537 MMIO_D(_MMIO(0xec408 + 0x18), D_ALL); 2538 MMIO_D(_MMIO(0xec40c + 0x18), D_ALL); 2539 MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL); 2540 MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL); 2541 MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL); 2542 MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL); 2543 MMIO_D(_MMIO(0xfc810), D_ALL); 2544 MMIO_D(_MMIO(0xfc81c), D_ALL); 2545 MMIO_D(_MMIO(0xfc828), D_ALL); 2546 MMIO_D(_MMIO(0xfc834), D_ALL); 2547 MMIO_D(_MMIO(0xfcc00), D_ALL); 2548 MMIO_D(_MMIO(0xfcc0c), D_ALL); 2549 MMIO_D(_MMIO(0xfcc18), D_ALL); 2550 MMIO_D(_MMIO(0xfcc24), D_ALL); 2551 MMIO_D(_MMIO(0xfd000), D_ALL); 2552 MMIO_D(_MMIO(0xfd00c), D_ALL); 2553 MMIO_D(_MMIO(0xfd018), D_ALL); 2554 MMIO_D(_MMIO(0xfd024), D_ALL); 2555 MMIO_D(_MMIO(0xfd034), D_ALL); 2556 2557 MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write); 2558 MMIO_D(_MMIO(0x2054), D_ALL); 2559 MMIO_D(_MMIO(0x12054), D_ALL); 2560 MMIO_D(_MMIO(0x22054), D_ALL); 2561 MMIO_D(_MMIO(0x1a054), D_ALL); 2562 2563 MMIO_D(_MMIO(0x44070), D_ALL); 2564 MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2565 MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL); 2566 MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL); 2567 MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL); 2568 MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL); 2569 2570 MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL); 2571 MMIO_D(_MMIO(0x2b00), D_BDW_PLUS); 2572 MMIO_D(_MMIO(0x2360), D_BDW_PLUS); 2573 MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2574 MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2575 MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2576 2577 MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2578 MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2579 MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL); 2580 2581 MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2582 MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2583 MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2584 MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2585 MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2586 MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2587 MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2588 MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2589 MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2590 MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2591 MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2592 MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2593 MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2594 MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2595 MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2596 MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2597 MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2598 2599 MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2600 MMIO_RING_GM_RDR(RING_BBADDR, D_ALL, NULL, NULL); 2601 MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL); 2602 MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL); 2603 MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL); 2604 MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL); 2605 MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL); 2606 MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2607 MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2608 MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2609 MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2610 return 0; 2611 } 2612 2613 static int init_broadwell_mmio_info(struct intel_gvt *gvt) 2614 { 2615 struct drm_i915_private *dev_priv = gvt->dev_priv; 2616 int ret; 2617 2618 MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2619 MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2620 MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2621 MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS); 2622 2623 MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2624 MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2625 MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2626 MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS); 2627 2628 MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2629 MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2630 MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2631 MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS); 2632 2633 MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2634 MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2635 MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2636 MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS); 2637 2638 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL, 2639 intel_vgpu_reg_imr_handler); 2640 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL, 2641 intel_vgpu_reg_ier_handler); 2642 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL, 2643 intel_vgpu_reg_iir_handler); 2644 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS); 2645 2646 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL, 2647 intel_vgpu_reg_imr_handler); 2648 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL, 2649 intel_vgpu_reg_ier_handler); 2650 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL, 2651 intel_vgpu_reg_iir_handler); 2652 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS); 2653 2654 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL, 2655 intel_vgpu_reg_imr_handler); 2656 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL, 2657 intel_vgpu_reg_ier_handler); 2658 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL, 2659 intel_vgpu_reg_iir_handler); 2660 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS); 2661 2662 MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2663 MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2664 MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2665 MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS); 2666 2667 MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2668 MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2669 MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2670 MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS); 2671 2672 MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2673 MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2674 MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2675 MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS); 2676 2677 MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL, 2678 intel_vgpu_reg_master_irq_handler); 2679 2680 MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, F_CMD_ACCESS, 2681 mmio_read_from_hw, NULL); 2682 2683 #define RING_REG(base) _MMIO((base) + 0xd0) 2684 MMIO_RING_F(RING_REG, 4, F_RO, 0, 2685 ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL, 2686 ring_reset_ctl_write); 2687 #undef RING_REG 2688 2689 #define RING_REG(base) _MMIO((base) + 0x230) 2690 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write); 2691 #undef RING_REG 2692 2693 #define RING_REG(base) _MMIO((base) + 0x234) 2694 MMIO_RING_F(RING_REG, 8, F_RO | F_CMD_ACCESS, 0, ~0, D_BDW_PLUS, 2695 NULL, NULL); 2696 #undef RING_REG 2697 2698 #define RING_REG(base) _MMIO((base) + 0x244) 2699 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2700 #undef RING_REG 2701 2702 #define RING_REG(base) _MMIO((base) + 0x370) 2703 MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL); 2704 #undef RING_REG 2705 2706 #define RING_REG(base) _MMIO((base) + 0x3a0) 2707 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2708 #undef RING_REG 2709 2710 MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS); 2711 MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS); 2712 MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS); 2713 MMIO_D(_MMIO(0x1c1d0), D_BDW_PLUS); 2714 MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS); 2715 MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS); 2716 MMIO_D(_MMIO(0x1c054), D_BDW_PLUS); 2717 2718 MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write); 2719 2720 MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS); 2721 MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS); 2722 2723 MMIO_D(GAMTARBMODE, D_BDW_PLUS); 2724 2725 #define RING_REG(base) _MMIO((base) + 0x270) 2726 MMIO_RING_F(RING_REG, 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL); 2727 #undef RING_REG 2728 2729 MMIO_RING_GM_RDR(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write); 2730 2731 MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2732 2733 MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS); 2734 MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS); 2735 MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS); 2736 2737 MMIO_D(WM_MISC, D_BDW); 2738 MMIO_D(_MMIO(BDW_EDP_PSR_BASE), D_BDW); 2739 2740 MMIO_D(_MMIO(0x6671c), D_BDW_PLUS); 2741 MMIO_D(_MMIO(0x66c00), D_BDW_PLUS); 2742 MMIO_D(_MMIO(0x66c04), D_BDW_PLUS); 2743 2744 MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS); 2745 2746 MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS); 2747 MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS); 2748 MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS); 2749 2750 MMIO_D(_MMIO(0xfdc), D_BDW_PLUS); 2751 MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2752 NULL, NULL); 2753 MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2754 NULL, NULL); 2755 MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2756 2757 MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL); 2758 MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL); 2759 MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2760 MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL); 2761 MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL); 2762 MMIO_D(_MMIO(0xb110), D_BDW); 2763 2764 MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, 2765 NULL, force_nonpriv_write); 2766 2767 MMIO_D(_MMIO(0x44484), D_BDW_PLUS); 2768 MMIO_D(_MMIO(0x4448c), D_BDW_PLUS); 2769 2770 MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL); 2771 MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS); 2772 2773 MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL); 2774 2775 MMIO_D(_MMIO(0x110000), D_BDW_PLUS); 2776 2777 MMIO_D(_MMIO(0x48400), D_BDW_PLUS); 2778 2779 MMIO_D(_MMIO(0x6e570), D_BDW_PLUS); 2780 MMIO_D(_MMIO(0x65f10), D_BDW_PLUS); 2781 2782 MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2783 MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2784 MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2785 MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2786 2787 MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL); 2788 2789 MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2790 MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2791 MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2792 MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2793 MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2794 MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2795 MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2796 MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2797 MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2798 return 0; 2799 } 2800 2801 static int init_skl_mmio_info(struct intel_gvt *gvt) 2802 { 2803 struct drm_i915_private *dev_priv = gvt->dev_priv; 2804 int ret; 2805 2806 MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2807 MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL); 2808 MMIO_DH(FORCEWAKE_BLITTER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2809 MMIO_DH(FORCEWAKE_ACK_BLITTER_GEN9, D_SKL_PLUS, NULL, NULL); 2810 MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2811 MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL); 2812 2813 MMIO_F(_MMIO(_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 2814 dp_aux_ch_ctl_mmio_write); 2815 MMIO_F(_MMIO(_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 2816 dp_aux_ch_ctl_mmio_write); 2817 MMIO_F(_MMIO(_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 2818 dp_aux_ch_ctl_mmio_write); 2819 2820 MMIO_D(HSW_PWR_WELL_CTL1, D_SKL_PLUS); 2821 MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write); 2822 2823 MMIO_DH(DBUF_CTL, D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write); 2824 2825 MMIO_D(_MMIO(0xa210), D_SKL_PLUS); 2826 MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS); 2827 MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS); 2828 MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2829 MMIO_DH(_MMIO(0x4ddc), D_SKL_PLUS, NULL, NULL); 2830 MMIO_DH(_MMIO(0x42080), D_SKL_PLUS, NULL, NULL); 2831 MMIO_D(_MMIO(0x45504), D_SKL_PLUS); 2832 MMIO_D(_MMIO(0x45520), D_SKL_PLUS); 2833 MMIO_D(_MMIO(0x46000), D_SKL_PLUS); 2834 MMIO_DH(_MMIO(0x46010), D_SKL_PLUS, NULL, skl_lcpll_write); 2835 MMIO_DH(_MMIO(0x46014), D_SKL_PLUS, NULL, skl_lcpll_write); 2836 MMIO_D(_MMIO(0x6C040), D_SKL_PLUS); 2837 MMIO_D(_MMIO(0x6C048), D_SKL_PLUS); 2838 MMIO_D(_MMIO(0x6C050), D_SKL_PLUS); 2839 MMIO_D(_MMIO(0x6C044), D_SKL_PLUS); 2840 MMIO_D(_MMIO(0x6C04C), D_SKL_PLUS); 2841 MMIO_D(_MMIO(0x6C054), D_SKL_PLUS); 2842 MMIO_D(_MMIO(0x6c058), D_SKL_PLUS); 2843 MMIO_D(_MMIO(0x6c05c), D_SKL_PLUS); 2844 MMIO_DH(_MMIO(0x6c060), D_SKL_PLUS, dpll_status_read, NULL); 2845 2846 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); 2847 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); 2848 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); 2849 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); 2850 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); 2851 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); 2852 2853 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); 2854 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); 2855 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); 2856 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); 2857 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); 2858 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); 2859 2860 MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); 2861 MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); 2862 MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); 2863 MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); 2864 MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); 2865 MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); 2866 2867 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 2868 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 2869 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 2870 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); 2871 2872 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 2873 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 2874 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 2875 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); 2876 2877 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 2878 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 2879 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2880 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); 2881 2882 MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL); 2883 MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL); 2884 MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL); 2885 2886 MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2887 MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2888 MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2889 2890 MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2891 MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2892 MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2893 2894 MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2895 MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2896 MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2897 2898 MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2899 MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2900 MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2901 2902 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 2903 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 2904 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 2905 2906 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 2907 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 2908 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 2909 2910 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 2911 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 2912 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2913 2914 MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL); 2915 MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL); 2916 MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL); 2917 2918 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 2919 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 2920 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 2921 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); 2922 2923 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 2924 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 2925 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 2926 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); 2927 2928 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 2929 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 2930 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2931 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); 2932 2933 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL); 2934 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL); 2935 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL); 2936 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL); 2937 2938 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL); 2939 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL); 2940 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL); 2941 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL); 2942 2943 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL); 2944 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL); 2945 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL); 2946 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL); 2947 2948 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL); 2949 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL); 2950 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL); 2951 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL); 2952 2953 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL); 2954 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL); 2955 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL); 2956 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL); 2957 2958 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL); 2959 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL); 2960 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL); 2961 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL); 2962 2963 MMIO_D(_MMIO(0x70380), D_SKL_PLUS); 2964 MMIO_D(_MMIO(0x71380), D_SKL_PLUS); 2965 MMIO_D(_MMIO(0x72380), D_SKL_PLUS); 2966 MMIO_D(_MMIO(0x7239c), D_SKL_PLUS); 2967 MMIO_D(_MMIO(0x7039c), D_SKL_PLUS); 2968 2969 MMIO_D(_MMIO(0x8f074), D_SKL_PLUS); 2970 MMIO_D(_MMIO(0x8f004), D_SKL_PLUS); 2971 MMIO_D(_MMIO(0x8f034), D_SKL_PLUS); 2972 2973 MMIO_D(_MMIO(0xb11c), D_SKL_PLUS); 2974 2975 MMIO_D(_MMIO(0x51000), D_SKL_PLUS); 2976 MMIO_D(_MMIO(0x6c00c), D_SKL_PLUS); 2977 2978 MMIO_F(_MMIO(0xc800), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS, 2979 NULL, NULL); 2980 MMIO_F(_MMIO(0xb020), 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS, 2981 NULL, NULL); 2982 2983 MMIO_D(RPM_CONFIG0, D_SKL_PLUS); 2984 MMIO_D(_MMIO(0xd08), D_SKL_PLUS); 2985 MMIO_D(RC6_LOCATION, D_SKL_PLUS); 2986 MMIO_DFH(_MMIO(0x20e0), D_SKL_PLUS, F_MODE_MASK, NULL, NULL); 2987 MMIO_DFH(_MMIO(0x20ec), D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2988 NULL, NULL); 2989 2990 /* TRTT */ 2991 MMIO_DFH(_MMIO(0x4de0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2992 MMIO_DFH(_MMIO(0x4de4), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2993 MMIO_DFH(_MMIO(0x4de8), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2994 MMIO_DFH(_MMIO(0x4dec), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2995 MMIO_DFH(_MMIO(0x4df0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2996 MMIO_DFH(_MMIO(0x4df4), D_SKL_PLUS, F_CMD_ACCESS, 2997 NULL, gen9_trtte_write); 2998 MMIO_DH(_MMIO(0x4dfc), D_SKL_PLUS, NULL, gen9_trtt_chicken_write); 2999 3000 MMIO_D(_MMIO(0x46430), D_SKL_PLUS); 3001 3002 MMIO_D(_MMIO(0x46520), D_SKL_PLUS); 3003 3004 MMIO_D(_MMIO(0xc403c), D_SKL_PLUS); 3005 MMIO_D(_MMIO(0xb004), D_SKL_PLUS); 3006 MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write); 3007 3008 MMIO_D(_MMIO(0x65900), D_SKL_PLUS); 3009 MMIO_D(_MMIO(0x1082c0), D_SKL_PLUS); 3010 MMIO_D(_MMIO(0x4068), D_SKL_PLUS); 3011 MMIO_D(_MMIO(0x67054), D_SKL_PLUS); 3012 MMIO_D(_MMIO(0x6e560), D_SKL_PLUS); 3013 MMIO_D(_MMIO(0x6e554), D_SKL_PLUS); 3014 MMIO_D(_MMIO(0x2b20), D_SKL_PLUS); 3015 MMIO_D(_MMIO(0x65f00), D_SKL_PLUS); 3016 MMIO_D(_MMIO(0x65f08), D_SKL_PLUS); 3017 MMIO_D(_MMIO(0x320f0), D_SKL_PLUS); 3018 3019 MMIO_D(_MMIO(0x70034), D_SKL_PLUS); 3020 MMIO_D(_MMIO(0x71034), D_SKL_PLUS); 3021 MMIO_D(_MMIO(0x72034), D_SKL_PLUS); 3022 3023 MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A)), D_SKL_PLUS); 3024 MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B)), D_SKL_PLUS); 3025 MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C)), D_SKL_PLUS); 3026 MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A)), D_SKL_PLUS); 3027 MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B)), D_SKL_PLUS); 3028 MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C)), D_SKL_PLUS); 3029 MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A)), D_SKL_PLUS); 3030 MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)), D_SKL_PLUS); 3031 MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)), D_SKL_PLUS); 3032 3033 MMIO_D(_MMIO(0x44500), D_SKL_PLUS); 3034 MMIO_DFH(GEN9_CSFE_CHICKEN1_RCS, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 3035 MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, 3036 NULL, NULL); 3037 MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, 3038 NULL, NULL); 3039 3040 MMIO_D(_MMIO(0x4ab8), D_KBL); 3041 MMIO_D(_MMIO(0x2248), D_KBL | D_SKL); 3042 3043 return 0; 3044 } 3045 3046 static int init_bxt_mmio_info(struct intel_gvt *gvt) 3047 { 3048 struct drm_i915_private *dev_priv = gvt->dev_priv; 3049 int ret; 3050 3051 MMIO_F(_MMIO(0x80000), 0x3000, 0, 0, 0, D_BXT, NULL, NULL); 3052 3053 MMIO_D(GEN7_SAMPLER_INSTDONE, D_BXT); 3054 MMIO_D(GEN7_ROW_INSTDONE, D_BXT); 3055 MMIO_D(GEN8_FAULT_TLB_DATA0, D_BXT); 3056 MMIO_D(GEN8_FAULT_TLB_DATA1, D_BXT); 3057 MMIO_D(ERROR_GEN6, D_BXT); 3058 MMIO_D(DONE_REG, D_BXT); 3059 MMIO_D(EIR, D_BXT); 3060 MMIO_D(PGTBL_ER, D_BXT); 3061 MMIO_D(_MMIO(0x4194), D_BXT); 3062 MMIO_D(_MMIO(0x4294), D_BXT); 3063 MMIO_D(_MMIO(0x4494), D_BXT); 3064 3065 MMIO_RING_D(RING_PSMI_CTL, D_BXT); 3066 MMIO_RING_D(RING_DMA_FADD, D_BXT); 3067 MMIO_RING_D(RING_DMA_FADD_UDW, D_BXT); 3068 MMIO_RING_D(RING_IPEHR, D_BXT); 3069 MMIO_RING_D(RING_INSTPS, D_BXT); 3070 MMIO_RING_D(RING_BBADDR_UDW, D_BXT); 3071 MMIO_RING_D(RING_BBSTATE, D_BXT); 3072 MMIO_RING_D(RING_IPEIR, D_BXT); 3073 3074 MMIO_F(SOFT_SCRATCH(0), 16 * 4, 0, 0, 0, D_BXT, NULL, NULL); 3075 3076 MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write); 3077 MMIO_D(BXT_RP_STATE_CAP, D_BXT); 3078 MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT, 3079 NULL, bxt_phy_ctl_family_write); 3080 MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT, 3081 NULL, bxt_phy_ctl_family_write); 3082 MMIO_D(BXT_PHY_CTL(PORT_A), D_BXT); 3083 MMIO_D(BXT_PHY_CTL(PORT_B), D_BXT); 3084 MMIO_D(BXT_PHY_CTL(PORT_C), D_BXT); 3085 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT, 3086 NULL, bxt_port_pll_enable_write); 3087 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT, 3088 NULL, bxt_port_pll_enable_write); 3089 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL, 3090 bxt_port_pll_enable_write); 3091 3092 MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY0), D_BXT); 3093 MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY0), D_BXT); 3094 MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY0), D_BXT); 3095 MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY0), D_BXT); 3096 MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY0), D_BXT); 3097 MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY0), D_BXT); 3098 MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY0), D_BXT); 3099 MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY0), D_BXT); 3100 MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY0), D_BXT); 3101 3102 MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY1), D_BXT); 3103 MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY1), D_BXT); 3104 MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY1), D_BXT); 3105 MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY1), D_BXT); 3106 MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY1), D_BXT); 3107 MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY1), D_BXT); 3108 MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY1), D_BXT); 3109 MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY1), D_BXT); 3110 MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY1), D_BXT); 3111 3112 MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH0), D_BXT); 3113 MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH0), D_BXT); 3114 MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH0), D_BXT); 3115 MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH0), D_BXT); 3116 MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH0), D_BXT); 3117 MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH0), D_BXT); 3118 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT, 3119 NULL, bxt_pcs_dw12_grp_write); 3120 MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH0), D_BXT); 3121 MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH0), D_BXT); 3122 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT, 3123 bxt_port_tx_dw3_read, NULL); 3124 MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH0), D_BXT); 3125 MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH0), D_BXT); 3126 MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH0), D_BXT); 3127 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT); 3128 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 1), D_BXT); 3129 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 2), D_BXT); 3130 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 3), D_BXT); 3131 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 0), D_BXT); 3132 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 1), D_BXT); 3133 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 2), D_BXT); 3134 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 3), D_BXT); 3135 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 6), D_BXT); 3136 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 8), D_BXT); 3137 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 9), D_BXT); 3138 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 10), D_BXT); 3139 3140 MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH1), D_BXT); 3141 MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH1), D_BXT); 3142 MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH1), D_BXT); 3143 MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH1), D_BXT); 3144 MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH1), D_BXT); 3145 MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH1), D_BXT); 3146 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT, 3147 NULL, bxt_pcs_dw12_grp_write); 3148 MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH1), D_BXT); 3149 MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH1), D_BXT); 3150 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT, 3151 bxt_port_tx_dw3_read, NULL); 3152 MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH1), D_BXT); 3153 MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH1), D_BXT); 3154 MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH1), D_BXT); 3155 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT); 3156 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 1), D_BXT); 3157 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 2), D_BXT); 3158 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 3), D_BXT); 3159 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 0), D_BXT); 3160 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 1), D_BXT); 3161 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 2), D_BXT); 3162 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 3), D_BXT); 3163 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 6), D_BXT); 3164 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 8), D_BXT); 3165 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 9), D_BXT); 3166 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 10), D_BXT); 3167 3168 MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY1, DPIO_CH0), D_BXT); 3169 MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY1, DPIO_CH0), D_BXT); 3170 MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY1, DPIO_CH0), D_BXT); 3171 MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY1, DPIO_CH0), D_BXT); 3172 MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY1, DPIO_CH0), D_BXT); 3173 MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY1, DPIO_CH0), D_BXT); 3174 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT, 3175 NULL, bxt_pcs_dw12_grp_write); 3176 MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY1, DPIO_CH0), D_BXT); 3177 MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY1, DPIO_CH0), D_BXT); 3178 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT, 3179 bxt_port_tx_dw3_read, NULL); 3180 MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY1, DPIO_CH0), D_BXT); 3181 MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY1, DPIO_CH0), D_BXT); 3182 MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY1, DPIO_CH0), D_BXT); 3183 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT); 3184 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 1), D_BXT); 3185 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 2), D_BXT); 3186 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 3), D_BXT); 3187 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 0), D_BXT); 3188 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 1), D_BXT); 3189 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 2), D_BXT); 3190 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 3), D_BXT); 3191 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 6), D_BXT); 3192 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 8), D_BXT); 3193 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 9), D_BXT); 3194 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 10), D_BXT); 3195 3196 MMIO_D(BXT_DE_PLL_CTL, D_BXT); 3197 MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write); 3198 MMIO_D(BXT_DSI_PLL_CTL, D_BXT); 3199 MMIO_D(BXT_DSI_PLL_ENABLE, D_BXT); 3200 3201 MMIO_D(GEN9_CLKGATE_DIS_0, D_BXT); 3202 MMIO_D(GEN9_CLKGATE_DIS_4, D_BXT); 3203 3204 MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_A), D_BXT); 3205 MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT); 3206 MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C), D_BXT); 3207 3208 MMIO_DH(EDP_PSR_IMR, D_BXT, NULL, bxt_edp_psr_imr_iir_write); 3209 MMIO_DH(EDP_PSR_IIR, D_BXT, NULL, bxt_edp_psr_imr_iir_write); 3210 3211 MMIO_D(RC6_CTX_BASE, D_BXT); 3212 3213 MMIO_D(GEN8_PUSHBUS_CONTROL, D_BXT); 3214 MMIO_D(GEN8_PUSHBUS_ENABLE, D_BXT); 3215 MMIO_D(GEN8_PUSHBUS_SHIFT, D_BXT); 3216 MMIO_D(GEN6_GFXPAUSE, D_BXT); 3217 MMIO_D(GEN8_L3SQCREG1, D_BXT); 3218 3219 MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL); 3220 3221 return 0; 3222 } 3223 3224 static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt, 3225 unsigned int offset) 3226 { 3227 unsigned long device = intel_gvt_get_device_type(gvt); 3228 struct gvt_mmio_block *block = gvt->mmio.mmio_block; 3229 int num = gvt->mmio.num_mmio_block; 3230 int i; 3231 3232 for (i = 0; i < num; i++, block++) { 3233 if (!(device & block->device)) 3234 continue; 3235 if (offset >= i915_mmio_reg_offset(block->offset) && 3236 offset < i915_mmio_reg_offset(block->offset) + block->size) 3237 return block; 3238 } 3239 return NULL; 3240 } 3241 3242 /** 3243 * intel_gvt_clean_mmio_info - clean up MMIO information table for GVT device 3244 * @gvt: GVT device 3245 * 3246 * This function is called at the driver unloading stage, to clean up the MMIO 3247 * information table of GVT device 3248 * 3249 */ 3250 void intel_gvt_clean_mmio_info(struct intel_gvt *gvt) 3251 { 3252 struct hlist_node *tmp; 3253 struct intel_gvt_mmio_info *e; 3254 int i; 3255 3256 hash_for_each_safe(gvt->mmio.mmio_info_table, i, tmp, e, node) 3257 kfree(e); 3258 3259 vfree(gvt->mmio.mmio_attribute); 3260 gvt->mmio.mmio_attribute = NULL; 3261 } 3262 3263 /* Special MMIO blocks. */ 3264 static struct gvt_mmio_block mmio_blocks[] = { 3265 {D_SKL_PLUS, _MMIO(CSR_MMIO_START_RANGE), 0x3000, NULL, NULL}, 3266 {D_ALL, _MMIO(MCHBAR_MIRROR_BASE_SNB), 0x40000, NULL, NULL}, 3267 {D_ALL, _MMIO(VGT_PVINFO_PAGE), VGT_PVINFO_SIZE, 3268 pvinfo_mmio_read, pvinfo_mmio_write}, 3269 {D_ALL, LGC_PALETTE(PIPE_A, 0), 1024, NULL, NULL}, 3270 {D_ALL, LGC_PALETTE(PIPE_B, 0), 1024, NULL, NULL}, 3271 {D_ALL, LGC_PALETTE(PIPE_C, 0), 1024, NULL, NULL}, 3272 }; 3273 3274 /** 3275 * intel_gvt_setup_mmio_info - setup MMIO information table for GVT device 3276 * @gvt: GVT device 3277 * 3278 * This function is called at the initialization stage, to setup the MMIO 3279 * information table for GVT device 3280 * 3281 * Returns: 3282 * zero on success, negative if failed. 3283 */ 3284 int intel_gvt_setup_mmio_info(struct intel_gvt *gvt) 3285 { 3286 struct intel_gvt_device_info *info = &gvt->device_info; 3287 struct drm_i915_private *dev_priv = gvt->dev_priv; 3288 int size = info->mmio_size / 4 * sizeof(*gvt->mmio.mmio_attribute); 3289 int ret; 3290 3291 gvt->mmio.mmio_attribute = vzalloc(size); 3292 if (!gvt->mmio.mmio_attribute) 3293 return -ENOMEM; 3294 3295 ret = init_generic_mmio_info(gvt); 3296 if (ret) 3297 goto err; 3298 3299 if (IS_BROADWELL(dev_priv)) { 3300 ret = init_broadwell_mmio_info(gvt); 3301 if (ret) 3302 goto err; 3303 } else if (IS_SKYLAKE(dev_priv) 3304 || IS_KABYLAKE(dev_priv)) { 3305 ret = init_broadwell_mmio_info(gvt); 3306 if (ret) 3307 goto err; 3308 ret = init_skl_mmio_info(gvt); 3309 if (ret) 3310 goto err; 3311 } else if (IS_BROXTON(dev_priv)) { 3312 ret = init_broadwell_mmio_info(gvt); 3313 if (ret) 3314 goto err; 3315 ret = init_skl_mmio_info(gvt); 3316 if (ret) 3317 goto err; 3318 ret = init_bxt_mmio_info(gvt); 3319 if (ret) 3320 goto err; 3321 } 3322 3323 gvt->mmio.mmio_block = mmio_blocks; 3324 gvt->mmio.num_mmio_block = ARRAY_SIZE(mmio_blocks); 3325 3326 return 0; 3327 err: 3328 intel_gvt_clean_mmio_info(gvt); 3329 return ret; 3330 } 3331 3332 /** 3333 * intel_gvt_for_each_tracked_mmio - iterate each tracked mmio 3334 * @gvt: a GVT device 3335 * @handler: the handler 3336 * @data: private data given to handler 3337 * 3338 * Returns: 3339 * Zero on success, negative error code if failed. 3340 */ 3341 int intel_gvt_for_each_tracked_mmio(struct intel_gvt *gvt, 3342 int (*handler)(struct intel_gvt *gvt, u32 offset, void *data), 3343 void *data) 3344 { 3345 struct gvt_mmio_block *block = gvt->mmio.mmio_block; 3346 struct intel_gvt_mmio_info *e; 3347 int i, j, ret; 3348 3349 hash_for_each(gvt->mmio.mmio_info_table, i, e, node) { 3350 ret = handler(gvt, e->offset, data); 3351 if (ret) 3352 return ret; 3353 } 3354 3355 for (i = 0; i < gvt->mmio.num_mmio_block; i++, block++) { 3356 for (j = 0; j < block->size; j += 4) { 3357 ret = handler(gvt, 3358 i915_mmio_reg_offset(block->offset) + j, 3359 data); 3360 if (ret) 3361 return ret; 3362 } 3363 } 3364 return 0; 3365 } 3366 3367 /** 3368 * intel_vgpu_default_mmio_read - default MMIO read handler 3369 * @vgpu: a vGPU 3370 * @offset: access offset 3371 * @p_data: data return buffer 3372 * @bytes: access data length 3373 * 3374 * Returns: 3375 * Zero on success, negative error code if failed. 3376 */ 3377 int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 3378 void *p_data, unsigned int bytes) 3379 { 3380 read_vreg(vgpu, offset, p_data, bytes); 3381 return 0; 3382 } 3383 3384 /** 3385 * intel_t_default_mmio_write - default MMIO write handler 3386 * @vgpu: a vGPU 3387 * @offset: access offset 3388 * @p_data: write data buffer 3389 * @bytes: access data length 3390 * 3391 * Returns: 3392 * Zero on success, negative error code if failed. 3393 */ 3394 int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 3395 void *p_data, unsigned int bytes) 3396 { 3397 write_vreg(vgpu, offset, p_data, bytes); 3398 return 0; 3399 } 3400 3401 /** 3402 * intel_vgpu_mask_mmio_write - write mask register 3403 * @vgpu: a vGPU 3404 * @offset: access offset 3405 * @p_data: write data buffer 3406 * @bytes: access data length 3407 * 3408 * Returns: 3409 * Zero on success, negative error code if failed. 3410 */ 3411 int intel_vgpu_mask_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 3412 void *p_data, unsigned int bytes) 3413 { 3414 u32 mask, old_vreg; 3415 3416 old_vreg = vgpu_vreg(vgpu, offset); 3417 write_vreg(vgpu, offset, p_data, bytes); 3418 mask = vgpu_vreg(vgpu, offset) >> 16; 3419 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask) | 3420 (vgpu_vreg(vgpu, offset) & mask); 3421 3422 return 0; 3423 } 3424 3425 /** 3426 * intel_gvt_in_force_nonpriv_whitelist - if a mmio is in whitelist to be 3427 * force-nopriv register 3428 * 3429 * @gvt: a GVT device 3430 * @offset: register offset 3431 * 3432 * Returns: 3433 * True if the register is in force-nonpriv whitelist; 3434 * False if outside; 3435 */ 3436 bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt, 3437 unsigned int offset) 3438 { 3439 return in_whitelist(offset); 3440 } 3441 3442 /** 3443 * intel_vgpu_mmio_reg_rw - emulate tracked mmio registers 3444 * @vgpu: a vGPU 3445 * @offset: register offset 3446 * @pdata: data buffer 3447 * @bytes: data length 3448 * @is_read: read or write 3449 * 3450 * Returns: 3451 * Zero on success, negative error code if failed. 3452 */ 3453 int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset, 3454 void *pdata, unsigned int bytes, bool is_read) 3455 { 3456 struct intel_gvt *gvt = vgpu->gvt; 3457 struct intel_gvt_mmio_info *mmio_info; 3458 struct gvt_mmio_block *mmio_block; 3459 gvt_mmio_func func; 3460 int ret; 3461 3462 if (WARN_ON(bytes > 8)) 3463 return -EINVAL; 3464 3465 /* 3466 * Handle special MMIO blocks. 3467 */ 3468 mmio_block = find_mmio_block(gvt, offset); 3469 if (mmio_block) { 3470 func = is_read ? mmio_block->read : mmio_block->write; 3471 if (func) 3472 return func(vgpu, offset, pdata, bytes); 3473 goto default_rw; 3474 } 3475 3476 /* 3477 * Normal tracked MMIOs. 3478 */ 3479 mmio_info = find_mmio_info(gvt, offset); 3480 if (!mmio_info) { 3481 gvt_dbg_mmio("untracked MMIO %08x len %d\n", offset, bytes); 3482 goto default_rw; 3483 } 3484 3485 if (is_read) 3486 return mmio_info->read(vgpu, offset, pdata, bytes); 3487 else { 3488 u64 ro_mask = mmio_info->ro_mask; 3489 u32 old_vreg = 0, old_sreg = 0; 3490 u64 data = 0; 3491 3492 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) { 3493 old_vreg = vgpu_vreg(vgpu, offset); 3494 old_sreg = vgpu_sreg(vgpu, offset); 3495 } 3496 3497 if (likely(!ro_mask)) 3498 ret = mmio_info->write(vgpu, offset, pdata, bytes); 3499 else if (!~ro_mask) { 3500 gvt_vgpu_err("try to write RO reg %x\n", offset); 3501 return 0; 3502 } else { 3503 /* keep the RO bits in the virtual register */ 3504 memcpy(&data, pdata, bytes); 3505 data &= ~ro_mask; 3506 data |= vgpu_vreg(vgpu, offset) & ro_mask; 3507 ret = mmio_info->write(vgpu, offset, &data, bytes); 3508 } 3509 3510 /* higher 16bits of mode ctl regs are mask bits for change */ 3511 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) { 3512 u32 mask = vgpu_vreg(vgpu, offset) >> 16; 3513 3514 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask) 3515 | (vgpu_vreg(vgpu, offset) & mask); 3516 vgpu_sreg(vgpu, offset) = (old_sreg & ~mask) 3517 | (vgpu_sreg(vgpu, offset) & mask); 3518 } 3519 } 3520 3521 return ret; 3522 3523 default_rw: 3524 return is_read ? 3525 intel_vgpu_default_mmio_read(vgpu, offset, pdata, bytes) : 3526 intel_vgpu_default_mmio_write(vgpu, offset, pdata, bytes); 3527 } 3528