1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Kevin Tian <kevin.tian@intel.com> 25 * Eddie Dong <eddie.dong@intel.com> 26 * Zhiyuan Lv <zhiyuan.lv@intel.com> 27 * 28 * Contributors: 29 * Min He <min.he@intel.com> 30 * Tina Zhang <tina.zhang@intel.com> 31 * Pei Zhang <pei.zhang@intel.com> 32 * Niu Bing <bing.niu@intel.com> 33 * Ping Gao <ping.a.gao@intel.com> 34 * Zhi Wang <zhi.a.wang@intel.com> 35 * 36 37 */ 38 39 #include "i915_drv.h" 40 #include "i915_reg.h" 41 #include "gvt.h" 42 #include "i915_pvinfo.h" 43 #include "intel_mchbar_regs.h" 44 #include "display/intel_display_types.h" 45 #include "display/intel_dmc_regs.h" 46 #include "display/intel_fbc.h" 47 #include "display/vlv_dsi_pll_regs.h" 48 #include "gt/intel_gt_regs.h" 49 50 /* XXX FIXME i915 has changed PP_XXX definition */ 51 #define PCH_PP_STATUS _MMIO(0xc7200) 52 #define PCH_PP_CONTROL _MMIO(0xc7204) 53 #define PCH_PP_ON_DELAYS _MMIO(0xc7208) 54 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c) 55 #define PCH_PP_DIVISOR _MMIO(0xc7210) 56 57 unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt) 58 { 59 struct drm_i915_private *i915 = gvt->gt->i915; 60 61 if (IS_BROADWELL(i915)) 62 return D_BDW; 63 else if (IS_SKYLAKE(i915)) 64 return D_SKL; 65 else if (IS_KABYLAKE(i915)) 66 return D_KBL; 67 else if (IS_BROXTON(i915)) 68 return D_BXT; 69 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) 70 return D_CFL; 71 72 return 0; 73 } 74 75 bool intel_gvt_match_device(struct intel_gvt *gvt, 76 unsigned long device) 77 { 78 return intel_gvt_get_device_type(gvt) & device; 79 } 80 81 static void read_vreg(struct intel_vgpu *vgpu, unsigned int offset, 82 void *p_data, unsigned int bytes) 83 { 84 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); 85 } 86 87 static void write_vreg(struct intel_vgpu *vgpu, unsigned int offset, 88 void *p_data, unsigned int bytes) 89 { 90 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes); 91 } 92 93 struct intel_gvt_mmio_info *intel_gvt_find_mmio_info(struct intel_gvt *gvt, 94 unsigned int offset) 95 { 96 struct intel_gvt_mmio_info *e; 97 98 hash_for_each_possible(gvt->mmio.mmio_info_table, e, node, offset) { 99 if (e->offset == offset) 100 return e; 101 } 102 return NULL; 103 } 104 105 static int new_mmio_info(struct intel_gvt *gvt, 106 u32 offset, u16 flags, u32 size, 107 u32 addr_mask, u32 ro_mask, u32 device, 108 gvt_mmio_func read, gvt_mmio_func write) 109 { 110 struct intel_gvt_mmio_info *info, *p; 111 u32 start, end, i; 112 113 if (!intel_gvt_match_device(gvt, device)) 114 return 0; 115 116 if (WARN_ON(!IS_ALIGNED(offset, 4))) 117 return -EINVAL; 118 119 start = offset; 120 end = offset + size; 121 122 for (i = start; i < end; i += 4) { 123 info = kzalloc(sizeof(*info), GFP_KERNEL); 124 if (!info) 125 return -ENOMEM; 126 127 info->offset = i; 128 p = intel_gvt_find_mmio_info(gvt, info->offset); 129 if (p) { 130 WARN(1, "dup mmio definition offset %x\n", 131 info->offset); 132 kfree(info); 133 134 /* We return -EEXIST here to make GVT-g load fail. 135 * So duplicated MMIO can be found as soon as 136 * possible. 137 */ 138 return -EEXIST; 139 } 140 141 info->ro_mask = ro_mask; 142 info->device = device; 143 info->read = read ? read : intel_vgpu_default_mmio_read; 144 info->write = write ? write : intel_vgpu_default_mmio_write; 145 gvt->mmio.mmio_attribute[info->offset / 4] = flags; 146 INIT_HLIST_NODE(&info->node); 147 hash_add(gvt->mmio.mmio_info_table, &info->node, info->offset); 148 gvt->mmio.num_tracked_mmio++; 149 } 150 return 0; 151 } 152 153 /** 154 * intel_gvt_render_mmio_to_engine - convert a mmio offset into the engine 155 * @gvt: a GVT device 156 * @offset: register offset 157 * 158 * Returns: 159 * The engine containing the offset within its mmio page. 160 */ 161 const struct intel_engine_cs * 162 intel_gvt_render_mmio_to_engine(struct intel_gvt *gvt, unsigned int offset) 163 { 164 struct intel_engine_cs *engine; 165 enum intel_engine_id id; 166 167 offset &= ~GENMASK(11, 0); 168 for_each_engine(engine, gvt->gt, id) 169 if (engine->mmio_base == offset) 170 return engine; 171 172 return NULL; 173 } 174 175 #define offset_to_fence_num(offset) \ 176 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3) 177 178 #define fence_num_to_offset(num) \ 179 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) 180 181 182 void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason) 183 { 184 switch (reason) { 185 case GVT_FAILSAFE_UNSUPPORTED_GUEST: 186 pr_err("Detected your guest driver doesn't support GVT-g.\n"); 187 break; 188 case GVT_FAILSAFE_INSUFFICIENT_RESOURCE: 189 pr_err("Graphics resource is not enough for the guest\n"); 190 break; 191 case GVT_FAILSAFE_GUEST_ERR: 192 pr_err("GVT Internal error for the guest\n"); 193 break; 194 default: 195 break; 196 } 197 pr_err("Now vgpu %d will enter failsafe mode.\n", vgpu->id); 198 vgpu->failsafe = true; 199 } 200 201 static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu, 202 unsigned int fence_num, void *p_data, unsigned int bytes) 203 { 204 unsigned int max_fence = vgpu_fence_sz(vgpu); 205 206 if (fence_num >= max_fence) { 207 gvt_vgpu_err("access oob fence reg %d/%d\n", 208 fence_num, max_fence); 209 210 /* When guest access oob fence regs without access 211 * pv_info first, we treat guest not supporting GVT, 212 * and we will let vgpu enter failsafe mode. 213 */ 214 if (!vgpu->pv_notified) 215 enter_failsafe_mode(vgpu, 216 GVT_FAILSAFE_UNSUPPORTED_GUEST); 217 218 memset(p_data, 0, bytes); 219 return -EINVAL; 220 } 221 return 0; 222 } 223 224 static int gamw_echo_dev_rw_ia_write(struct intel_vgpu *vgpu, 225 unsigned int offset, void *p_data, unsigned int bytes) 226 { 227 u32 ips = (*(u32 *)p_data) & GAMW_ECO_ENABLE_64K_IPS_FIELD; 228 229 if (GRAPHICS_VER(vgpu->gvt->gt->i915) <= 10) { 230 if (ips == GAMW_ECO_ENABLE_64K_IPS_FIELD) 231 gvt_dbg_core("vgpu%d: ips enabled\n", vgpu->id); 232 else if (!ips) 233 gvt_dbg_core("vgpu%d: ips disabled\n", vgpu->id); 234 else { 235 /* All engines must be enabled together for vGPU, 236 * since we don't know which engine the ppgtt will 237 * bind to when shadowing. 238 */ 239 gvt_vgpu_err("Unsupported IPS setting %x, cannot enable 64K gtt.\n", 240 ips); 241 return -EINVAL; 242 } 243 } 244 245 write_vreg(vgpu, offset, p_data, bytes); 246 return 0; 247 } 248 249 static int fence_mmio_read(struct intel_vgpu *vgpu, unsigned int off, 250 void *p_data, unsigned int bytes) 251 { 252 int ret; 253 254 ret = sanitize_fence_mmio_access(vgpu, offset_to_fence_num(off), 255 p_data, bytes); 256 if (ret) 257 return ret; 258 read_vreg(vgpu, off, p_data, bytes); 259 return 0; 260 } 261 262 static int fence_mmio_write(struct intel_vgpu *vgpu, unsigned int off, 263 void *p_data, unsigned int bytes) 264 { 265 struct intel_gvt *gvt = vgpu->gvt; 266 unsigned int fence_num = offset_to_fence_num(off); 267 int ret; 268 269 ret = sanitize_fence_mmio_access(vgpu, fence_num, p_data, bytes); 270 if (ret) 271 return ret; 272 write_vreg(vgpu, off, p_data, bytes); 273 274 mmio_hw_access_pre(gvt->gt); 275 intel_vgpu_write_fence(vgpu, fence_num, 276 vgpu_vreg64(vgpu, fence_num_to_offset(fence_num))); 277 mmio_hw_access_post(gvt->gt); 278 return 0; 279 } 280 281 #define CALC_MODE_MASK_REG(old, new) \ 282 (((new) & GENMASK(31, 16)) \ 283 | ((((old) & GENMASK(15, 0)) & ~((new) >> 16)) \ 284 | ((new) & ((new) >> 16)))) 285 286 static int mul_force_wake_write(struct intel_vgpu *vgpu, 287 unsigned int offset, void *p_data, unsigned int bytes) 288 { 289 u32 old, new; 290 u32 ack_reg_offset; 291 292 old = vgpu_vreg(vgpu, offset); 293 new = CALC_MODE_MASK_REG(old, *(u32 *)p_data); 294 295 if (GRAPHICS_VER(vgpu->gvt->gt->i915) >= 9) { 296 switch (offset) { 297 case FORCEWAKE_RENDER_GEN9_REG: 298 ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG; 299 break; 300 case FORCEWAKE_GT_GEN9_REG: 301 ack_reg_offset = FORCEWAKE_ACK_GT_GEN9_REG; 302 break; 303 case FORCEWAKE_MEDIA_GEN9_REG: 304 ack_reg_offset = FORCEWAKE_ACK_MEDIA_GEN9_REG; 305 break; 306 default: 307 /*should not hit here*/ 308 gvt_vgpu_err("invalid forcewake offset 0x%x\n", offset); 309 return -EINVAL; 310 } 311 } else { 312 ack_reg_offset = FORCEWAKE_ACK_HSW_REG; 313 } 314 315 vgpu_vreg(vgpu, offset) = new; 316 vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0)); 317 return 0; 318 } 319 320 static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 321 void *p_data, unsigned int bytes) 322 { 323 intel_engine_mask_t engine_mask = 0; 324 u32 data; 325 326 write_vreg(vgpu, offset, p_data, bytes); 327 data = vgpu_vreg(vgpu, offset); 328 329 if (data & GEN6_GRDOM_FULL) { 330 gvt_dbg_mmio("vgpu%d: request full GPU reset\n", vgpu->id); 331 engine_mask = ALL_ENGINES; 332 } else { 333 if (data & GEN6_GRDOM_RENDER) { 334 gvt_dbg_mmio("vgpu%d: request RCS reset\n", vgpu->id); 335 engine_mask |= BIT(RCS0); 336 } 337 if (data & GEN6_GRDOM_MEDIA) { 338 gvt_dbg_mmio("vgpu%d: request VCS reset\n", vgpu->id); 339 engine_mask |= BIT(VCS0); 340 } 341 if (data & GEN6_GRDOM_BLT) { 342 gvt_dbg_mmio("vgpu%d: request BCS Reset\n", vgpu->id); 343 engine_mask |= BIT(BCS0); 344 } 345 if (data & GEN6_GRDOM_VECS) { 346 gvt_dbg_mmio("vgpu%d: request VECS Reset\n", vgpu->id); 347 engine_mask |= BIT(VECS0); 348 } 349 if (data & GEN8_GRDOM_MEDIA2) { 350 gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id); 351 engine_mask |= BIT(VCS1); 352 } 353 if (data & GEN9_GRDOM_GUC) { 354 gvt_dbg_mmio("vgpu%d: request GUC Reset\n", vgpu->id); 355 vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET; 356 } 357 engine_mask &= vgpu->gvt->gt->info.engine_mask; 358 } 359 360 /* vgpu_lock already hold by emulate mmio r/w */ 361 intel_gvt_reset_vgpu_locked(vgpu, false, engine_mask); 362 363 /* sw will wait for the device to ack the reset request */ 364 vgpu_vreg(vgpu, offset) = 0; 365 366 return 0; 367 } 368 369 static int gmbus_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 370 void *p_data, unsigned int bytes) 371 { 372 return intel_gvt_i2c_handle_gmbus_read(vgpu, offset, p_data, bytes); 373 } 374 375 static int gmbus_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 376 void *p_data, unsigned int bytes) 377 { 378 return intel_gvt_i2c_handle_gmbus_write(vgpu, offset, p_data, bytes); 379 } 380 381 static int pch_pp_control_mmio_write(struct intel_vgpu *vgpu, 382 unsigned int offset, void *p_data, unsigned int bytes) 383 { 384 write_vreg(vgpu, offset, p_data, bytes); 385 386 if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) { 387 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_ON; 388 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE; 389 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN; 390 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE; 391 392 } else 393 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= 394 ~(PP_ON | PP_SEQUENCE_POWER_DOWN 395 | PP_CYCLE_DELAY_ACTIVE); 396 return 0; 397 } 398 399 static int transconf_mmio_write(struct intel_vgpu *vgpu, 400 unsigned int offset, void *p_data, unsigned int bytes) 401 { 402 write_vreg(vgpu, offset, p_data, bytes); 403 404 if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE) 405 vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE; 406 else 407 vgpu_vreg(vgpu, offset) &= ~TRANS_STATE_ENABLE; 408 return 0; 409 } 410 411 static int lcpll_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 412 void *p_data, unsigned int bytes) 413 { 414 write_vreg(vgpu, offset, p_data, bytes); 415 416 if (vgpu_vreg(vgpu, offset) & LCPLL_PLL_DISABLE) 417 vgpu_vreg(vgpu, offset) &= ~LCPLL_PLL_LOCK; 418 else 419 vgpu_vreg(vgpu, offset) |= LCPLL_PLL_LOCK; 420 421 if (vgpu_vreg(vgpu, offset) & LCPLL_CD_SOURCE_FCLK) 422 vgpu_vreg(vgpu, offset) |= LCPLL_CD_SOURCE_FCLK_DONE; 423 else 424 vgpu_vreg(vgpu, offset) &= ~LCPLL_CD_SOURCE_FCLK_DONE; 425 426 return 0; 427 } 428 429 static int dpy_reg_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 430 void *p_data, unsigned int bytes) 431 { 432 switch (offset) { 433 case 0xe651c: 434 case 0xe661c: 435 case 0xe671c: 436 case 0xe681c: 437 vgpu_vreg(vgpu, offset) = 1 << 17; 438 break; 439 case 0xe6c04: 440 vgpu_vreg(vgpu, offset) = 0x3; 441 break; 442 case 0xe6e1c: 443 vgpu_vreg(vgpu, offset) = 0x2f << 16; 444 break; 445 default: 446 return -EINVAL; 447 } 448 449 read_vreg(vgpu, offset, p_data, bytes); 450 return 0; 451 } 452 453 /* 454 * Only PIPE_A is enabled in current vGPU display and PIPE_A is tied to 455 * TRANSCODER_A in HW. DDI/PORT could be PORT_x depends on 456 * setup_virtual_dp_monitor(). 457 * emulate_monitor_status_change() set up PLL for PORT_x as the initial enabled 458 * DPLL. Later guest driver may setup a different DPLLx when setting mode. 459 * So the correct sequence to find DP stream clock is: 460 * Check TRANS_DDI_FUNC_CTL on TRANSCODER_A to get PORT_x. 461 * Check correct PLLx for PORT_x to get PLL frequency and DP bitrate. 462 * Then Refresh rate then can be calculated based on follow equations: 463 * Pixel clock = h_total * v_total * refresh_rate 464 * stream clock = Pixel clock 465 * ls_clk = DP bitrate 466 * Link M/N = strm_clk / ls_clk 467 */ 468 469 static u32 bdw_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port) 470 { 471 u32 dp_br = 0; 472 u32 ddi_pll_sel = vgpu_vreg_t(vgpu, PORT_CLK_SEL(port)); 473 474 switch (ddi_pll_sel) { 475 case PORT_CLK_SEL_LCPLL_2700: 476 dp_br = 270000 * 2; 477 break; 478 case PORT_CLK_SEL_LCPLL_1350: 479 dp_br = 135000 * 2; 480 break; 481 case PORT_CLK_SEL_LCPLL_810: 482 dp_br = 81000 * 2; 483 break; 484 case PORT_CLK_SEL_SPLL: 485 { 486 switch (vgpu_vreg_t(vgpu, SPLL_CTL) & SPLL_FREQ_MASK) { 487 case SPLL_FREQ_810MHz: 488 dp_br = 81000 * 2; 489 break; 490 case SPLL_FREQ_1350MHz: 491 dp_br = 135000 * 2; 492 break; 493 case SPLL_FREQ_2700MHz: 494 dp_br = 270000 * 2; 495 break; 496 default: 497 gvt_dbg_dpy("vgpu-%d PORT_%c can't get freq from SPLL 0x%08x\n", 498 vgpu->id, port_name(port), vgpu_vreg_t(vgpu, SPLL_CTL)); 499 break; 500 } 501 break; 502 } 503 case PORT_CLK_SEL_WRPLL1: 504 case PORT_CLK_SEL_WRPLL2: 505 { 506 u32 wrpll_ctl; 507 int refclk, n, p, r; 508 509 if (ddi_pll_sel == PORT_CLK_SEL_WRPLL1) 510 wrpll_ctl = vgpu_vreg_t(vgpu, WRPLL_CTL(DPLL_ID_WRPLL1)); 511 else 512 wrpll_ctl = vgpu_vreg_t(vgpu, WRPLL_CTL(DPLL_ID_WRPLL2)); 513 514 switch (wrpll_ctl & WRPLL_REF_MASK) { 515 case WRPLL_REF_PCH_SSC: 516 refclk = vgpu->gvt->gt->i915->dpll.ref_clks.ssc; 517 break; 518 case WRPLL_REF_LCPLL: 519 refclk = 2700000; 520 break; 521 default: 522 gvt_dbg_dpy("vgpu-%d PORT_%c WRPLL can't get refclk 0x%08x\n", 523 vgpu->id, port_name(port), wrpll_ctl); 524 goto out; 525 } 526 527 r = wrpll_ctl & WRPLL_DIVIDER_REF_MASK; 528 p = (wrpll_ctl & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT; 529 n = (wrpll_ctl & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT; 530 531 dp_br = (refclk * n / 10) / (p * r) * 2; 532 break; 533 } 534 default: 535 gvt_dbg_dpy("vgpu-%d PORT_%c has invalid clock select 0x%08x\n", 536 vgpu->id, port_name(port), vgpu_vreg_t(vgpu, PORT_CLK_SEL(port))); 537 break; 538 } 539 540 out: 541 return dp_br; 542 } 543 544 static u32 bxt_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port) 545 { 546 u32 dp_br = 0; 547 int refclk = vgpu->gvt->gt->i915->dpll.ref_clks.nssc; 548 enum dpio_phy phy = DPIO_PHY0; 549 enum dpio_channel ch = DPIO_CH0; 550 struct dpll clock = {0}; 551 u32 temp; 552 553 /* Port to PHY mapping is fixed, see bxt_ddi_phy_info{} */ 554 switch (port) { 555 case PORT_A: 556 phy = DPIO_PHY1; 557 ch = DPIO_CH0; 558 break; 559 case PORT_B: 560 phy = DPIO_PHY0; 561 ch = DPIO_CH0; 562 break; 563 case PORT_C: 564 phy = DPIO_PHY0; 565 ch = DPIO_CH1; 566 break; 567 default: 568 gvt_dbg_dpy("vgpu-%d no PHY for PORT_%c\n", vgpu->id, port_name(port)); 569 goto out; 570 } 571 572 temp = vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(port)); 573 if (!(temp & PORT_PLL_ENABLE) || !(temp & PORT_PLL_LOCK)) { 574 gvt_dbg_dpy("vgpu-%d PORT_%c PLL_ENABLE 0x%08x isn't enabled or locked\n", 575 vgpu->id, port_name(port), temp); 576 goto out; 577 } 578 579 clock.m1 = 2; 580 clock.m2 = REG_FIELD_GET(PORT_PLL_M2_INT_MASK, 581 vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 0))) << 22; 582 if (vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 3)) & PORT_PLL_M2_FRAC_ENABLE) 583 clock.m2 |= REG_FIELD_GET(PORT_PLL_M2_FRAC_MASK, 584 vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 2))); 585 clock.n = REG_FIELD_GET(PORT_PLL_N_MASK, 586 vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 1))); 587 clock.p1 = REG_FIELD_GET(PORT_PLL_P1_MASK, 588 vgpu_vreg_t(vgpu, BXT_PORT_PLL_EBB_0(phy, ch))); 589 clock.p2 = REG_FIELD_GET(PORT_PLL_P2_MASK, 590 vgpu_vreg_t(vgpu, BXT_PORT_PLL_EBB_0(phy, ch))); 591 clock.m = clock.m1 * clock.m2; 592 clock.p = clock.p1 * clock.p2 * 5; 593 594 if (clock.n == 0 || clock.p == 0) { 595 gvt_dbg_dpy("vgpu-%d PORT_%c PLL has invalid divider\n", vgpu->id, port_name(port)); 596 goto out; 597 } 598 599 clock.vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock.m), clock.n << 22); 600 clock.dot = DIV_ROUND_CLOSEST(clock.vco, clock.p); 601 602 dp_br = clock.dot; 603 604 out: 605 return dp_br; 606 } 607 608 static u32 skl_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port) 609 { 610 u32 dp_br = 0; 611 enum intel_dpll_id dpll_id = DPLL_ID_SKL_DPLL0; 612 613 /* Find the enabled DPLL for the DDI/PORT */ 614 if (!(vgpu_vreg_t(vgpu, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)) && 615 (vgpu_vreg_t(vgpu, DPLL_CTRL2) & DPLL_CTRL2_DDI_SEL_OVERRIDE(port))) { 616 dpll_id += (vgpu_vreg_t(vgpu, DPLL_CTRL2) & 617 DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> 618 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); 619 } else { 620 gvt_dbg_dpy("vgpu-%d DPLL for PORT_%c isn't turned on\n", 621 vgpu->id, port_name(port)); 622 return dp_br; 623 } 624 625 /* Find PLL output frequency from correct DPLL, and get bir rate */ 626 switch ((vgpu_vreg_t(vgpu, DPLL_CTRL1) & 627 DPLL_CTRL1_LINK_RATE_MASK(dpll_id)) >> 628 DPLL_CTRL1_LINK_RATE_SHIFT(dpll_id)) { 629 case DPLL_CTRL1_LINK_RATE_810: 630 dp_br = 81000 * 2; 631 break; 632 case DPLL_CTRL1_LINK_RATE_1080: 633 dp_br = 108000 * 2; 634 break; 635 case DPLL_CTRL1_LINK_RATE_1350: 636 dp_br = 135000 * 2; 637 break; 638 case DPLL_CTRL1_LINK_RATE_1620: 639 dp_br = 162000 * 2; 640 break; 641 case DPLL_CTRL1_LINK_RATE_2160: 642 dp_br = 216000 * 2; 643 break; 644 case DPLL_CTRL1_LINK_RATE_2700: 645 dp_br = 270000 * 2; 646 break; 647 default: 648 dp_br = 0; 649 gvt_dbg_dpy("vgpu-%d PORT_%c fail to get DPLL-%d freq\n", 650 vgpu->id, port_name(port), dpll_id); 651 } 652 653 return dp_br; 654 } 655 656 static void vgpu_update_refresh_rate(struct intel_vgpu *vgpu) 657 { 658 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 659 enum port port; 660 u32 dp_br, link_m, link_n, htotal, vtotal; 661 662 /* Find DDI/PORT assigned to TRANSCODER_A, expect B or D */ 663 port = (vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) & 664 TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; 665 if (port != PORT_B && port != PORT_D) { 666 gvt_dbg_dpy("vgpu-%d unsupported PORT_%c\n", vgpu->id, port_name(port)); 667 return; 668 } 669 670 /* Calculate DP bitrate from PLL */ 671 if (IS_BROADWELL(dev_priv)) 672 dp_br = bdw_vgpu_get_dp_bitrate(vgpu, port); 673 else if (IS_BROXTON(dev_priv)) 674 dp_br = bxt_vgpu_get_dp_bitrate(vgpu, port); 675 else 676 dp_br = skl_vgpu_get_dp_bitrate(vgpu, port); 677 678 /* Get DP link symbol clock M/N */ 679 link_m = vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)); 680 link_n = vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)); 681 682 /* Get H/V total from transcoder timing */ 683 htotal = (vgpu_vreg_t(vgpu, HTOTAL(TRANSCODER_A)) >> TRANS_HTOTAL_SHIFT); 684 vtotal = (vgpu_vreg_t(vgpu, VTOTAL(TRANSCODER_A)) >> TRANS_VTOTAL_SHIFT); 685 686 if (dp_br && link_n && htotal && vtotal) { 687 u64 pixel_clk = 0; 688 u32 new_rate = 0; 689 u32 *old_rate = &(intel_vgpu_port(vgpu, vgpu->display.port_num)->vrefresh_k); 690 691 /* Calcuate pixel clock by (ls_clk * M / N) */ 692 pixel_clk = div_u64(mul_u32_u32(link_m, dp_br), link_n); 693 pixel_clk *= MSEC_PER_SEC; 694 695 /* Calcuate refresh rate by (pixel_clk / (h_total * v_total)) */ 696 new_rate = DIV64_U64_ROUND_CLOSEST(mul_u64_u32_shr(pixel_clk, MSEC_PER_SEC, 0), mul_u32_u32(htotal + 1, vtotal + 1)); 697 698 if (*old_rate != new_rate) 699 *old_rate = new_rate; 700 701 gvt_dbg_dpy("vgpu-%d PIPE_%c refresh rate updated to %d\n", 702 vgpu->id, pipe_name(PIPE_A), new_rate); 703 } 704 } 705 706 static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 707 void *p_data, unsigned int bytes) 708 { 709 u32 data; 710 711 write_vreg(vgpu, offset, p_data, bytes); 712 data = vgpu_vreg(vgpu, offset); 713 714 if (data & PIPECONF_ENABLE) { 715 vgpu_vreg(vgpu, offset) |= PIPECONF_STATE_ENABLE; 716 vgpu_update_refresh_rate(vgpu); 717 vgpu_update_vblank_emulation(vgpu, true); 718 } else { 719 vgpu_vreg(vgpu, offset) &= ~PIPECONF_STATE_ENABLE; 720 vgpu_update_vblank_emulation(vgpu, false); 721 } 722 return 0; 723 } 724 725 /* sorted in ascending order */ 726 static i915_reg_t force_nonpriv_white_list[] = { 727 _MMIO(0xd80), 728 GEN9_CS_DEBUG_MODE1, //_MMIO(0x20ec) 729 GEN9_CTX_PREEMPT_REG,//_MMIO(0x2248) 730 CL_PRIMITIVES_COUNT, //_MMIO(0x2340) 731 PS_INVOCATION_COUNT, //_MMIO(0x2348) 732 PS_DEPTH_COUNT, //_MMIO(0x2350) 733 GEN8_CS_CHICKEN1,//_MMIO(0x2580) 734 _MMIO(0x2690), 735 _MMIO(0x2694), 736 _MMIO(0x2698), 737 _MMIO(0x2754), 738 _MMIO(0x28a0), 739 _MMIO(0x4de0), 740 _MMIO(0x4de4), 741 _MMIO(0x4dfc), 742 GEN7_COMMON_SLICE_CHICKEN1,//_MMIO(0x7010) 743 _MMIO(0x7014), 744 HDC_CHICKEN0,//_MMIO(0x7300) 745 GEN8_HDC_CHICKEN1,//_MMIO(0x7304) 746 _MMIO(0x7700), 747 _MMIO(0x7704), 748 _MMIO(0x7708), 749 _MMIO(0x770c), 750 _MMIO(0x83a8), 751 _MMIO(0xb110), 752 GEN8_L3SQCREG4,//_MMIO(0xb118) 753 _MMIO(0xe100), 754 _MMIO(0xe18c), 755 _MMIO(0xe48c), 756 _MMIO(0xe5f4), 757 _MMIO(0x64844), 758 }; 759 760 /* a simple bsearch */ 761 static inline bool in_whitelist(u32 reg) 762 { 763 int left = 0, right = ARRAY_SIZE(force_nonpriv_white_list); 764 i915_reg_t *array = force_nonpriv_white_list; 765 766 while (left < right) { 767 int mid = (left + right)/2; 768 769 if (reg > array[mid].reg) 770 left = mid + 1; 771 else if (reg < array[mid].reg) 772 right = mid; 773 else 774 return true; 775 } 776 return false; 777 } 778 779 static int force_nonpriv_write(struct intel_vgpu *vgpu, 780 unsigned int offset, void *p_data, unsigned int bytes) 781 { 782 u32 reg_nonpriv = (*(u32 *)p_data) & REG_GENMASK(25, 2); 783 const struct intel_engine_cs *engine = 784 intel_gvt_render_mmio_to_engine(vgpu->gvt, offset); 785 786 if (bytes != 4 || !IS_ALIGNED(offset, bytes) || !engine) { 787 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV offset %x(%dB)\n", 788 vgpu->id, offset, bytes); 789 return -EINVAL; 790 } 791 792 if (!in_whitelist(reg_nonpriv) && 793 reg_nonpriv != i915_mmio_reg_offset(RING_NOPID(engine->mmio_base))) { 794 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x at offset %x\n", 795 vgpu->id, reg_nonpriv, offset); 796 } else 797 intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes); 798 799 return 0; 800 } 801 802 static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 803 void *p_data, unsigned int bytes) 804 { 805 write_vreg(vgpu, offset, p_data, bytes); 806 807 if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) { 808 vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE; 809 } else { 810 vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE; 811 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E))) 812 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) 813 &= ~DP_TP_STATUS_AUTOTRAIN_DONE; 814 } 815 return 0; 816 } 817 818 static int fdi_rx_iir_mmio_write(struct intel_vgpu *vgpu, 819 unsigned int offset, void *p_data, unsigned int bytes) 820 { 821 vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data; 822 return 0; 823 } 824 825 #define FDI_LINK_TRAIN_PATTERN1 0 826 #define FDI_LINK_TRAIN_PATTERN2 1 827 828 static int fdi_auto_training_started(struct intel_vgpu *vgpu) 829 { 830 u32 ddi_buf_ctl = vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_E)); 831 u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL); 832 u32 tx_ctl = vgpu_vreg_t(vgpu, DP_TP_CTL(PORT_E)); 833 834 if ((ddi_buf_ctl & DDI_BUF_CTL_ENABLE) && 835 (rx_ctl & FDI_RX_ENABLE) && 836 (rx_ctl & FDI_AUTO_TRAINING) && 837 (tx_ctl & DP_TP_CTL_ENABLE) && 838 (tx_ctl & DP_TP_CTL_FDI_AUTOTRAIN)) 839 return 1; 840 else 841 return 0; 842 } 843 844 static int check_fdi_rx_train_status(struct intel_vgpu *vgpu, 845 enum pipe pipe, unsigned int train_pattern) 846 { 847 i915_reg_t fdi_rx_imr, fdi_tx_ctl, fdi_rx_ctl; 848 unsigned int fdi_rx_check_bits, fdi_tx_check_bits; 849 unsigned int fdi_rx_train_bits, fdi_tx_train_bits; 850 unsigned int fdi_iir_check_bits; 851 852 fdi_rx_imr = FDI_RX_IMR(pipe); 853 fdi_tx_ctl = FDI_TX_CTL(pipe); 854 fdi_rx_ctl = FDI_RX_CTL(pipe); 855 856 if (train_pattern == FDI_LINK_TRAIN_PATTERN1) { 857 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_1_CPT; 858 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_1; 859 fdi_iir_check_bits = FDI_RX_BIT_LOCK; 860 } else if (train_pattern == FDI_LINK_TRAIN_PATTERN2) { 861 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_2_CPT; 862 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_2; 863 fdi_iir_check_bits = FDI_RX_SYMBOL_LOCK; 864 } else { 865 gvt_vgpu_err("Invalid train pattern %d\n", train_pattern); 866 return -EINVAL; 867 } 868 869 fdi_rx_check_bits = FDI_RX_ENABLE | fdi_rx_train_bits; 870 fdi_tx_check_bits = FDI_TX_ENABLE | fdi_tx_train_bits; 871 872 /* If imr bit has been masked */ 873 if (vgpu_vreg_t(vgpu, fdi_rx_imr) & fdi_iir_check_bits) 874 return 0; 875 876 if (((vgpu_vreg_t(vgpu, fdi_tx_ctl) & fdi_tx_check_bits) 877 == fdi_tx_check_bits) 878 && ((vgpu_vreg_t(vgpu, fdi_rx_ctl) & fdi_rx_check_bits) 879 == fdi_rx_check_bits)) 880 return 1; 881 else 882 return 0; 883 } 884 885 #define INVALID_INDEX (~0U) 886 887 static unsigned int calc_index(unsigned int offset, unsigned int start, 888 unsigned int next, unsigned int end, i915_reg_t i915_end) 889 { 890 unsigned int range = next - start; 891 892 if (!end) 893 end = i915_mmio_reg_offset(i915_end); 894 if (offset < start || offset > end) 895 return INVALID_INDEX; 896 offset -= start; 897 return offset / range; 898 } 899 900 #define FDI_RX_CTL_TO_PIPE(offset) \ 901 calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, 0, FDI_RX_CTL(PIPE_C)) 902 903 #define FDI_TX_CTL_TO_PIPE(offset) \ 904 calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, 0, FDI_TX_CTL(PIPE_C)) 905 906 #define FDI_RX_IMR_TO_PIPE(offset) \ 907 calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, 0, FDI_RX_IMR(PIPE_C)) 908 909 static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu, 910 unsigned int offset, void *p_data, unsigned int bytes) 911 { 912 i915_reg_t fdi_rx_iir; 913 unsigned int index; 914 int ret; 915 916 if (FDI_RX_CTL_TO_PIPE(offset) != INVALID_INDEX) 917 index = FDI_RX_CTL_TO_PIPE(offset); 918 else if (FDI_TX_CTL_TO_PIPE(offset) != INVALID_INDEX) 919 index = FDI_TX_CTL_TO_PIPE(offset); 920 else if (FDI_RX_IMR_TO_PIPE(offset) != INVALID_INDEX) 921 index = FDI_RX_IMR_TO_PIPE(offset); 922 else { 923 gvt_vgpu_err("Unsupport registers %x\n", offset); 924 return -EINVAL; 925 } 926 927 write_vreg(vgpu, offset, p_data, bytes); 928 929 fdi_rx_iir = FDI_RX_IIR(index); 930 931 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN1); 932 if (ret < 0) 933 return ret; 934 if (ret) 935 vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK; 936 937 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN2); 938 if (ret < 0) 939 return ret; 940 if (ret) 941 vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK; 942 943 if (offset == _FDI_RXA_CTL) 944 if (fdi_auto_training_started(vgpu)) 945 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) |= 946 DP_TP_STATUS_AUTOTRAIN_DONE; 947 return 0; 948 } 949 950 #define DP_TP_CTL_TO_PORT(offset) \ 951 calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, 0, DP_TP_CTL(PORT_E)) 952 953 static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 954 void *p_data, unsigned int bytes) 955 { 956 i915_reg_t status_reg; 957 unsigned int index; 958 u32 data; 959 960 write_vreg(vgpu, offset, p_data, bytes); 961 962 index = DP_TP_CTL_TO_PORT(offset); 963 data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8; 964 if (data == 0x2) { 965 status_reg = DP_TP_STATUS(index); 966 vgpu_vreg_t(vgpu, status_reg) |= (1 << 25); 967 } 968 return 0; 969 } 970 971 static int dp_tp_status_mmio_write(struct intel_vgpu *vgpu, 972 unsigned int offset, void *p_data, unsigned int bytes) 973 { 974 u32 reg_val; 975 u32 sticky_mask; 976 977 reg_val = *((u32 *)p_data); 978 sticky_mask = GENMASK(27, 26) | (1 << 24); 979 980 vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) | 981 (vgpu_vreg(vgpu, offset) & sticky_mask); 982 vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask); 983 return 0; 984 } 985 986 static int pch_adpa_mmio_write(struct intel_vgpu *vgpu, 987 unsigned int offset, void *p_data, unsigned int bytes) 988 { 989 u32 data; 990 991 write_vreg(vgpu, offset, p_data, bytes); 992 data = vgpu_vreg(vgpu, offset); 993 994 if (data & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) 995 vgpu_vreg(vgpu, offset) &= ~ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 996 return 0; 997 } 998 999 static int south_chicken2_mmio_write(struct intel_vgpu *vgpu, 1000 unsigned int offset, void *p_data, unsigned int bytes) 1001 { 1002 u32 data; 1003 1004 write_vreg(vgpu, offset, p_data, bytes); 1005 data = vgpu_vreg(vgpu, offset); 1006 1007 if (data & FDI_MPHY_IOSFSB_RESET_CTL) 1008 vgpu_vreg(vgpu, offset) |= FDI_MPHY_IOSFSB_RESET_STATUS; 1009 else 1010 vgpu_vreg(vgpu, offset) &= ~FDI_MPHY_IOSFSB_RESET_STATUS; 1011 return 0; 1012 } 1013 1014 #define DSPSURF_TO_PIPE(offset) \ 1015 calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C)) 1016 1017 static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1018 void *p_data, unsigned int bytes) 1019 { 1020 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 1021 u32 pipe = DSPSURF_TO_PIPE(offset); 1022 int event = SKL_FLIP_EVENT(pipe, PLANE_PRIMARY); 1023 1024 write_vreg(vgpu, offset, p_data, bytes); 1025 vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); 1026 1027 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++; 1028 1029 if (vgpu_vreg_t(vgpu, DSPCNTR(pipe)) & PLANE_CTL_ASYNC_FLIP) 1030 intel_vgpu_trigger_virtual_event(vgpu, event); 1031 else 1032 set_bit(event, vgpu->irq.flip_done_event[pipe]); 1033 1034 return 0; 1035 } 1036 1037 #define SPRSURF_TO_PIPE(offset) \ 1038 calc_index(offset, _SPRA_SURF, _SPRB_SURF, 0, SPRSURF(PIPE_C)) 1039 1040 static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1041 void *p_data, unsigned int bytes) 1042 { 1043 u32 pipe = SPRSURF_TO_PIPE(offset); 1044 int event = SKL_FLIP_EVENT(pipe, PLANE_SPRITE0); 1045 1046 write_vreg(vgpu, offset, p_data, bytes); 1047 vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); 1048 1049 if (vgpu_vreg_t(vgpu, SPRCTL(pipe)) & PLANE_CTL_ASYNC_FLIP) 1050 intel_vgpu_trigger_virtual_event(vgpu, event); 1051 else 1052 set_bit(event, vgpu->irq.flip_done_event[pipe]); 1053 1054 return 0; 1055 } 1056 1057 static int reg50080_mmio_write(struct intel_vgpu *vgpu, 1058 unsigned int offset, void *p_data, 1059 unsigned int bytes) 1060 { 1061 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 1062 enum pipe pipe = REG_50080_TO_PIPE(offset); 1063 enum plane_id plane = REG_50080_TO_PLANE(offset); 1064 int event = SKL_FLIP_EVENT(pipe, plane); 1065 1066 write_vreg(vgpu, offset, p_data, bytes); 1067 if (plane == PLANE_PRIMARY) { 1068 vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); 1069 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++; 1070 } else { 1071 vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); 1072 } 1073 1074 if ((vgpu_vreg(vgpu, offset) & REG50080_FLIP_TYPE_MASK) == REG50080_FLIP_TYPE_ASYNC) 1075 intel_vgpu_trigger_virtual_event(vgpu, event); 1076 else 1077 set_bit(event, vgpu->irq.flip_done_event[pipe]); 1078 1079 return 0; 1080 } 1081 1082 static int trigger_aux_channel_interrupt(struct intel_vgpu *vgpu, 1083 unsigned int reg) 1084 { 1085 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 1086 enum intel_gvt_event_type event; 1087 1088 if (reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_A))) 1089 event = AUX_CHANNEL_A; 1090 else if (reg == _PCH_DPB_AUX_CH_CTL || 1091 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_B))) 1092 event = AUX_CHANNEL_B; 1093 else if (reg == _PCH_DPC_AUX_CH_CTL || 1094 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_C))) 1095 event = AUX_CHANNEL_C; 1096 else if (reg == _PCH_DPD_AUX_CH_CTL || 1097 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_D))) 1098 event = AUX_CHANNEL_D; 1099 else { 1100 drm_WARN_ON(&dev_priv->drm, true); 1101 return -EINVAL; 1102 } 1103 1104 intel_vgpu_trigger_virtual_event(vgpu, event); 1105 return 0; 1106 } 1107 1108 static int dp_aux_ch_ctl_trans_done(struct intel_vgpu *vgpu, u32 value, 1109 unsigned int reg, int len, bool data_valid) 1110 { 1111 /* mark transaction done */ 1112 value |= DP_AUX_CH_CTL_DONE; 1113 value &= ~DP_AUX_CH_CTL_SEND_BUSY; 1114 value &= ~DP_AUX_CH_CTL_RECEIVE_ERROR; 1115 1116 if (data_valid) 1117 value &= ~DP_AUX_CH_CTL_TIME_OUT_ERROR; 1118 else 1119 value |= DP_AUX_CH_CTL_TIME_OUT_ERROR; 1120 1121 /* message size */ 1122 value &= ~(0xf << 20); 1123 value |= (len << 20); 1124 vgpu_vreg(vgpu, reg) = value; 1125 1126 if (value & DP_AUX_CH_CTL_INTERRUPT) 1127 return trigger_aux_channel_interrupt(vgpu, reg); 1128 return 0; 1129 } 1130 1131 static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd, 1132 u8 t) 1133 { 1134 if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == DPCD_TRAINING_PATTERN_1) { 1135 /* training pattern 1 for CR */ 1136 /* set LANE0_CR_DONE, LANE1_CR_DONE */ 1137 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_CR_DONE; 1138 /* set LANE2_CR_DONE, LANE3_CR_DONE */ 1139 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_CR_DONE; 1140 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == 1141 DPCD_TRAINING_PATTERN_2) { 1142 /* training pattern 2 for EQ */ 1143 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane0_1 */ 1144 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_EQ_DONE; 1145 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_SYMBOL_LOCKED; 1146 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane2_3 */ 1147 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_EQ_DONE; 1148 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_SYMBOL_LOCKED; 1149 /* set INTERLANE_ALIGN_DONE */ 1150 dpcd->data[DPCD_LANE_ALIGN_STATUS_UPDATED] |= 1151 DPCD_INTERLANE_ALIGN_DONE; 1152 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == 1153 DPCD_LINK_TRAINING_DISABLED) { 1154 /* finish link training */ 1155 /* set sink status as synchronized */ 1156 dpcd->data[DPCD_SINK_STATUS] = DPCD_SINK_IN_SYNC; 1157 } 1158 } 1159 1160 #define _REG_HSW_DP_AUX_CH_CTL(dp) \ 1161 ((dp) ? (_PCH_DPB_AUX_CH_CTL + ((dp)-1)*0x100) : 0x64010) 1162 1163 #define _REG_SKL_DP_AUX_CH_CTL(dp) (0x64010 + (dp) * 0x100) 1164 1165 #define OFFSET_TO_DP_AUX_PORT(offset) (((offset) & 0xF00) >> 8) 1166 1167 #define dpy_is_valid_port(port) \ 1168 (((port) >= PORT_A) && ((port) < I915_MAX_PORTS)) 1169 1170 static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu, 1171 unsigned int offset, void *p_data, unsigned int bytes) 1172 { 1173 struct intel_vgpu_display *display = &vgpu->display; 1174 int msg, addr, ctrl, op, len; 1175 int port_index = OFFSET_TO_DP_AUX_PORT(offset); 1176 struct intel_vgpu_dpcd_data *dpcd = NULL; 1177 struct intel_vgpu_port *port = NULL; 1178 u32 data; 1179 1180 if (!dpy_is_valid_port(port_index)) { 1181 gvt_vgpu_err("Unsupported DP port access!\n"); 1182 return 0; 1183 } 1184 1185 write_vreg(vgpu, offset, p_data, bytes); 1186 data = vgpu_vreg(vgpu, offset); 1187 1188 if ((GRAPHICS_VER(vgpu->gvt->gt->i915) >= 9) 1189 && offset != _REG_SKL_DP_AUX_CH_CTL(port_index)) { 1190 /* SKL DPB/C/D aux ctl register changed */ 1191 return 0; 1192 } else if (IS_BROADWELL(vgpu->gvt->gt->i915) && 1193 offset != _REG_HSW_DP_AUX_CH_CTL(port_index)) { 1194 /* write to the data registers */ 1195 return 0; 1196 } 1197 1198 if (!(data & DP_AUX_CH_CTL_SEND_BUSY)) { 1199 /* just want to clear the sticky bits */ 1200 vgpu_vreg(vgpu, offset) = 0; 1201 return 0; 1202 } 1203 1204 port = &display->ports[port_index]; 1205 dpcd = port->dpcd; 1206 1207 /* read out message from DATA1 register */ 1208 msg = vgpu_vreg(vgpu, offset + 4); 1209 addr = (msg >> 8) & 0xffff; 1210 ctrl = (msg >> 24) & 0xff; 1211 len = msg & 0xff; 1212 op = ctrl >> 4; 1213 1214 if (op == GVT_AUX_NATIVE_WRITE) { 1215 int t; 1216 u8 buf[16]; 1217 1218 if ((addr + len + 1) >= DPCD_SIZE) { 1219 /* 1220 * Write request exceeds what we supported, 1221 * DCPD spec: When a Source Device is writing a DPCD 1222 * address not supported by the Sink Device, the Sink 1223 * Device shall reply with AUX NACK and “M” equal to 1224 * zero. 1225 */ 1226 1227 /* NAK the write */ 1228 vgpu_vreg(vgpu, offset + 4) = AUX_NATIVE_REPLY_NAK; 1229 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 2, true); 1230 return 0; 1231 } 1232 1233 /* 1234 * Write request format: Headr (command + address + size) occupies 1235 * 4 bytes, followed by (len + 1) bytes of data. See details at 1236 * intel_dp_aux_transfer(). 1237 */ 1238 if ((len + 1 + 4) > AUX_BURST_SIZE) { 1239 gvt_vgpu_err("dp_aux_header: len %d is too large\n", len); 1240 return -EINVAL; 1241 } 1242 1243 /* unpack data from vreg to buf */ 1244 for (t = 0; t < 4; t++) { 1245 u32 r = vgpu_vreg(vgpu, offset + 8 + t * 4); 1246 1247 buf[t * 4] = (r >> 24) & 0xff; 1248 buf[t * 4 + 1] = (r >> 16) & 0xff; 1249 buf[t * 4 + 2] = (r >> 8) & 0xff; 1250 buf[t * 4 + 3] = r & 0xff; 1251 } 1252 1253 /* write to virtual DPCD */ 1254 if (dpcd && dpcd->data_valid) { 1255 for (t = 0; t <= len; t++) { 1256 int p = addr + t; 1257 1258 dpcd->data[p] = buf[t]; 1259 /* check for link training */ 1260 if (p == DPCD_TRAINING_PATTERN_SET) 1261 dp_aux_ch_ctl_link_training(dpcd, 1262 buf[t]); 1263 } 1264 } 1265 1266 /* ACK the write */ 1267 vgpu_vreg(vgpu, offset + 4) = 0; 1268 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 1, 1269 dpcd && dpcd->data_valid); 1270 return 0; 1271 } 1272 1273 if (op == GVT_AUX_NATIVE_READ) { 1274 int idx, i, ret = 0; 1275 1276 if ((addr + len + 1) >= DPCD_SIZE) { 1277 /* 1278 * read request exceeds what we supported 1279 * DPCD spec: A Sink Device receiving a Native AUX CH 1280 * read request for an unsupported DPCD address must 1281 * reply with an AUX ACK and read data set equal to 1282 * zero instead of replying with AUX NACK. 1283 */ 1284 1285 /* ACK the READ*/ 1286 vgpu_vreg(vgpu, offset + 4) = 0; 1287 vgpu_vreg(vgpu, offset + 8) = 0; 1288 vgpu_vreg(vgpu, offset + 12) = 0; 1289 vgpu_vreg(vgpu, offset + 16) = 0; 1290 vgpu_vreg(vgpu, offset + 20) = 0; 1291 1292 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2, 1293 true); 1294 return 0; 1295 } 1296 1297 for (idx = 1; idx <= 5; idx++) { 1298 /* clear the data registers */ 1299 vgpu_vreg(vgpu, offset + 4 * idx) = 0; 1300 } 1301 1302 /* 1303 * Read reply format: ACK (1 byte) plus (len + 1) bytes of data. 1304 */ 1305 if ((len + 2) > AUX_BURST_SIZE) { 1306 gvt_vgpu_err("dp_aux_header: len %d is too large\n", len); 1307 return -EINVAL; 1308 } 1309 1310 /* read from virtual DPCD to vreg */ 1311 /* first 4 bytes: [ACK][addr][addr+1][addr+2] */ 1312 if (dpcd && dpcd->data_valid) { 1313 for (i = 1; i <= (len + 1); i++) { 1314 int t; 1315 1316 t = dpcd->data[addr + i - 1]; 1317 t <<= (24 - 8 * (i % 4)); 1318 ret |= t; 1319 1320 if ((i % 4 == 3) || (i == (len + 1))) { 1321 vgpu_vreg(vgpu, offset + 1322 (i / 4 + 1) * 4) = ret; 1323 ret = 0; 1324 } 1325 } 1326 } 1327 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2, 1328 dpcd && dpcd->data_valid); 1329 return 0; 1330 } 1331 1332 /* i2c transaction starts */ 1333 intel_gvt_i2c_handle_aux_ch_write(vgpu, port_index, offset, p_data); 1334 1335 if (data & DP_AUX_CH_CTL_INTERRUPT) 1336 trigger_aux_channel_interrupt(vgpu, offset); 1337 return 0; 1338 } 1339 1340 static int mbctl_write(struct intel_vgpu *vgpu, unsigned int offset, 1341 void *p_data, unsigned int bytes) 1342 { 1343 *(u32 *)p_data &= (~GEN6_MBCTL_ENABLE_BOOT_FETCH); 1344 write_vreg(vgpu, offset, p_data, bytes); 1345 return 0; 1346 } 1347 1348 static int vga_control_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1349 void *p_data, unsigned int bytes) 1350 { 1351 bool vga_disable; 1352 1353 write_vreg(vgpu, offset, p_data, bytes); 1354 vga_disable = vgpu_vreg(vgpu, offset) & VGA_DISP_DISABLE; 1355 1356 gvt_dbg_core("vgpu%d: %s VGA mode\n", vgpu->id, 1357 vga_disable ? "Disable" : "Enable"); 1358 return 0; 1359 } 1360 1361 static u32 read_virtual_sbi_register(struct intel_vgpu *vgpu, 1362 unsigned int sbi_offset) 1363 { 1364 struct intel_vgpu_display *display = &vgpu->display; 1365 int num = display->sbi.number; 1366 int i; 1367 1368 for (i = 0; i < num; ++i) 1369 if (display->sbi.registers[i].offset == sbi_offset) 1370 break; 1371 1372 if (i == num) 1373 return 0; 1374 1375 return display->sbi.registers[i].value; 1376 } 1377 1378 static void write_virtual_sbi_register(struct intel_vgpu *vgpu, 1379 unsigned int offset, u32 value) 1380 { 1381 struct intel_vgpu_display *display = &vgpu->display; 1382 int num = display->sbi.number; 1383 int i; 1384 1385 for (i = 0; i < num; ++i) { 1386 if (display->sbi.registers[i].offset == offset) 1387 break; 1388 } 1389 1390 if (i == num) { 1391 if (num == SBI_REG_MAX) { 1392 gvt_vgpu_err("SBI caching meets maximum limits\n"); 1393 return; 1394 } 1395 display->sbi.number++; 1396 } 1397 1398 display->sbi.registers[i].offset = offset; 1399 display->sbi.registers[i].value = value; 1400 } 1401 1402 static int sbi_data_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 1403 void *p_data, unsigned int bytes) 1404 { 1405 if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> 1406 SBI_OPCODE_SHIFT) == SBI_CMD_CRRD) { 1407 unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) & 1408 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; 1409 vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu, 1410 sbi_offset); 1411 } 1412 read_vreg(vgpu, offset, p_data, bytes); 1413 return 0; 1414 } 1415 1416 static int sbi_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1417 void *p_data, unsigned int bytes) 1418 { 1419 u32 data; 1420 1421 write_vreg(vgpu, offset, p_data, bytes); 1422 data = vgpu_vreg(vgpu, offset); 1423 1424 data &= ~(SBI_STAT_MASK << SBI_STAT_SHIFT); 1425 data |= SBI_READY; 1426 1427 data &= ~(SBI_RESPONSE_MASK << SBI_RESPONSE_SHIFT); 1428 data |= SBI_RESPONSE_SUCCESS; 1429 1430 vgpu_vreg(vgpu, offset) = data; 1431 1432 if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> 1433 SBI_OPCODE_SHIFT) == SBI_CMD_CRWR) { 1434 unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) & 1435 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; 1436 1437 write_virtual_sbi_register(vgpu, sbi_offset, 1438 vgpu_vreg_t(vgpu, SBI_DATA)); 1439 } 1440 return 0; 1441 } 1442 1443 #define _vgtif_reg(x) \ 1444 (VGT_PVINFO_PAGE + offsetof(struct vgt_if, x)) 1445 1446 static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 1447 void *p_data, unsigned int bytes) 1448 { 1449 bool invalid_read = false; 1450 1451 read_vreg(vgpu, offset, p_data, bytes); 1452 1453 switch (offset) { 1454 case _vgtif_reg(magic) ... _vgtif_reg(vgt_id): 1455 if (offset + bytes > _vgtif_reg(vgt_id) + 4) 1456 invalid_read = true; 1457 break; 1458 case _vgtif_reg(avail_rs.mappable_gmadr.base) ... 1459 _vgtif_reg(avail_rs.fence_num): 1460 if (offset + bytes > 1461 _vgtif_reg(avail_rs.fence_num) + 4) 1462 invalid_read = true; 1463 break; 1464 case 0x78010: /* vgt_caps */ 1465 case 0x7881c: 1466 break; 1467 default: 1468 invalid_read = true; 1469 break; 1470 } 1471 if (invalid_read) 1472 gvt_vgpu_err("invalid pvinfo read: [%x:%x] = %x\n", 1473 offset, bytes, *(u32 *)p_data); 1474 vgpu->pv_notified = true; 1475 return 0; 1476 } 1477 1478 static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification) 1479 { 1480 enum intel_gvt_gtt_type root_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY; 1481 struct intel_vgpu_mm *mm; 1482 u64 *pdps; 1483 1484 pdps = (u64 *)&vgpu_vreg64_t(vgpu, vgtif_reg(pdp[0])); 1485 1486 switch (notification) { 1487 case VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE: 1488 root_entry_type = GTT_TYPE_PPGTT_ROOT_L3_ENTRY; 1489 fallthrough; 1490 case VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE: 1491 mm = intel_vgpu_get_ppgtt_mm(vgpu, root_entry_type, pdps); 1492 return PTR_ERR_OR_ZERO(mm); 1493 case VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY: 1494 case VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY: 1495 return intel_vgpu_put_ppgtt_mm(vgpu, pdps); 1496 case VGT_G2V_EXECLIST_CONTEXT_CREATE: 1497 case VGT_G2V_EXECLIST_CONTEXT_DESTROY: 1498 case 1: /* Remove this in guest driver. */ 1499 break; 1500 default: 1501 gvt_vgpu_err("Invalid PV notification %d\n", notification); 1502 } 1503 return 0; 1504 } 1505 1506 static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready) 1507 { 1508 struct kobject *kobj = &vgpu->gvt->gt->i915->drm.primary->kdev->kobj; 1509 char *env[3] = {NULL, NULL, NULL}; 1510 char vmid_str[20]; 1511 char display_ready_str[20]; 1512 1513 snprintf(display_ready_str, 20, "GVT_DISPLAY_READY=%d", ready); 1514 env[0] = display_ready_str; 1515 1516 snprintf(vmid_str, 20, "VMID=%d", vgpu->id); 1517 env[1] = vmid_str; 1518 1519 return kobject_uevent_env(kobj, KOBJ_ADD, env); 1520 } 1521 1522 static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1523 void *p_data, unsigned int bytes) 1524 { 1525 u32 data = *(u32 *)p_data; 1526 bool invalid_write = false; 1527 1528 switch (offset) { 1529 case _vgtif_reg(display_ready): 1530 send_display_ready_uevent(vgpu, data ? 1 : 0); 1531 break; 1532 case _vgtif_reg(g2v_notify): 1533 handle_g2v_notification(vgpu, data); 1534 break; 1535 /* add xhot and yhot to handled list to avoid error log */ 1536 case _vgtif_reg(cursor_x_hot): 1537 case _vgtif_reg(cursor_y_hot): 1538 case _vgtif_reg(pdp[0].lo): 1539 case _vgtif_reg(pdp[0].hi): 1540 case _vgtif_reg(pdp[1].lo): 1541 case _vgtif_reg(pdp[1].hi): 1542 case _vgtif_reg(pdp[2].lo): 1543 case _vgtif_reg(pdp[2].hi): 1544 case _vgtif_reg(pdp[3].lo): 1545 case _vgtif_reg(pdp[3].hi): 1546 case _vgtif_reg(execlist_context_descriptor_lo): 1547 case _vgtif_reg(execlist_context_descriptor_hi): 1548 break; 1549 case _vgtif_reg(rsv5[0])..._vgtif_reg(rsv5[3]): 1550 invalid_write = true; 1551 enter_failsafe_mode(vgpu, GVT_FAILSAFE_INSUFFICIENT_RESOURCE); 1552 break; 1553 default: 1554 invalid_write = true; 1555 gvt_vgpu_err("invalid pvinfo write offset %x bytes %x data %x\n", 1556 offset, bytes, data); 1557 break; 1558 } 1559 1560 if (!invalid_write) 1561 write_vreg(vgpu, offset, p_data, bytes); 1562 1563 return 0; 1564 } 1565 1566 static int pf_write(struct intel_vgpu *vgpu, 1567 unsigned int offset, void *p_data, unsigned int bytes) 1568 { 1569 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 1570 u32 val = *(u32 *)p_data; 1571 1572 if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL || 1573 offset == _PS_1B_CTRL || offset == _PS_2B_CTRL || 1574 offset == _PS_1C_CTRL) && (val & PS_PLANE_SEL_MASK) != 0) { 1575 drm_WARN_ONCE(&i915->drm, true, 1576 "VM(%d): guest is trying to scaling a plane\n", 1577 vgpu->id); 1578 return 0; 1579 } 1580 1581 return intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes); 1582 } 1583 1584 static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu, 1585 unsigned int offset, void *p_data, unsigned int bytes) 1586 { 1587 write_vreg(vgpu, offset, p_data, bytes); 1588 1589 if (vgpu_vreg(vgpu, offset) & 1590 HSW_PWR_WELL_CTL_REQ(HSW_PW_CTL_IDX_GLOBAL)) 1591 vgpu_vreg(vgpu, offset) |= 1592 HSW_PWR_WELL_CTL_STATE(HSW_PW_CTL_IDX_GLOBAL); 1593 else 1594 vgpu_vreg(vgpu, offset) &= 1595 ~HSW_PWR_WELL_CTL_STATE(HSW_PW_CTL_IDX_GLOBAL); 1596 return 0; 1597 } 1598 1599 static int gen9_dbuf_ctl_mmio_write(struct intel_vgpu *vgpu, 1600 unsigned int offset, void *p_data, unsigned int bytes) 1601 { 1602 write_vreg(vgpu, offset, p_data, bytes); 1603 1604 if (vgpu_vreg(vgpu, offset) & DBUF_POWER_REQUEST) 1605 vgpu_vreg(vgpu, offset) |= DBUF_POWER_STATE; 1606 else 1607 vgpu_vreg(vgpu, offset) &= ~DBUF_POWER_STATE; 1608 1609 return 0; 1610 } 1611 1612 static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu, 1613 unsigned int offset, void *p_data, unsigned int bytes) 1614 { 1615 write_vreg(vgpu, offset, p_data, bytes); 1616 1617 if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM) 1618 vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM; 1619 return 0; 1620 } 1621 1622 static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset, 1623 void *p_data, unsigned int bytes) 1624 { 1625 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 1626 u32 mode; 1627 1628 write_vreg(vgpu, offset, p_data, bytes); 1629 mode = vgpu_vreg(vgpu, offset); 1630 1631 if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) { 1632 drm_WARN_ONCE(&i915->drm, 1, 1633 "VM(%d): iGVT-g doesn't support GuC\n", 1634 vgpu->id); 1635 return 0; 1636 } 1637 1638 return 0; 1639 } 1640 1641 static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset, 1642 void *p_data, unsigned int bytes) 1643 { 1644 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 1645 u32 trtte = *(u32 *)p_data; 1646 1647 if ((trtte & 1) && (trtte & (1 << 1)) == 0) { 1648 drm_WARN(&i915->drm, 1, 1649 "VM(%d): Use physical address for TRTT!\n", 1650 vgpu->id); 1651 return -EINVAL; 1652 } 1653 write_vreg(vgpu, offset, p_data, bytes); 1654 1655 return 0; 1656 } 1657 1658 static int gen9_trtt_chicken_write(struct intel_vgpu *vgpu, unsigned int offset, 1659 void *p_data, unsigned int bytes) 1660 { 1661 write_vreg(vgpu, offset, p_data, bytes); 1662 return 0; 1663 } 1664 1665 static int dpll_status_read(struct intel_vgpu *vgpu, unsigned int offset, 1666 void *p_data, unsigned int bytes) 1667 { 1668 u32 v = 0; 1669 1670 if (vgpu_vreg(vgpu, 0x46010) & (1 << 31)) 1671 v |= (1 << 0); 1672 1673 if (vgpu_vreg(vgpu, 0x46014) & (1 << 31)) 1674 v |= (1 << 8); 1675 1676 if (vgpu_vreg(vgpu, 0x46040) & (1 << 31)) 1677 v |= (1 << 16); 1678 1679 if (vgpu_vreg(vgpu, 0x46060) & (1 << 31)) 1680 v |= (1 << 24); 1681 1682 vgpu_vreg(vgpu, offset) = v; 1683 1684 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1685 } 1686 1687 static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset, 1688 void *p_data, unsigned int bytes) 1689 { 1690 u32 value = *(u32 *)p_data; 1691 u32 cmd = value & 0xff; 1692 u32 *data0 = &vgpu_vreg_t(vgpu, GEN6_PCODE_DATA); 1693 1694 switch (cmd) { 1695 case GEN9_PCODE_READ_MEM_LATENCY: 1696 if (IS_SKYLAKE(vgpu->gvt->gt->i915) || 1697 IS_KABYLAKE(vgpu->gvt->gt->i915) || 1698 IS_COFFEELAKE(vgpu->gvt->gt->i915) || 1699 IS_COMETLAKE(vgpu->gvt->gt->i915)) { 1700 /** 1701 * "Read memory latency" command on gen9. 1702 * Below memory latency values are read 1703 * from skylake platform. 1704 */ 1705 if (!*data0) 1706 *data0 = 0x1e1a1100; 1707 else 1708 *data0 = 0x61514b3d; 1709 } else if (IS_BROXTON(vgpu->gvt->gt->i915)) { 1710 /** 1711 * "Read memory latency" command on gen9. 1712 * Below memory latency values are read 1713 * from Broxton MRB. 1714 */ 1715 if (!*data0) 1716 *data0 = 0x16080707; 1717 else 1718 *data0 = 0x16161616; 1719 } 1720 break; 1721 case SKL_PCODE_CDCLK_CONTROL: 1722 if (IS_SKYLAKE(vgpu->gvt->gt->i915) || 1723 IS_KABYLAKE(vgpu->gvt->gt->i915) || 1724 IS_COFFEELAKE(vgpu->gvt->gt->i915) || 1725 IS_COMETLAKE(vgpu->gvt->gt->i915)) 1726 *data0 = SKL_CDCLK_READY_FOR_CHANGE; 1727 break; 1728 case GEN6_PCODE_READ_RC6VIDS: 1729 *data0 |= 0x1; 1730 break; 1731 } 1732 1733 gvt_dbg_core("VM(%d) write %x to mailbox, return data0 %x\n", 1734 vgpu->id, value, *data0); 1735 /** 1736 * PCODE_READY clear means ready for pcode read/write, 1737 * PCODE_ERROR_MASK clear means no error happened. In GVT-g we 1738 * always emulate as pcode read/write success and ready for access 1739 * anytime, since we don't touch real physical registers here. 1740 */ 1741 value &= ~(GEN6_PCODE_READY | GEN6_PCODE_ERROR_MASK); 1742 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes); 1743 } 1744 1745 static int hws_pga_write(struct intel_vgpu *vgpu, unsigned int offset, 1746 void *p_data, unsigned int bytes) 1747 { 1748 u32 value = *(u32 *)p_data; 1749 const struct intel_engine_cs *engine = 1750 intel_gvt_render_mmio_to_engine(vgpu->gvt, offset); 1751 1752 if (value != 0 && 1753 !intel_gvt_ggtt_validate_range(vgpu, value, I915_GTT_PAGE_SIZE)) { 1754 gvt_vgpu_err("write invalid HWSP address, reg:0x%x, value:0x%x\n", 1755 offset, value); 1756 return -EINVAL; 1757 } 1758 1759 /* 1760 * Need to emulate all the HWSP register write to ensure host can 1761 * update the VM CSB status correctly. Here listed registers can 1762 * support BDW, SKL or other platforms with same HWSP registers. 1763 */ 1764 if (unlikely(!engine)) { 1765 gvt_vgpu_err("access unknown hardware status page register:0x%x\n", 1766 offset); 1767 return -EINVAL; 1768 } 1769 vgpu->hws_pga[engine->id] = value; 1770 gvt_dbg_mmio("VM(%d) write: 0x%x to HWSP: 0x%x\n", 1771 vgpu->id, value, offset); 1772 1773 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes); 1774 } 1775 1776 static int skl_power_well_ctl_write(struct intel_vgpu *vgpu, 1777 unsigned int offset, void *p_data, unsigned int bytes) 1778 { 1779 u32 v = *(u32 *)p_data; 1780 1781 if (IS_BROXTON(vgpu->gvt->gt->i915)) 1782 v &= (1 << 31) | (1 << 29); 1783 else 1784 v &= (1 << 31) | (1 << 29) | (1 << 9) | 1785 (1 << 7) | (1 << 5) | (1 << 3) | (1 << 1); 1786 v |= (v >> 1); 1787 1788 return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes); 1789 } 1790 1791 static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset, 1792 void *p_data, unsigned int bytes) 1793 { 1794 u32 v = *(u32 *)p_data; 1795 1796 /* other bits are MBZ. */ 1797 v &= (1 << 31) | (1 << 30); 1798 v & (1 << 31) ? (v |= (1 << 30)) : (v &= ~(1 << 30)); 1799 1800 vgpu_vreg(vgpu, offset) = v; 1801 1802 return 0; 1803 } 1804 1805 static int bxt_de_pll_enable_write(struct intel_vgpu *vgpu, 1806 unsigned int offset, void *p_data, unsigned int bytes) 1807 { 1808 u32 v = *(u32 *)p_data; 1809 1810 if (v & BXT_DE_PLL_PLL_ENABLE) 1811 v |= BXT_DE_PLL_LOCK; 1812 1813 vgpu_vreg(vgpu, offset) = v; 1814 1815 return 0; 1816 } 1817 1818 static int bxt_port_pll_enable_write(struct intel_vgpu *vgpu, 1819 unsigned int offset, void *p_data, unsigned int bytes) 1820 { 1821 u32 v = *(u32 *)p_data; 1822 1823 if (v & PORT_PLL_ENABLE) 1824 v |= PORT_PLL_LOCK; 1825 1826 vgpu_vreg(vgpu, offset) = v; 1827 1828 return 0; 1829 } 1830 1831 static int bxt_phy_ctl_family_write(struct intel_vgpu *vgpu, 1832 unsigned int offset, void *p_data, unsigned int bytes) 1833 { 1834 u32 v = *(u32 *)p_data; 1835 u32 data = v & COMMON_RESET_DIS ? BXT_PHY_LANE_ENABLED : 0; 1836 1837 switch (offset) { 1838 case _PHY_CTL_FAMILY_EDP: 1839 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_A) = data; 1840 break; 1841 case _PHY_CTL_FAMILY_DDI: 1842 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_B) = data; 1843 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_C) = data; 1844 break; 1845 } 1846 1847 vgpu_vreg(vgpu, offset) = v; 1848 1849 return 0; 1850 } 1851 1852 static int bxt_port_tx_dw3_read(struct intel_vgpu *vgpu, 1853 unsigned int offset, void *p_data, unsigned int bytes) 1854 { 1855 u32 v = vgpu_vreg(vgpu, offset); 1856 1857 v &= ~UNIQUE_TRANGE_EN_METHOD; 1858 1859 vgpu_vreg(vgpu, offset) = v; 1860 1861 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1862 } 1863 1864 static int bxt_pcs_dw12_grp_write(struct intel_vgpu *vgpu, 1865 unsigned int offset, void *p_data, unsigned int bytes) 1866 { 1867 u32 v = *(u32 *)p_data; 1868 1869 if (offset == _PORT_PCS_DW12_GRP_A || offset == _PORT_PCS_DW12_GRP_B) { 1870 vgpu_vreg(vgpu, offset - 0x600) = v; 1871 vgpu_vreg(vgpu, offset - 0x800) = v; 1872 } else { 1873 vgpu_vreg(vgpu, offset - 0x400) = v; 1874 vgpu_vreg(vgpu, offset - 0x600) = v; 1875 } 1876 1877 vgpu_vreg(vgpu, offset) = v; 1878 1879 return 0; 1880 } 1881 1882 static int bxt_gt_disp_pwron_write(struct intel_vgpu *vgpu, 1883 unsigned int offset, void *p_data, unsigned int bytes) 1884 { 1885 u32 v = *(u32 *)p_data; 1886 1887 if (v & BIT(0)) { 1888 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &= 1889 ~PHY_RESERVED; 1890 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |= 1891 PHY_POWER_GOOD; 1892 } 1893 1894 if (v & BIT(1)) { 1895 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &= 1896 ~PHY_RESERVED; 1897 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |= 1898 PHY_POWER_GOOD; 1899 } 1900 1901 1902 vgpu_vreg(vgpu, offset) = v; 1903 1904 return 0; 1905 } 1906 1907 static int edp_psr_imr_iir_write(struct intel_vgpu *vgpu, 1908 unsigned int offset, void *p_data, unsigned int bytes) 1909 { 1910 vgpu_vreg(vgpu, offset) = 0; 1911 return 0; 1912 } 1913 1914 /* 1915 * FixMe: 1916 * If guest fills non-priv batch buffer on ApolloLake/Broxton as Mesa i965 did: 1917 * 717e7539124d (i965: Use a WC map and memcpy for the batch instead of pwrite.) 1918 * Due to the missing flush of bb filled by VM vCPU, host GPU hangs on executing 1919 * these MI_BATCH_BUFFER. 1920 * Temporarily workaround this by setting SNOOP bit for PAT3 used by PPGTT 1921 * PML4 PTE: PAT(0) PCD(1) PWT(1). 1922 * The performance is still expected to be low, will need further improvement. 1923 */ 1924 static int bxt_ppat_low_write(struct intel_vgpu *vgpu, unsigned int offset, 1925 void *p_data, unsigned int bytes) 1926 { 1927 u64 pat = 1928 GEN8_PPAT(0, CHV_PPAT_SNOOP) | 1929 GEN8_PPAT(1, 0) | 1930 GEN8_PPAT(2, 0) | 1931 GEN8_PPAT(3, CHV_PPAT_SNOOP) | 1932 GEN8_PPAT(4, CHV_PPAT_SNOOP) | 1933 GEN8_PPAT(5, CHV_PPAT_SNOOP) | 1934 GEN8_PPAT(6, CHV_PPAT_SNOOP) | 1935 GEN8_PPAT(7, CHV_PPAT_SNOOP); 1936 1937 vgpu_vreg(vgpu, offset) = lower_32_bits(pat); 1938 1939 return 0; 1940 } 1941 1942 static int guc_status_read(struct intel_vgpu *vgpu, 1943 unsigned int offset, void *p_data, 1944 unsigned int bytes) 1945 { 1946 /* keep MIA_IN_RESET before clearing */ 1947 read_vreg(vgpu, offset, p_data, bytes); 1948 vgpu_vreg(vgpu, offset) &= ~GS_MIA_IN_RESET; 1949 return 0; 1950 } 1951 1952 static int mmio_read_from_hw(struct intel_vgpu *vgpu, 1953 unsigned int offset, void *p_data, unsigned int bytes) 1954 { 1955 struct intel_gvt *gvt = vgpu->gvt; 1956 const struct intel_engine_cs *engine = 1957 intel_gvt_render_mmio_to_engine(gvt, offset); 1958 1959 /** 1960 * Read HW reg in following case 1961 * a. the offset isn't a ring mmio 1962 * b. the offset's ring is running on hw. 1963 * c. the offset is ring time stamp mmio 1964 */ 1965 1966 if (!engine || 1967 vgpu == gvt->scheduler.engine_owner[engine->id] || 1968 offset == i915_mmio_reg_offset(RING_TIMESTAMP(engine->mmio_base)) || 1969 offset == i915_mmio_reg_offset(RING_TIMESTAMP_UDW(engine->mmio_base))) { 1970 mmio_hw_access_pre(gvt->gt); 1971 vgpu_vreg(vgpu, offset) = 1972 intel_uncore_read(gvt->gt->uncore, _MMIO(offset)); 1973 mmio_hw_access_post(gvt->gt); 1974 } 1975 1976 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1977 } 1978 1979 static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1980 void *p_data, unsigned int bytes) 1981 { 1982 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 1983 const struct intel_engine_cs *engine = intel_gvt_render_mmio_to_engine(vgpu->gvt, offset); 1984 struct intel_vgpu_execlist *execlist; 1985 u32 data = *(u32 *)p_data; 1986 int ret = 0; 1987 1988 if (drm_WARN_ON(&i915->drm, !engine)) 1989 return -EINVAL; 1990 1991 /* 1992 * Due to d3_entered is used to indicate skipping PPGTT invalidation on 1993 * vGPU reset, it's set on D0->D3 on PCI config write, and cleared after 1994 * vGPU reset if in resuming. 1995 * In S0ix exit, the device power state also transite from D3 to D0 as 1996 * S3 resume, but no vGPU reset (triggered by QEMU devic model). After 1997 * S0ix exit, all engines continue to work. However the d3_entered 1998 * remains set which will break next vGPU reset logic (miss the expected 1999 * PPGTT invalidation). 2000 * Engines can only work in D0. Thus the 1st elsp write gives GVT a 2001 * chance to clear d3_entered. 2002 */ 2003 if (vgpu->d3_entered) 2004 vgpu->d3_entered = false; 2005 2006 execlist = &vgpu->submission.execlist[engine->id]; 2007 2008 execlist->elsp_dwords.data[3 - execlist->elsp_dwords.index] = data; 2009 if (execlist->elsp_dwords.index == 3) { 2010 ret = intel_vgpu_submit_execlist(vgpu, engine); 2011 if(ret) 2012 gvt_vgpu_err("fail submit workload on ring %s\n", 2013 engine->name); 2014 } 2015 2016 ++execlist->elsp_dwords.index; 2017 execlist->elsp_dwords.index &= 0x3; 2018 return ret; 2019 } 2020 2021 static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 2022 void *p_data, unsigned int bytes) 2023 { 2024 u32 data = *(u32 *)p_data; 2025 const struct intel_engine_cs *engine = 2026 intel_gvt_render_mmio_to_engine(vgpu->gvt, offset); 2027 bool enable_execlist; 2028 int ret; 2029 2030 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(1); 2031 if (IS_COFFEELAKE(vgpu->gvt->gt->i915) || 2032 IS_COMETLAKE(vgpu->gvt->gt->i915)) 2033 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(2); 2034 write_vreg(vgpu, offset, p_data, bytes); 2035 2036 if (IS_MASKED_BITS_ENABLED(data, 1)) { 2037 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); 2038 return 0; 2039 } 2040 2041 if ((IS_COFFEELAKE(vgpu->gvt->gt->i915) || 2042 IS_COMETLAKE(vgpu->gvt->gt->i915)) && 2043 IS_MASKED_BITS_ENABLED(data, 2)) { 2044 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); 2045 return 0; 2046 } 2047 2048 /* when PPGTT mode enabled, we will check if guest has called 2049 * pvinfo, if not, we will treat this guest as non-gvtg-aware 2050 * guest, and stop emulating its cfg space, mmio, gtt, etc. 2051 */ 2052 if ((IS_MASKED_BITS_ENABLED(data, GFX_PPGTT_ENABLE) || 2053 IS_MASKED_BITS_ENABLED(data, GFX_RUN_LIST_ENABLE)) && 2054 !vgpu->pv_notified) { 2055 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); 2056 return 0; 2057 } 2058 if (IS_MASKED_BITS_ENABLED(data, GFX_RUN_LIST_ENABLE) || 2059 IS_MASKED_BITS_DISABLED(data, GFX_RUN_LIST_ENABLE)) { 2060 enable_execlist = !!(data & GFX_RUN_LIST_ENABLE); 2061 2062 gvt_dbg_core("EXECLIST %s on ring %s\n", 2063 (enable_execlist ? "enabling" : "disabling"), 2064 engine->name); 2065 2066 if (!enable_execlist) 2067 return 0; 2068 2069 ret = intel_vgpu_select_submission_ops(vgpu, 2070 engine->mask, 2071 INTEL_VGPU_EXECLIST_SUBMISSION); 2072 if (ret) 2073 return ret; 2074 2075 intel_vgpu_start_schedule(vgpu); 2076 } 2077 return 0; 2078 } 2079 2080 static int gvt_reg_tlb_control_handler(struct intel_vgpu *vgpu, 2081 unsigned int offset, void *p_data, unsigned int bytes) 2082 { 2083 unsigned int id = 0; 2084 2085 write_vreg(vgpu, offset, p_data, bytes); 2086 vgpu_vreg(vgpu, offset) = 0; 2087 2088 switch (offset) { 2089 case 0x4260: 2090 id = RCS0; 2091 break; 2092 case 0x4264: 2093 id = VCS0; 2094 break; 2095 case 0x4268: 2096 id = VCS1; 2097 break; 2098 case 0x426c: 2099 id = BCS0; 2100 break; 2101 case 0x4270: 2102 id = VECS0; 2103 break; 2104 default: 2105 return -EINVAL; 2106 } 2107 set_bit(id, (void *)vgpu->submission.tlb_handle_pending); 2108 2109 return 0; 2110 } 2111 2112 static int ring_reset_ctl_write(struct intel_vgpu *vgpu, 2113 unsigned int offset, void *p_data, unsigned int bytes) 2114 { 2115 u32 data; 2116 2117 write_vreg(vgpu, offset, p_data, bytes); 2118 data = vgpu_vreg(vgpu, offset); 2119 2120 if (IS_MASKED_BITS_ENABLED(data, RESET_CTL_REQUEST_RESET)) 2121 data |= RESET_CTL_READY_TO_RESET; 2122 else if (data & _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET)) 2123 data &= ~RESET_CTL_READY_TO_RESET; 2124 2125 vgpu_vreg(vgpu, offset) = data; 2126 return 0; 2127 } 2128 2129 static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu, 2130 unsigned int offset, void *p_data, 2131 unsigned int bytes) 2132 { 2133 u32 data = *(u32 *)p_data; 2134 2135 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(0x18); 2136 write_vreg(vgpu, offset, p_data, bytes); 2137 2138 if (IS_MASKED_BITS_ENABLED(data, 0x10) || 2139 IS_MASKED_BITS_ENABLED(data, 0x8)) 2140 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); 2141 2142 return 0; 2143 } 2144 2145 #define MMIO_F(reg, s, f, am, rm, d, r, w) do { \ 2146 ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \ 2147 f, s, am, rm, d, r, w); \ 2148 if (ret) \ 2149 return ret; \ 2150 } while (0) 2151 2152 #define MMIO_D(reg, d) \ 2153 MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL) 2154 2155 #define MMIO_DH(reg, d, r, w) \ 2156 MMIO_F(reg, 4, 0, 0, 0, d, r, w) 2157 2158 #define MMIO_DFH(reg, d, f, r, w) \ 2159 MMIO_F(reg, 4, f, 0, 0, d, r, w) 2160 2161 #define MMIO_GM(reg, d, r, w) \ 2162 MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w) 2163 2164 #define MMIO_GM_RDR(reg, d, r, w) \ 2165 MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w) 2166 2167 #define MMIO_RO(reg, d, f, rm, r, w) \ 2168 MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w) 2169 2170 #define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \ 2171 MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \ 2172 MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \ 2173 MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \ 2174 MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \ 2175 if (HAS_ENGINE(gvt->gt, VCS1)) \ 2176 MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \ 2177 } while (0) 2178 2179 #define MMIO_RING_D(prefix, d) \ 2180 MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL) 2181 2182 #define MMIO_RING_DFH(prefix, d, f, r, w) \ 2183 MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w) 2184 2185 #define MMIO_RING_GM(prefix, d, r, w) \ 2186 MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w) 2187 2188 #define MMIO_RING_GM_RDR(prefix, d, r, w) \ 2189 MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w) 2190 2191 #define MMIO_RING_RO(prefix, d, f, rm, r, w) \ 2192 MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w) 2193 2194 static int init_generic_mmio_info(struct intel_gvt *gvt) 2195 { 2196 struct drm_i915_private *dev_priv = gvt->gt->i915; 2197 int ret; 2198 2199 MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL, 2200 intel_vgpu_reg_imr_handler); 2201 2202 MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler); 2203 MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler); 2204 MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler); 2205 MMIO_D(SDEISR, D_ALL); 2206 2207 MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL); 2208 2209 2210 MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL, 2211 gamw_echo_dev_rw_ia_write); 2212 2213 MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL); 2214 MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL); 2215 MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL); 2216 2217 #define RING_REG(base) _MMIO((base) + 0x28) 2218 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL); 2219 #undef RING_REG 2220 2221 #define RING_REG(base) _MMIO((base) + 0x134) 2222 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL); 2223 #undef RING_REG 2224 2225 #define RING_REG(base) _MMIO((base) + 0x6c) 2226 MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL); 2227 #undef RING_REG 2228 MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL); 2229 2230 MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL); 2231 MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL); 2232 MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL); 2233 MMIO_D(GEN7_CXT_SIZE, D_ALL); 2234 2235 MMIO_RING_DFH(RING_TAIL, D_ALL, 0, NULL, NULL); 2236 MMIO_RING_DFH(RING_HEAD, D_ALL, 0, NULL, NULL); 2237 MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL); 2238 MMIO_RING_DFH(RING_ACTHD, D_ALL, 0, mmio_read_from_hw, NULL); 2239 MMIO_RING_GM(RING_START, D_ALL, NULL, NULL); 2240 2241 /* RING MODE */ 2242 #define RING_REG(base) _MMIO((base) + 0x29c) 2243 MMIO_RING_DFH(RING_REG, D_ALL, 2244 F_MODE_MASK | F_CMD_ACCESS | F_CMD_WRITE_PATCH, NULL, 2245 ring_mode_mmio_write); 2246 #undef RING_REG 2247 2248 MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 2249 NULL, NULL); 2250 MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 2251 NULL, NULL); 2252 MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS, 2253 mmio_read_from_hw, NULL); 2254 MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS, 2255 mmio_read_from_hw, NULL); 2256 2257 MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2258 MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 2259 NULL, NULL); 2260 MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2261 MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2262 MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2263 2264 MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2265 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2266 MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2267 MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL, 2268 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2269 MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2270 MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL); 2271 MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 2272 NULL, NULL); 2273 MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 2274 NULL, NULL); 2275 MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL); 2276 MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL); 2277 MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL); 2278 MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL); 2279 MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL); 2280 MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL); 2281 MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL); 2282 MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2283 MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2284 MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2285 2286 /* display */ 2287 MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL); 2288 MMIO_D(_MMIO(0x602a0), D_ALL); 2289 2290 MMIO_D(_MMIO(0x65050), D_ALL); 2291 MMIO_D(_MMIO(0x650b4), D_ALL); 2292 2293 MMIO_D(_MMIO(0xc4040), D_ALL); 2294 MMIO_D(DERRMR, D_ALL); 2295 2296 MMIO_D(PIPEDSL(PIPE_A), D_ALL); 2297 MMIO_D(PIPEDSL(PIPE_B), D_ALL); 2298 MMIO_D(PIPEDSL(PIPE_C), D_ALL); 2299 MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL); 2300 2301 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write); 2302 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write); 2303 MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write); 2304 MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write); 2305 2306 MMIO_D(PIPESTAT(PIPE_A), D_ALL); 2307 MMIO_D(PIPESTAT(PIPE_B), D_ALL); 2308 MMIO_D(PIPESTAT(PIPE_C), D_ALL); 2309 MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL); 2310 2311 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL); 2312 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL); 2313 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL); 2314 MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL); 2315 2316 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL); 2317 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL); 2318 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL); 2319 MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL); 2320 2321 MMIO_D(CURCNTR(PIPE_A), D_ALL); 2322 MMIO_D(CURCNTR(PIPE_B), D_ALL); 2323 MMIO_D(CURCNTR(PIPE_C), D_ALL); 2324 2325 MMIO_D(CURPOS(PIPE_A), D_ALL); 2326 MMIO_D(CURPOS(PIPE_B), D_ALL); 2327 MMIO_D(CURPOS(PIPE_C), D_ALL); 2328 2329 MMIO_D(CURBASE(PIPE_A), D_ALL); 2330 MMIO_D(CURBASE(PIPE_B), D_ALL); 2331 MMIO_D(CURBASE(PIPE_C), D_ALL); 2332 2333 MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL); 2334 MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL); 2335 MMIO_D(CUR_FBC_CTL(PIPE_C), D_ALL); 2336 2337 MMIO_D(_MMIO(0x700ac), D_ALL); 2338 MMIO_D(_MMIO(0x710ac), D_ALL); 2339 MMIO_D(_MMIO(0x720ac), D_ALL); 2340 2341 MMIO_D(_MMIO(0x70090), D_ALL); 2342 MMIO_D(_MMIO(0x70094), D_ALL); 2343 MMIO_D(_MMIO(0x70098), D_ALL); 2344 MMIO_D(_MMIO(0x7009c), D_ALL); 2345 2346 MMIO_D(DSPCNTR(PIPE_A), D_ALL); 2347 MMIO_D(DSPADDR(PIPE_A), D_ALL); 2348 MMIO_D(DSPSTRIDE(PIPE_A), D_ALL); 2349 MMIO_D(DSPPOS(PIPE_A), D_ALL); 2350 MMIO_D(DSPSIZE(PIPE_A), D_ALL); 2351 MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write); 2352 MMIO_D(DSPOFFSET(PIPE_A), D_ALL); 2353 MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL); 2354 MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL, 2355 reg50080_mmio_write); 2356 2357 MMIO_D(DSPCNTR(PIPE_B), D_ALL); 2358 MMIO_D(DSPADDR(PIPE_B), D_ALL); 2359 MMIO_D(DSPSTRIDE(PIPE_B), D_ALL); 2360 MMIO_D(DSPPOS(PIPE_B), D_ALL); 2361 MMIO_D(DSPSIZE(PIPE_B), D_ALL); 2362 MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write); 2363 MMIO_D(DSPOFFSET(PIPE_B), D_ALL); 2364 MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL); 2365 MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL, 2366 reg50080_mmio_write); 2367 2368 MMIO_D(DSPCNTR(PIPE_C), D_ALL); 2369 MMIO_D(DSPADDR(PIPE_C), D_ALL); 2370 MMIO_D(DSPSTRIDE(PIPE_C), D_ALL); 2371 MMIO_D(DSPPOS(PIPE_C), D_ALL); 2372 MMIO_D(DSPSIZE(PIPE_C), D_ALL); 2373 MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write); 2374 MMIO_D(DSPOFFSET(PIPE_C), D_ALL); 2375 MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL); 2376 MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL, 2377 reg50080_mmio_write); 2378 2379 MMIO_D(SPRCTL(PIPE_A), D_ALL); 2380 MMIO_D(SPRLINOFF(PIPE_A), D_ALL); 2381 MMIO_D(SPRSTRIDE(PIPE_A), D_ALL); 2382 MMIO_D(SPRPOS(PIPE_A), D_ALL); 2383 MMIO_D(SPRSIZE(PIPE_A), D_ALL); 2384 MMIO_D(SPRKEYVAL(PIPE_A), D_ALL); 2385 MMIO_D(SPRKEYMSK(PIPE_A), D_ALL); 2386 MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write); 2387 MMIO_D(SPRKEYMAX(PIPE_A), D_ALL); 2388 MMIO_D(SPROFFSET(PIPE_A), D_ALL); 2389 MMIO_D(SPRSCALE(PIPE_A), D_ALL); 2390 MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL); 2391 MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL, 2392 reg50080_mmio_write); 2393 2394 MMIO_D(SPRCTL(PIPE_B), D_ALL); 2395 MMIO_D(SPRLINOFF(PIPE_B), D_ALL); 2396 MMIO_D(SPRSTRIDE(PIPE_B), D_ALL); 2397 MMIO_D(SPRPOS(PIPE_B), D_ALL); 2398 MMIO_D(SPRSIZE(PIPE_B), D_ALL); 2399 MMIO_D(SPRKEYVAL(PIPE_B), D_ALL); 2400 MMIO_D(SPRKEYMSK(PIPE_B), D_ALL); 2401 MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write); 2402 MMIO_D(SPRKEYMAX(PIPE_B), D_ALL); 2403 MMIO_D(SPROFFSET(PIPE_B), D_ALL); 2404 MMIO_D(SPRSCALE(PIPE_B), D_ALL); 2405 MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL); 2406 MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL, 2407 reg50080_mmio_write); 2408 2409 MMIO_D(SPRCTL(PIPE_C), D_ALL); 2410 MMIO_D(SPRLINOFF(PIPE_C), D_ALL); 2411 MMIO_D(SPRSTRIDE(PIPE_C), D_ALL); 2412 MMIO_D(SPRPOS(PIPE_C), D_ALL); 2413 MMIO_D(SPRSIZE(PIPE_C), D_ALL); 2414 MMIO_D(SPRKEYVAL(PIPE_C), D_ALL); 2415 MMIO_D(SPRKEYMSK(PIPE_C), D_ALL); 2416 MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write); 2417 MMIO_D(SPRKEYMAX(PIPE_C), D_ALL); 2418 MMIO_D(SPROFFSET(PIPE_C), D_ALL); 2419 MMIO_D(SPRSCALE(PIPE_C), D_ALL); 2420 MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL); 2421 MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL, 2422 reg50080_mmio_write); 2423 2424 MMIO_D(HTOTAL(TRANSCODER_A), D_ALL); 2425 MMIO_D(HBLANK(TRANSCODER_A), D_ALL); 2426 MMIO_D(HSYNC(TRANSCODER_A), D_ALL); 2427 MMIO_D(VTOTAL(TRANSCODER_A), D_ALL); 2428 MMIO_D(VBLANK(TRANSCODER_A), D_ALL); 2429 MMIO_D(VSYNC(TRANSCODER_A), D_ALL); 2430 MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL); 2431 MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL); 2432 MMIO_D(PIPESRC(TRANSCODER_A), D_ALL); 2433 2434 MMIO_D(HTOTAL(TRANSCODER_B), D_ALL); 2435 MMIO_D(HBLANK(TRANSCODER_B), D_ALL); 2436 MMIO_D(HSYNC(TRANSCODER_B), D_ALL); 2437 MMIO_D(VTOTAL(TRANSCODER_B), D_ALL); 2438 MMIO_D(VBLANK(TRANSCODER_B), D_ALL); 2439 MMIO_D(VSYNC(TRANSCODER_B), D_ALL); 2440 MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL); 2441 MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL); 2442 MMIO_D(PIPESRC(TRANSCODER_B), D_ALL); 2443 2444 MMIO_D(HTOTAL(TRANSCODER_C), D_ALL); 2445 MMIO_D(HBLANK(TRANSCODER_C), D_ALL); 2446 MMIO_D(HSYNC(TRANSCODER_C), D_ALL); 2447 MMIO_D(VTOTAL(TRANSCODER_C), D_ALL); 2448 MMIO_D(VBLANK(TRANSCODER_C), D_ALL); 2449 MMIO_D(VSYNC(TRANSCODER_C), D_ALL); 2450 MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL); 2451 MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL); 2452 MMIO_D(PIPESRC(TRANSCODER_C), D_ALL); 2453 2454 MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL); 2455 MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL); 2456 MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL); 2457 MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL); 2458 MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL); 2459 MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL); 2460 MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL); 2461 MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL); 2462 2463 MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL); 2464 MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL); 2465 MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL); 2466 MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL); 2467 MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL); 2468 MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL); 2469 MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL); 2470 MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL); 2471 2472 MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL); 2473 MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL); 2474 MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL); 2475 MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL); 2476 MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL); 2477 MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL); 2478 MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL); 2479 MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL); 2480 2481 MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL); 2482 MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL); 2483 MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL); 2484 MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL); 2485 MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL); 2486 MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL); 2487 MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL); 2488 MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL); 2489 2490 MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL); 2491 MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL); 2492 MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL); 2493 MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL); 2494 MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL); 2495 MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL); 2496 MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL); 2497 MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL); 2498 2499 MMIO_D(PF_CTL(PIPE_A), D_ALL); 2500 MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL); 2501 MMIO_D(PF_WIN_POS(PIPE_A), D_ALL); 2502 MMIO_D(PF_VSCALE(PIPE_A), D_ALL); 2503 MMIO_D(PF_HSCALE(PIPE_A), D_ALL); 2504 2505 MMIO_D(PF_CTL(PIPE_B), D_ALL); 2506 MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL); 2507 MMIO_D(PF_WIN_POS(PIPE_B), D_ALL); 2508 MMIO_D(PF_VSCALE(PIPE_B), D_ALL); 2509 MMIO_D(PF_HSCALE(PIPE_B), D_ALL); 2510 2511 MMIO_D(PF_CTL(PIPE_C), D_ALL); 2512 MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL); 2513 MMIO_D(PF_WIN_POS(PIPE_C), D_ALL); 2514 MMIO_D(PF_VSCALE(PIPE_C), D_ALL); 2515 MMIO_D(PF_HSCALE(PIPE_C), D_ALL); 2516 2517 MMIO_D(WM0_PIPE_ILK(PIPE_A), D_ALL); 2518 MMIO_D(WM0_PIPE_ILK(PIPE_B), D_ALL); 2519 MMIO_D(WM0_PIPE_ILK(PIPE_C), D_ALL); 2520 MMIO_D(WM1_LP_ILK, D_ALL); 2521 MMIO_D(WM2_LP_ILK, D_ALL); 2522 MMIO_D(WM3_LP_ILK, D_ALL); 2523 MMIO_D(WM1S_LP_ILK, D_ALL); 2524 MMIO_D(WM2S_LP_IVB, D_ALL); 2525 MMIO_D(WM3S_LP_IVB, D_ALL); 2526 2527 MMIO_D(BLC_PWM_CPU_CTL2, D_ALL); 2528 MMIO_D(BLC_PWM_CPU_CTL, D_ALL); 2529 MMIO_D(BLC_PWM_PCH_CTL1, D_ALL); 2530 MMIO_D(BLC_PWM_PCH_CTL2, D_ALL); 2531 2532 MMIO_D(_MMIO(0x48268), D_ALL); 2533 2534 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read, 2535 gmbus_mmio_write); 2536 MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL); 2537 MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL); 2538 2539 MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 2540 dp_aux_ch_ctl_mmio_write); 2541 MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 2542 dp_aux_ch_ctl_mmio_write); 2543 MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 2544 dp_aux_ch_ctl_mmio_write); 2545 2546 MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write); 2547 2548 MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write); 2549 MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write); 2550 2551 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write); 2552 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write); 2553 MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write); 2554 MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); 2555 MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); 2556 MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); 2557 MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); 2558 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); 2559 MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); 2560 2561 MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A), D_ALL); 2562 MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A), D_ALL); 2563 MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A), D_ALL); 2564 MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A), D_ALL); 2565 MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A), D_ALL); 2566 MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A), D_ALL); 2567 MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A), D_ALL); 2568 2569 MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B), D_ALL); 2570 MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B), D_ALL); 2571 MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B), D_ALL); 2572 MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B), D_ALL); 2573 MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B), D_ALL); 2574 MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B), D_ALL); 2575 MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B), D_ALL); 2576 2577 MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1), D_ALL); 2578 MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1), D_ALL); 2579 MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2), D_ALL); 2580 MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2), D_ALL); 2581 MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1), D_ALL); 2582 MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1), D_ALL); 2583 MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2), D_ALL); 2584 MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2), D_ALL); 2585 2586 MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL); 2587 MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL); 2588 MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL); 2589 2590 MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL); 2591 MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL); 2592 MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL); 2593 2594 MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL); 2595 MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL); 2596 MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL); 2597 2598 MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL); 2599 MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL); 2600 MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL); 2601 2602 MMIO_D(_MMIO(_FDI_RXA_MISC), D_ALL); 2603 MMIO_D(_MMIO(_FDI_RXB_MISC), D_ALL); 2604 MMIO_D(_MMIO(_FDI_RXA_TUSIZE1), D_ALL); 2605 MMIO_D(_MMIO(_FDI_RXA_TUSIZE2), D_ALL); 2606 MMIO_D(_MMIO(_FDI_RXB_TUSIZE1), D_ALL); 2607 MMIO_D(_MMIO(_FDI_RXB_TUSIZE2), D_ALL); 2608 2609 MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write); 2610 MMIO_D(PCH_PP_DIVISOR, D_ALL); 2611 MMIO_D(PCH_PP_STATUS, D_ALL); 2612 MMIO_D(PCH_LVDS, D_ALL); 2613 MMIO_D(_MMIO(_PCH_DPLL_A), D_ALL); 2614 MMIO_D(_MMIO(_PCH_DPLL_B), D_ALL); 2615 MMIO_D(_MMIO(_PCH_FPA0), D_ALL); 2616 MMIO_D(_MMIO(_PCH_FPA1), D_ALL); 2617 MMIO_D(_MMIO(_PCH_FPB0), D_ALL); 2618 MMIO_D(_MMIO(_PCH_FPB1), D_ALL); 2619 MMIO_D(PCH_DREF_CONTROL, D_ALL); 2620 MMIO_D(PCH_RAWCLK_FREQ, D_ALL); 2621 MMIO_D(PCH_DPLL_SEL, D_ALL); 2622 2623 MMIO_D(_MMIO(0x61208), D_ALL); 2624 MMIO_D(_MMIO(0x6120c), D_ALL); 2625 MMIO_D(PCH_PP_ON_DELAYS, D_ALL); 2626 MMIO_D(PCH_PP_OFF_DELAYS, D_ALL); 2627 2628 MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL); 2629 MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL); 2630 MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL); 2631 MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL); 2632 MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL); 2633 MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL); 2634 2635 MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0, 2636 PORTA_HOTPLUG_STATUS_MASK 2637 | PORTB_HOTPLUG_STATUS_MASK 2638 | PORTC_HOTPLUG_STATUS_MASK 2639 | PORTD_HOTPLUG_STATUS_MASK, 2640 NULL, NULL); 2641 2642 MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write); 2643 MMIO_D(FUSE_STRAP, D_ALL); 2644 MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL); 2645 2646 MMIO_D(DISP_ARB_CTL, D_ALL); 2647 MMIO_D(DISP_ARB_CTL2, D_ALL); 2648 2649 MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL); 2650 MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL); 2651 MMIO_D(ILK_DSPCLK_GATE_D, D_ALL); 2652 2653 MMIO_D(SOUTH_CHICKEN1, D_ALL); 2654 MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write); 2655 MMIO_D(_MMIO(_TRANSA_CHICKEN1), D_ALL); 2656 MMIO_D(_MMIO(_TRANSB_CHICKEN1), D_ALL); 2657 MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL); 2658 MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL); 2659 MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL); 2660 2661 MMIO_D(ILK_DPFC_CB_BASE(INTEL_FBC_A), D_ALL); 2662 MMIO_D(ILK_DPFC_CONTROL(INTEL_FBC_A), D_ALL); 2663 MMIO_D(ILK_DPFC_RECOMP_CTL(INTEL_FBC_A), D_ALL); 2664 MMIO_D(ILK_DPFC_STATUS(INTEL_FBC_A), D_ALL); 2665 MMIO_D(ILK_DPFC_FENCE_YOFF(INTEL_FBC_A), D_ALL); 2666 MMIO_D(ILK_DPFC_CHICKEN(INTEL_FBC_A), D_ALL); 2667 MMIO_D(ILK_FBC_RT_BASE, D_ALL); 2668 2669 MMIO_D(IPS_CTL, D_ALL); 2670 2671 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL); 2672 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL); 2673 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL); 2674 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL); 2675 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL); 2676 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL); 2677 MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL); 2678 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL); 2679 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL); 2680 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL); 2681 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL); 2682 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL); 2683 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL); 2684 2685 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL); 2686 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL); 2687 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL); 2688 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL); 2689 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL); 2690 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL); 2691 MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL); 2692 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL); 2693 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL); 2694 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL); 2695 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL); 2696 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL); 2697 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL); 2698 2699 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL); 2700 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL); 2701 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL); 2702 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL); 2703 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL); 2704 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL); 2705 MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL); 2706 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL); 2707 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL); 2708 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL); 2709 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL); 2710 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL); 2711 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL); 2712 2713 MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL); 2714 MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL); 2715 MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 2716 2717 MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL); 2718 MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL); 2719 MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 2720 2721 MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL); 2722 MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL); 2723 MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 2724 2725 MMIO_D(_MMIO(0x60110), D_ALL); 2726 MMIO_D(_MMIO(0x61110), D_ALL); 2727 MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL); 2728 MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL); 2729 MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL); 2730 MMIO_F(_MMIO(0x70440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2731 MMIO_F(_MMIO(0x71440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2732 MMIO_F(_MMIO(0x72440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2733 MMIO_F(_MMIO(0x7044c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2734 MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2735 MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2736 2737 MMIO_D(WM_LINETIME(PIPE_A), D_ALL); 2738 MMIO_D(WM_LINETIME(PIPE_B), D_ALL); 2739 MMIO_D(WM_LINETIME(PIPE_C), D_ALL); 2740 MMIO_D(SPLL_CTL, D_ALL); 2741 MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL); 2742 MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL); 2743 MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL); 2744 MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL); 2745 MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL); 2746 MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL); 2747 MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL); 2748 MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL); 2749 MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL); 2750 MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL); 2751 2752 MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL); 2753 MMIO_D(_MMIO(0x46508), D_ALL); 2754 2755 MMIO_D(_MMIO(0x49080), D_ALL); 2756 MMIO_D(_MMIO(0x49180), D_ALL); 2757 MMIO_D(_MMIO(0x49280), D_ALL); 2758 2759 MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL); 2760 MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL); 2761 MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL); 2762 2763 MMIO_D(GAMMA_MODE(PIPE_A), D_ALL); 2764 MMIO_D(GAMMA_MODE(PIPE_B), D_ALL); 2765 MMIO_D(GAMMA_MODE(PIPE_C), D_ALL); 2766 2767 MMIO_D(PIPE_MULT(PIPE_A), D_ALL); 2768 MMIO_D(PIPE_MULT(PIPE_B), D_ALL); 2769 MMIO_D(PIPE_MULT(PIPE_C), D_ALL); 2770 2771 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL); 2772 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL); 2773 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL); 2774 2775 MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL); 2776 MMIO_D(SBI_ADDR, D_ALL); 2777 MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL); 2778 MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write); 2779 MMIO_D(PIXCLK_GATE, D_ALL); 2780 2781 MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL, 2782 dp_aux_ch_ctl_mmio_write); 2783 2784 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2785 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2786 MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2787 MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2788 MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2789 2790 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write); 2791 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write); 2792 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write); 2793 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write); 2794 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write); 2795 2796 MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write); 2797 MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write); 2798 MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write); 2799 MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write); 2800 MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL); 2801 2802 MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2803 MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2804 MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2805 MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2806 MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2807 2808 MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL); 2809 MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL); 2810 MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A), D_ALL); 2811 2812 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL); 2813 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL); 2814 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL); 2815 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL); 2816 2817 MMIO_D(_MMIO(_TRANSA_MSA_MISC), D_ALL); 2818 MMIO_D(_MMIO(_TRANSB_MSA_MISC), D_ALL); 2819 MMIO_D(_MMIO(_TRANSC_MSA_MISC), D_ALL); 2820 MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC), D_ALL); 2821 2822 MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL); 2823 MMIO_D(FORCEWAKE_ACK, D_ALL); 2824 MMIO_D(GEN6_GT_CORE_STATUS, D_ALL); 2825 MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL); 2826 MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL); 2827 MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL); 2828 MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write); 2829 MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL); 2830 MMIO_D(ECOBUS, D_ALL); 2831 MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL); 2832 MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL); 2833 MMIO_D(GEN6_RPNSWREQ, D_ALL); 2834 MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL); 2835 MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL); 2836 MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL); 2837 MMIO_D(GEN6_RPSTAT1, D_ALL); 2838 MMIO_D(GEN6_RP_CONTROL, D_ALL); 2839 MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL); 2840 MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL); 2841 MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL); 2842 MMIO_D(GEN6_RP_CUR_UP, D_ALL); 2843 MMIO_D(GEN6_RP_PREV_UP, D_ALL); 2844 MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL); 2845 MMIO_D(GEN6_RP_CUR_DOWN, D_ALL); 2846 MMIO_D(GEN6_RP_PREV_DOWN, D_ALL); 2847 MMIO_D(GEN6_RP_UP_EI, D_ALL); 2848 MMIO_D(GEN6_RP_DOWN_EI, D_ALL); 2849 MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL); 2850 MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL); 2851 MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL); 2852 MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL); 2853 MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL); 2854 MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL); 2855 MMIO_D(GEN6_RC_SLEEP, D_ALL); 2856 MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL); 2857 MMIO_D(GEN6_RC6_THRESHOLD, D_ALL); 2858 MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL); 2859 MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL); 2860 MMIO_D(GEN6_PMINTRMSK, D_ALL); 2861 MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write); 2862 MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write); 2863 MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write); 2864 MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write); 2865 MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write); 2866 MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write); 2867 2868 MMIO_D(RSTDBYCTL, D_ALL); 2869 2870 MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write); 2871 MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write); 2872 MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write); 2873 2874 MMIO_D(TILECTL, D_ALL); 2875 2876 MMIO_D(GEN6_UCGCTL1, D_ALL); 2877 MMIO_D(GEN6_UCGCTL2, D_ALL); 2878 2879 MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL); 2880 2881 MMIO_D(GEN6_PCODE_DATA, D_ALL); 2882 MMIO_D(_MMIO(0x13812c), D_ALL); 2883 MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL); 2884 MMIO_D(HSW_EDRAM_CAP, D_ALL); 2885 MMIO_D(HSW_IDICR, D_ALL); 2886 MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL); 2887 2888 MMIO_D(_MMIO(0x3c), D_ALL); 2889 MMIO_D(_MMIO(0x860), D_ALL); 2890 MMIO_D(ECOSKPD(RENDER_RING_BASE), D_ALL); 2891 MMIO_D(_MMIO(0x121d0), D_ALL); 2892 MMIO_D(ECOSKPD(BLT_RING_BASE), D_ALL); 2893 MMIO_D(_MMIO(0x41d0), D_ALL); 2894 MMIO_D(GAC_ECO_BITS, D_ALL); 2895 MMIO_D(_MMIO(0x6200), D_ALL); 2896 MMIO_D(_MMIO(0x6204), D_ALL); 2897 MMIO_D(_MMIO(0x6208), D_ALL); 2898 MMIO_D(_MMIO(0x7118), D_ALL); 2899 MMIO_D(_MMIO(0x7180), D_ALL); 2900 MMIO_D(_MMIO(0x7408), D_ALL); 2901 MMIO_D(_MMIO(0x7c00), D_ALL); 2902 MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write); 2903 MMIO_D(_MMIO(0x911c), D_ALL); 2904 MMIO_D(_MMIO(0x9120), D_ALL); 2905 MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL); 2906 2907 MMIO_D(GAB_CTL, D_ALL); 2908 MMIO_D(_MMIO(0x48800), D_ALL); 2909 MMIO_D(_MMIO(0xce044), D_ALL); 2910 MMIO_D(_MMIO(0xe6500), D_ALL); 2911 MMIO_D(_MMIO(0xe6504), D_ALL); 2912 MMIO_D(_MMIO(0xe6600), D_ALL); 2913 MMIO_D(_MMIO(0xe6604), D_ALL); 2914 MMIO_D(_MMIO(0xe6700), D_ALL); 2915 MMIO_D(_MMIO(0xe6704), D_ALL); 2916 MMIO_D(_MMIO(0xe6800), D_ALL); 2917 MMIO_D(_MMIO(0xe6804), D_ALL); 2918 MMIO_D(PCH_GMBUS4, D_ALL); 2919 MMIO_D(PCH_GMBUS5, D_ALL); 2920 2921 MMIO_D(_MMIO(0x902c), D_ALL); 2922 MMIO_D(_MMIO(0xec008), D_ALL); 2923 MMIO_D(_MMIO(0xec00c), D_ALL); 2924 MMIO_D(_MMIO(0xec008 + 0x18), D_ALL); 2925 MMIO_D(_MMIO(0xec00c + 0x18), D_ALL); 2926 MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL); 2927 MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL); 2928 MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL); 2929 MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL); 2930 MMIO_D(_MMIO(0xec408), D_ALL); 2931 MMIO_D(_MMIO(0xec40c), D_ALL); 2932 MMIO_D(_MMIO(0xec408 + 0x18), D_ALL); 2933 MMIO_D(_MMIO(0xec40c + 0x18), D_ALL); 2934 MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL); 2935 MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL); 2936 MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL); 2937 MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL); 2938 MMIO_D(_MMIO(0xfc810), D_ALL); 2939 MMIO_D(_MMIO(0xfc81c), D_ALL); 2940 MMIO_D(_MMIO(0xfc828), D_ALL); 2941 MMIO_D(_MMIO(0xfc834), D_ALL); 2942 MMIO_D(_MMIO(0xfcc00), D_ALL); 2943 MMIO_D(_MMIO(0xfcc0c), D_ALL); 2944 MMIO_D(_MMIO(0xfcc18), D_ALL); 2945 MMIO_D(_MMIO(0xfcc24), D_ALL); 2946 MMIO_D(_MMIO(0xfd000), D_ALL); 2947 MMIO_D(_MMIO(0xfd00c), D_ALL); 2948 MMIO_D(_MMIO(0xfd018), D_ALL); 2949 MMIO_D(_MMIO(0xfd024), D_ALL); 2950 MMIO_D(_MMIO(0xfd034), D_ALL); 2951 2952 MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write); 2953 MMIO_D(_MMIO(0x2054), D_ALL); 2954 MMIO_D(_MMIO(0x12054), D_ALL); 2955 MMIO_D(_MMIO(0x22054), D_ALL); 2956 MMIO_D(_MMIO(0x1a054), D_ALL); 2957 2958 MMIO_D(_MMIO(0x44070), D_ALL); 2959 MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2960 MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL); 2961 MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL); 2962 MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL); 2963 MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL); 2964 2965 MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL); 2966 MMIO_D(_MMIO(0x2b00), D_BDW_PLUS); 2967 MMIO_D(_MMIO(0x2360), D_BDW_PLUS); 2968 MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2969 MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2970 MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2971 2972 MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2973 MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2974 MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL); 2975 2976 MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2977 MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2978 MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2979 MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2980 MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2981 MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2982 MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2983 MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2984 MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2985 MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2986 MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2987 MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2988 MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2989 MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2990 MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2991 MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2992 MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2993 2994 MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2995 MMIO_RING_GM(RING_BBADDR, D_ALL, NULL, NULL); 2996 MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL); 2997 MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL); 2998 MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL); 2999 MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL); 3000 MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL); 3001 MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 3002 MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 3003 MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 3004 MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 3005 3006 MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write); 3007 MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write); 3008 MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL); 3009 3010 return 0; 3011 } 3012 3013 static int init_bdw_mmio_info(struct intel_gvt *gvt) 3014 { 3015 struct drm_i915_private *dev_priv = gvt->gt->i915; 3016 int ret; 3017 3018 MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 3019 MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 3020 MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 3021 MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS); 3022 3023 MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 3024 MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 3025 MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 3026 MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS); 3027 3028 MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 3029 MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 3030 MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 3031 MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS); 3032 3033 MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 3034 MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 3035 MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 3036 MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS); 3037 3038 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL, 3039 intel_vgpu_reg_imr_handler); 3040 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL, 3041 intel_vgpu_reg_ier_handler); 3042 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL, 3043 intel_vgpu_reg_iir_handler); 3044 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS); 3045 3046 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL, 3047 intel_vgpu_reg_imr_handler); 3048 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL, 3049 intel_vgpu_reg_ier_handler); 3050 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL, 3051 intel_vgpu_reg_iir_handler); 3052 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS); 3053 3054 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL, 3055 intel_vgpu_reg_imr_handler); 3056 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL, 3057 intel_vgpu_reg_ier_handler); 3058 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL, 3059 intel_vgpu_reg_iir_handler); 3060 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS); 3061 3062 MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 3063 MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 3064 MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 3065 MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS); 3066 3067 MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 3068 MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 3069 MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 3070 MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS); 3071 3072 MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 3073 MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 3074 MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 3075 MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS); 3076 3077 MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL, 3078 intel_vgpu_reg_master_irq_handler); 3079 3080 MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, 0, 3081 mmio_read_from_hw, NULL); 3082 3083 #define RING_REG(base) _MMIO((base) + 0xd0) 3084 MMIO_RING_F(RING_REG, 4, F_RO, 0, 3085 ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL, 3086 ring_reset_ctl_write); 3087 #undef RING_REG 3088 3089 #define RING_REG(base) _MMIO((base) + 0x230) 3090 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write); 3091 #undef RING_REG 3092 3093 #define RING_REG(base) _MMIO((base) + 0x234) 3094 MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS, 3095 NULL, NULL); 3096 #undef RING_REG 3097 3098 #define RING_REG(base) _MMIO((base) + 0x244) 3099 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 3100 #undef RING_REG 3101 3102 #define RING_REG(base) _MMIO((base) + 0x370) 3103 MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL); 3104 #undef RING_REG 3105 3106 #define RING_REG(base) _MMIO((base) + 0x3a0) 3107 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 3108 #undef RING_REG 3109 3110 MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS); 3111 MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS); 3112 MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS); 3113 MMIO_D(_MMIO(0x1c1d0), D_BDW_PLUS); 3114 MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS); 3115 MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS); 3116 MMIO_D(_MMIO(0x1c054), D_BDW_PLUS); 3117 3118 MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write); 3119 3120 MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS & ~D_BXT); 3121 MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS); 3122 3123 MMIO_D(GAMTARBMODE, D_BDW_PLUS); 3124 3125 #define RING_REG(base) _MMIO((base) + 0x270) 3126 MMIO_RING_F(RING_REG, 32, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL); 3127 #undef RING_REG 3128 3129 MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write); 3130 3131 MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 3132 3133 MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS); 3134 MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS); 3135 MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS); 3136 3137 MMIO_D(WM_MISC, D_BDW); 3138 MMIO_D(_MMIO(_SRD_CTL_EDP), D_BDW); 3139 3140 MMIO_D(_MMIO(0x6671c), D_BDW_PLUS); 3141 MMIO_D(_MMIO(0x66c00), D_BDW_PLUS); 3142 MMIO_D(_MMIO(0x66c04), D_BDW_PLUS); 3143 3144 MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS); 3145 3146 MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS); 3147 MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS); 3148 MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS); 3149 3150 MMIO_D(_MMIO(0xfdc), D_BDW_PLUS); 3151 MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, 3152 NULL, NULL); 3153 MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, 3154 NULL, NULL); 3155 MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 3156 3157 MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL); 3158 MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL); 3159 MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 3160 MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL); 3161 MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL); 3162 MMIO_D(_MMIO(0xb110), D_BDW); 3163 MMIO_D(GEN9_SCRATCH_LNCF1, D_BDW_PLUS); 3164 3165 MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS | F_CMD_WRITE_PATCH, 0, 0, 3166 D_BDW_PLUS, NULL, force_nonpriv_write); 3167 3168 MMIO_D(_MMIO(0x44484), D_BDW_PLUS); 3169 MMIO_D(_MMIO(0x4448c), D_BDW_PLUS); 3170 3171 MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL); 3172 MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS); 3173 3174 MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL); 3175 3176 MMIO_D(_MMIO(0x110000), D_BDW_PLUS); 3177 3178 MMIO_D(_MMIO(0x48400), D_BDW_PLUS); 3179 3180 MMIO_D(_MMIO(0x6e570), D_BDW_PLUS); 3181 MMIO_D(_MMIO(0x65f10), D_BDW_PLUS); 3182 3183 MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 3184 MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 3185 MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 3186 MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 3187 3188 MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL); 3189 3190 MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 3191 MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 3192 MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 3193 MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 3194 MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 3195 MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 3196 MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 3197 MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 3198 MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 3199 MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 3200 return 0; 3201 } 3202 3203 static int init_skl_mmio_info(struct intel_gvt *gvt) 3204 { 3205 struct drm_i915_private *dev_priv = gvt->gt->i915; 3206 int ret; 3207 3208 MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 3209 MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL); 3210 MMIO_DH(FORCEWAKE_GT_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 3211 MMIO_DH(FORCEWAKE_ACK_GT_GEN9, D_SKL_PLUS, NULL, NULL); 3212 MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 3213 MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL); 3214 3215 MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 3216 dp_aux_ch_ctl_mmio_write); 3217 MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 3218 dp_aux_ch_ctl_mmio_write); 3219 MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 3220 dp_aux_ch_ctl_mmio_write); 3221 3222 MMIO_D(HSW_PWR_WELL_CTL1, D_SKL_PLUS); 3223 MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write); 3224 3225 MMIO_DH(DBUF_CTL_S(0), D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write); 3226 3227 MMIO_D(GEN9_PG_ENABLE, D_SKL_PLUS); 3228 MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS); 3229 MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS); 3230 MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 3231 MMIO_DFH(MMCD_MISC_CTRL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 3232 MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL); 3233 MMIO_D(DC_STATE_EN, D_SKL_PLUS); 3234 MMIO_D(DC_STATE_DEBUG, D_SKL_PLUS); 3235 MMIO_D(CDCLK_CTL, D_SKL_PLUS); 3236 MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write); 3237 MMIO_DH(LCPLL2_CTL, D_SKL_PLUS, NULL, skl_lcpll_write); 3238 MMIO_D(_MMIO(_DPLL1_CFGCR1), D_SKL_PLUS); 3239 MMIO_D(_MMIO(_DPLL2_CFGCR1), D_SKL_PLUS); 3240 MMIO_D(_MMIO(_DPLL3_CFGCR1), D_SKL_PLUS); 3241 MMIO_D(_MMIO(_DPLL1_CFGCR2), D_SKL_PLUS); 3242 MMIO_D(_MMIO(_DPLL2_CFGCR2), D_SKL_PLUS); 3243 MMIO_D(_MMIO(_DPLL3_CFGCR2), D_SKL_PLUS); 3244 MMIO_D(DPLL_CTRL1, D_SKL_PLUS); 3245 MMIO_D(DPLL_CTRL2, D_SKL_PLUS); 3246 MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL); 3247 3248 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); 3249 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); 3250 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); 3251 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); 3252 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); 3253 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); 3254 3255 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); 3256 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); 3257 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); 3258 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); 3259 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); 3260 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); 3261 3262 MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); 3263 MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); 3264 MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); 3265 MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); 3266 MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); 3267 MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); 3268 3269 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 3270 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 3271 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 3272 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); 3273 3274 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 3275 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 3276 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 3277 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); 3278 3279 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 3280 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 3281 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 3282 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); 3283 3284 MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL); 3285 MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL); 3286 MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL); 3287 3288 MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 3289 MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 3290 MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 3291 3292 MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 3293 MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 3294 MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 3295 3296 MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 3297 MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 3298 MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 3299 3300 MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 3301 MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 3302 MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 3303 3304 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 3305 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 3306 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 3307 3308 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 3309 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 3310 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 3311 3312 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 3313 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 3314 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 3315 3316 MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL); 3317 MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL); 3318 MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL); 3319 3320 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 3321 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 3322 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 3323 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); 3324 3325 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 3326 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 3327 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 3328 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); 3329 3330 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 3331 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 3332 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 3333 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); 3334 3335 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL); 3336 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL); 3337 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL); 3338 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL); 3339 3340 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL); 3341 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL); 3342 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL); 3343 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL); 3344 3345 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL); 3346 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL); 3347 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL); 3348 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL); 3349 3350 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL); 3351 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL); 3352 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL); 3353 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL); 3354 3355 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL); 3356 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL); 3357 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL); 3358 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL); 3359 3360 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL); 3361 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL); 3362 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL); 3363 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL); 3364 3365 MMIO_D(_MMIO(_PLANE_CTL_3_A), D_SKL_PLUS); 3366 MMIO_D(_MMIO(_PLANE_CTL_3_B), D_SKL_PLUS); 3367 MMIO_D(_MMIO(0x72380), D_SKL_PLUS); 3368 MMIO_D(_MMIO(0x7239c), D_SKL_PLUS); 3369 MMIO_D(_MMIO(_PLANE_SURF_3_A), D_SKL_PLUS); 3370 MMIO_D(_MMIO(_PLANE_SURF_3_B), D_SKL_PLUS); 3371 3372 MMIO_D(DMC_SSP_BASE, D_SKL_PLUS); 3373 MMIO_D(DMC_HTP_SKL, D_SKL_PLUS); 3374 MMIO_D(DMC_LAST_WRITE, D_SKL_PLUS); 3375 3376 MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 3377 3378 MMIO_D(SKL_DFSM, D_SKL_PLUS); 3379 MMIO_D(DISPIO_CR_TX_BMU_CR0, D_SKL_PLUS); 3380 3381 MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS, 3382 NULL, NULL); 3383 MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS, 3384 NULL, NULL); 3385 3386 MMIO_D(RPM_CONFIG0, D_SKL_PLUS); 3387 MMIO_D(_MMIO(0xd08), D_SKL_PLUS); 3388 MMIO_D(RC6_LOCATION, D_SKL_PLUS); 3389 MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS, 3390 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 3391 MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, 3392 NULL, NULL); 3393 3394 /* TRTT */ 3395 MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 3396 MMIO_DFH(TRVATTL3PTRDW(1), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 3397 MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 3398 MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 3399 MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 3400 MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS | F_PM_SAVE, 3401 NULL, gen9_trtte_write); 3402 MMIO_DFH(_MMIO(0x4dfc), D_SKL_PLUS, F_PM_SAVE, 3403 NULL, gen9_trtt_chicken_write); 3404 3405 MMIO_D(_MMIO(0x46430), D_SKL_PLUS); 3406 3407 MMIO_D(_MMIO(0x46520), D_SKL_PLUS); 3408 3409 MMIO_D(_MMIO(0xc403c), D_SKL_PLUS); 3410 MMIO_DFH(GEN8_GARBCNTL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 3411 MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write); 3412 3413 MMIO_D(_MMIO(0x65900), D_SKL_PLUS); 3414 MMIO_D(GEN6_STOLEN_RESERVED, D_SKL_PLUS); 3415 MMIO_D(_MMIO(0x4068), D_SKL_PLUS); 3416 MMIO_D(_MMIO(0x67054), D_SKL_PLUS); 3417 MMIO_D(_MMIO(0x6e560), D_SKL_PLUS); 3418 MMIO_D(_MMIO(0x6e554), D_SKL_PLUS); 3419 MMIO_D(_MMIO(0x2b20), D_SKL_PLUS); 3420 MMIO_D(_MMIO(0x65f00), D_SKL_PLUS); 3421 MMIO_D(_MMIO(0x65f08), D_SKL_PLUS); 3422 MMIO_D(_MMIO(0x320f0), D_SKL_PLUS); 3423 3424 MMIO_D(_MMIO(0x70034), D_SKL_PLUS); 3425 MMIO_D(_MMIO(0x71034), D_SKL_PLUS); 3426 MMIO_D(_MMIO(0x72034), D_SKL_PLUS); 3427 3428 MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A)), D_SKL_PLUS); 3429 MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B)), D_SKL_PLUS); 3430 MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C)), D_SKL_PLUS); 3431 MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A)), D_SKL_PLUS); 3432 MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B)), D_SKL_PLUS); 3433 MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C)), D_SKL_PLUS); 3434 MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A)), D_SKL_PLUS); 3435 MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)), D_SKL_PLUS); 3436 MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)), D_SKL_PLUS); 3437 3438 MMIO_D(_MMIO(0x44500), D_SKL_PLUS); 3439 #define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4) 3440 MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, 3441 NULL, csfe_chicken1_mmio_write); 3442 #undef CSFE_CHICKEN1_REG 3443 MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, 3444 NULL, NULL); 3445 MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, 3446 NULL, NULL); 3447 3448 MMIO_DFH(GAMT_CHKN_BIT_REG, D_KBL | D_CFL, F_CMD_ACCESS, NULL, NULL); 3449 MMIO_D(GEN9_CTX_PREEMPT_REG, D_SKL_PLUS & ~D_BXT); 3450 MMIO_DFH(_MMIO(0xe4cc), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 3451 3452 return 0; 3453 } 3454 3455 static int init_bxt_mmio_info(struct intel_gvt *gvt) 3456 { 3457 struct drm_i915_private *dev_priv = gvt->gt->i915; 3458 int ret; 3459 3460 MMIO_F(_MMIO(0x80000), 0x3000, 0, 0, 0, D_BXT, NULL, NULL); 3461 3462 MMIO_D(GEN7_SAMPLER_INSTDONE, D_BXT); 3463 MMIO_D(GEN7_ROW_INSTDONE, D_BXT); 3464 MMIO_D(GEN8_FAULT_TLB_DATA0, D_BXT); 3465 MMIO_D(GEN8_FAULT_TLB_DATA1, D_BXT); 3466 MMIO_D(ERROR_GEN6, D_BXT); 3467 MMIO_D(DONE_REG, D_BXT); 3468 MMIO_D(EIR, D_BXT); 3469 MMIO_D(PGTBL_ER, D_BXT); 3470 MMIO_D(_MMIO(0x4194), D_BXT); 3471 MMIO_D(_MMIO(0x4294), D_BXT); 3472 MMIO_D(_MMIO(0x4494), D_BXT); 3473 3474 MMIO_RING_D(RING_PSMI_CTL, D_BXT); 3475 MMIO_RING_D(RING_DMA_FADD, D_BXT); 3476 MMIO_RING_D(RING_DMA_FADD_UDW, D_BXT); 3477 MMIO_RING_D(RING_IPEHR, D_BXT); 3478 MMIO_RING_D(RING_INSTPS, D_BXT); 3479 MMIO_RING_D(RING_BBADDR_UDW, D_BXT); 3480 MMIO_RING_D(RING_BBSTATE, D_BXT); 3481 MMIO_RING_D(RING_IPEIR, D_BXT); 3482 3483 MMIO_F(SOFT_SCRATCH(0), 16 * 4, 0, 0, 0, D_BXT, NULL, NULL); 3484 3485 MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write); 3486 MMIO_D(BXT_RP_STATE_CAP, D_BXT); 3487 MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT, 3488 NULL, bxt_phy_ctl_family_write); 3489 MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT, 3490 NULL, bxt_phy_ctl_family_write); 3491 MMIO_D(BXT_PHY_CTL(PORT_A), D_BXT); 3492 MMIO_D(BXT_PHY_CTL(PORT_B), D_BXT); 3493 MMIO_D(BXT_PHY_CTL(PORT_C), D_BXT); 3494 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT, 3495 NULL, bxt_port_pll_enable_write); 3496 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT, 3497 NULL, bxt_port_pll_enable_write); 3498 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL, 3499 bxt_port_pll_enable_write); 3500 3501 MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY0), D_BXT); 3502 MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY0), D_BXT); 3503 MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY0), D_BXT); 3504 MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY0), D_BXT); 3505 MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY0), D_BXT); 3506 MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY0), D_BXT); 3507 MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY0), D_BXT); 3508 MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY0), D_BXT); 3509 MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY0), D_BXT); 3510 3511 MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY1), D_BXT); 3512 MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY1), D_BXT); 3513 MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY1), D_BXT); 3514 MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY1), D_BXT); 3515 MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY1), D_BXT); 3516 MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY1), D_BXT); 3517 MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY1), D_BXT); 3518 MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY1), D_BXT); 3519 MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY1), D_BXT); 3520 3521 MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH0), D_BXT); 3522 MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH0), D_BXT); 3523 MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH0), D_BXT); 3524 MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH0), D_BXT); 3525 MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH0), D_BXT); 3526 MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH0), D_BXT); 3527 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT, 3528 NULL, bxt_pcs_dw12_grp_write); 3529 MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH0), D_BXT); 3530 MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH0), D_BXT); 3531 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT, 3532 bxt_port_tx_dw3_read, NULL); 3533 MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH0), D_BXT); 3534 MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH0), D_BXT); 3535 MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH0), D_BXT); 3536 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT); 3537 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 1), D_BXT); 3538 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 2), D_BXT); 3539 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 3), D_BXT); 3540 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 0), D_BXT); 3541 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 1), D_BXT); 3542 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 2), D_BXT); 3543 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 3), D_BXT); 3544 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 6), D_BXT); 3545 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 8), D_BXT); 3546 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 9), D_BXT); 3547 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 10), D_BXT); 3548 3549 MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH1), D_BXT); 3550 MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH1), D_BXT); 3551 MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH1), D_BXT); 3552 MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH1), D_BXT); 3553 MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH1), D_BXT); 3554 MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH1), D_BXT); 3555 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT, 3556 NULL, bxt_pcs_dw12_grp_write); 3557 MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH1), D_BXT); 3558 MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH1), D_BXT); 3559 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT, 3560 bxt_port_tx_dw3_read, NULL); 3561 MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH1), D_BXT); 3562 MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH1), D_BXT); 3563 MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH1), D_BXT); 3564 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT); 3565 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 1), D_BXT); 3566 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 2), D_BXT); 3567 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 3), D_BXT); 3568 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 0), D_BXT); 3569 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 1), D_BXT); 3570 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 2), D_BXT); 3571 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 3), D_BXT); 3572 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 6), D_BXT); 3573 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 8), D_BXT); 3574 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 9), D_BXT); 3575 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 10), D_BXT); 3576 3577 MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY1, DPIO_CH0), D_BXT); 3578 MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY1, DPIO_CH0), D_BXT); 3579 MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY1, DPIO_CH0), D_BXT); 3580 MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY1, DPIO_CH0), D_BXT); 3581 MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY1, DPIO_CH0), D_BXT); 3582 MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY1, DPIO_CH0), D_BXT); 3583 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT, 3584 NULL, bxt_pcs_dw12_grp_write); 3585 MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY1, DPIO_CH0), D_BXT); 3586 MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY1, DPIO_CH0), D_BXT); 3587 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT, 3588 bxt_port_tx_dw3_read, NULL); 3589 MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY1, DPIO_CH0), D_BXT); 3590 MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY1, DPIO_CH0), D_BXT); 3591 MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY1, DPIO_CH0), D_BXT); 3592 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT); 3593 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 1), D_BXT); 3594 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 2), D_BXT); 3595 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 3), D_BXT); 3596 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 0), D_BXT); 3597 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 1), D_BXT); 3598 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 2), D_BXT); 3599 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 3), D_BXT); 3600 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 6), D_BXT); 3601 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 8), D_BXT); 3602 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 9), D_BXT); 3603 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 10), D_BXT); 3604 3605 MMIO_D(BXT_DE_PLL_CTL, D_BXT); 3606 MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write); 3607 MMIO_D(BXT_DSI_PLL_CTL, D_BXT); 3608 MMIO_D(BXT_DSI_PLL_ENABLE, D_BXT); 3609 3610 MMIO_D(GEN9_CLKGATE_DIS_0, D_BXT); 3611 MMIO_D(GEN9_CLKGATE_DIS_4, D_BXT); 3612 3613 MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_A), D_BXT); 3614 MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT); 3615 MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C), D_BXT); 3616 3617 MMIO_D(RC6_CTX_BASE, D_BXT); 3618 3619 MMIO_D(GEN8_PUSHBUS_CONTROL, D_BXT); 3620 MMIO_D(GEN8_PUSHBUS_ENABLE, D_BXT); 3621 MMIO_D(GEN8_PUSHBUS_SHIFT, D_BXT); 3622 MMIO_D(GEN6_GFXPAUSE, D_BXT); 3623 MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL); 3624 MMIO_DFH(GEN8_L3CNTLREG, D_BXT, F_CMD_ACCESS, NULL, NULL); 3625 MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL); 3626 MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS, 3627 0, 0, D_BXT, NULL, NULL); 3628 MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS, 3629 0, 0, D_BXT, NULL, NULL); 3630 MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS, 3631 0, 0, D_BXT, NULL, NULL); 3632 MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS, 3633 0, 0, D_BXT, NULL, NULL); 3634 3635 MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL); 3636 3637 MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BXT, NULL, bxt_ppat_low_write); 3638 3639 return 0; 3640 } 3641 3642 static const struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt, 3643 unsigned int offset) 3644 { 3645 unsigned long device = intel_gvt_get_device_type(gvt); 3646 const struct gvt_mmio_block *block = gvt->mmio.mmio_block; 3647 int num = gvt->mmio.num_mmio_block; 3648 int i; 3649 3650 for (i = 0; i < num; i++, block++) { 3651 if (!(device & block->device)) 3652 continue; 3653 if (offset >= i915_mmio_reg_offset(block->offset) && 3654 offset < i915_mmio_reg_offset(block->offset) + block->size) 3655 return block; 3656 } 3657 return NULL; 3658 } 3659 3660 /** 3661 * intel_gvt_clean_mmio_info - clean up MMIO information table for GVT device 3662 * @gvt: GVT device 3663 * 3664 * This function is called at the driver unloading stage, to clean up the MMIO 3665 * information table of GVT device 3666 * 3667 */ 3668 void intel_gvt_clean_mmio_info(struct intel_gvt *gvt) 3669 { 3670 struct hlist_node *tmp; 3671 struct intel_gvt_mmio_info *e; 3672 int i; 3673 3674 hash_for_each_safe(gvt->mmio.mmio_info_table, i, tmp, e, node) 3675 kfree(e); 3676 3677 vfree(gvt->mmio.mmio_attribute); 3678 gvt->mmio.mmio_attribute = NULL; 3679 } 3680 3681 /* Special MMIO blocks. registers in MMIO block ranges should not be command 3682 * accessible (should have no F_CMD_ACCESS flag). 3683 * otherwise, need to update cmd_reg_handler in cmd_parser.c 3684 */ 3685 static const struct gvt_mmio_block mmio_blocks[] = { 3686 {D_SKL_PLUS, _MMIO(DMC_MMIO_START_RANGE), 0x3000, NULL, NULL}, 3687 {D_ALL, _MMIO(MCHBAR_MIRROR_BASE_SNB), 0x40000, NULL, NULL}, 3688 {D_ALL, _MMIO(VGT_PVINFO_PAGE), VGT_PVINFO_SIZE, 3689 pvinfo_mmio_read, pvinfo_mmio_write}, 3690 {D_ALL, LGC_PALETTE(PIPE_A, 0), 1024, NULL, NULL}, 3691 {D_ALL, LGC_PALETTE(PIPE_B, 0), 1024, NULL, NULL}, 3692 {D_ALL, LGC_PALETTE(PIPE_C, 0), 1024, NULL, NULL}, 3693 }; 3694 3695 /** 3696 * intel_gvt_setup_mmio_info - setup MMIO information table for GVT device 3697 * @gvt: GVT device 3698 * 3699 * This function is called at the initialization stage, to setup the MMIO 3700 * information table for GVT device 3701 * 3702 * Returns: 3703 * zero on success, negative if failed. 3704 */ 3705 int intel_gvt_setup_mmio_info(struct intel_gvt *gvt) 3706 { 3707 struct intel_gvt_device_info *info = &gvt->device_info; 3708 struct drm_i915_private *i915 = gvt->gt->i915; 3709 int size = info->mmio_size / 4 * sizeof(*gvt->mmio.mmio_attribute); 3710 int ret; 3711 3712 gvt->mmio.mmio_attribute = vzalloc(size); 3713 if (!gvt->mmio.mmio_attribute) 3714 return -ENOMEM; 3715 3716 ret = init_generic_mmio_info(gvt); 3717 if (ret) 3718 goto err; 3719 3720 if (IS_BROADWELL(i915)) { 3721 ret = init_bdw_mmio_info(gvt); 3722 if (ret) 3723 goto err; 3724 } else if (IS_SKYLAKE(i915) || 3725 IS_KABYLAKE(i915) || 3726 IS_COFFEELAKE(i915) || 3727 IS_COMETLAKE(i915)) { 3728 ret = init_bdw_mmio_info(gvt); 3729 if (ret) 3730 goto err; 3731 ret = init_skl_mmio_info(gvt); 3732 if (ret) 3733 goto err; 3734 } else if (IS_BROXTON(i915)) { 3735 ret = init_bdw_mmio_info(gvt); 3736 if (ret) 3737 goto err; 3738 ret = init_skl_mmio_info(gvt); 3739 if (ret) 3740 goto err; 3741 ret = init_bxt_mmio_info(gvt); 3742 if (ret) 3743 goto err; 3744 } 3745 3746 gvt->mmio.mmio_block = mmio_blocks; 3747 gvt->mmio.num_mmio_block = ARRAY_SIZE(mmio_blocks); 3748 3749 return 0; 3750 err: 3751 intel_gvt_clean_mmio_info(gvt); 3752 return ret; 3753 } 3754 3755 /** 3756 * intel_gvt_for_each_tracked_mmio - iterate each tracked mmio 3757 * @gvt: a GVT device 3758 * @handler: the handler 3759 * @data: private data given to handler 3760 * 3761 * Returns: 3762 * Zero on success, negative error code if failed. 3763 */ 3764 int intel_gvt_for_each_tracked_mmio(struct intel_gvt *gvt, 3765 int (*handler)(struct intel_gvt *gvt, u32 offset, void *data), 3766 void *data) 3767 { 3768 const struct gvt_mmio_block *block = gvt->mmio.mmio_block; 3769 struct intel_gvt_mmio_info *e; 3770 int i, j, ret; 3771 3772 hash_for_each(gvt->mmio.mmio_info_table, i, e, node) { 3773 ret = handler(gvt, e->offset, data); 3774 if (ret) 3775 return ret; 3776 } 3777 3778 for (i = 0; i < gvt->mmio.num_mmio_block; i++, block++) { 3779 /* pvinfo data doesn't come from hw mmio */ 3780 if (i915_mmio_reg_offset(block->offset) == VGT_PVINFO_PAGE) 3781 continue; 3782 3783 for (j = 0; j < block->size; j += 4) { 3784 ret = handler(gvt, 3785 i915_mmio_reg_offset(block->offset) + j, 3786 data); 3787 if (ret) 3788 return ret; 3789 } 3790 } 3791 return 0; 3792 } 3793 3794 /** 3795 * intel_vgpu_default_mmio_read - default MMIO read handler 3796 * @vgpu: a vGPU 3797 * @offset: access offset 3798 * @p_data: data return buffer 3799 * @bytes: access data length 3800 * 3801 * Returns: 3802 * Zero on success, negative error code if failed. 3803 */ 3804 int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 3805 void *p_data, unsigned int bytes) 3806 { 3807 read_vreg(vgpu, offset, p_data, bytes); 3808 return 0; 3809 } 3810 3811 /** 3812 * intel_t_default_mmio_write - default MMIO write handler 3813 * @vgpu: a vGPU 3814 * @offset: access offset 3815 * @p_data: write data buffer 3816 * @bytes: access data length 3817 * 3818 * Returns: 3819 * Zero on success, negative error code if failed. 3820 */ 3821 int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 3822 void *p_data, unsigned int bytes) 3823 { 3824 write_vreg(vgpu, offset, p_data, bytes); 3825 return 0; 3826 } 3827 3828 /** 3829 * intel_vgpu_mask_mmio_write - write mask register 3830 * @vgpu: a vGPU 3831 * @offset: access offset 3832 * @p_data: write data buffer 3833 * @bytes: access data length 3834 * 3835 * Returns: 3836 * Zero on success, negative error code if failed. 3837 */ 3838 int intel_vgpu_mask_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 3839 void *p_data, unsigned int bytes) 3840 { 3841 u32 mask, old_vreg; 3842 3843 old_vreg = vgpu_vreg(vgpu, offset); 3844 write_vreg(vgpu, offset, p_data, bytes); 3845 mask = vgpu_vreg(vgpu, offset) >> 16; 3846 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask) | 3847 (vgpu_vreg(vgpu, offset) & mask); 3848 3849 return 0; 3850 } 3851 3852 /** 3853 * intel_gvt_in_force_nonpriv_whitelist - if a mmio is in whitelist to be 3854 * force-nopriv register 3855 * 3856 * @gvt: a GVT device 3857 * @offset: register offset 3858 * 3859 * Returns: 3860 * True if the register is in force-nonpriv whitelist; 3861 * False if outside; 3862 */ 3863 bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt, 3864 unsigned int offset) 3865 { 3866 return in_whitelist(offset); 3867 } 3868 3869 /** 3870 * intel_vgpu_mmio_reg_rw - emulate tracked mmio registers 3871 * @vgpu: a vGPU 3872 * @offset: register offset 3873 * @pdata: data buffer 3874 * @bytes: data length 3875 * @is_read: read or write 3876 * 3877 * Returns: 3878 * Zero on success, negative error code if failed. 3879 */ 3880 int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset, 3881 void *pdata, unsigned int bytes, bool is_read) 3882 { 3883 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 3884 struct intel_gvt *gvt = vgpu->gvt; 3885 struct intel_gvt_mmio_info *mmio_info; 3886 const struct gvt_mmio_block *mmio_block; 3887 gvt_mmio_func func; 3888 int ret; 3889 3890 if (drm_WARN_ON(&i915->drm, bytes > 8)) 3891 return -EINVAL; 3892 3893 /* 3894 * Handle special MMIO blocks. 3895 */ 3896 mmio_block = find_mmio_block(gvt, offset); 3897 if (mmio_block) { 3898 func = is_read ? mmio_block->read : mmio_block->write; 3899 if (func) 3900 return func(vgpu, offset, pdata, bytes); 3901 goto default_rw; 3902 } 3903 3904 /* 3905 * Normal tracked MMIOs. 3906 */ 3907 mmio_info = intel_gvt_find_mmio_info(gvt, offset); 3908 if (!mmio_info) { 3909 gvt_dbg_mmio("untracked MMIO %08x len %d\n", offset, bytes); 3910 goto default_rw; 3911 } 3912 3913 if (is_read) 3914 return mmio_info->read(vgpu, offset, pdata, bytes); 3915 else { 3916 u64 ro_mask = mmio_info->ro_mask; 3917 u32 old_vreg = 0; 3918 u64 data = 0; 3919 3920 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) { 3921 old_vreg = vgpu_vreg(vgpu, offset); 3922 } 3923 3924 if (likely(!ro_mask)) 3925 ret = mmio_info->write(vgpu, offset, pdata, bytes); 3926 else if (!~ro_mask) { 3927 gvt_vgpu_err("try to write RO reg %x\n", offset); 3928 return 0; 3929 } else { 3930 /* keep the RO bits in the virtual register */ 3931 memcpy(&data, pdata, bytes); 3932 data &= ~ro_mask; 3933 data |= vgpu_vreg(vgpu, offset) & ro_mask; 3934 ret = mmio_info->write(vgpu, offset, &data, bytes); 3935 } 3936 3937 /* higher 16bits of mode ctl regs are mask bits for change */ 3938 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) { 3939 u32 mask = vgpu_vreg(vgpu, offset) >> 16; 3940 3941 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask) 3942 | (vgpu_vreg(vgpu, offset) & mask); 3943 } 3944 } 3945 3946 return ret; 3947 3948 default_rw: 3949 return is_read ? 3950 intel_vgpu_default_mmio_read(vgpu, offset, pdata, bytes) : 3951 intel_vgpu_default_mmio_write(vgpu, offset, pdata, bytes); 3952 } 3953 3954 void intel_gvt_restore_fence(struct intel_gvt *gvt) 3955 { 3956 struct intel_vgpu *vgpu; 3957 int i, id; 3958 3959 idr_for_each_entry(&(gvt)->vgpu_idr, vgpu, id) { 3960 mmio_hw_access_pre(gvt->gt); 3961 for (i = 0; i < vgpu_fence_sz(vgpu); i++) 3962 intel_vgpu_write_fence(vgpu, i, vgpu_vreg64(vgpu, fence_num_to_offset(i))); 3963 mmio_hw_access_post(gvt->gt); 3964 } 3965 } 3966 3967 static int mmio_pm_restore_handler(struct intel_gvt *gvt, u32 offset, void *data) 3968 { 3969 struct intel_vgpu *vgpu = data; 3970 struct drm_i915_private *dev_priv = gvt->gt->i915; 3971 3972 if (gvt->mmio.mmio_attribute[offset >> 2] & F_PM_SAVE) 3973 intel_uncore_write(&dev_priv->uncore, _MMIO(offset), vgpu_vreg(vgpu, offset)); 3974 3975 return 0; 3976 } 3977 3978 void intel_gvt_restore_mmio(struct intel_gvt *gvt) 3979 { 3980 struct intel_vgpu *vgpu; 3981 int id; 3982 3983 idr_for_each_entry(&(gvt)->vgpu_idr, vgpu, id) { 3984 mmio_hw_access_pre(gvt->gt); 3985 intel_gvt_for_each_tracked_mmio(gvt, mmio_pm_restore_handler, vgpu); 3986 mmio_hw_access_post(gvt->gt); 3987 } 3988 } 3989