1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Kevin Tian <kevin.tian@intel.com> 25 * Eddie Dong <eddie.dong@intel.com> 26 * Zhiyuan Lv <zhiyuan.lv@intel.com> 27 * 28 * Contributors: 29 * Min He <min.he@intel.com> 30 * Tina Zhang <tina.zhang@intel.com> 31 * Pei Zhang <pei.zhang@intel.com> 32 * Niu Bing <bing.niu@intel.com> 33 * Ping Gao <ping.a.gao@intel.com> 34 * Zhi Wang <zhi.a.wang@intel.com> 35 * 36 37 */ 38 39 #include "i915_drv.h" 40 #include "gvt.h" 41 #include "i915_pvinfo.h" 42 43 /* XXX FIXME i915 has changed PP_XXX definition */ 44 #define PCH_PP_STATUS _MMIO(0xc7200) 45 #define PCH_PP_CONTROL _MMIO(0xc7204) 46 #define PCH_PP_ON_DELAYS _MMIO(0xc7208) 47 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c) 48 #define PCH_PP_DIVISOR _MMIO(0xc7210) 49 50 /* Register contains RO bits */ 51 #define F_RO (1 << 0) 52 /* Register contains graphics address */ 53 #define F_GMADR (1 << 1) 54 /* Mode mask registers with high 16 bits as the mask bits */ 55 #define F_MODE_MASK (1 << 2) 56 /* This reg can be accessed by GPU commands */ 57 #define F_CMD_ACCESS (1 << 3) 58 /* This reg has been accessed by a VM */ 59 #define F_ACCESSED (1 << 4) 60 /* This reg has been accessed through GPU commands */ 61 #define F_CMD_ACCESSED (1 << 5) 62 /* This reg could be accessed by unaligned address */ 63 #define F_UNALIGN (1 << 6) 64 65 unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt) 66 { 67 if (IS_BROADWELL(gvt->dev_priv)) 68 return D_BDW; 69 else if (IS_SKYLAKE(gvt->dev_priv)) 70 return D_SKL; 71 72 return 0; 73 } 74 75 bool intel_gvt_match_device(struct intel_gvt *gvt, 76 unsigned long device) 77 { 78 return intel_gvt_get_device_type(gvt) & device; 79 } 80 81 static void read_vreg(struct intel_vgpu *vgpu, unsigned int offset, 82 void *p_data, unsigned int bytes) 83 { 84 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); 85 } 86 87 static void write_vreg(struct intel_vgpu *vgpu, unsigned int offset, 88 void *p_data, unsigned int bytes) 89 { 90 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes); 91 } 92 93 static int new_mmio_info(struct intel_gvt *gvt, 94 u32 offset, u32 flags, u32 size, 95 u32 addr_mask, u32 ro_mask, u32 device, 96 int (*read)(struct intel_vgpu *, unsigned int, void *, unsigned int), 97 int (*write)(struct intel_vgpu *, unsigned int, void *, unsigned int)) 98 { 99 struct intel_gvt_mmio_info *info, *p; 100 u32 start, end, i; 101 102 if (!intel_gvt_match_device(gvt, device)) 103 return 0; 104 105 if (WARN_ON(!IS_ALIGNED(offset, 4))) 106 return -EINVAL; 107 108 start = offset; 109 end = offset + size; 110 111 for (i = start; i < end; i += 4) { 112 info = kzalloc(sizeof(*info), GFP_KERNEL); 113 if (!info) 114 return -ENOMEM; 115 116 info->offset = i; 117 p = intel_gvt_find_mmio_info(gvt, info->offset); 118 if (p) 119 gvt_err("dup mmio definition offset %x\n", 120 info->offset); 121 info->size = size; 122 info->length = (i + 4) < end ? 4 : (end - i); 123 info->addr_mask = addr_mask; 124 info->ro_mask = ro_mask; 125 info->device = device; 126 info->read = read ? read : intel_vgpu_default_mmio_read; 127 info->write = write ? write : intel_vgpu_default_mmio_write; 128 gvt->mmio.mmio_attribute[info->offset / 4] = flags; 129 INIT_HLIST_NODE(&info->node); 130 hash_add(gvt->mmio.mmio_info_table, &info->node, info->offset); 131 } 132 return 0; 133 } 134 135 static int render_mmio_to_ring_id(struct intel_gvt *gvt, unsigned int reg) 136 { 137 enum intel_engine_id id; 138 struct intel_engine_cs *engine; 139 140 reg &= ~GENMASK(11, 0); 141 for_each_engine(engine, gvt->dev_priv, id) { 142 if (engine->mmio_base == reg) 143 return id; 144 } 145 return -1; 146 } 147 148 #define offset_to_fence_num(offset) \ 149 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3) 150 151 #define fence_num_to_offset(num) \ 152 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) 153 154 155 static void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason) 156 { 157 switch (reason) { 158 case GVT_FAILSAFE_UNSUPPORTED_GUEST: 159 pr_err("Detected your guest driver doesn't support GVT-g.\n"); 160 break; 161 case GVT_FAILSAFE_INSUFFICIENT_RESOURCE: 162 pr_err("Graphics resource is not enough for the guest\n"); 163 default: 164 break; 165 } 166 pr_err("Now vgpu %d will enter failsafe mode.\n", vgpu->id); 167 vgpu->failsafe = true; 168 } 169 170 static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu, 171 unsigned int fence_num, void *p_data, unsigned int bytes) 172 { 173 if (fence_num >= vgpu_fence_sz(vgpu)) { 174 175 /* When guest access oob fence regs without access 176 * pv_info first, we treat guest not supporting GVT, 177 * and we will let vgpu enter failsafe mode. 178 */ 179 if (!vgpu->pv_notified) 180 enter_failsafe_mode(vgpu, 181 GVT_FAILSAFE_UNSUPPORTED_GUEST); 182 183 if (!vgpu->mmio.disable_warn_untrack) { 184 gvt_err("vgpu%d: found oob fence register access\n", 185 vgpu->id); 186 gvt_err("vgpu%d: total fence %d, access fence %d\n", 187 vgpu->id, vgpu_fence_sz(vgpu), 188 fence_num); 189 } 190 memset(p_data, 0, bytes); 191 return -EINVAL; 192 } 193 return 0; 194 } 195 196 static int fence_mmio_read(struct intel_vgpu *vgpu, unsigned int off, 197 void *p_data, unsigned int bytes) 198 { 199 int ret; 200 201 ret = sanitize_fence_mmio_access(vgpu, offset_to_fence_num(off), 202 p_data, bytes); 203 if (ret) 204 return ret; 205 read_vreg(vgpu, off, p_data, bytes); 206 return 0; 207 } 208 209 static int fence_mmio_write(struct intel_vgpu *vgpu, unsigned int off, 210 void *p_data, unsigned int bytes) 211 { 212 unsigned int fence_num = offset_to_fence_num(off); 213 int ret; 214 215 ret = sanitize_fence_mmio_access(vgpu, fence_num, p_data, bytes); 216 if (ret) 217 return ret; 218 write_vreg(vgpu, off, p_data, bytes); 219 220 intel_vgpu_write_fence(vgpu, fence_num, 221 vgpu_vreg64(vgpu, fence_num_to_offset(fence_num))); 222 return 0; 223 } 224 225 #define CALC_MODE_MASK_REG(old, new) \ 226 (((new) & GENMASK(31, 16)) \ 227 | ((((old) & GENMASK(15, 0)) & ~((new) >> 16)) \ 228 | ((new) & ((new) >> 16)))) 229 230 static int mul_force_wake_write(struct intel_vgpu *vgpu, 231 unsigned int offset, void *p_data, unsigned int bytes) 232 { 233 u32 old, new; 234 uint32_t ack_reg_offset; 235 236 old = vgpu_vreg(vgpu, offset); 237 new = CALC_MODE_MASK_REG(old, *(u32 *)p_data); 238 239 if (IS_SKYLAKE(vgpu->gvt->dev_priv)) { 240 switch (offset) { 241 case FORCEWAKE_RENDER_GEN9_REG: 242 ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG; 243 break; 244 case FORCEWAKE_BLITTER_GEN9_REG: 245 ack_reg_offset = FORCEWAKE_ACK_BLITTER_GEN9_REG; 246 break; 247 case FORCEWAKE_MEDIA_GEN9_REG: 248 ack_reg_offset = FORCEWAKE_ACK_MEDIA_GEN9_REG; 249 break; 250 default: 251 /*should not hit here*/ 252 gvt_err("invalid forcewake offset 0x%x\n", offset); 253 return -EINVAL; 254 } 255 } else { 256 ack_reg_offset = FORCEWAKE_ACK_HSW_REG; 257 } 258 259 vgpu_vreg(vgpu, offset) = new; 260 vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0)); 261 return 0; 262 } 263 264 static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 265 void *p_data, unsigned int bytes) 266 { 267 unsigned int engine_mask = 0; 268 u32 data; 269 270 write_vreg(vgpu, offset, p_data, bytes); 271 data = vgpu_vreg(vgpu, offset); 272 273 if (data & GEN6_GRDOM_FULL) { 274 gvt_dbg_mmio("vgpu%d: request full GPU reset\n", vgpu->id); 275 engine_mask = ALL_ENGINES; 276 } else { 277 if (data & GEN6_GRDOM_RENDER) { 278 gvt_dbg_mmio("vgpu%d: request RCS reset\n", vgpu->id); 279 engine_mask |= (1 << RCS); 280 } 281 if (data & GEN6_GRDOM_MEDIA) { 282 gvt_dbg_mmio("vgpu%d: request VCS reset\n", vgpu->id); 283 engine_mask |= (1 << VCS); 284 } 285 if (data & GEN6_GRDOM_BLT) { 286 gvt_dbg_mmio("vgpu%d: request BCS Reset\n", vgpu->id); 287 engine_mask |= (1 << BCS); 288 } 289 if (data & GEN6_GRDOM_VECS) { 290 gvt_dbg_mmio("vgpu%d: request VECS Reset\n", vgpu->id); 291 engine_mask |= (1 << VECS); 292 } 293 if (data & GEN8_GRDOM_MEDIA2) { 294 gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id); 295 if (HAS_BSD2(vgpu->gvt->dev_priv)) 296 engine_mask |= (1 << VCS2); 297 } 298 } 299 300 intel_gvt_reset_vgpu_locked(vgpu, false, engine_mask); 301 302 return 0; 303 } 304 305 static int gmbus_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 306 void *p_data, unsigned int bytes) 307 { 308 return intel_gvt_i2c_handle_gmbus_read(vgpu, offset, p_data, bytes); 309 } 310 311 static int gmbus_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 312 void *p_data, unsigned int bytes) 313 { 314 return intel_gvt_i2c_handle_gmbus_write(vgpu, offset, p_data, bytes); 315 } 316 317 static int pch_pp_control_mmio_write(struct intel_vgpu *vgpu, 318 unsigned int offset, void *p_data, unsigned int bytes) 319 { 320 write_vreg(vgpu, offset, p_data, bytes); 321 322 if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) { 323 vgpu_vreg(vgpu, PCH_PP_STATUS) |= PP_ON; 324 vgpu_vreg(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE; 325 vgpu_vreg(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN; 326 vgpu_vreg(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE; 327 328 } else 329 vgpu_vreg(vgpu, PCH_PP_STATUS) &= 330 ~(PP_ON | PP_SEQUENCE_POWER_DOWN 331 | PP_CYCLE_DELAY_ACTIVE); 332 return 0; 333 } 334 335 static int transconf_mmio_write(struct intel_vgpu *vgpu, 336 unsigned int offset, void *p_data, unsigned int bytes) 337 { 338 write_vreg(vgpu, offset, p_data, bytes); 339 340 if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE) 341 vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE; 342 else 343 vgpu_vreg(vgpu, offset) &= ~TRANS_STATE_ENABLE; 344 return 0; 345 } 346 347 static int lcpll_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 348 void *p_data, unsigned int bytes) 349 { 350 write_vreg(vgpu, offset, p_data, bytes); 351 352 if (vgpu_vreg(vgpu, offset) & LCPLL_PLL_DISABLE) 353 vgpu_vreg(vgpu, offset) &= ~LCPLL_PLL_LOCK; 354 else 355 vgpu_vreg(vgpu, offset) |= LCPLL_PLL_LOCK; 356 357 if (vgpu_vreg(vgpu, offset) & LCPLL_CD_SOURCE_FCLK) 358 vgpu_vreg(vgpu, offset) |= LCPLL_CD_SOURCE_FCLK_DONE; 359 else 360 vgpu_vreg(vgpu, offset) &= ~LCPLL_CD_SOURCE_FCLK_DONE; 361 362 return 0; 363 } 364 365 static int dpy_reg_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 366 void *p_data, unsigned int bytes) 367 { 368 *(u32 *)p_data = (1 << 17); 369 return 0; 370 } 371 372 static int dpy_reg_mmio_read_2(struct intel_vgpu *vgpu, unsigned int offset, 373 void *p_data, unsigned int bytes) 374 { 375 *(u32 *)p_data = 3; 376 return 0; 377 } 378 379 static int dpy_reg_mmio_read_3(struct intel_vgpu *vgpu, unsigned int offset, 380 void *p_data, unsigned int bytes) 381 { 382 *(u32 *)p_data = (0x2f << 16); 383 return 0; 384 } 385 386 static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 387 void *p_data, unsigned int bytes) 388 { 389 u32 data; 390 391 write_vreg(vgpu, offset, p_data, bytes); 392 data = vgpu_vreg(vgpu, offset); 393 394 if (data & PIPECONF_ENABLE) 395 vgpu_vreg(vgpu, offset) |= I965_PIPECONF_ACTIVE; 396 else 397 vgpu_vreg(vgpu, offset) &= ~I965_PIPECONF_ACTIVE; 398 intel_gvt_check_vblank_emulation(vgpu->gvt); 399 return 0; 400 } 401 402 /* ascendingly sorted */ 403 static i915_reg_t force_nonpriv_white_list[] = { 404 GEN9_CS_DEBUG_MODE1, //_MMIO(0x20ec) 405 GEN9_CTX_PREEMPT_REG,//_MMIO(0x2248) 406 GEN8_CS_CHICKEN1,//_MMIO(0x2580) 407 _MMIO(0x2690), 408 _MMIO(0x2694), 409 _MMIO(0x2698), 410 _MMIO(0x4de0), 411 _MMIO(0x4de4), 412 _MMIO(0x4dfc), 413 GEN7_COMMON_SLICE_CHICKEN1,//_MMIO(0x7010) 414 _MMIO(0x7014), 415 HDC_CHICKEN0,//_MMIO(0x7300) 416 GEN8_HDC_CHICKEN1,//_MMIO(0x7304) 417 _MMIO(0x7700), 418 _MMIO(0x7704), 419 _MMIO(0x7708), 420 _MMIO(0x770c), 421 _MMIO(0xb110), 422 GEN8_L3SQCREG4,//_MMIO(0xb118) 423 _MMIO(0xe100), 424 _MMIO(0xe18c), 425 _MMIO(0xe48c), 426 _MMIO(0xe5f4), 427 }; 428 429 /* a simple bsearch */ 430 static inline bool in_whitelist(unsigned int reg) 431 { 432 int left = 0, right = ARRAY_SIZE(force_nonpriv_white_list); 433 i915_reg_t *array = force_nonpriv_white_list; 434 435 while (left < right) { 436 int mid = (left + right)/2; 437 438 if (reg > array[mid].reg) 439 left = mid + 1; 440 else if (reg < array[mid].reg) 441 right = mid; 442 else 443 return true; 444 } 445 return false; 446 } 447 448 static int force_nonpriv_write(struct intel_vgpu *vgpu, 449 unsigned int offset, void *p_data, unsigned int bytes) 450 { 451 u32 reg_nonpriv = *(u32 *)p_data; 452 int ret = -EINVAL; 453 454 if ((bytes != 4) || ((offset & (bytes - 1)) != 0)) { 455 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV offset %x(%dB)\n", 456 vgpu->id, offset, bytes); 457 return ret; 458 } 459 460 if (in_whitelist(reg_nonpriv)) { 461 ret = intel_vgpu_default_mmio_write(vgpu, offset, p_data, 462 bytes); 463 } else { 464 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x\n", 465 vgpu->id, reg_nonpriv); 466 } 467 return ret; 468 } 469 470 static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 471 void *p_data, unsigned int bytes) 472 { 473 write_vreg(vgpu, offset, p_data, bytes); 474 475 if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) { 476 vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE; 477 } else { 478 vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE; 479 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E))) 480 vgpu_vreg(vgpu, DP_TP_STATUS(PORT_E)) 481 &= ~DP_TP_STATUS_AUTOTRAIN_DONE; 482 } 483 return 0; 484 } 485 486 static int fdi_rx_iir_mmio_write(struct intel_vgpu *vgpu, 487 unsigned int offset, void *p_data, unsigned int bytes) 488 { 489 vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data; 490 return 0; 491 } 492 493 #define FDI_LINK_TRAIN_PATTERN1 0 494 #define FDI_LINK_TRAIN_PATTERN2 1 495 496 static int fdi_auto_training_started(struct intel_vgpu *vgpu) 497 { 498 u32 ddi_buf_ctl = vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_E)); 499 u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL); 500 u32 tx_ctl = vgpu_vreg(vgpu, DP_TP_CTL(PORT_E)); 501 502 if ((ddi_buf_ctl & DDI_BUF_CTL_ENABLE) && 503 (rx_ctl & FDI_RX_ENABLE) && 504 (rx_ctl & FDI_AUTO_TRAINING) && 505 (tx_ctl & DP_TP_CTL_ENABLE) && 506 (tx_ctl & DP_TP_CTL_FDI_AUTOTRAIN)) 507 return 1; 508 else 509 return 0; 510 } 511 512 static int check_fdi_rx_train_status(struct intel_vgpu *vgpu, 513 enum pipe pipe, unsigned int train_pattern) 514 { 515 i915_reg_t fdi_rx_imr, fdi_tx_ctl, fdi_rx_ctl; 516 unsigned int fdi_rx_check_bits, fdi_tx_check_bits; 517 unsigned int fdi_rx_train_bits, fdi_tx_train_bits; 518 unsigned int fdi_iir_check_bits; 519 520 fdi_rx_imr = FDI_RX_IMR(pipe); 521 fdi_tx_ctl = FDI_TX_CTL(pipe); 522 fdi_rx_ctl = FDI_RX_CTL(pipe); 523 524 if (train_pattern == FDI_LINK_TRAIN_PATTERN1) { 525 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_1_CPT; 526 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_1; 527 fdi_iir_check_bits = FDI_RX_BIT_LOCK; 528 } else if (train_pattern == FDI_LINK_TRAIN_PATTERN2) { 529 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_2_CPT; 530 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_2; 531 fdi_iir_check_bits = FDI_RX_SYMBOL_LOCK; 532 } else { 533 gvt_err("Invalid train pattern %d\n", train_pattern); 534 return -EINVAL; 535 } 536 537 fdi_rx_check_bits = FDI_RX_ENABLE | fdi_rx_train_bits; 538 fdi_tx_check_bits = FDI_TX_ENABLE | fdi_tx_train_bits; 539 540 /* If imr bit has been masked */ 541 if (vgpu_vreg(vgpu, fdi_rx_imr) & fdi_iir_check_bits) 542 return 0; 543 544 if (((vgpu_vreg(vgpu, fdi_tx_ctl) & fdi_tx_check_bits) 545 == fdi_tx_check_bits) 546 && ((vgpu_vreg(vgpu, fdi_rx_ctl) & fdi_rx_check_bits) 547 == fdi_rx_check_bits)) 548 return 1; 549 else 550 return 0; 551 } 552 553 #define INVALID_INDEX (~0U) 554 555 static unsigned int calc_index(unsigned int offset, unsigned int start, 556 unsigned int next, unsigned int end, i915_reg_t i915_end) 557 { 558 unsigned int range = next - start; 559 560 if (!end) 561 end = i915_mmio_reg_offset(i915_end); 562 if (offset < start || offset > end) 563 return INVALID_INDEX; 564 offset -= start; 565 return offset / range; 566 } 567 568 #define FDI_RX_CTL_TO_PIPE(offset) \ 569 calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, 0, FDI_RX_CTL(PIPE_C)) 570 571 #define FDI_TX_CTL_TO_PIPE(offset) \ 572 calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, 0, FDI_TX_CTL(PIPE_C)) 573 574 #define FDI_RX_IMR_TO_PIPE(offset) \ 575 calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, 0, FDI_RX_IMR(PIPE_C)) 576 577 static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu, 578 unsigned int offset, void *p_data, unsigned int bytes) 579 { 580 i915_reg_t fdi_rx_iir; 581 unsigned int index; 582 int ret; 583 584 if (FDI_RX_CTL_TO_PIPE(offset) != INVALID_INDEX) 585 index = FDI_RX_CTL_TO_PIPE(offset); 586 else if (FDI_TX_CTL_TO_PIPE(offset) != INVALID_INDEX) 587 index = FDI_TX_CTL_TO_PIPE(offset); 588 else if (FDI_RX_IMR_TO_PIPE(offset) != INVALID_INDEX) 589 index = FDI_RX_IMR_TO_PIPE(offset); 590 else { 591 gvt_err("Unsupport registers %x\n", offset); 592 return -EINVAL; 593 } 594 595 write_vreg(vgpu, offset, p_data, bytes); 596 597 fdi_rx_iir = FDI_RX_IIR(index); 598 599 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN1); 600 if (ret < 0) 601 return ret; 602 if (ret) 603 vgpu_vreg(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK; 604 605 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN2); 606 if (ret < 0) 607 return ret; 608 if (ret) 609 vgpu_vreg(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK; 610 611 if (offset == _FDI_RXA_CTL) 612 if (fdi_auto_training_started(vgpu)) 613 vgpu_vreg(vgpu, DP_TP_STATUS(PORT_E)) |= 614 DP_TP_STATUS_AUTOTRAIN_DONE; 615 return 0; 616 } 617 618 #define DP_TP_CTL_TO_PORT(offset) \ 619 calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, 0, DP_TP_CTL(PORT_E)) 620 621 static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 622 void *p_data, unsigned int bytes) 623 { 624 i915_reg_t status_reg; 625 unsigned int index; 626 u32 data; 627 628 write_vreg(vgpu, offset, p_data, bytes); 629 630 index = DP_TP_CTL_TO_PORT(offset); 631 data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8; 632 if (data == 0x2) { 633 status_reg = DP_TP_STATUS(index); 634 vgpu_vreg(vgpu, status_reg) |= (1 << 25); 635 } 636 return 0; 637 } 638 639 static int dp_tp_status_mmio_write(struct intel_vgpu *vgpu, 640 unsigned int offset, void *p_data, unsigned int bytes) 641 { 642 u32 reg_val; 643 u32 sticky_mask; 644 645 reg_val = *((u32 *)p_data); 646 sticky_mask = GENMASK(27, 26) | (1 << 24); 647 648 vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) | 649 (vgpu_vreg(vgpu, offset) & sticky_mask); 650 vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask); 651 return 0; 652 } 653 654 static int pch_adpa_mmio_write(struct intel_vgpu *vgpu, 655 unsigned int offset, void *p_data, unsigned int bytes) 656 { 657 u32 data; 658 659 write_vreg(vgpu, offset, p_data, bytes); 660 data = vgpu_vreg(vgpu, offset); 661 662 if (data & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) 663 vgpu_vreg(vgpu, offset) &= ~ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 664 return 0; 665 } 666 667 static int south_chicken2_mmio_write(struct intel_vgpu *vgpu, 668 unsigned int offset, void *p_data, unsigned int bytes) 669 { 670 u32 data; 671 672 write_vreg(vgpu, offset, p_data, bytes); 673 data = vgpu_vreg(vgpu, offset); 674 675 if (data & FDI_MPHY_IOSFSB_RESET_CTL) 676 vgpu_vreg(vgpu, offset) |= FDI_MPHY_IOSFSB_RESET_STATUS; 677 else 678 vgpu_vreg(vgpu, offset) &= ~FDI_MPHY_IOSFSB_RESET_STATUS; 679 return 0; 680 } 681 682 #define DSPSURF_TO_PIPE(offset) \ 683 calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C)) 684 685 static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 686 void *p_data, unsigned int bytes) 687 { 688 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 689 unsigned int index = DSPSURF_TO_PIPE(offset); 690 i915_reg_t surflive_reg = DSPSURFLIVE(index); 691 int flip_event[] = { 692 [PIPE_A] = PRIMARY_A_FLIP_DONE, 693 [PIPE_B] = PRIMARY_B_FLIP_DONE, 694 [PIPE_C] = PRIMARY_C_FLIP_DONE, 695 }; 696 697 write_vreg(vgpu, offset, p_data, bytes); 698 vgpu_vreg(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset); 699 700 set_bit(flip_event[index], vgpu->irq.flip_done_event[index]); 701 return 0; 702 } 703 704 #define SPRSURF_TO_PIPE(offset) \ 705 calc_index(offset, _SPRA_SURF, _SPRB_SURF, 0, SPRSURF(PIPE_C)) 706 707 static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 708 void *p_data, unsigned int bytes) 709 { 710 unsigned int index = SPRSURF_TO_PIPE(offset); 711 i915_reg_t surflive_reg = SPRSURFLIVE(index); 712 int flip_event[] = { 713 [PIPE_A] = SPRITE_A_FLIP_DONE, 714 [PIPE_B] = SPRITE_B_FLIP_DONE, 715 [PIPE_C] = SPRITE_C_FLIP_DONE, 716 }; 717 718 write_vreg(vgpu, offset, p_data, bytes); 719 vgpu_vreg(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset); 720 721 set_bit(flip_event[index], vgpu->irq.flip_done_event[index]); 722 return 0; 723 } 724 725 static int trigger_aux_channel_interrupt(struct intel_vgpu *vgpu, 726 unsigned int reg) 727 { 728 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 729 enum intel_gvt_event_type event; 730 731 if (reg == _DPA_AUX_CH_CTL) 732 event = AUX_CHANNEL_A; 733 else if (reg == _PCH_DPB_AUX_CH_CTL || reg == _DPB_AUX_CH_CTL) 734 event = AUX_CHANNEL_B; 735 else if (reg == _PCH_DPC_AUX_CH_CTL || reg == _DPC_AUX_CH_CTL) 736 event = AUX_CHANNEL_C; 737 else if (reg == _PCH_DPD_AUX_CH_CTL || reg == _DPD_AUX_CH_CTL) 738 event = AUX_CHANNEL_D; 739 else { 740 WARN_ON(true); 741 return -EINVAL; 742 } 743 744 intel_vgpu_trigger_virtual_event(vgpu, event); 745 return 0; 746 } 747 748 static int dp_aux_ch_ctl_trans_done(struct intel_vgpu *vgpu, u32 value, 749 unsigned int reg, int len, bool data_valid) 750 { 751 /* mark transaction done */ 752 value |= DP_AUX_CH_CTL_DONE; 753 value &= ~DP_AUX_CH_CTL_SEND_BUSY; 754 value &= ~DP_AUX_CH_CTL_RECEIVE_ERROR; 755 756 if (data_valid) 757 value &= ~DP_AUX_CH_CTL_TIME_OUT_ERROR; 758 else 759 value |= DP_AUX_CH_CTL_TIME_OUT_ERROR; 760 761 /* message size */ 762 value &= ~(0xf << 20); 763 value |= (len << 20); 764 vgpu_vreg(vgpu, reg) = value; 765 766 if (value & DP_AUX_CH_CTL_INTERRUPT) 767 return trigger_aux_channel_interrupt(vgpu, reg); 768 return 0; 769 } 770 771 static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd, 772 uint8_t t) 773 { 774 if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == DPCD_TRAINING_PATTERN_1) { 775 /* training pattern 1 for CR */ 776 /* set LANE0_CR_DONE, LANE1_CR_DONE */ 777 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_CR_DONE; 778 /* set LANE2_CR_DONE, LANE3_CR_DONE */ 779 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_CR_DONE; 780 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == 781 DPCD_TRAINING_PATTERN_2) { 782 /* training pattern 2 for EQ */ 783 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane0_1 */ 784 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_EQ_DONE; 785 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_SYMBOL_LOCKED; 786 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane2_3 */ 787 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_EQ_DONE; 788 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_SYMBOL_LOCKED; 789 /* set INTERLANE_ALIGN_DONE */ 790 dpcd->data[DPCD_LANE_ALIGN_STATUS_UPDATED] |= 791 DPCD_INTERLANE_ALIGN_DONE; 792 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == 793 DPCD_LINK_TRAINING_DISABLED) { 794 /* finish link training */ 795 /* set sink status as synchronized */ 796 dpcd->data[DPCD_SINK_STATUS] = DPCD_SINK_IN_SYNC; 797 } 798 } 799 800 #define _REG_HSW_DP_AUX_CH_CTL(dp) \ 801 ((dp) ? (_PCH_DPB_AUX_CH_CTL + ((dp)-1)*0x100) : 0x64010) 802 803 #define _REG_SKL_DP_AUX_CH_CTL(dp) (0x64010 + (dp) * 0x100) 804 805 #define OFFSET_TO_DP_AUX_PORT(offset) (((offset) & 0xF00) >> 8) 806 807 #define dpy_is_valid_port(port) \ 808 (((port) >= PORT_A) && ((port) < I915_MAX_PORTS)) 809 810 static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu, 811 unsigned int offset, void *p_data, unsigned int bytes) 812 { 813 struct intel_vgpu_display *display = &vgpu->display; 814 int msg, addr, ctrl, op, len; 815 int port_index = OFFSET_TO_DP_AUX_PORT(offset); 816 struct intel_vgpu_dpcd_data *dpcd = NULL; 817 struct intel_vgpu_port *port = NULL; 818 u32 data; 819 820 if (!dpy_is_valid_port(port_index)) { 821 gvt_err("GVT(%d): Unsupported DP port access!\n", vgpu->id); 822 return 0; 823 } 824 825 write_vreg(vgpu, offset, p_data, bytes); 826 data = vgpu_vreg(vgpu, offset); 827 828 if (IS_SKYLAKE(vgpu->gvt->dev_priv) && 829 offset != _REG_SKL_DP_AUX_CH_CTL(port_index)) { 830 /* SKL DPB/C/D aux ctl register changed */ 831 return 0; 832 } else if (IS_BROADWELL(vgpu->gvt->dev_priv) && 833 offset != _REG_HSW_DP_AUX_CH_CTL(port_index)) { 834 /* write to the data registers */ 835 return 0; 836 } 837 838 if (!(data & DP_AUX_CH_CTL_SEND_BUSY)) { 839 /* just want to clear the sticky bits */ 840 vgpu_vreg(vgpu, offset) = 0; 841 return 0; 842 } 843 844 port = &display->ports[port_index]; 845 dpcd = port->dpcd; 846 847 /* read out message from DATA1 register */ 848 msg = vgpu_vreg(vgpu, offset + 4); 849 addr = (msg >> 8) & 0xffff; 850 ctrl = (msg >> 24) & 0xff; 851 len = msg & 0xff; 852 op = ctrl >> 4; 853 854 if (op == GVT_AUX_NATIVE_WRITE) { 855 int t; 856 uint8_t buf[16]; 857 858 if ((addr + len + 1) >= DPCD_SIZE) { 859 /* 860 * Write request exceeds what we supported, 861 * DCPD spec: When a Source Device is writing a DPCD 862 * address not supported by the Sink Device, the Sink 863 * Device shall reply with AUX NACK and “M” equal to 864 * zero. 865 */ 866 867 /* NAK the write */ 868 vgpu_vreg(vgpu, offset + 4) = AUX_NATIVE_REPLY_NAK; 869 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 2, true); 870 return 0; 871 } 872 873 /* 874 * Write request format: (command + address) occupies 875 * 3 bytes, followed by (len + 1) bytes of data. 876 */ 877 if (WARN_ON((len + 4) > AUX_BURST_SIZE)) 878 return -EINVAL; 879 880 /* unpack data from vreg to buf */ 881 for (t = 0; t < 4; t++) { 882 u32 r = vgpu_vreg(vgpu, offset + 8 + t * 4); 883 884 buf[t * 4] = (r >> 24) & 0xff; 885 buf[t * 4 + 1] = (r >> 16) & 0xff; 886 buf[t * 4 + 2] = (r >> 8) & 0xff; 887 buf[t * 4 + 3] = r & 0xff; 888 } 889 890 /* write to virtual DPCD */ 891 if (dpcd && dpcd->data_valid) { 892 for (t = 0; t <= len; t++) { 893 int p = addr + t; 894 895 dpcd->data[p] = buf[t]; 896 /* check for link training */ 897 if (p == DPCD_TRAINING_PATTERN_SET) 898 dp_aux_ch_ctl_link_training(dpcd, 899 buf[t]); 900 } 901 } 902 903 /* ACK the write */ 904 vgpu_vreg(vgpu, offset + 4) = 0; 905 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 1, 906 dpcd && dpcd->data_valid); 907 return 0; 908 } 909 910 if (op == GVT_AUX_NATIVE_READ) { 911 int idx, i, ret = 0; 912 913 if ((addr + len + 1) >= DPCD_SIZE) { 914 /* 915 * read request exceeds what we supported 916 * DPCD spec: A Sink Device receiving a Native AUX CH 917 * read request for an unsupported DPCD address must 918 * reply with an AUX ACK and read data set equal to 919 * zero instead of replying with AUX NACK. 920 */ 921 922 /* ACK the READ*/ 923 vgpu_vreg(vgpu, offset + 4) = 0; 924 vgpu_vreg(vgpu, offset + 8) = 0; 925 vgpu_vreg(vgpu, offset + 12) = 0; 926 vgpu_vreg(vgpu, offset + 16) = 0; 927 vgpu_vreg(vgpu, offset + 20) = 0; 928 929 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2, 930 true); 931 return 0; 932 } 933 934 for (idx = 1; idx <= 5; idx++) { 935 /* clear the data registers */ 936 vgpu_vreg(vgpu, offset + 4 * idx) = 0; 937 } 938 939 /* 940 * Read reply format: ACK (1 byte) plus (len + 1) bytes of data. 941 */ 942 if (WARN_ON((len + 2) > AUX_BURST_SIZE)) 943 return -EINVAL; 944 945 /* read from virtual DPCD to vreg */ 946 /* first 4 bytes: [ACK][addr][addr+1][addr+2] */ 947 if (dpcd && dpcd->data_valid) { 948 for (i = 1; i <= (len + 1); i++) { 949 int t; 950 951 t = dpcd->data[addr + i - 1]; 952 t <<= (24 - 8 * (i % 4)); 953 ret |= t; 954 955 if ((i % 4 == 3) || (i == (len + 1))) { 956 vgpu_vreg(vgpu, offset + 957 (i / 4 + 1) * 4) = ret; 958 ret = 0; 959 } 960 } 961 } 962 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2, 963 dpcd && dpcd->data_valid); 964 return 0; 965 } 966 967 /* i2c transaction starts */ 968 intel_gvt_i2c_handle_aux_ch_write(vgpu, port_index, offset, p_data); 969 970 if (data & DP_AUX_CH_CTL_INTERRUPT) 971 trigger_aux_channel_interrupt(vgpu, offset); 972 return 0; 973 } 974 975 static int vga_control_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 976 void *p_data, unsigned int bytes) 977 { 978 bool vga_disable; 979 980 write_vreg(vgpu, offset, p_data, bytes); 981 vga_disable = vgpu_vreg(vgpu, offset) & VGA_DISP_DISABLE; 982 983 gvt_dbg_core("vgpu%d: %s VGA mode\n", vgpu->id, 984 vga_disable ? "Disable" : "Enable"); 985 return 0; 986 } 987 988 static u32 read_virtual_sbi_register(struct intel_vgpu *vgpu, 989 unsigned int sbi_offset) 990 { 991 struct intel_vgpu_display *display = &vgpu->display; 992 int num = display->sbi.number; 993 int i; 994 995 for (i = 0; i < num; ++i) 996 if (display->sbi.registers[i].offset == sbi_offset) 997 break; 998 999 if (i == num) 1000 return 0; 1001 1002 return display->sbi.registers[i].value; 1003 } 1004 1005 static void write_virtual_sbi_register(struct intel_vgpu *vgpu, 1006 unsigned int offset, u32 value) 1007 { 1008 struct intel_vgpu_display *display = &vgpu->display; 1009 int num = display->sbi.number; 1010 int i; 1011 1012 for (i = 0; i < num; ++i) { 1013 if (display->sbi.registers[i].offset == offset) 1014 break; 1015 } 1016 1017 if (i == num) { 1018 if (num == SBI_REG_MAX) { 1019 gvt_err("vgpu%d: SBI caching meets maximum limits\n", 1020 vgpu->id); 1021 return; 1022 } 1023 display->sbi.number++; 1024 } 1025 1026 display->sbi.registers[i].offset = offset; 1027 display->sbi.registers[i].value = value; 1028 } 1029 1030 static int sbi_data_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 1031 void *p_data, unsigned int bytes) 1032 { 1033 if (((vgpu_vreg(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> 1034 SBI_OPCODE_SHIFT) == SBI_CMD_CRRD) { 1035 unsigned int sbi_offset = (vgpu_vreg(vgpu, SBI_ADDR) & 1036 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; 1037 vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu, 1038 sbi_offset); 1039 } 1040 read_vreg(vgpu, offset, p_data, bytes); 1041 return 0; 1042 } 1043 1044 static int sbi_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1045 void *p_data, unsigned int bytes) 1046 { 1047 u32 data; 1048 1049 write_vreg(vgpu, offset, p_data, bytes); 1050 data = vgpu_vreg(vgpu, offset); 1051 1052 data &= ~(SBI_STAT_MASK << SBI_STAT_SHIFT); 1053 data |= SBI_READY; 1054 1055 data &= ~(SBI_RESPONSE_MASK << SBI_RESPONSE_SHIFT); 1056 data |= SBI_RESPONSE_SUCCESS; 1057 1058 vgpu_vreg(vgpu, offset) = data; 1059 1060 if (((vgpu_vreg(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> 1061 SBI_OPCODE_SHIFT) == SBI_CMD_CRWR) { 1062 unsigned int sbi_offset = (vgpu_vreg(vgpu, SBI_ADDR) & 1063 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; 1064 1065 write_virtual_sbi_register(vgpu, sbi_offset, 1066 vgpu_vreg(vgpu, SBI_DATA)); 1067 } 1068 return 0; 1069 } 1070 1071 #define _vgtif_reg(x) \ 1072 (VGT_PVINFO_PAGE + offsetof(struct vgt_if, x)) 1073 1074 static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 1075 void *p_data, unsigned int bytes) 1076 { 1077 bool invalid_read = false; 1078 1079 read_vreg(vgpu, offset, p_data, bytes); 1080 1081 switch (offset) { 1082 case _vgtif_reg(magic) ... _vgtif_reg(vgt_id): 1083 if (offset + bytes > _vgtif_reg(vgt_id) + 4) 1084 invalid_read = true; 1085 break; 1086 case _vgtif_reg(avail_rs.mappable_gmadr.base) ... 1087 _vgtif_reg(avail_rs.fence_num): 1088 if (offset + bytes > 1089 _vgtif_reg(avail_rs.fence_num) + 4) 1090 invalid_read = true; 1091 break; 1092 case 0x78010: /* vgt_caps */ 1093 case 0x7881c: 1094 break; 1095 default: 1096 invalid_read = true; 1097 break; 1098 } 1099 if (invalid_read) 1100 gvt_err("invalid pvinfo read: [%x:%x] = %x\n", 1101 offset, bytes, *(u32 *)p_data); 1102 vgpu->pv_notified = true; 1103 return 0; 1104 } 1105 1106 static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification) 1107 { 1108 int ret = 0; 1109 1110 switch (notification) { 1111 case VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE: 1112 ret = intel_vgpu_g2v_create_ppgtt_mm(vgpu, 3); 1113 break; 1114 case VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY: 1115 ret = intel_vgpu_g2v_destroy_ppgtt_mm(vgpu, 3); 1116 break; 1117 case VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE: 1118 ret = intel_vgpu_g2v_create_ppgtt_mm(vgpu, 4); 1119 break; 1120 case VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY: 1121 ret = intel_vgpu_g2v_destroy_ppgtt_mm(vgpu, 4); 1122 break; 1123 case VGT_G2V_EXECLIST_CONTEXT_CREATE: 1124 case VGT_G2V_EXECLIST_CONTEXT_DESTROY: 1125 case 1: /* Remove this in guest driver. */ 1126 break; 1127 default: 1128 gvt_err("Invalid PV notification %d\n", notification); 1129 } 1130 return ret; 1131 } 1132 1133 static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready) 1134 { 1135 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1136 struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj; 1137 char *env[3] = {NULL, NULL, NULL}; 1138 char vmid_str[20]; 1139 char display_ready_str[20]; 1140 1141 snprintf(display_ready_str, 20, "GVT_DISPLAY_READY=%d", ready); 1142 env[0] = display_ready_str; 1143 1144 snprintf(vmid_str, 20, "VMID=%d", vgpu->id); 1145 env[1] = vmid_str; 1146 1147 return kobject_uevent_env(kobj, KOBJ_ADD, env); 1148 } 1149 1150 static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1151 void *p_data, unsigned int bytes) 1152 { 1153 u32 data; 1154 int ret; 1155 1156 write_vreg(vgpu, offset, p_data, bytes); 1157 data = vgpu_vreg(vgpu, offset); 1158 1159 switch (offset) { 1160 case _vgtif_reg(display_ready): 1161 send_display_ready_uevent(vgpu, data ? 1 : 0); 1162 break; 1163 case _vgtif_reg(g2v_notify): 1164 ret = handle_g2v_notification(vgpu, data); 1165 break; 1166 /* add xhot and yhot to handled list to avoid error log */ 1167 case 0x78830: 1168 case 0x78834: 1169 case _vgtif_reg(pdp[0].lo): 1170 case _vgtif_reg(pdp[0].hi): 1171 case _vgtif_reg(pdp[1].lo): 1172 case _vgtif_reg(pdp[1].hi): 1173 case _vgtif_reg(pdp[2].lo): 1174 case _vgtif_reg(pdp[2].hi): 1175 case _vgtif_reg(pdp[3].lo): 1176 case _vgtif_reg(pdp[3].hi): 1177 case _vgtif_reg(execlist_context_descriptor_lo): 1178 case _vgtif_reg(execlist_context_descriptor_hi): 1179 break; 1180 case _vgtif_reg(rsv5[0])..._vgtif_reg(rsv5[3]): 1181 enter_failsafe_mode(vgpu, GVT_FAILSAFE_INSUFFICIENT_RESOURCE); 1182 break; 1183 default: 1184 gvt_err("invalid pvinfo write offset %x bytes %x data %x\n", 1185 offset, bytes, data); 1186 break; 1187 } 1188 return 0; 1189 } 1190 1191 static int pf_write(struct intel_vgpu *vgpu, 1192 unsigned int offset, void *p_data, unsigned int bytes) 1193 { 1194 u32 val = *(u32 *)p_data; 1195 1196 if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL || 1197 offset == _PS_1B_CTRL || offset == _PS_2B_CTRL || 1198 offset == _PS_1C_CTRL) && (val & PS_PLANE_SEL_MASK) != 0) { 1199 WARN_ONCE(true, "VM(%d): guest is trying to scaling a plane\n", 1200 vgpu->id); 1201 return 0; 1202 } 1203 1204 return intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes); 1205 } 1206 1207 static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu, 1208 unsigned int offset, void *p_data, unsigned int bytes) 1209 { 1210 write_vreg(vgpu, offset, p_data, bytes); 1211 1212 if (vgpu_vreg(vgpu, offset) & HSW_PWR_WELL_ENABLE_REQUEST) 1213 vgpu_vreg(vgpu, offset) |= HSW_PWR_WELL_STATE_ENABLED; 1214 else 1215 vgpu_vreg(vgpu, offset) &= ~HSW_PWR_WELL_STATE_ENABLED; 1216 return 0; 1217 } 1218 1219 static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu, 1220 unsigned int offset, void *p_data, unsigned int bytes) 1221 { 1222 write_vreg(vgpu, offset, p_data, bytes); 1223 1224 if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM) 1225 vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM; 1226 return 0; 1227 } 1228 1229 static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset, 1230 void *p_data, unsigned int bytes) 1231 { 1232 u32 mode; 1233 1234 write_vreg(vgpu, offset, p_data, bytes); 1235 mode = vgpu_vreg(vgpu, offset); 1236 1237 if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) { 1238 WARN_ONCE(1, "VM(%d): iGVT-g doesn't supporte GuC\n", 1239 vgpu->id); 1240 return 0; 1241 } 1242 1243 return 0; 1244 } 1245 1246 static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset, 1247 void *p_data, unsigned int bytes) 1248 { 1249 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1250 u32 trtte = *(u32 *)p_data; 1251 1252 if ((trtte & 1) && (trtte & (1 << 1)) == 0) { 1253 WARN(1, "VM(%d): Use physical address for TRTT!\n", 1254 vgpu->id); 1255 return -EINVAL; 1256 } 1257 write_vreg(vgpu, offset, p_data, bytes); 1258 /* TRTTE is not per-context */ 1259 I915_WRITE(_MMIO(offset), vgpu_vreg(vgpu, offset)); 1260 1261 return 0; 1262 } 1263 1264 static int gen9_trtt_chicken_write(struct intel_vgpu *vgpu, unsigned int offset, 1265 void *p_data, unsigned int bytes) 1266 { 1267 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1268 u32 val = *(u32 *)p_data; 1269 1270 if (val & 1) { 1271 /* unblock hw logic */ 1272 I915_WRITE(_MMIO(offset), val); 1273 } 1274 write_vreg(vgpu, offset, p_data, bytes); 1275 return 0; 1276 } 1277 1278 static int dpll_status_read(struct intel_vgpu *vgpu, unsigned int offset, 1279 void *p_data, unsigned int bytes) 1280 { 1281 u32 v = 0; 1282 1283 if (vgpu_vreg(vgpu, 0x46010) & (1 << 31)) 1284 v |= (1 << 0); 1285 1286 if (vgpu_vreg(vgpu, 0x46014) & (1 << 31)) 1287 v |= (1 << 8); 1288 1289 if (vgpu_vreg(vgpu, 0x46040) & (1 << 31)) 1290 v |= (1 << 16); 1291 1292 if (vgpu_vreg(vgpu, 0x46060) & (1 << 31)) 1293 v |= (1 << 24); 1294 1295 vgpu_vreg(vgpu, offset) = v; 1296 1297 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1298 } 1299 1300 static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset, 1301 void *p_data, unsigned int bytes) 1302 { 1303 u32 value = *(u32 *)p_data; 1304 u32 cmd = value & 0xff; 1305 u32 *data0 = &vgpu_vreg(vgpu, GEN6_PCODE_DATA); 1306 1307 switch (cmd) { 1308 case GEN9_PCODE_READ_MEM_LATENCY: 1309 if (IS_SKYLAKE(vgpu->gvt->dev_priv)) { 1310 /** 1311 * "Read memory latency" command on gen9. 1312 * Below memory latency values are read 1313 * from skylake platform. 1314 */ 1315 if (!*data0) 1316 *data0 = 0x1e1a1100; 1317 else 1318 *data0 = 0x61514b3d; 1319 } 1320 break; 1321 case SKL_PCODE_CDCLK_CONTROL: 1322 if (IS_SKYLAKE(vgpu->gvt->dev_priv)) 1323 *data0 = SKL_CDCLK_READY_FOR_CHANGE; 1324 break; 1325 case GEN6_PCODE_READ_RC6VIDS: 1326 *data0 |= 0x1; 1327 break; 1328 } 1329 1330 gvt_dbg_core("VM(%d) write %x to mailbox, return data0 %x\n", 1331 vgpu->id, value, *data0); 1332 /** 1333 * PCODE_READY clear means ready for pcode read/write, 1334 * PCODE_ERROR_MASK clear means no error happened. In GVT-g we 1335 * always emulate as pcode read/write success and ready for access 1336 * anytime, since we don't touch real physical registers here. 1337 */ 1338 value &= ~(GEN6_PCODE_READY | GEN6_PCODE_ERROR_MASK); 1339 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes); 1340 } 1341 1342 static int skl_power_well_ctl_write(struct intel_vgpu *vgpu, 1343 unsigned int offset, void *p_data, unsigned int bytes) 1344 { 1345 u32 v = *(u32 *)p_data; 1346 1347 v &= (1 << 31) | (1 << 29) | (1 << 9) | 1348 (1 << 7) | (1 << 5) | (1 << 3) | (1 << 1); 1349 v |= (v >> 1); 1350 1351 return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes); 1352 } 1353 1354 static int skl_misc_ctl_write(struct intel_vgpu *vgpu, unsigned int offset, 1355 void *p_data, unsigned int bytes) 1356 { 1357 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1358 i915_reg_t reg = {.reg = offset}; 1359 1360 switch (offset) { 1361 case 0x4ddc: 1362 vgpu_vreg(vgpu, offset) = 0x8000003c; 1363 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl */ 1364 I915_WRITE(reg, vgpu_vreg(vgpu, offset)); 1365 break; 1366 case 0x42080: 1367 vgpu_vreg(vgpu, offset) = 0x8000; 1368 /* WaCompressedResourceDisplayNewHashMode:skl */ 1369 I915_WRITE(reg, vgpu_vreg(vgpu, offset)); 1370 break; 1371 default: 1372 return -EINVAL; 1373 } 1374 1375 return 0; 1376 } 1377 1378 static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset, 1379 void *p_data, unsigned int bytes) 1380 { 1381 u32 v = *(u32 *)p_data; 1382 1383 /* other bits are MBZ. */ 1384 v &= (1 << 31) | (1 << 30); 1385 v & (1 << 31) ? (v |= (1 << 30)) : (v &= ~(1 << 30)); 1386 1387 vgpu_vreg(vgpu, offset) = v; 1388 1389 return 0; 1390 } 1391 1392 static int ring_timestamp_mmio_read(struct intel_vgpu *vgpu, 1393 unsigned int offset, void *p_data, unsigned int bytes) 1394 { 1395 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1396 1397 vgpu_vreg(vgpu, offset) = I915_READ(_MMIO(offset)); 1398 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1399 } 1400 1401 static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1402 void *p_data, unsigned int bytes) 1403 { 1404 int ring_id = render_mmio_to_ring_id(vgpu->gvt, offset); 1405 struct intel_vgpu_execlist *execlist; 1406 u32 data = *(u32 *)p_data; 1407 int ret = 0; 1408 1409 if (WARN_ON(ring_id < 0 || ring_id > I915_NUM_ENGINES - 1)) 1410 return -EINVAL; 1411 1412 execlist = &vgpu->execlist[ring_id]; 1413 1414 execlist->elsp_dwords.data[execlist->elsp_dwords.index] = data; 1415 if (execlist->elsp_dwords.index == 3) { 1416 ret = intel_vgpu_submit_execlist(vgpu, ring_id); 1417 if(ret) 1418 gvt_err("fail submit workload on ring %d\n", ring_id); 1419 } 1420 1421 ++execlist->elsp_dwords.index; 1422 execlist->elsp_dwords.index &= 0x3; 1423 return ret; 1424 } 1425 1426 static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1427 void *p_data, unsigned int bytes) 1428 { 1429 u32 data = *(u32 *)p_data; 1430 int ring_id = render_mmio_to_ring_id(vgpu->gvt, offset); 1431 bool enable_execlist; 1432 1433 write_vreg(vgpu, offset, p_data, bytes); 1434 1435 /* when PPGTT mode enabled, we will check if guest has called 1436 * pvinfo, if not, we will treat this guest as non-gvtg-aware 1437 * guest, and stop emulating its cfg space, mmio, gtt, etc. 1438 */ 1439 if (((data & _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)) || 1440 (data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE))) 1441 && !vgpu->pv_notified) { 1442 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); 1443 return 0; 1444 } 1445 if ((data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)) 1446 || (data & _MASKED_BIT_DISABLE(GFX_RUN_LIST_ENABLE))) { 1447 enable_execlist = !!(data & GFX_RUN_LIST_ENABLE); 1448 1449 gvt_dbg_core("EXECLIST %s on ring %d\n", 1450 (enable_execlist ? "enabling" : "disabling"), 1451 ring_id); 1452 1453 if (enable_execlist) 1454 intel_vgpu_start_schedule(vgpu); 1455 } 1456 return 0; 1457 } 1458 1459 static int gvt_reg_tlb_control_handler(struct intel_vgpu *vgpu, 1460 unsigned int offset, void *p_data, unsigned int bytes) 1461 { 1462 unsigned int id = 0; 1463 1464 write_vreg(vgpu, offset, p_data, bytes); 1465 vgpu_vreg(vgpu, offset) = 0; 1466 1467 switch (offset) { 1468 case 0x4260: 1469 id = RCS; 1470 break; 1471 case 0x4264: 1472 id = VCS; 1473 break; 1474 case 0x4268: 1475 id = VCS2; 1476 break; 1477 case 0x426c: 1478 id = BCS; 1479 break; 1480 case 0x4270: 1481 id = VECS; 1482 break; 1483 default: 1484 return -EINVAL; 1485 } 1486 set_bit(id, (void *)vgpu->tlb_handle_pending); 1487 1488 return 0; 1489 } 1490 1491 static int ring_reset_ctl_write(struct intel_vgpu *vgpu, 1492 unsigned int offset, void *p_data, unsigned int bytes) 1493 { 1494 u32 data; 1495 1496 write_vreg(vgpu, offset, p_data, bytes); 1497 data = vgpu_vreg(vgpu, offset); 1498 1499 if (data & _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET)) 1500 data |= RESET_CTL_READY_TO_RESET; 1501 else if (data & _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET)) 1502 data &= ~RESET_CTL_READY_TO_RESET; 1503 1504 vgpu_vreg(vgpu, offset) = data; 1505 return 0; 1506 } 1507 1508 #define MMIO_F(reg, s, f, am, rm, d, r, w) do { \ 1509 ret = new_mmio_info(gvt, INTEL_GVT_MMIO_OFFSET(reg), \ 1510 f, s, am, rm, d, r, w); \ 1511 if (ret) \ 1512 return ret; \ 1513 } while (0) 1514 1515 #define MMIO_D(reg, d) \ 1516 MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL) 1517 1518 #define MMIO_DH(reg, d, r, w) \ 1519 MMIO_F(reg, 4, 0, 0, 0, d, r, w) 1520 1521 #define MMIO_DFH(reg, d, f, r, w) \ 1522 MMIO_F(reg, 4, f, 0, 0, d, r, w) 1523 1524 #define MMIO_GM(reg, d, r, w) \ 1525 MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w) 1526 1527 #define MMIO_GM_RDR(reg, d, r, w) \ 1528 MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w) 1529 1530 #define MMIO_RO(reg, d, f, rm, r, w) \ 1531 MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w) 1532 1533 #define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \ 1534 MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \ 1535 MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \ 1536 MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \ 1537 MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \ 1538 } while (0) 1539 1540 #define MMIO_RING_D(prefix, d) \ 1541 MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL) 1542 1543 #define MMIO_RING_DFH(prefix, d, f, r, w) \ 1544 MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w) 1545 1546 #define MMIO_RING_GM(prefix, d, r, w) \ 1547 MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w) 1548 1549 #define MMIO_RING_GM_RDR(prefix, d, r, w) \ 1550 MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w) 1551 1552 #define MMIO_RING_RO(prefix, d, f, rm, r, w) \ 1553 MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w) 1554 1555 static int init_generic_mmio_info(struct intel_gvt *gvt) 1556 { 1557 struct drm_i915_private *dev_priv = gvt->dev_priv; 1558 int ret; 1559 1560 MMIO_RING_DFH(RING_IMR, D_ALL, F_CMD_ACCESS, NULL, 1561 intel_vgpu_reg_imr_handler); 1562 1563 MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler); 1564 MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler); 1565 MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler); 1566 MMIO_D(SDEISR, D_ALL); 1567 1568 MMIO_RING_DFH(RING_HWSTAM, D_ALL, F_CMD_ACCESS, NULL, NULL); 1569 1570 MMIO_GM_RDR(RENDER_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1571 MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1572 MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1573 MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1574 1575 #define RING_REG(base) (base + 0x28) 1576 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL); 1577 #undef RING_REG 1578 1579 #define RING_REG(base) (base + 0x134) 1580 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL); 1581 #undef RING_REG 1582 1583 MMIO_GM_RDR(0x2148, D_ALL, NULL, NULL); 1584 MMIO_GM_RDR(CCID, D_ALL, NULL, NULL); 1585 MMIO_GM_RDR(0x12198, D_ALL, NULL, NULL); 1586 MMIO_D(GEN7_CXT_SIZE, D_ALL); 1587 1588 MMIO_RING_DFH(RING_TAIL, D_ALL, F_CMD_ACCESS, NULL, NULL); 1589 MMIO_RING_DFH(RING_HEAD, D_ALL, F_CMD_ACCESS, NULL, NULL); 1590 MMIO_RING_DFH(RING_CTL, D_ALL, F_CMD_ACCESS, NULL, NULL); 1591 MMIO_RING_DFH(RING_ACTHD, D_ALL, F_CMD_ACCESS, NULL, NULL); 1592 MMIO_RING_GM_RDR(RING_START, D_ALL, NULL, NULL); 1593 1594 /* RING MODE */ 1595 #define RING_REG(base) (base + 0x29c) 1596 MMIO_RING_DFH(RING_REG, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, 1597 ring_mode_mmio_write); 1598 #undef RING_REG 1599 1600 MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 1601 NULL, NULL); 1602 MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 1603 NULL, NULL); 1604 MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS, 1605 ring_timestamp_mmio_read, NULL); 1606 MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS, 1607 ring_timestamp_mmio_read, NULL); 1608 1609 MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1610 MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 1611 NULL, NULL); 1612 MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1613 MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1614 MMIO_DFH(0x2124, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1615 1616 MMIO_DFH(0x20dc, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1617 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1618 MMIO_DFH(0x2088, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1619 MMIO_DFH(0x20e4, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1620 MMIO_DFH(0x2470, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1621 MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL); 1622 MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 1623 NULL, NULL); 1624 MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1625 MMIO_DFH(0x9030, D_ALL, F_CMD_ACCESS, NULL, NULL); 1626 MMIO_DFH(0x20a0, D_ALL, F_CMD_ACCESS, NULL, NULL); 1627 MMIO_DFH(0x2420, D_ALL, F_CMD_ACCESS, NULL, NULL); 1628 MMIO_DFH(0x2430, D_ALL, F_CMD_ACCESS, NULL, NULL); 1629 MMIO_DFH(0x2434, D_ALL, F_CMD_ACCESS, NULL, NULL); 1630 MMIO_DFH(0x2438, D_ALL, F_CMD_ACCESS, NULL, NULL); 1631 MMIO_DFH(0x243c, D_ALL, F_CMD_ACCESS, NULL, NULL); 1632 MMIO_DFH(0x7018, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1633 MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1634 MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1635 1636 /* display */ 1637 MMIO_F(0x60220, 0x20, 0, 0, 0, D_ALL, NULL, NULL); 1638 MMIO_D(0x602a0, D_ALL); 1639 1640 MMIO_D(0x65050, D_ALL); 1641 MMIO_D(0x650b4, D_ALL); 1642 1643 MMIO_D(0xc4040, D_ALL); 1644 MMIO_D(DERRMR, D_ALL); 1645 1646 MMIO_D(PIPEDSL(PIPE_A), D_ALL); 1647 MMIO_D(PIPEDSL(PIPE_B), D_ALL); 1648 MMIO_D(PIPEDSL(PIPE_C), D_ALL); 1649 MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL); 1650 1651 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write); 1652 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write); 1653 MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write); 1654 MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write); 1655 1656 MMIO_D(PIPESTAT(PIPE_A), D_ALL); 1657 MMIO_D(PIPESTAT(PIPE_B), D_ALL); 1658 MMIO_D(PIPESTAT(PIPE_C), D_ALL); 1659 MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL); 1660 1661 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL); 1662 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL); 1663 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL); 1664 MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL); 1665 1666 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL); 1667 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL); 1668 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL); 1669 MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL); 1670 1671 MMIO_D(CURCNTR(PIPE_A), D_ALL); 1672 MMIO_D(CURCNTR(PIPE_B), D_ALL); 1673 MMIO_D(CURCNTR(PIPE_C), D_ALL); 1674 1675 MMIO_D(CURPOS(PIPE_A), D_ALL); 1676 MMIO_D(CURPOS(PIPE_B), D_ALL); 1677 MMIO_D(CURPOS(PIPE_C), D_ALL); 1678 1679 MMIO_D(CURBASE(PIPE_A), D_ALL); 1680 MMIO_D(CURBASE(PIPE_B), D_ALL); 1681 MMIO_D(CURBASE(PIPE_C), D_ALL); 1682 1683 MMIO_D(0x700ac, D_ALL); 1684 MMIO_D(0x710ac, D_ALL); 1685 MMIO_D(0x720ac, D_ALL); 1686 1687 MMIO_D(0x70090, D_ALL); 1688 MMIO_D(0x70094, D_ALL); 1689 MMIO_D(0x70098, D_ALL); 1690 MMIO_D(0x7009c, D_ALL); 1691 1692 MMIO_D(DSPCNTR(PIPE_A), D_ALL); 1693 MMIO_D(DSPADDR(PIPE_A), D_ALL); 1694 MMIO_D(DSPSTRIDE(PIPE_A), D_ALL); 1695 MMIO_D(DSPPOS(PIPE_A), D_ALL); 1696 MMIO_D(DSPSIZE(PIPE_A), D_ALL); 1697 MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write); 1698 MMIO_D(DSPOFFSET(PIPE_A), D_ALL); 1699 MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL); 1700 1701 MMIO_D(DSPCNTR(PIPE_B), D_ALL); 1702 MMIO_D(DSPADDR(PIPE_B), D_ALL); 1703 MMIO_D(DSPSTRIDE(PIPE_B), D_ALL); 1704 MMIO_D(DSPPOS(PIPE_B), D_ALL); 1705 MMIO_D(DSPSIZE(PIPE_B), D_ALL); 1706 MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write); 1707 MMIO_D(DSPOFFSET(PIPE_B), D_ALL); 1708 MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL); 1709 1710 MMIO_D(DSPCNTR(PIPE_C), D_ALL); 1711 MMIO_D(DSPADDR(PIPE_C), D_ALL); 1712 MMIO_D(DSPSTRIDE(PIPE_C), D_ALL); 1713 MMIO_D(DSPPOS(PIPE_C), D_ALL); 1714 MMIO_D(DSPSIZE(PIPE_C), D_ALL); 1715 MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write); 1716 MMIO_D(DSPOFFSET(PIPE_C), D_ALL); 1717 MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL); 1718 1719 MMIO_D(SPRCTL(PIPE_A), D_ALL); 1720 MMIO_D(SPRLINOFF(PIPE_A), D_ALL); 1721 MMIO_D(SPRSTRIDE(PIPE_A), D_ALL); 1722 MMIO_D(SPRPOS(PIPE_A), D_ALL); 1723 MMIO_D(SPRSIZE(PIPE_A), D_ALL); 1724 MMIO_D(SPRKEYVAL(PIPE_A), D_ALL); 1725 MMIO_D(SPRKEYMSK(PIPE_A), D_ALL); 1726 MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write); 1727 MMIO_D(SPRKEYMAX(PIPE_A), D_ALL); 1728 MMIO_D(SPROFFSET(PIPE_A), D_ALL); 1729 MMIO_D(SPRSCALE(PIPE_A), D_ALL); 1730 MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL); 1731 1732 MMIO_D(SPRCTL(PIPE_B), D_ALL); 1733 MMIO_D(SPRLINOFF(PIPE_B), D_ALL); 1734 MMIO_D(SPRSTRIDE(PIPE_B), D_ALL); 1735 MMIO_D(SPRPOS(PIPE_B), D_ALL); 1736 MMIO_D(SPRSIZE(PIPE_B), D_ALL); 1737 MMIO_D(SPRKEYVAL(PIPE_B), D_ALL); 1738 MMIO_D(SPRKEYMSK(PIPE_B), D_ALL); 1739 MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write); 1740 MMIO_D(SPRKEYMAX(PIPE_B), D_ALL); 1741 MMIO_D(SPROFFSET(PIPE_B), D_ALL); 1742 MMIO_D(SPRSCALE(PIPE_B), D_ALL); 1743 MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL); 1744 1745 MMIO_D(SPRCTL(PIPE_C), D_ALL); 1746 MMIO_D(SPRLINOFF(PIPE_C), D_ALL); 1747 MMIO_D(SPRSTRIDE(PIPE_C), D_ALL); 1748 MMIO_D(SPRPOS(PIPE_C), D_ALL); 1749 MMIO_D(SPRSIZE(PIPE_C), D_ALL); 1750 MMIO_D(SPRKEYVAL(PIPE_C), D_ALL); 1751 MMIO_D(SPRKEYMSK(PIPE_C), D_ALL); 1752 MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write); 1753 MMIO_D(SPRKEYMAX(PIPE_C), D_ALL); 1754 MMIO_D(SPROFFSET(PIPE_C), D_ALL); 1755 MMIO_D(SPRSCALE(PIPE_C), D_ALL); 1756 MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL); 1757 1758 MMIO_F(LGC_PALETTE(PIPE_A, 0), 4 * 256, 0, 0, 0, D_ALL, NULL, NULL); 1759 MMIO_F(LGC_PALETTE(PIPE_B, 0), 4 * 256, 0, 0, 0, D_ALL, NULL, NULL); 1760 MMIO_F(LGC_PALETTE(PIPE_C, 0), 4 * 256, 0, 0, 0, D_ALL, NULL, NULL); 1761 1762 MMIO_D(HTOTAL(TRANSCODER_A), D_ALL); 1763 MMIO_D(HBLANK(TRANSCODER_A), D_ALL); 1764 MMIO_D(HSYNC(TRANSCODER_A), D_ALL); 1765 MMIO_D(VTOTAL(TRANSCODER_A), D_ALL); 1766 MMIO_D(VBLANK(TRANSCODER_A), D_ALL); 1767 MMIO_D(VSYNC(TRANSCODER_A), D_ALL); 1768 MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL); 1769 MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL); 1770 MMIO_D(PIPESRC(TRANSCODER_A), D_ALL); 1771 1772 MMIO_D(HTOTAL(TRANSCODER_B), D_ALL); 1773 MMIO_D(HBLANK(TRANSCODER_B), D_ALL); 1774 MMIO_D(HSYNC(TRANSCODER_B), D_ALL); 1775 MMIO_D(VTOTAL(TRANSCODER_B), D_ALL); 1776 MMIO_D(VBLANK(TRANSCODER_B), D_ALL); 1777 MMIO_D(VSYNC(TRANSCODER_B), D_ALL); 1778 MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL); 1779 MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL); 1780 MMIO_D(PIPESRC(TRANSCODER_B), D_ALL); 1781 1782 MMIO_D(HTOTAL(TRANSCODER_C), D_ALL); 1783 MMIO_D(HBLANK(TRANSCODER_C), D_ALL); 1784 MMIO_D(HSYNC(TRANSCODER_C), D_ALL); 1785 MMIO_D(VTOTAL(TRANSCODER_C), D_ALL); 1786 MMIO_D(VBLANK(TRANSCODER_C), D_ALL); 1787 MMIO_D(VSYNC(TRANSCODER_C), D_ALL); 1788 MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL); 1789 MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL); 1790 MMIO_D(PIPESRC(TRANSCODER_C), D_ALL); 1791 1792 MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL); 1793 MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL); 1794 MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL); 1795 MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL); 1796 MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL); 1797 MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL); 1798 MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL); 1799 MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL); 1800 1801 MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL); 1802 MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL); 1803 MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL); 1804 MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL); 1805 MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL); 1806 MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL); 1807 MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL); 1808 MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL); 1809 1810 MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL); 1811 MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL); 1812 MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL); 1813 MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL); 1814 MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL); 1815 MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL); 1816 MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL); 1817 MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL); 1818 1819 MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL); 1820 MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL); 1821 MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL); 1822 MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL); 1823 MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL); 1824 MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL); 1825 MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL); 1826 MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL); 1827 1828 MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL); 1829 MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL); 1830 MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL); 1831 MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL); 1832 MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL); 1833 MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL); 1834 MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL); 1835 MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL); 1836 1837 MMIO_D(PF_CTL(PIPE_A), D_ALL); 1838 MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL); 1839 MMIO_D(PF_WIN_POS(PIPE_A), D_ALL); 1840 MMIO_D(PF_VSCALE(PIPE_A), D_ALL); 1841 MMIO_D(PF_HSCALE(PIPE_A), D_ALL); 1842 1843 MMIO_D(PF_CTL(PIPE_B), D_ALL); 1844 MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL); 1845 MMIO_D(PF_WIN_POS(PIPE_B), D_ALL); 1846 MMIO_D(PF_VSCALE(PIPE_B), D_ALL); 1847 MMIO_D(PF_HSCALE(PIPE_B), D_ALL); 1848 1849 MMIO_D(PF_CTL(PIPE_C), D_ALL); 1850 MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL); 1851 MMIO_D(PF_WIN_POS(PIPE_C), D_ALL); 1852 MMIO_D(PF_VSCALE(PIPE_C), D_ALL); 1853 MMIO_D(PF_HSCALE(PIPE_C), D_ALL); 1854 1855 MMIO_D(WM0_PIPEA_ILK, D_ALL); 1856 MMIO_D(WM0_PIPEB_ILK, D_ALL); 1857 MMIO_D(WM0_PIPEC_IVB, D_ALL); 1858 MMIO_D(WM1_LP_ILK, D_ALL); 1859 MMIO_D(WM2_LP_ILK, D_ALL); 1860 MMIO_D(WM3_LP_ILK, D_ALL); 1861 MMIO_D(WM1S_LP_ILK, D_ALL); 1862 MMIO_D(WM2S_LP_IVB, D_ALL); 1863 MMIO_D(WM3S_LP_IVB, D_ALL); 1864 1865 MMIO_D(BLC_PWM_CPU_CTL2, D_ALL); 1866 MMIO_D(BLC_PWM_CPU_CTL, D_ALL); 1867 MMIO_D(BLC_PWM_PCH_CTL1, D_ALL); 1868 MMIO_D(BLC_PWM_PCH_CTL2, D_ALL); 1869 1870 MMIO_D(0x48268, D_ALL); 1871 1872 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read, 1873 gmbus_mmio_write); 1874 MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL); 1875 MMIO_F(0xe4f00, 0x28, 0, 0, 0, D_ALL, NULL, NULL); 1876 1877 MMIO_F(_PCH_DPB_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 1878 dp_aux_ch_ctl_mmio_write); 1879 MMIO_F(_PCH_DPC_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 1880 dp_aux_ch_ctl_mmio_write); 1881 MMIO_F(_PCH_DPD_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 1882 dp_aux_ch_ctl_mmio_write); 1883 1884 MMIO_RO(PCH_ADPA, D_ALL, 0, ADPA_CRT_HOTPLUG_MONITOR_MASK, NULL, pch_adpa_mmio_write); 1885 1886 MMIO_DH(_PCH_TRANSACONF, D_ALL, NULL, transconf_mmio_write); 1887 MMIO_DH(_PCH_TRANSBCONF, D_ALL, NULL, transconf_mmio_write); 1888 1889 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write); 1890 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write); 1891 MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write); 1892 MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); 1893 MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); 1894 MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); 1895 MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); 1896 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); 1897 MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); 1898 1899 MMIO_D(_PCH_TRANS_HTOTAL_A, D_ALL); 1900 MMIO_D(_PCH_TRANS_HBLANK_A, D_ALL); 1901 MMIO_D(_PCH_TRANS_HSYNC_A, D_ALL); 1902 MMIO_D(_PCH_TRANS_VTOTAL_A, D_ALL); 1903 MMIO_D(_PCH_TRANS_VBLANK_A, D_ALL); 1904 MMIO_D(_PCH_TRANS_VSYNC_A, D_ALL); 1905 MMIO_D(_PCH_TRANS_VSYNCSHIFT_A, D_ALL); 1906 1907 MMIO_D(_PCH_TRANS_HTOTAL_B, D_ALL); 1908 MMIO_D(_PCH_TRANS_HBLANK_B, D_ALL); 1909 MMIO_D(_PCH_TRANS_HSYNC_B, D_ALL); 1910 MMIO_D(_PCH_TRANS_VTOTAL_B, D_ALL); 1911 MMIO_D(_PCH_TRANS_VBLANK_B, D_ALL); 1912 MMIO_D(_PCH_TRANS_VSYNC_B, D_ALL); 1913 MMIO_D(_PCH_TRANS_VSYNCSHIFT_B, D_ALL); 1914 1915 MMIO_D(_PCH_TRANSA_DATA_M1, D_ALL); 1916 MMIO_D(_PCH_TRANSA_DATA_N1, D_ALL); 1917 MMIO_D(_PCH_TRANSA_DATA_M2, D_ALL); 1918 MMIO_D(_PCH_TRANSA_DATA_N2, D_ALL); 1919 MMIO_D(_PCH_TRANSA_LINK_M1, D_ALL); 1920 MMIO_D(_PCH_TRANSA_LINK_N1, D_ALL); 1921 MMIO_D(_PCH_TRANSA_LINK_M2, D_ALL); 1922 MMIO_D(_PCH_TRANSA_LINK_N2, D_ALL); 1923 1924 MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL); 1925 MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL); 1926 MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL); 1927 1928 MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL); 1929 MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL); 1930 MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL); 1931 1932 MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL); 1933 MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL); 1934 MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL); 1935 1936 MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL); 1937 MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL); 1938 MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL); 1939 1940 MMIO_D(_FDI_RXA_MISC, D_ALL); 1941 MMIO_D(_FDI_RXB_MISC, D_ALL); 1942 MMIO_D(_FDI_RXA_TUSIZE1, D_ALL); 1943 MMIO_D(_FDI_RXA_TUSIZE2, D_ALL); 1944 MMIO_D(_FDI_RXB_TUSIZE1, D_ALL); 1945 MMIO_D(_FDI_RXB_TUSIZE2, D_ALL); 1946 1947 MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write); 1948 MMIO_D(PCH_PP_DIVISOR, D_ALL); 1949 MMIO_D(PCH_PP_STATUS, D_ALL); 1950 MMIO_D(PCH_LVDS, D_ALL); 1951 MMIO_D(_PCH_DPLL_A, D_ALL); 1952 MMIO_D(_PCH_DPLL_B, D_ALL); 1953 MMIO_D(_PCH_FPA0, D_ALL); 1954 MMIO_D(_PCH_FPA1, D_ALL); 1955 MMIO_D(_PCH_FPB0, D_ALL); 1956 MMIO_D(_PCH_FPB1, D_ALL); 1957 MMIO_D(PCH_DREF_CONTROL, D_ALL); 1958 MMIO_D(PCH_RAWCLK_FREQ, D_ALL); 1959 MMIO_D(PCH_DPLL_SEL, D_ALL); 1960 1961 MMIO_D(0x61208, D_ALL); 1962 MMIO_D(0x6120c, D_ALL); 1963 MMIO_D(PCH_PP_ON_DELAYS, D_ALL); 1964 MMIO_D(PCH_PP_OFF_DELAYS, D_ALL); 1965 1966 MMIO_DH(0xe651c, D_ALL, dpy_reg_mmio_read, NULL); 1967 MMIO_DH(0xe661c, D_ALL, dpy_reg_mmio_read, NULL); 1968 MMIO_DH(0xe671c, D_ALL, dpy_reg_mmio_read, NULL); 1969 MMIO_DH(0xe681c, D_ALL, dpy_reg_mmio_read, NULL); 1970 MMIO_DH(0xe6c04, D_ALL, dpy_reg_mmio_read_2, NULL); 1971 MMIO_DH(0xe6e1c, D_ALL, dpy_reg_mmio_read_3, NULL); 1972 1973 MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0, 1974 PORTA_HOTPLUG_STATUS_MASK 1975 | PORTB_HOTPLUG_STATUS_MASK 1976 | PORTC_HOTPLUG_STATUS_MASK 1977 | PORTD_HOTPLUG_STATUS_MASK, 1978 NULL, NULL); 1979 1980 MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write); 1981 MMIO_D(FUSE_STRAP, D_ALL); 1982 MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL); 1983 1984 MMIO_D(DISP_ARB_CTL, D_ALL); 1985 MMIO_D(DISP_ARB_CTL2, D_ALL); 1986 1987 MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL); 1988 MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL); 1989 MMIO_D(ILK_DSPCLK_GATE_D, D_ALL); 1990 1991 MMIO_D(SOUTH_CHICKEN1, D_ALL); 1992 MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write); 1993 MMIO_D(_TRANSA_CHICKEN1, D_ALL); 1994 MMIO_D(_TRANSB_CHICKEN1, D_ALL); 1995 MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL); 1996 MMIO_D(_TRANSA_CHICKEN2, D_ALL); 1997 MMIO_D(_TRANSB_CHICKEN2, D_ALL); 1998 1999 MMIO_D(ILK_DPFC_CB_BASE, D_ALL); 2000 MMIO_D(ILK_DPFC_CONTROL, D_ALL); 2001 MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL); 2002 MMIO_D(ILK_DPFC_STATUS, D_ALL); 2003 MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL); 2004 MMIO_D(ILK_DPFC_CHICKEN, D_ALL); 2005 MMIO_D(ILK_FBC_RT_BASE, D_ALL); 2006 2007 MMIO_D(IPS_CTL, D_ALL); 2008 2009 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL); 2010 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL); 2011 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL); 2012 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL); 2013 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL); 2014 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL); 2015 MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL); 2016 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL); 2017 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL); 2018 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL); 2019 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL); 2020 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL); 2021 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL); 2022 2023 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL); 2024 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL); 2025 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL); 2026 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL); 2027 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL); 2028 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL); 2029 MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL); 2030 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL); 2031 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL); 2032 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL); 2033 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL); 2034 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL); 2035 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL); 2036 2037 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL); 2038 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL); 2039 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL); 2040 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL); 2041 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL); 2042 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL); 2043 MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL); 2044 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL); 2045 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL); 2046 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL); 2047 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL); 2048 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL); 2049 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL); 2050 2051 MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL); 2052 MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL); 2053 MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 2054 2055 MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL); 2056 MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL); 2057 MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 2058 2059 MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL); 2060 MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL); 2061 MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 2062 2063 MMIO_D(0x60110, D_ALL); 2064 MMIO_D(0x61110, D_ALL); 2065 MMIO_F(0x70400, 0x40, 0, 0, 0, D_ALL, NULL, NULL); 2066 MMIO_F(0x71400, 0x40, 0, 0, 0, D_ALL, NULL, NULL); 2067 MMIO_F(0x72400, 0x40, 0, 0, 0, D_ALL, NULL, NULL); 2068 MMIO_F(0x70440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2069 MMIO_F(0x71440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2070 MMIO_F(0x72440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2071 MMIO_F(0x7044c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2072 MMIO_F(0x7144c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2073 MMIO_F(0x7244c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2074 2075 MMIO_D(PIPE_WM_LINETIME(PIPE_A), D_ALL); 2076 MMIO_D(PIPE_WM_LINETIME(PIPE_B), D_ALL); 2077 MMIO_D(PIPE_WM_LINETIME(PIPE_C), D_ALL); 2078 MMIO_D(SPLL_CTL, D_ALL); 2079 MMIO_D(_WRPLL_CTL1, D_ALL); 2080 MMIO_D(_WRPLL_CTL2, D_ALL); 2081 MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL); 2082 MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL); 2083 MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL); 2084 MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL); 2085 MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL); 2086 MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL); 2087 MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL); 2088 MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL); 2089 2090 MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL); 2091 MMIO_D(0x46508, D_ALL); 2092 2093 MMIO_D(0x49080, D_ALL); 2094 MMIO_D(0x49180, D_ALL); 2095 MMIO_D(0x49280, D_ALL); 2096 2097 MMIO_F(0x49090, 0x14, 0, 0, 0, D_ALL, NULL, NULL); 2098 MMIO_F(0x49190, 0x14, 0, 0, 0, D_ALL, NULL, NULL); 2099 MMIO_F(0x49290, 0x14, 0, 0, 0, D_ALL, NULL, NULL); 2100 2101 MMIO_D(GAMMA_MODE(PIPE_A), D_ALL); 2102 MMIO_D(GAMMA_MODE(PIPE_B), D_ALL); 2103 MMIO_D(GAMMA_MODE(PIPE_C), D_ALL); 2104 2105 MMIO_D(PIPE_MULT(PIPE_A), D_ALL); 2106 MMIO_D(PIPE_MULT(PIPE_B), D_ALL); 2107 MMIO_D(PIPE_MULT(PIPE_C), D_ALL); 2108 2109 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL); 2110 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL); 2111 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL); 2112 2113 MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL); 2114 MMIO_D(SBI_ADDR, D_ALL); 2115 MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL); 2116 MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write); 2117 MMIO_D(PIXCLK_GATE, D_ALL); 2118 2119 MMIO_F(_DPA_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_ALL, NULL, 2120 dp_aux_ch_ctl_mmio_write); 2121 2122 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2123 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2124 MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2125 MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2126 MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2127 2128 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write); 2129 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write); 2130 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write); 2131 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write); 2132 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write); 2133 2134 MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write); 2135 MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write); 2136 MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write); 2137 MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write); 2138 MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL); 2139 2140 MMIO_F(_DDI_BUF_TRANS_A, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2141 MMIO_F(0x64e60, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2142 MMIO_F(0x64eC0, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2143 MMIO_F(0x64f20, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2144 MMIO_F(0x64f80, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2145 2146 MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL); 2147 MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL); 2148 2149 MMIO_DH(_TRANS_DDI_FUNC_CTL_A, D_ALL, NULL, NULL); 2150 MMIO_DH(_TRANS_DDI_FUNC_CTL_B, D_ALL, NULL, NULL); 2151 MMIO_DH(_TRANS_DDI_FUNC_CTL_C, D_ALL, NULL, NULL); 2152 MMIO_DH(_TRANS_DDI_FUNC_CTL_EDP, D_ALL, NULL, NULL); 2153 2154 MMIO_D(_TRANSA_MSA_MISC, D_ALL); 2155 MMIO_D(_TRANSB_MSA_MISC, D_ALL); 2156 MMIO_D(_TRANSC_MSA_MISC, D_ALL); 2157 MMIO_D(_TRANS_EDP_MSA_MISC, D_ALL); 2158 2159 MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL); 2160 MMIO_D(FORCEWAKE_ACK, D_ALL); 2161 MMIO_D(GEN6_GT_CORE_STATUS, D_ALL); 2162 MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL); 2163 MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL); 2164 MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL); 2165 MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write); 2166 MMIO_DH(FORCEWAKE_ACK_HSW, D_HSW | D_BDW, NULL, NULL); 2167 MMIO_D(ECOBUS, D_ALL); 2168 MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL); 2169 MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL); 2170 MMIO_D(GEN6_RPNSWREQ, D_ALL); 2171 MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL); 2172 MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL); 2173 MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL); 2174 MMIO_D(GEN6_RPSTAT1, D_ALL); 2175 MMIO_D(GEN6_RP_CONTROL, D_ALL); 2176 MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL); 2177 MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL); 2178 MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL); 2179 MMIO_D(GEN6_RP_CUR_UP, D_ALL); 2180 MMIO_D(GEN6_RP_PREV_UP, D_ALL); 2181 MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL); 2182 MMIO_D(GEN6_RP_CUR_DOWN, D_ALL); 2183 MMIO_D(GEN6_RP_PREV_DOWN, D_ALL); 2184 MMIO_D(GEN6_RP_UP_EI, D_ALL); 2185 MMIO_D(GEN6_RP_DOWN_EI, D_ALL); 2186 MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL); 2187 MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL); 2188 MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL); 2189 MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL); 2190 MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL); 2191 MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL); 2192 MMIO_D(GEN6_RC_SLEEP, D_ALL); 2193 MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL); 2194 MMIO_D(GEN6_RC6_THRESHOLD, D_ALL); 2195 MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL); 2196 MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL); 2197 MMIO_D(GEN6_PMINTRMSK, D_ALL); 2198 MMIO_DH(HSW_PWR_WELL_BIOS, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); 2199 MMIO_DH(HSW_PWR_WELL_DRIVER, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); 2200 MMIO_DH(HSW_PWR_WELL_KVMR, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); 2201 MMIO_DH(HSW_PWR_WELL_DEBUG, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); 2202 MMIO_DH(HSW_PWR_WELL_CTL5, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); 2203 MMIO_DH(HSW_PWR_WELL_CTL6, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); 2204 2205 MMIO_D(RSTDBYCTL, D_ALL); 2206 2207 MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write); 2208 MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write); 2209 MMIO_F(VGT_PVINFO_PAGE, VGT_PVINFO_SIZE, F_UNALIGN, 0, 0, D_ALL, pvinfo_mmio_read, pvinfo_mmio_write); 2210 MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write); 2211 2212 MMIO_F(MCHBAR_MIRROR_BASE_SNB, 0x40000, 0, 0, 0, D_ALL, NULL, NULL); 2213 2214 MMIO_D(TILECTL, D_ALL); 2215 2216 MMIO_D(GEN6_UCGCTL1, D_ALL); 2217 MMIO_D(GEN6_UCGCTL2, D_ALL); 2218 2219 MMIO_F(0x4f000, 0x90, 0, 0, 0, D_ALL, NULL, NULL); 2220 2221 MMIO_D(GEN6_PCODE_MAILBOX, D_PRE_BDW); 2222 MMIO_D(GEN6_PCODE_DATA, D_ALL); 2223 MMIO_D(0x13812c, D_ALL); 2224 MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL); 2225 MMIO_D(HSW_EDRAM_CAP, D_ALL); 2226 MMIO_D(HSW_IDICR, D_ALL); 2227 MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL); 2228 2229 MMIO_D(0x3c, D_ALL); 2230 MMIO_D(0x860, D_ALL); 2231 MMIO_D(ECOSKPD, D_ALL); 2232 MMIO_D(0x121d0, D_ALL); 2233 MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL); 2234 MMIO_D(0x41d0, D_ALL); 2235 MMIO_D(GAC_ECO_BITS, D_ALL); 2236 MMIO_D(0x6200, D_ALL); 2237 MMIO_D(0x6204, D_ALL); 2238 MMIO_D(0x6208, D_ALL); 2239 MMIO_D(0x7118, D_ALL); 2240 MMIO_D(0x7180, D_ALL); 2241 MMIO_D(0x7408, D_ALL); 2242 MMIO_D(0x7c00, D_ALL); 2243 MMIO_D(GEN6_MBCTL, D_ALL); 2244 MMIO_D(0x911c, D_ALL); 2245 MMIO_D(0x9120, D_ALL); 2246 MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL); 2247 2248 MMIO_D(GAB_CTL, D_ALL); 2249 MMIO_D(0x48800, D_ALL); 2250 MMIO_D(0xce044, D_ALL); 2251 MMIO_D(0xe6500, D_ALL); 2252 MMIO_D(0xe6504, D_ALL); 2253 MMIO_D(0xe6600, D_ALL); 2254 MMIO_D(0xe6604, D_ALL); 2255 MMIO_D(0xe6700, D_ALL); 2256 MMIO_D(0xe6704, D_ALL); 2257 MMIO_D(0xe6800, D_ALL); 2258 MMIO_D(0xe6804, D_ALL); 2259 MMIO_D(PCH_GMBUS4, D_ALL); 2260 MMIO_D(PCH_GMBUS5, D_ALL); 2261 2262 MMIO_D(0x902c, D_ALL); 2263 MMIO_D(0xec008, D_ALL); 2264 MMIO_D(0xec00c, D_ALL); 2265 MMIO_D(0xec008 + 0x18, D_ALL); 2266 MMIO_D(0xec00c + 0x18, D_ALL); 2267 MMIO_D(0xec008 + 0x18 * 2, D_ALL); 2268 MMIO_D(0xec00c + 0x18 * 2, D_ALL); 2269 MMIO_D(0xec008 + 0x18 * 3, D_ALL); 2270 MMIO_D(0xec00c + 0x18 * 3, D_ALL); 2271 MMIO_D(0xec408, D_ALL); 2272 MMIO_D(0xec40c, D_ALL); 2273 MMIO_D(0xec408 + 0x18, D_ALL); 2274 MMIO_D(0xec40c + 0x18, D_ALL); 2275 MMIO_D(0xec408 + 0x18 * 2, D_ALL); 2276 MMIO_D(0xec40c + 0x18 * 2, D_ALL); 2277 MMIO_D(0xec408 + 0x18 * 3, D_ALL); 2278 MMIO_D(0xec40c + 0x18 * 3, D_ALL); 2279 MMIO_D(0xfc810, D_ALL); 2280 MMIO_D(0xfc81c, D_ALL); 2281 MMIO_D(0xfc828, D_ALL); 2282 MMIO_D(0xfc834, D_ALL); 2283 MMIO_D(0xfcc00, D_ALL); 2284 MMIO_D(0xfcc0c, D_ALL); 2285 MMIO_D(0xfcc18, D_ALL); 2286 MMIO_D(0xfcc24, D_ALL); 2287 MMIO_D(0xfd000, D_ALL); 2288 MMIO_D(0xfd00c, D_ALL); 2289 MMIO_D(0xfd018, D_ALL); 2290 MMIO_D(0xfd024, D_ALL); 2291 MMIO_D(0xfd034, D_ALL); 2292 2293 MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write); 2294 MMIO_D(0x2054, D_ALL); 2295 MMIO_D(0x12054, D_ALL); 2296 MMIO_D(0x22054, D_ALL); 2297 MMIO_D(0x1a054, D_ALL); 2298 2299 MMIO_D(0x44070, D_ALL); 2300 MMIO_DFH(0x215c, D_HSW_PLUS, F_CMD_ACCESS, NULL, NULL); 2301 MMIO_DFH(0x2178, D_ALL, F_CMD_ACCESS, NULL, NULL); 2302 MMIO_DFH(0x217c, D_ALL, F_CMD_ACCESS, NULL, NULL); 2303 MMIO_DFH(0x12178, D_ALL, F_CMD_ACCESS, NULL, NULL); 2304 MMIO_DFH(0x1217c, D_ALL, F_CMD_ACCESS, NULL, NULL); 2305 2306 MMIO_F(0x2290, 8, F_CMD_ACCESS, 0, 0, D_HSW_PLUS, NULL, NULL); 2307 MMIO_DFH(GEN7_OACONTROL, D_HSW, F_CMD_ACCESS, NULL, NULL); 2308 MMIO_D(0x2b00, D_BDW_PLUS); 2309 MMIO_D(0x2360, D_BDW_PLUS); 2310 MMIO_F(0x5200, 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2311 MMIO_F(0x5240, 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2312 MMIO_F(0x5280, 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2313 2314 MMIO_DFH(0x1c17c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2315 MMIO_DFH(0x1c178, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2316 MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL); 2317 2318 MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2319 MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2320 MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2321 MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2322 MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2323 MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2324 MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2325 MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2326 MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2327 MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2328 MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2329 MMIO_DH(0x4260, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2330 MMIO_DH(0x4264, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2331 MMIO_DH(0x4268, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2332 MMIO_DH(0x426c, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2333 MMIO_DH(0x4270, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2334 MMIO_DFH(0x4094, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2335 2336 MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2337 MMIO_RING_GM_RDR(RING_BBADDR, D_ALL, NULL, NULL); 2338 MMIO_DFH(0x2220, D_ALL, F_CMD_ACCESS, NULL, NULL); 2339 MMIO_DFH(0x12220, D_ALL, F_CMD_ACCESS, NULL, NULL); 2340 MMIO_DFH(0x22220, D_ALL, F_CMD_ACCESS, NULL, NULL); 2341 MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL); 2342 MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL); 2343 MMIO_DFH(0x22178, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2344 MMIO_DFH(0x1a178, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2345 MMIO_DFH(0x1a17c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2346 MMIO_DFH(0x2217c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2347 return 0; 2348 } 2349 2350 static int init_broadwell_mmio_info(struct intel_gvt *gvt) 2351 { 2352 struct drm_i915_private *dev_priv = gvt->dev_priv; 2353 int ret; 2354 2355 MMIO_DFH(RING_IMR(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS, NULL, 2356 intel_vgpu_reg_imr_handler); 2357 2358 MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2359 MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2360 MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2361 MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS); 2362 2363 MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2364 MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2365 MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2366 MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS); 2367 2368 MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2369 MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2370 MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2371 MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS); 2372 2373 MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2374 MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2375 MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2376 MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS); 2377 2378 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL, 2379 intel_vgpu_reg_imr_handler); 2380 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL, 2381 intel_vgpu_reg_ier_handler); 2382 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL, 2383 intel_vgpu_reg_iir_handler); 2384 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS); 2385 2386 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL, 2387 intel_vgpu_reg_imr_handler); 2388 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL, 2389 intel_vgpu_reg_ier_handler); 2390 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL, 2391 intel_vgpu_reg_iir_handler); 2392 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS); 2393 2394 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL, 2395 intel_vgpu_reg_imr_handler); 2396 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL, 2397 intel_vgpu_reg_ier_handler); 2398 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL, 2399 intel_vgpu_reg_iir_handler); 2400 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS); 2401 2402 MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2403 MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2404 MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2405 MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS); 2406 2407 MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2408 MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2409 MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2410 MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS); 2411 2412 MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2413 MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2414 MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2415 MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS); 2416 2417 MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL, 2418 intel_vgpu_reg_master_irq_handler); 2419 2420 MMIO_DFH(RING_HWSTAM(GEN8_BSD2_RING_BASE), D_BDW_PLUS, 2421 F_CMD_ACCESS, NULL, NULL); 2422 MMIO_DFH(0x1c134, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2423 2424 MMIO_DFH(RING_TAIL(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS, 2425 NULL, NULL); 2426 MMIO_DFH(RING_HEAD(GEN8_BSD2_RING_BASE), D_BDW_PLUS, 2427 F_CMD_ACCESS, NULL, NULL); 2428 MMIO_GM_RDR(RING_START(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, NULL); 2429 MMIO_DFH(RING_CTL(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS, 2430 NULL, NULL); 2431 MMIO_DFH(RING_ACTHD(GEN8_BSD2_RING_BASE), D_BDW_PLUS, 2432 F_CMD_ACCESS, NULL, NULL); 2433 MMIO_DFH(RING_ACTHD_UDW(GEN8_BSD2_RING_BASE), D_BDW_PLUS, 2434 F_CMD_ACCESS, NULL, NULL); 2435 MMIO_DFH(0x1c29c, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, 2436 ring_mode_mmio_write); 2437 MMIO_DFH(RING_MI_MODE(GEN8_BSD2_RING_BASE), D_BDW_PLUS, 2438 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2439 MMIO_DFH(RING_INSTPM(GEN8_BSD2_RING_BASE), D_BDW_PLUS, 2440 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2441 MMIO_DFH(RING_TIMESTAMP(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS, 2442 ring_timestamp_mmio_read, NULL); 2443 2444 MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2445 2446 #define RING_REG(base) (base + 0xd0) 2447 MMIO_RING_F(RING_REG, 4, F_RO, 0, 2448 ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL, 2449 ring_reset_ctl_write); 2450 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 4, F_RO, 0, 2451 ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL, 2452 ring_reset_ctl_write); 2453 #undef RING_REG 2454 2455 #define RING_REG(base) (base + 0x230) 2456 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write); 2457 MMIO_DH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, elsp_mmio_write); 2458 #undef RING_REG 2459 2460 #define RING_REG(base) (base + 0x234) 2461 MMIO_RING_F(RING_REG, 8, F_RO | F_CMD_ACCESS, 0, ~0, D_BDW_PLUS, 2462 NULL, NULL); 2463 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 4, F_RO | F_CMD_ACCESS, 0, 2464 ~0LL, D_BDW_PLUS, NULL, NULL); 2465 #undef RING_REG 2466 2467 #define RING_REG(base) (base + 0x244) 2468 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2469 MMIO_DFH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS, 2470 NULL, NULL); 2471 #undef RING_REG 2472 2473 #define RING_REG(base) (base + 0x370) 2474 MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL); 2475 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 48, F_RO, 0, ~0, D_BDW_PLUS, 2476 NULL, NULL); 2477 #undef RING_REG 2478 2479 #define RING_REG(base) (base + 0x3a0) 2480 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2481 MMIO_DFH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2482 #undef RING_REG 2483 2484 MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS); 2485 MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS); 2486 MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS); 2487 MMIO_D(0x1c1d0, D_BDW_PLUS); 2488 MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS); 2489 MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS); 2490 MMIO_D(0x1c054, D_BDW_PLUS); 2491 2492 MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write); 2493 2494 MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS); 2495 MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS); 2496 2497 MMIO_D(GAMTARBMODE, D_BDW_PLUS); 2498 2499 #define RING_REG(base) (base + 0x270) 2500 MMIO_RING_F(RING_REG, 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL); 2501 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL); 2502 #undef RING_REG 2503 2504 MMIO_RING_GM_RDR(RING_HWS_PGA, D_BDW_PLUS, NULL, NULL); 2505 MMIO_GM_RDR(RING_HWS_PGA(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, NULL); 2506 2507 MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2508 2509 MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS); 2510 MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS); 2511 MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS); 2512 2513 MMIO_D(WM_MISC, D_BDW); 2514 MMIO_D(BDW_EDP_PSR_BASE, D_BDW); 2515 2516 MMIO_D(0x66c00, D_BDW_PLUS); 2517 MMIO_D(0x66c04, D_BDW_PLUS); 2518 2519 MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS); 2520 2521 MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS); 2522 MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS); 2523 MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS); 2524 2525 MMIO_D(0xfdc, D_BDW_PLUS); 2526 MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2527 NULL, NULL); 2528 MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2529 NULL, NULL); 2530 MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2531 2532 MMIO_DFH(0xb1f0, D_BDW, F_CMD_ACCESS, NULL, NULL); 2533 MMIO_DFH(0xb1c0, D_BDW, F_CMD_ACCESS, NULL, NULL); 2534 MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2535 MMIO_DFH(0xb100, D_BDW, F_CMD_ACCESS, NULL, NULL); 2536 MMIO_DFH(0xb10c, D_BDW, F_CMD_ACCESS, NULL, NULL); 2537 MMIO_D(0xb110, D_BDW); 2538 2539 MMIO_F(0x24d0, 48, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, 2540 NULL, force_nonpriv_write); 2541 2542 MMIO_D(0x22040, D_BDW_PLUS); 2543 MMIO_D(0x44484, D_BDW_PLUS); 2544 MMIO_D(0x4448c, D_BDW_PLUS); 2545 2546 MMIO_DFH(0x83a4, D_BDW, F_CMD_ACCESS, NULL, NULL); 2547 MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS); 2548 2549 MMIO_DFH(0x8430, D_BDW, F_CMD_ACCESS, NULL, NULL); 2550 2551 MMIO_D(0x110000, D_BDW_PLUS); 2552 2553 MMIO_D(0x48400, D_BDW_PLUS); 2554 2555 MMIO_D(0x6e570, D_BDW_PLUS); 2556 MMIO_D(0x65f10, D_BDW_PLUS); 2557 2558 MMIO_DFH(0xe194, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2559 MMIO_DFH(0xe188, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2560 MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2561 MMIO_DFH(0x2580, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2562 2563 MMIO_DFH(0x2248, D_BDW, F_CMD_ACCESS, NULL, NULL); 2564 2565 MMIO_DFH(0xe220, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2566 MMIO_DFH(0xe230, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2567 MMIO_DFH(0xe240, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2568 MMIO_DFH(0xe260, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2569 MMIO_DFH(0xe270, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2570 MMIO_DFH(0xe280, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2571 MMIO_DFH(0xe2a0, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2572 MMIO_DFH(0xe2b0, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2573 MMIO_DFH(0xe2c0, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2574 return 0; 2575 } 2576 2577 static int init_skl_mmio_info(struct intel_gvt *gvt) 2578 { 2579 struct drm_i915_private *dev_priv = gvt->dev_priv; 2580 int ret; 2581 2582 MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2583 MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL); 2584 MMIO_DH(FORCEWAKE_BLITTER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2585 MMIO_DH(FORCEWAKE_ACK_BLITTER_GEN9, D_SKL_PLUS, NULL, NULL); 2586 MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2587 MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL); 2588 2589 MMIO_F(_DPB_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL, NULL, dp_aux_ch_ctl_mmio_write); 2590 MMIO_F(_DPC_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL, NULL, dp_aux_ch_ctl_mmio_write); 2591 MMIO_F(_DPD_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL, NULL, dp_aux_ch_ctl_mmio_write); 2592 2593 MMIO_D(HSW_PWR_WELL_BIOS, D_SKL); 2594 MMIO_DH(HSW_PWR_WELL_DRIVER, D_SKL, NULL, skl_power_well_ctl_write); 2595 2596 MMIO_D(0xa210, D_SKL_PLUS); 2597 MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS); 2598 MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS); 2599 MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2600 MMIO_DH(0x4ddc, D_SKL, NULL, skl_misc_ctl_write); 2601 MMIO_DH(0x42080, D_SKL, NULL, skl_misc_ctl_write); 2602 MMIO_D(0x45504, D_SKL); 2603 MMIO_D(0x45520, D_SKL); 2604 MMIO_D(0x46000, D_SKL); 2605 MMIO_DH(0x46010, D_SKL, NULL, skl_lcpll_write); 2606 MMIO_DH(0x46014, D_SKL, NULL, skl_lcpll_write); 2607 MMIO_D(0x6C040, D_SKL); 2608 MMIO_D(0x6C048, D_SKL); 2609 MMIO_D(0x6C050, D_SKL); 2610 MMIO_D(0x6C044, D_SKL); 2611 MMIO_D(0x6C04C, D_SKL); 2612 MMIO_D(0x6C054, D_SKL); 2613 MMIO_D(0x6c058, D_SKL); 2614 MMIO_D(0x6c05c, D_SKL); 2615 MMIO_DH(0X6c060, D_SKL, dpll_status_read, NULL); 2616 2617 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL, NULL, pf_write); 2618 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL, NULL, pf_write); 2619 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL, NULL, pf_write); 2620 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL, NULL, pf_write); 2621 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL, NULL, pf_write); 2622 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL, NULL, pf_write); 2623 2624 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL, NULL, pf_write); 2625 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL, NULL, pf_write); 2626 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL, NULL, pf_write); 2627 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL, NULL, pf_write); 2628 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL, NULL, pf_write); 2629 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL, NULL, pf_write); 2630 2631 MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL, NULL, pf_write); 2632 MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL, NULL, pf_write); 2633 MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL, NULL, pf_write); 2634 MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL, NULL, pf_write); 2635 MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL, NULL, pf_write); 2636 MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL, NULL, pf_write); 2637 2638 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL, NULL, NULL); 2639 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL, NULL, NULL); 2640 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL, NULL, NULL); 2641 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL, NULL, NULL); 2642 2643 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL, NULL, NULL); 2644 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL, NULL, NULL); 2645 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL, NULL, NULL); 2646 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL, NULL, NULL); 2647 2648 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL, NULL, NULL); 2649 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL, NULL, NULL); 2650 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL, NULL, NULL); 2651 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL, NULL, NULL); 2652 2653 MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL, NULL, NULL); 2654 MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL, NULL, NULL); 2655 MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL, NULL, NULL); 2656 2657 MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2658 MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2659 MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2660 2661 MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2662 MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2663 MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2664 2665 MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2666 MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2667 MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2668 2669 MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2670 MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2671 MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL); 2672 2673 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL, NULL, NULL); 2674 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL, NULL, NULL); 2675 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL, NULL, NULL); 2676 2677 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL, NULL, NULL); 2678 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL, NULL, NULL); 2679 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL, NULL, NULL); 2680 2681 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL, NULL, NULL); 2682 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL, NULL, NULL); 2683 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL, NULL, NULL); 2684 2685 MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL, NULL, NULL); 2686 MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL, NULL, NULL); 2687 MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL, NULL, NULL); 2688 2689 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL, NULL, NULL); 2690 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL, NULL, NULL); 2691 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL, NULL, NULL); 2692 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL, NULL, NULL); 2693 2694 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL, NULL, NULL); 2695 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL, NULL, NULL); 2696 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL, NULL, NULL); 2697 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL, NULL, NULL); 2698 2699 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL, NULL, NULL); 2700 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL, NULL, NULL); 2701 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL, NULL, NULL); 2702 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL, NULL, NULL); 2703 2704 MMIO_DH(_REG_701C0(PIPE_A, 1), D_SKL, NULL, NULL); 2705 MMIO_DH(_REG_701C0(PIPE_A, 2), D_SKL, NULL, NULL); 2706 MMIO_DH(_REG_701C0(PIPE_A, 3), D_SKL, NULL, NULL); 2707 MMIO_DH(_REG_701C0(PIPE_A, 4), D_SKL, NULL, NULL); 2708 2709 MMIO_DH(_REG_701C0(PIPE_B, 1), D_SKL, NULL, NULL); 2710 MMIO_DH(_REG_701C0(PIPE_B, 2), D_SKL, NULL, NULL); 2711 MMIO_DH(_REG_701C0(PIPE_B, 3), D_SKL, NULL, NULL); 2712 MMIO_DH(_REG_701C0(PIPE_B, 4), D_SKL, NULL, NULL); 2713 2714 MMIO_DH(_REG_701C0(PIPE_C, 1), D_SKL, NULL, NULL); 2715 MMIO_DH(_REG_701C0(PIPE_C, 2), D_SKL, NULL, NULL); 2716 MMIO_DH(_REG_701C0(PIPE_C, 3), D_SKL, NULL, NULL); 2717 MMIO_DH(_REG_701C0(PIPE_C, 4), D_SKL, NULL, NULL); 2718 2719 MMIO_DH(_REG_701C4(PIPE_A, 1), D_SKL, NULL, NULL); 2720 MMIO_DH(_REG_701C4(PIPE_A, 2), D_SKL, NULL, NULL); 2721 MMIO_DH(_REG_701C4(PIPE_A, 3), D_SKL, NULL, NULL); 2722 MMIO_DH(_REG_701C4(PIPE_A, 4), D_SKL, NULL, NULL); 2723 2724 MMIO_DH(_REG_701C4(PIPE_B, 1), D_SKL, NULL, NULL); 2725 MMIO_DH(_REG_701C4(PIPE_B, 2), D_SKL, NULL, NULL); 2726 MMIO_DH(_REG_701C4(PIPE_B, 3), D_SKL, NULL, NULL); 2727 MMIO_DH(_REG_701C4(PIPE_B, 4), D_SKL, NULL, NULL); 2728 2729 MMIO_DH(_REG_701C4(PIPE_C, 1), D_SKL, NULL, NULL); 2730 MMIO_DH(_REG_701C4(PIPE_C, 2), D_SKL, NULL, NULL); 2731 MMIO_DH(_REG_701C4(PIPE_C, 3), D_SKL, NULL, NULL); 2732 MMIO_DH(_REG_701C4(PIPE_C, 4), D_SKL, NULL, NULL); 2733 2734 MMIO_D(0x70380, D_SKL); 2735 MMIO_D(0x71380, D_SKL); 2736 MMIO_D(0x72380, D_SKL); 2737 MMIO_D(0x7039c, D_SKL); 2738 2739 MMIO_F(0x80000, 0x3000, 0, 0, 0, D_SKL, NULL, NULL); 2740 MMIO_D(0x8f074, D_SKL); 2741 MMIO_D(0x8f004, D_SKL); 2742 MMIO_D(0x8f034, D_SKL); 2743 2744 MMIO_D(0xb11c, D_SKL); 2745 2746 MMIO_D(0x51000, D_SKL); 2747 MMIO_D(0x6c00c, D_SKL); 2748 2749 MMIO_F(0xc800, 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL, NULL, NULL); 2750 MMIO_F(0xb020, 0x80, F_CMD_ACCESS, 0, 0, D_SKL, NULL, NULL); 2751 2752 MMIO_D(0xd08, D_SKL); 2753 MMIO_DFH(0x20e0, D_SKL, F_MODE_MASK, NULL, NULL); 2754 MMIO_DFH(0x20ec, D_SKL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2755 2756 /* TRTT */ 2757 MMIO_DFH(0x4de0, D_SKL, F_CMD_ACCESS, NULL, NULL); 2758 MMIO_DFH(0x4de4, D_SKL, F_CMD_ACCESS, NULL, NULL); 2759 MMIO_DFH(0x4de8, D_SKL, F_CMD_ACCESS, NULL, NULL); 2760 MMIO_DFH(0x4dec, D_SKL, F_CMD_ACCESS, NULL, NULL); 2761 MMIO_DFH(0x4df0, D_SKL, F_CMD_ACCESS, NULL, NULL); 2762 MMIO_DFH(0x4df4, D_SKL, F_CMD_ACCESS, NULL, gen9_trtte_write); 2763 MMIO_DH(0x4dfc, D_SKL, NULL, gen9_trtt_chicken_write); 2764 2765 MMIO_D(0x45008, D_SKL); 2766 2767 MMIO_D(0x46430, D_SKL); 2768 2769 MMIO_D(0x46520, D_SKL); 2770 2771 MMIO_D(0xc403c, D_SKL); 2772 MMIO_D(0xb004, D_SKL); 2773 MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write); 2774 2775 MMIO_D(0x65900, D_SKL); 2776 MMIO_D(0x1082c0, D_SKL); 2777 MMIO_D(0x4068, D_SKL); 2778 MMIO_D(0x67054, D_SKL); 2779 MMIO_D(0x6e560, D_SKL); 2780 MMIO_D(0x6e554, D_SKL); 2781 MMIO_D(0x2b20, D_SKL); 2782 MMIO_D(0x65f00, D_SKL); 2783 MMIO_D(0x65f08, D_SKL); 2784 MMIO_D(0x320f0, D_SKL); 2785 2786 MMIO_DFH(_REG_VCS2_EXCC, D_SKL, F_CMD_ACCESS, NULL, NULL); 2787 MMIO_D(0x70034, D_SKL); 2788 MMIO_D(0x71034, D_SKL); 2789 MMIO_D(0x72034, D_SKL); 2790 2791 MMIO_D(_PLANE_KEYVAL_1(PIPE_A), D_SKL); 2792 MMIO_D(_PLANE_KEYVAL_1(PIPE_B), D_SKL); 2793 MMIO_D(_PLANE_KEYVAL_1(PIPE_C), D_SKL); 2794 MMIO_D(_PLANE_KEYMSK_1(PIPE_A), D_SKL); 2795 MMIO_D(_PLANE_KEYMSK_1(PIPE_B), D_SKL); 2796 MMIO_D(_PLANE_KEYMSK_1(PIPE_C), D_SKL); 2797 2798 MMIO_D(0x44500, D_SKL); 2799 MMIO_DFH(GEN9_CSFE_CHICKEN1_RCS, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2800 MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL, F_MODE_MASK | F_CMD_ACCESS, 2801 NULL, NULL); 2802 return 0; 2803 } 2804 2805 /** 2806 * intel_gvt_find_mmio_info - find MMIO information entry by aligned offset 2807 * @gvt: GVT device 2808 * @offset: register offset 2809 * 2810 * This function is used to find the MMIO information entry from hash table 2811 * 2812 * Returns: 2813 * pointer to MMIO information entry, NULL if not exists 2814 */ 2815 struct intel_gvt_mmio_info *intel_gvt_find_mmio_info(struct intel_gvt *gvt, 2816 unsigned int offset) 2817 { 2818 struct intel_gvt_mmio_info *e; 2819 2820 WARN_ON(!IS_ALIGNED(offset, 4)); 2821 2822 hash_for_each_possible(gvt->mmio.mmio_info_table, e, node, offset) { 2823 if (e->offset == offset) 2824 return e; 2825 } 2826 return NULL; 2827 } 2828 2829 /** 2830 * intel_gvt_clean_mmio_info - clean up MMIO information table for GVT device 2831 * @gvt: GVT device 2832 * 2833 * This function is called at the driver unloading stage, to clean up the MMIO 2834 * information table of GVT device 2835 * 2836 */ 2837 void intel_gvt_clean_mmio_info(struct intel_gvt *gvt) 2838 { 2839 struct hlist_node *tmp; 2840 struct intel_gvt_mmio_info *e; 2841 int i; 2842 2843 hash_for_each_safe(gvt->mmio.mmio_info_table, i, tmp, e, node) 2844 kfree(e); 2845 2846 vfree(gvt->mmio.mmio_attribute); 2847 gvt->mmio.mmio_attribute = NULL; 2848 } 2849 2850 /** 2851 * intel_gvt_setup_mmio_info - setup MMIO information table for GVT device 2852 * @gvt: GVT device 2853 * 2854 * This function is called at the initialization stage, to setup the MMIO 2855 * information table for GVT device 2856 * 2857 * Returns: 2858 * zero on success, negative if failed. 2859 */ 2860 int intel_gvt_setup_mmio_info(struct intel_gvt *gvt) 2861 { 2862 struct intel_gvt_device_info *info = &gvt->device_info; 2863 struct drm_i915_private *dev_priv = gvt->dev_priv; 2864 int ret; 2865 2866 gvt->mmio.mmio_attribute = vzalloc(info->mmio_size); 2867 if (!gvt->mmio.mmio_attribute) 2868 return -ENOMEM; 2869 2870 ret = init_generic_mmio_info(gvt); 2871 if (ret) 2872 goto err; 2873 2874 if (IS_BROADWELL(dev_priv)) { 2875 ret = init_broadwell_mmio_info(gvt); 2876 if (ret) 2877 goto err; 2878 } else if (IS_SKYLAKE(dev_priv)) { 2879 ret = init_broadwell_mmio_info(gvt); 2880 if (ret) 2881 goto err; 2882 ret = init_skl_mmio_info(gvt); 2883 if (ret) 2884 goto err; 2885 } 2886 return 0; 2887 err: 2888 intel_gvt_clean_mmio_info(gvt); 2889 return ret; 2890 } 2891 2892 /** 2893 * intel_gvt_mmio_set_accessed - mark a MMIO has been accessed 2894 * @gvt: a GVT device 2895 * @offset: register offset 2896 * 2897 */ 2898 void intel_gvt_mmio_set_accessed(struct intel_gvt *gvt, unsigned int offset) 2899 { 2900 gvt->mmio.mmio_attribute[offset >> 2] |= 2901 F_ACCESSED; 2902 } 2903 2904 /** 2905 * intel_gvt_mmio_is_cmd_accessed - mark a MMIO could be accessed by command 2906 * @gvt: a GVT device 2907 * @offset: register offset 2908 * 2909 */ 2910 bool intel_gvt_mmio_is_cmd_access(struct intel_gvt *gvt, 2911 unsigned int offset) 2912 { 2913 return gvt->mmio.mmio_attribute[offset >> 2] & 2914 F_CMD_ACCESS; 2915 } 2916 2917 /** 2918 * intel_gvt_mmio_is_unalign - mark a MMIO could be accessed unaligned 2919 * @gvt: a GVT device 2920 * @offset: register offset 2921 * 2922 */ 2923 bool intel_gvt_mmio_is_unalign(struct intel_gvt *gvt, 2924 unsigned int offset) 2925 { 2926 return gvt->mmio.mmio_attribute[offset >> 2] & 2927 F_UNALIGN; 2928 } 2929 2930 /** 2931 * intel_gvt_mmio_set_cmd_accessed - mark a MMIO has been accessed by command 2932 * @gvt: a GVT device 2933 * @offset: register offset 2934 * 2935 */ 2936 void intel_gvt_mmio_set_cmd_accessed(struct intel_gvt *gvt, 2937 unsigned int offset) 2938 { 2939 gvt->mmio.mmio_attribute[offset >> 2] |= 2940 F_CMD_ACCESSED; 2941 } 2942 2943 /** 2944 * intel_gvt_mmio_has_mode_mask - if a MMIO has a mode mask 2945 * @gvt: a GVT device 2946 * @offset: register offset 2947 * 2948 * Returns: 2949 * True if a MMIO has a mode mask in its higher 16 bits, false if it isn't. 2950 * 2951 */ 2952 bool intel_gvt_mmio_has_mode_mask(struct intel_gvt *gvt, unsigned int offset) 2953 { 2954 return gvt->mmio.mmio_attribute[offset >> 2] & 2955 F_MODE_MASK; 2956 } 2957 2958 /** 2959 * intel_vgpu_default_mmio_read - default MMIO read handler 2960 * @vgpu: a vGPU 2961 * @offset: access offset 2962 * @p_data: data return buffer 2963 * @bytes: access data length 2964 * 2965 * Returns: 2966 * Zero on success, negative error code if failed. 2967 */ 2968 int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 2969 void *p_data, unsigned int bytes) 2970 { 2971 read_vreg(vgpu, offset, p_data, bytes); 2972 return 0; 2973 } 2974 2975 /** 2976 * intel_t_default_mmio_write - default MMIO write handler 2977 * @vgpu: a vGPU 2978 * @offset: access offset 2979 * @p_data: write data buffer 2980 * @bytes: access data length 2981 * 2982 * Returns: 2983 * Zero on success, negative error code if failed. 2984 */ 2985 int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 2986 void *p_data, unsigned int bytes) 2987 { 2988 write_vreg(vgpu, offset, p_data, bytes); 2989 return 0; 2990 } 2991