xref: /openbmc/linux/drivers/gpu/drm/i915/gvt/handlers.c (revision 1fa0a7dc)
1 /*
2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21  * SOFTWARE.
22  *
23  * Authors:
24  *    Kevin Tian <kevin.tian@intel.com>
25  *    Eddie Dong <eddie.dong@intel.com>
26  *    Zhiyuan Lv <zhiyuan.lv@intel.com>
27  *
28  * Contributors:
29  *    Min He <min.he@intel.com>
30  *    Tina Zhang <tina.zhang@intel.com>
31  *    Pei Zhang <pei.zhang@intel.com>
32  *    Niu Bing <bing.niu@intel.com>
33  *    Ping Gao <ping.a.gao@intel.com>
34  *    Zhi Wang <zhi.a.wang@intel.com>
35  *
36 
37  */
38 
39 #include "i915_drv.h"
40 #include "gvt.h"
41 #include "i915_pvinfo.h"
42 
43 /* XXX FIXME i915 has changed PP_XXX definition */
44 #define PCH_PP_STATUS  _MMIO(0xc7200)
45 #define PCH_PP_CONTROL _MMIO(0xc7204)
46 #define PCH_PP_ON_DELAYS _MMIO(0xc7208)
47 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
48 #define PCH_PP_DIVISOR _MMIO(0xc7210)
49 
50 unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt)
51 {
52 	if (IS_BROADWELL(gvt->dev_priv))
53 		return D_BDW;
54 	else if (IS_SKYLAKE(gvt->dev_priv))
55 		return D_SKL;
56 	else if (IS_KABYLAKE(gvt->dev_priv))
57 		return D_KBL;
58 	else if (IS_BROXTON(gvt->dev_priv))
59 		return D_BXT;
60 	else if (IS_COFFEELAKE(gvt->dev_priv))
61 		return D_CFL;
62 
63 	return 0;
64 }
65 
66 bool intel_gvt_match_device(struct intel_gvt *gvt,
67 		unsigned long device)
68 {
69 	return intel_gvt_get_device_type(gvt) & device;
70 }
71 
72 static void read_vreg(struct intel_vgpu *vgpu, unsigned int offset,
73 	void *p_data, unsigned int bytes)
74 {
75 	memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
76 }
77 
78 static void write_vreg(struct intel_vgpu *vgpu, unsigned int offset,
79 	void *p_data, unsigned int bytes)
80 {
81 	memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
82 }
83 
84 static struct intel_gvt_mmio_info *find_mmio_info(struct intel_gvt *gvt,
85 						  unsigned int offset)
86 {
87 	struct intel_gvt_mmio_info *e;
88 
89 	hash_for_each_possible(gvt->mmio.mmio_info_table, e, node, offset) {
90 		if (e->offset == offset)
91 			return e;
92 	}
93 	return NULL;
94 }
95 
96 static int new_mmio_info(struct intel_gvt *gvt,
97 		u32 offset, u8 flags, u32 size,
98 		u32 addr_mask, u32 ro_mask, u32 device,
99 		gvt_mmio_func read, gvt_mmio_func write)
100 {
101 	struct intel_gvt_mmio_info *info, *p;
102 	u32 start, end, i;
103 
104 	if (!intel_gvt_match_device(gvt, device))
105 		return 0;
106 
107 	if (WARN_ON(!IS_ALIGNED(offset, 4)))
108 		return -EINVAL;
109 
110 	start = offset;
111 	end = offset + size;
112 
113 	for (i = start; i < end; i += 4) {
114 		info = kzalloc(sizeof(*info), GFP_KERNEL);
115 		if (!info)
116 			return -ENOMEM;
117 
118 		info->offset = i;
119 		p = find_mmio_info(gvt, info->offset);
120 		if (p) {
121 			WARN(1, "dup mmio definition offset %x\n",
122 				info->offset);
123 			kfree(info);
124 
125 			/* We return -EEXIST here to make GVT-g load fail.
126 			 * So duplicated MMIO can be found as soon as
127 			 * possible.
128 			 */
129 			return -EEXIST;
130 		}
131 
132 		info->ro_mask = ro_mask;
133 		info->device = device;
134 		info->read = read ? read : intel_vgpu_default_mmio_read;
135 		info->write = write ? write : intel_vgpu_default_mmio_write;
136 		gvt->mmio.mmio_attribute[info->offset / 4] = flags;
137 		INIT_HLIST_NODE(&info->node);
138 		hash_add(gvt->mmio.mmio_info_table, &info->node, info->offset);
139 		gvt->mmio.num_tracked_mmio++;
140 	}
141 	return 0;
142 }
143 
144 /**
145  * intel_gvt_render_mmio_to_ring_id - convert a mmio offset into ring id
146  * @gvt: a GVT device
147  * @offset: register offset
148  *
149  * Returns:
150  * Ring ID on success, negative error code if failed.
151  */
152 int intel_gvt_render_mmio_to_ring_id(struct intel_gvt *gvt,
153 		unsigned int offset)
154 {
155 	enum intel_engine_id id;
156 	struct intel_engine_cs *engine;
157 
158 	offset &= ~GENMASK(11, 0);
159 	for_each_engine(engine, gvt->dev_priv, id) {
160 		if (engine->mmio_base == offset)
161 			return id;
162 	}
163 	return -ENODEV;
164 }
165 
166 #define offset_to_fence_num(offset) \
167 	((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3)
168 
169 #define fence_num_to_offset(num) \
170 	(num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0)))
171 
172 
173 void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason)
174 {
175 	switch (reason) {
176 	case GVT_FAILSAFE_UNSUPPORTED_GUEST:
177 		pr_err("Detected your guest driver doesn't support GVT-g.\n");
178 		break;
179 	case GVT_FAILSAFE_INSUFFICIENT_RESOURCE:
180 		pr_err("Graphics resource is not enough for the guest\n");
181 		break;
182 	case GVT_FAILSAFE_GUEST_ERR:
183 		pr_err("GVT Internal error  for the guest\n");
184 		break;
185 	default:
186 		break;
187 	}
188 	pr_err("Now vgpu %d will enter failsafe mode.\n", vgpu->id);
189 	vgpu->failsafe = true;
190 }
191 
192 static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu,
193 		unsigned int fence_num, void *p_data, unsigned int bytes)
194 {
195 	unsigned int max_fence = vgpu_fence_sz(vgpu);
196 
197 	if (fence_num >= max_fence) {
198 		gvt_vgpu_err("access oob fence reg %d/%d\n",
199 			     fence_num, max_fence);
200 
201 		/* When guest access oob fence regs without access
202 		 * pv_info first, we treat guest not supporting GVT,
203 		 * and we will let vgpu enter failsafe mode.
204 		 */
205 		if (!vgpu->pv_notified)
206 			enter_failsafe_mode(vgpu,
207 					GVT_FAILSAFE_UNSUPPORTED_GUEST);
208 
209 		memset(p_data, 0, bytes);
210 		return -EINVAL;
211 	}
212 	return 0;
213 }
214 
215 static int gamw_echo_dev_rw_ia_write(struct intel_vgpu *vgpu,
216 		unsigned int offset, void *p_data, unsigned int bytes)
217 {
218 	u32 ips = (*(u32 *)p_data) & GAMW_ECO_ENABLE_64K_IPS_FIELD;
219 
220 	if (INTEL_GEN(vgpu->gvt->dev_priv) <= 10) {
221 		if (ips == GAMW_ECO_ENABLE_64K_IPS_FIELD)
222 			gvt_dbg_core("vgpu%d: ips enabled\n", vgpu->id);
223 		else if (!ips)
224 			gvt_dbg_core("vgpu%d: ips disabled\n", vgpu->id);
225 		else {
226 			/* All engines must be enabled together for vGPU,
227 			 * since we don't know which engine the ppgtt will
228 			 * bind to when shadowing.
229 			 */
230 			gvt_vgpu_err("Unsupported IPS setting %x, cannot enable 64K gtt.\n",
231 				     ips);
232 			return -EINVAL;
233 		}
234 	}
235 
236 	write_vreg(vgpu, offset, p_data, bytes);
237 	return 0;
238 }
239 
240 static int fence_mmio_read(struct intel_vgpu *vgpu, unsigned int off,
241 		void *p_data, unsigned int bytes)
242 {
243 	int ret;
244 
245 	ret = sanitize_fence_mmio_access(vgpu, offset_to_fence_num(off),
246 			p_data, bytes);
247 	if (ret)
248 		return ret;
249 	read_vreg(vgpu, off, p_data, bytes);
250 	return 0;
251 }
252 
253 static int fence_mmio_write(struct intel_vgpu *vgpu, unsigned int off,
254 		void *p_data, unsigned int bytes)
255 {
256 	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
257 	unsigned int fence_num = offset_to_fence_num(off);
258 	int ret;
259 
260 	ret = sanitize_fence_mmio_access(vgpu, fence_num, p_data, bytes);
261 	if (ret)
262 		return ret;
263 	write_vreg(vgpu, off, p_data, bytes);
264 
265 	mmio_hw_access_pre(dev_priv);
266 	intel_vgpu_write_fence(vgpu, fence_num,
267 			vgpu_vreg64(vgpu, fence_num_to_offset(fence_num)));
268 	mmio_hw_access_post(dev_priv);
269 	return 0;
270 }
271 
272 #define CALC_MODE_MASK_REG(old, new) \
273 	(((new) & GENMASK(31, 16)) \
274 	 | ((((old) & GENMASK(15, 0)) & ~((new) >> 16)) \
275 	 | ((new) & ((new) >> 16))))
276 
277 static int mul_force_wake_write(struct intel_vgpu *vgpu,
278 		unsigned int offset, void *p_data, unsigned int bytes)
279 {
280 	u32 old, new;
281 	u32 ack_reg_offset;
282 
283 	old = vgpu_vreg(vgpu, offset);
284 	new = CALC_MODE_MASK_REG(old, *(u32 *)p_data);
285 
286 	if (INTEL_GEN(vgpu->gvt->dev_priv)  >=  9) {
287 		switch (offset) {
288 		case FORCEWAKE_RENDER_GEN9_REG:
289 			ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG;
290 			break;
291 		case FORCEWAKE_BLITTER_GEN9_REG:
292 			ack_reg_offset = FORCEWAKE_ACK_BLITTER_GEN9_REG;
293 			break;
294 		case FORCEWAKE_MEDIA_GEN9_REG:
295 			ack_reg_offset = FORCEWAKE_ACK_MEDIA_GEN9_REG;
296 			break;
297 		default:
298 			/*should not hit here*/
299 			gvt_vgpu_err("invalid forcewake offset 0x%x\n", offset);
300 			return -EINVAL;
301 		}
302 	} else {
303 		ack_reg_offset = FORCEWAKE_ACK_HSW_REG;
304 	}
305 
306 	vgpu_vreg(vgpu, offset) = new;
307 	vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0));
308 	return 0;
309 }
310 
311 static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
312 			    void *p_data, unsigned int bytes)
313 {
314 	intel_engine_mask_t engine_mask = 0;
315 	u32 data;
316 
317 	write_vreg(vgpu, offset, p_data, bytes);
318 	data = vgpu_vreg(vgpu, offset);
319 
320 	if (data & GEN6_GRDOM_FULL) {
321 		gvt_dbg_mmio("vgpu%d: request full GPU reset\n", vgpu->id);
322 		engine_mask = ALL_ENGINES;
323 	} else {
324 		if (data & GEN6_GRDOM_RENDER) {
325 			gvt_dbg_mmio("vgpu%d: request RCS reset\n", vgpu->id);
326 			engine_mask |= BIT(RCS0);
327 		}
328 		if (data & GEN6_GRDOM_MEDIA) {
329 			gvt_dbg_mmio("vgpu%d: request VCS reset\n", vgpu->id);
330 			engine_mask |= BIT(VCS0);
331 		}
332 		if (data & GEN6_GRDOM_BLT) {
333 			gvt_dbg_mmio("vgpu%d: request BCS Reset\n", vgpu->id);
334 			engine_mask |= BIT(BCS0);
335 		}
336 		if (data & GEN6_GRDOM_VECS) {
337 			gvt_dbg_mmio("vgpu%d: request VECS Reset\n", vgpu->id);
338 			engine_mask |= BIT(VECS0);
339 		}
340 		if (data & GEN8_GRDOM_MEDIA2) {
341 			gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id);
342 			engine_mask |= BIT(VCS1);
343 		}
344 		engine_mask &= INTEL_INFO(vgpu->gvt->dev_priv)->engine_mask;
345 	}
346 
347 	/* vgpu_lock already hold by emulate mmio r/w */
348 	intel_gvt_reset_vgpu_locked(vgpu, false, engine_mask);
349 
350 	/* sw will wait for the device to ack the reset request */
351 	vgpu_vreg(vgpu, offset) = 0;
352 
353 	return 0;
354 }
355 
356 static int gmbus_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
357 		void *p_data, unsigned int bytes)
358 {
359 	return intel_gvt_i2c_handle_gmbus_read(vgpu, offset, p_data, bytes);
360 }
361 
362 static int gmbus_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
363 		void *p_data, unsigned int bytes)
364 {
365 	return intel_gvt_i2c_handle_gmbus_write(vgpu, offset, p_data, bytes);
366 }
367 
368 static int pch_pp_control_mmio_write(struct intel_vgpu *vgpu,
369 		unsigned int offset, void *p_data, unsigned int bytes)
370 {
371 	write_vreg(vgpu, offset, p_data, bytes);
372 
373 	if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) {
374 		vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_ON;
375 		vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE;
376 		vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN;
377 		vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE;
378 
379 	} else
380 		vgpu_vreg_t(vgpu, PCH_PP_STATUS) &=
381 			~(PP_ON | PP_SEQUENCE_POWER_DOWN
382 					| PP_CYCLE_DELAY_ACTIVE);
383 	return 0;
384 }
385 
386 static int transconf_mmio_write(struct intel_vgpu *vgpu,
387 		unsigned int offset, void *p_data, unsigned int bytes)
388 {
389 	write_vreg(vgpu, offset, p_data, bytes);
390 
391 	if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE)
392 		vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE;
393 	else
394 		vgpu_vreg(vgpu, offset) &= ~TRANS_STATE_ENABLE;
395 	return 0;
396 }
397 
398 static int lcpll_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
399 		void *p_data, unsigned int bytes)
400 {
401 	write_vreg(vgpu, offset, p_data, bytes);
402 
403 	if (vgpu_vreg(vgpu, offset) & LCPLL_PLL_DISABLE)
404 		vgpu_vreg(vgpu, offset) &= ~LCPLL_PLL_LOCK;
405 	else
406 		vgpu_vreg(vgpu, offset) |= LCPLL_PLL_LOCK;
407 
408 	if (vgpu_vreg(vgpu, offset) & LCPLL_CD_SOURCE_FCLK)
409 		vgpu_vreg(vgpu, offset) |= LCPLL_CD_SOURCE_FCLK_DONE;
410 	else
411 		vgpu_vreg(vgpu, offset) &= ~LCPLL_CD_SOURCE_FCLK_DONE;
412 
413 	return 0;
414 }
415 
416 static int dpy_reg_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
417 		void *p_data, unsigned int bytes)
418 {
419 	switch (offset) {
420 	case 0xe651c:
421 	case 0xe661c:
422 	case 0xe671c:
423 	case 0xe681c:
424 		vgpu_vreg(vgpu, offset) = 1 << 17;
425 		break;
426 	case 0xe6c04:
427 		vgpu_vreg(vgpu, offset) = 0x3;
428 		break;
429 	case 0xe6e1c:
430 		vgpu_vreg(vgpu, offset) = 0x2f << 16;
431 		break;
432 	default:
433 		return -EINVAL;
434 	}
435 
436 	read_vreg(vgpu, offset, p_data, bytes);
437 	return 0;
438 }
439 
440 static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
441 		void *p_data, unsigned int bytes)
442 {
443 	u32 data;
444 
445 	write_vreg(vgpu, offset, p_data, bytes);
446 	data = vgpu_vreg(vgpu, offset);
447 
448 	if (data & PIPECONF_ENABLE)
449 		vgpu_vreg(vgpu, offset) |= I965_PIPECONF_ACTIVE;
450 	else
451 		vgpu_vreg(vgpu, offset) &= ~I965_PIPECONF_ACTIVE;
452 	/* vgpu_lock already hold by emulate mmio r/w */
453 	mutex_unlock(&vgpu->vgpu_lock);
454 	intel_gvt_check_vblank_emulation(vgpu->gvt);
455 	mutex_lock(&vgpu->vgpu_lock);
456 	return 0;
457 }
458 
459 /* ascendingly sorted */
460 static i915_reg_t force_nonpriv_white_list[] = {
461 	GEN9_CS_DEBUG_MODE1, //_MMIO(0x20ec)
462 	GEN9_CTX_PREEMPT_REG,//_MMIO(0x2248)
463 	GEN8_CS_CHICKEN1,//_MMIO(0x2580)
464 	_MMIO(0x2690),
465 	_MMIO(0x2694),
466 	_MMIO(0x2698),
467 	_MMIO(0x4de0),
468 	_MMIO(0x4de4),
469 	_MMIO(0x4dfc),
470 	GEN7_COMMON_SLICE_CHICKEN1,//_MMIO(0x7010)
471 	_MMIO(0x7014),
472 	HDC_CHICKEN0,//_MMIO(0x7300)
473 	GEN8_HDC_CHICKEN1,//_MMIO(0x7304)
474 	_MMIO(0x7700),
475 	_MMIO(0x7704),
476 	_MMIO(0x7708),
477 	_MMIO(0x770c),
478 	_MMIO(0x83a8),
479 	_MMIO(0xb110),
480 	GEN8_L3SQCREG4,//_MMIO(0xb118)
481 	_MMIO(0xe100),
482 	_MMIO(0xe18c),
483 	_MMIO(0xe48c),
484 	_MMIO(0xe5f4),
485 };
486 
487 /* a simple bsearch */
488 static inline bool in_whitelist(unsigned int reg)
489 {
490 	int left = 0, right = ARRAY_SIZE(force_nonpriv_white_list);
491 	i915_reg_t *array = force_nonpriv_white_list;
492 
493 	while (left < right) {
494 		int mid = (left + right)/2;
495 
496 		if (reg > array[mid].reg)
497 			left = mid + 1;
498 		else if (reg < array[mid].reg)
499 			right = mid;
500 		else
501 			return true;
502 	}
503 	return false;
504 }
505 
506 static int force_nonpriv_write(struct intel_vgpu *vgpu,
507 	unsigned int offset, void *p_data, unsigned int bytes)
508 {
509 	u32 reg_nonpriv = *(u32 *)p_data;
510 	int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset);
511 	u32 ring_base;
512 	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
513 	int ret = -EINVAL;
514 
515 	if ((bytes != 4) || ((offset & (bytes - 1)) != 0) || ring_id < 0) {
516 		gvt_err("vgpu(%d) ring %d Invalid FORCE_NONPRIV offset %x(%dB)\n",
517 			vgpu->id, ring_id, offset, bytes);
518 		return ret;
519 	}
520 
521 	ring_base = dev_priv->engine[ring_id]->mmio_base;
522 
523 	if (in_whitelist(reg_nonpriv) ||
524 		reg_nonpriv == i915_mmio_reg_offset(RING_NOPID(ring_base))) {
525 		ret = intel_vgpu_default_mmio_write(vgpu, offset, p_data,
526 			bytes);
527 	} else
528 		gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x at offset %x\n",
529 			vgpu->id, reg_nonpriv, offset);
530 
531 	return 0;
532 }
533 
534 static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
535 		void *p_data, unsigned int bytes)
536 {
537 	write_vreg(vgpu, offset, p_data, bytes);
538 
539 	if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) {
540 		vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE;
541 	} else {
542 		vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE;
543 		if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E)))
544 			vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E))
545 				&= ~DP_TP_STATUS_AUTOTRAIN_DONE;
546 	}
547 	return 0;
548 }
549 
550 static int fdi_rx_iir_mmio_write(struct intel_vgpu *vgpu,
551 		unsigned int offset, void *p_data, unsigned int bytes)
552 {
553 	vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data;
554 	return 0;
555 }
556 
557 #define FDI_LINK_TRAIN_PATTERN1         0
558 #define FDI_LINK_TRAIN_PATTERN2         1
559 
560 static int fdi_auto_training_started(struct intel_vgpu *vgpu)
561 {
562 	u32 ddi_buf_ctl = vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_E));
563 	u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL);
564 	u32 tx_ctl = vgpu_vreg_t(vgpu, DP_TP_CTL(PORT_E));
565 
566 	if ((ddi_buf_ctl & DDI_BUF_CTL_ENABLE) &&
567 			(rx_ctl & FDI_RX_ENABLE) &&
568 			(rx_ctl & FDI_AUTO_TRAINING) &&
569 			(tx_ctl & DP_TP_CTL_ENABLE) &&
570 			(tx_ctl & DP_TP_CTL_FDI_AUTOTRAIN))
571 		return 1;
572 	else
573 		return 0;
574 }
575 
576 static int check_fdi_rx_train_status(struct intel_vgpu *vgpu,
577 		enum pipe pipe, unsigned int train_pattern)
578 {
579 	i915_reg_t fdi_rx_imr, fdi_tx_ctl, fdi_rx_ctl;
580 	unsigned int fdi_rx_check_bits, fdi_tx_check_bits;
581 	unsigned int fdi_rx_train_bits, fdi_tx_train_bits;
582 	unsigned int fdi_iir_check_bits;
583 
584 	fdi_rx_imr = FDI_RX_IMR(pipe);
585 	fdi_tx_ctl = FDI_TX_CTL(pipe);
586 	fdi_rx_ctl = FDI_RX_CTL(pipe);
587 
588 	if (train_pattern == FDI_LINK_TRAIN_PATTERN1) {
589 		fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_1_CPT;
590 		fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_1;
591 		fdi_iir_check_bits = FDI_RX_BIT_LOCK;
592 	} else if (train_pattern == FDI_LINK_TRAIN_PATTERN2) {
593 		fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_2_CPT;
594 		fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_2;
595 		fdi_iir_check_bits = FDI_RX_SYMBOL_LOCK;
596 	} else {
597 		gvt_vgpu_err("Invalid train pattern %d\n", train_pattern);
598 		return -EINVAL;
599 	}
600 
601 	fdi_rx_check_bits = FDI_RX_ENABLE | fdi_rx_train_bits;
602 	fdi_tx_check_bits = FDI_TX_ENABLE | fdi_tx_train_bits;
603 
604 	/* If imr bit has been masked */
605 	if (vgpu_vreg_t(vgpu, fdi_rx_imr) & fdi_iir_check_bits)
606 		return 0;
607 
608 	if (((vgpu_vreg_t(vgpu, fdi_tx_ctl) & fdi_tx_check_bits)
609 			== fdi_tx_check_bits)
610 		&& ((vgpu_vreg_t(vgpu, fdi_rx_ctl) & fdi_rx_check_bits)
611 			== fdi_rx_check_bits))
612 		return 1;
613 	else
614 		return 0;
615 }
616 
617 #define INVALID_INDEX (~0U)
618 
619 static unsigned int calc_index(unsigned int offset, unsigned int start,
620 	unsigned int next, unsigned int end, i915_reg_t i915_end)
621 {
622 	unsigned int range = next - start;
623 
624 	if (!end)
625 		end = i915_mmio_reg_offset(i915_end);
626 	if (offset < start || offset > end)
627 		return INVALID_INDEX;
628 	offset -= start;
629 	return offset / range;
630 }
631 
632 #define FDI_RX_CTL_TO_PIPE(offset) \
633 	calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, 0, FDI_RX_CTL(PIPE_C))
634 
635 #define FDI_TX_CTL_TO_PIPE(offset) \
636 	calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, 0, FDI_TX_CTL(PIPE_C))
637 
638 #define FDI_RX_IMR_TO_PIPE(offset) \
639 	calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, 0, FDI_RX_IMR(PIPE_C))
640 
641 static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu,
642 		unsigned int offset, void *p_data, unsigned int bytes)
643 {
644 	i915_reg_t fdi_rx_iir;
645 	unsigned int index;
646 	int ret;
647 
648 	if (FDI_RX_CTL_TO_PIPE(offset) != INVALID_INDEX)
649 		index = FDI_RX_CTL_TO_PIPE(offset);
650 	else if (FDI_TX_CTL_TO_PIPE(offset) != INVALID_INDEX)
651 		index = FDI_TX_CTL_TO_PIPE(offset);
652 	else if (FDI_RX_IMR_TO_PIPE(offset) != INVALID_INDEX)
653 		index = FDI_RX_IMR_TO_PIPE(offset);
654 	else {
655 		gvt_vgpu_err("Unsupport registers %x\n", offset);
656 		return -EINVAL;
657 	}
658 
659 	write_vreg(vgpu, offset, p_data, bytes);
660 
661 	fdi_rx_iir = FDI_RX_IIR(index);
662 
663 	ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN1);
664 	if (ret < 0)
665 		return ret;
666 	if (ret)
667 		vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK;
668 
669 	ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN2);
670 	if (ret < 0)
671 		return ret;
672 	if (ret)
673 		vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK;
674 
675 	if (offset == _FDI_RXA_CTL)
676 		if (fdi_auto_training_started(vgpu))
677 			vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) |=
678 				DP_TP_STATUS_AUTOTRAIN_DONE;
679 	return 0;
680 }
681 
682 #define DP_TP_CTL_TO_PORT(offset) \
683 	calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, 0, DP_TP_CTL(PORT_E))
684 
685 static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
686 		void *p_data, unsigned int bytes)
687 {
688 	i915_reg_t status_reg;
689 	unsigned int index;
690 	u32 data;
691 
692 	write_vreg(vgpu, offset, p_data, bytes);
693 
694 	index = DP_TP_CTL_TO_PORT(offset);
695 	data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8;
696 	if (data == 0x2) {
697 		status_reg = DP_TP_STATUS(index);
698 		vgpu_vreg_t(vgpu, status_reg) |= (1 << 25);
699 	}
700 	return 0;
701 }
702 
703 static int dp_tp_status_mmio_write(struct intel_vgpu *vgpu,
704 		unsigned int offset, void *p_data, unsigned int bytes)
705 {
706 	u32 reg_val;
707 	u32 sticky_mask;
708 
709 	reg_val = *((u32 *)p_data);
710 	sticky_mask = GENMASK(27, 26) | (1 << 24);
711 
712 	vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) |
713 		(vgpu_vreg(vgpu, offset) & sticky_mask);
714 	vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask);
715 	return 0;
716 }
717 
718 static int pch_adpa_mmio_write(struct intel_vgpu *vgpu,
719 		unsigned int offset, void *p_data, unsigned int bytes)
720 {
721 	u32 data;
722 
723 	write_vreg(vgpu, offset, p_data, bytes);
724 	data = vgpu_vreg(vgpu, offset);
725 
726 	if (data & ADPA_CRT_HOTPLUG_FORCE_TRIGGER)
727 		vgpu_vreg(vgpu, offset) &= ~ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
728 	return 0;
729 }
730 
731 static int south_chicken2_mmio_write(struct intel_vgpu *vgpu,
732 		unsigned int offset, void *p_data, unsigned int bytes)
733 {
734 	u32 data;
735 
736 	write_vreg(vgpu, offset, p_data, bytes);
737 	data = vgpu_vreg(vgpu, offset);
738 
739 	if (data & FDI_MPHY_IOSFSB_RESET_CTL)
740 		vgpu_vreg(vgpu, offset) |= FDI_MPHY_IOSFSB_RESET_STATUS;
741 	else
742 		vgpu_vreg(vgpu, offset) &= ~FDI_MPHY_IOSFSB_RESET_STATUS;
743 	return 0;
744 }
745 
746 #define DSPSURF_TO_PIPE(offset) \
747 	calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C))
748 
749 static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
750 		void *p_data, unsigned int bytes)
751 {
752 	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
753 	u32 pipe = DSPSURF_TO_PIPE(offset);
754 	int event = SKL_FLIP_EVENT(pipe, PLANE_PRIMARY);
755 
756 	write_vreg(vgpu, offset, p_data, bytes);
757 	vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
758 
759 	vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++;
760 
761 	if (vgpu_vreg_t(vgpu, DSPCNTR(pipe)) & PLANE_CTL_ASYNC_FLIP)
762 		intel_vgpu_trigger_virtual_event(vgpu, event);
763 	else
764 		set_bit(event, vgpu->irq.flip_done_event[pipe]);
765 
766 	return 0;
767 }
768 
769 #define SPRSURF_TO_PIPE(offset) \
770 	calc_index(offset, _SPRA_SURF, _SPRB_SURF, 0, SPRSURF(PIPE_C))
771 
772 static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
773 		void *p_data, unsigned int bytes)
774 {
775 	u32 pipe = SPRSURF_TO_PIPE(offset);
776 	int event = SKL_FLIP_EVENT(pipe, PLANE_SPRITE0);
777 
778 	write_vreg(vgpu, offset, p_data, bytes);
779 	vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
780 
781 	if (vgpu_vreg_t(vgpu, SPRCTL(pipe)) & PLANE_CTL_ASYNC_FLIP)
782 		intel_vgpu_trigger_virtual_event(vgpu, event);
783 	else
784 		set_bit(event, vgpu->irq.flip_done_event[pipe]);
785 
786 	return 0;
787 }
788 
789 static int reg50080_mmio_write(struct intel_vgpu *vgpu,
790 			       unsigned int offset, void *p_data,
791 			       unsigned int bytes)
792 {
793 	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
794 	enum pipe pipe = REG_50080_TO_PIPE(offset);
795 	enum plane_id plane = REG_50080_TO_PLANE(offset);
796 	int event = SKL_FLIP_EVENT(pipe, plane);
797 
798 	write_vreg(vgpu, offset, p_data, bytes);
799 	if (plane == PLANE_PRIMARY) {
800 		vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
801 		vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++;
802 	} else {
803 		vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
804 	}
805 
806 	if ((vgpu_vreg(vgpu, offset) & REG50080_FLIP_TYPE_MASK) == REG50080_FLIP_TYPE_ASYNC)
807 		intel_vgpu_trigger_virtual_event(vgpu, event);
808 	else
809 		set_bit(event, vgpu->irq.flip_done_event[pipe]);
810 
811 	return 0;
812 }
813 
814 static int trigger_aux_channel_interrupt(struct intel_vgpu *vgpu,
815 		unsigned int reg)
816 {
817 	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
818 	enum intel_gvt_event_type event;
819 
820 	if (reg == _DPA_AUX_CH_CTL)
821 		event = AUX_CHANNEL_A;
822 	else if (reg == _PCH_DPB_AUX_CH_CTL || reg == _DPB_AUX_CH_CTL)
823 		event = AUX_CHANNEL_B;
824 	else if (reg == _PCH_DPC_AUX_CH_CTL || reg == _DPC_AUX_CH_CTL)
825 		event = AUX_CHANNEL_C;
826 	else if (reg == _PCH_DPD_AUX_CH_CTL || reg == _DPD_AUX_CH_CTL)
827 		event = AUX_CHANNEL_D;
828 	else {
829 		WARN_ON(true);
830 		return -EINVAL;
831 	}
832 
833 	intel_vgpu_trigger_virtual_event(vgpu, event);
834 	return 0;
835 }
836 
837 static int dp_aux_ch_ctl_trans_done(struct intel_vgpu *vgpu, u32 value,
838 		unsigned int reg, int len, bool data_valid)
839 {
840 	/* mark transaction done */
841 	value |= DP_AUX_CH_CTL_DONE;
842 	value &= ~DP_AUX_CH_CTL_SEND_BUSY;
843 	value &= ~DP_AUX_CH_CTL_RECEIVE_ERROR;
844 
845 	if (data_valid)
846 		value &= ~DP_AUX_CH_CTL_TIME_OUT_ERROR;
847 	else
848 		value |= DP_AUX_CH_CTL_TIME_OUT_ERROR;
849 
850 	/* message size */
851 	value &= ~(0xf << 20);
852 	value |= (len << 20);
853 	vgpu_vreg(vgpu, reg) = value;
854 
855 	if (value & DP_AUX_CH_CTL_INTERRUPT)
856 		return trigger_aux_channel_interrupt(vgpu, reg);
857 	return 0;
858 }
859 
860 static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd,
861 		u8 t)
862 {
863 	if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == DPCD_TRAINING_PATTERN_1) {
864 		/* training pattern 1 for CR */
865 		/* set LANE0_CR_DONE, LANE1_CR_DONE */
866 		dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_CR_DONE;
867 		/* set LANE2_CR_DONE, LANE3_CR_DONE */
868 		dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_CR_DONE;
869 	} else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) ==
870 			DPCD_TRAINING_PATTERN_2) {
871 		/* training pattern 2 for EQ */
872 		/* Set CHANNEL_EQ_DONE and  SYMBOL_LOCKED for Lane0_1 */
873 		dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_EQ_DONE;
874 		dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_SYMBOL_LOCKED;
875 		/* Set CHANNEL_EQ_DONE and  SYMBOL_LOCKED for Lane2_3 */
876 		dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_EQ_DONE;
877 		dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_SYMBOL_LOCKED;
878 		/* set INTERLANE_ALIGN_DONE */
879 		dpcd->data[DPCD_LANE_ALIGN_STATUS_UPDATED] |=
880 			DPCD_INTERLANE_ALIGN_DONE;
881 	} else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) ==
882 			DPCD_LINK_TRAINING_DISABLED) {
883 		/* finish link training */
884 		/* set sink status as synchronized */
885 		dpcd->data[DPCD_SINK_STATUS] = DPCD_SINK_IN_SYNC;
886 	}
887 }
888 
889 #define _REG_HSW_DP_AUX_CH_CTL(dp) \
890 	((dp) ? (_PCH_DPB_AUX_CH_CTL + ((dp)-1)*0x100) : 0x64010)
891 
892 #define _REG_SKL_DP_AUX_CH_CTL(dp) (0x64010 + (dp) * 0x100)
893 
894 #define OFFSET_TO_DP_AUX_PORT(offset) (((offset) & 0xF00) >> 8)
895 
896 #define dpy_is_valid_port(port)	\
897 		(((port) >= PORT_A) && ((port) < I915_MAX_PORTS))
898 
899 static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu,
900 		unsigned int offset, void *p_data, unsigned int bytes)
901 {
902 	struct intel_vgpu_display *display = &vgpu->display;
903 	int msg, addr, ctrl, op, len;
904 	int port_index = OFFSET_TO_DP_AUX_PORT(offset);
905 	struct intel_vgpu_dpcd_data *dpcd = NULL;
906 	struct intel_vgpu_port *port = NULL;
907 	u32 data;
908 
909 	if (!dpy_is_valid_port(port_index)) {
910 		gvt_vgpu_err("Unsupported DP port access!\n");
911 		return 0;
912 	}
913 
914 	write_vreg(vgpu, offset, p_data, bytes);
915 	data = vgpu_vreg(vgpu, offset);
916 
917 	if ((INTEL_GEN(vgpu->gvt->dev_priv) >= 9)
918 		&& offset != _REG_SKL_DP_AUX_CH_CTL(port_index)) {
919 		/* SKL DPB/C/D aux ctl register changed */
920 		return 0;
921 	} else if (IS_BROADWELL(vgpu->gvt->dev_priv) &&
922 		   offset != _REG_HSW_DP_AUX_CH_CTL(port_index)) {
923 		/* write to the data registers */
924 		return 0;
925 	}
926 
927 	if (!(data & DP_AUX_CH_CTL_SEND_BUSY)) {
928 		/* just want to clear the sticky bits */
929 		vgpu_vreg(vgpu, offset) = 0;
930 		return 0;
931 	}
932 
933 	port = &display->ports[port_index];
934 	dpcd = port->dpcd;
935 
936 	/* read out message from DATA1 register */
937 	msg = vgpu_vreg(vgpu, offset + 4);
938 	addr = (msg >> 8) & 0xffff;
939 	ctrl = (msg >> 24) & 0xff;
940 	len = msg & 0xff;
941 	op = ctrl >> 4;
942 
943 	if (op == GVT_AUX_NATIVE_WRITE) {
944 		int t;
945 		u8 buf[16];
946 
947 		if ((addr + len + 1) >= DPCD_SIZE) {
948 			/*
949 			 * Write request exceeds what we supported,
950 			 * DCPD spec: When a Source Device is writing a DPCD
951 			 * address not supported by the Sink Device, the Sink
952 			 * Device shall reply with AUX NACK and “M” equal to
953 			 * zero.
954 			 */
955 
956 			/* NAK the write */
957 			vgpu_vreg(vgpu, offset + 4) = AUX_NATIVE_REPLY_NAK;
958 			dp_aux_ch_ctl_trans_done(vgpu, data, offset, 2, true);
959 			return 0;
960 		}
961 
962 		/*
963 		 * Write request format: Headr (command + address + size) occupies
964 		 * 4 bytes, followed by (len + 1) bytes of data. See details at
965 		 * intel_dp_aux_transfer().
966 		 */
967 		if ((len + 1 + 4) > AUX_BURST_SIZE) {
968 			gvt_vgpu_err("dp_aux_header: len %d is too large\n", len);
969 			return -EINVAL;
970 		}
971 
972 		/* unpack data from vreg to buf */
973 		for (t = 0; t < 4; t++) {
974 			u32 r = vgpu_vreg(vgpu, offset + 8 + t * 4);
975 
976 			buf[t * 4] = (r >> 24) & 0xff;
977 			buf[t * 4 + 1] = (r >> 16) & 0xff;
978 			buf[t * 4 + 2] = (r >> 8) & 0xff;
979 			buf[t * 4 + 3] = r & 0xff;
980 		}
981 
982 		/* write to virtual DPCD */
983 		if (dpcd && dpcd->data_valid) {
984 			for (t = 0; t <= len; t++) {
985 				int p = addr + t;
986 
987 				dpcd->data[p] = buf[t];
988 				/* check for link training */
989 				if (p == DPCD_TRAINING_PATTERN_SET)
990 					dp_aux_ch_ctl_link_training(dpcd,
991 							buf[t]);
992 			}
993 		}
994 
995 		/* ACK the write */
996 		vgpu_vreg(vgpu, offset + 4) = 0;
997 		dp_aux_ch_ctl_trans_done(vgpu, data, offset, 1,
998 				dpcd && dpcd->data_valid);
999 		return 0;
1000 	}
1001 
1002 	if (op == GVT_AUX_NATIVE_READ) {
1003 		int idx, i, ret = 0;
1004 
1005 		if ((addr + len + 1) >= DPCD_SIZE) {
1006 			/*
1007 			 * read request exceeds what we supported
1008 			 * DPCD spec: A Sink Device receiving a Native AUX CH
1009 			 * read request for an unsupported DPCD address must
1010 			 * reply with an AUX ACK and read data set equal to
1011 			 * zero instead of replying with AUX NACK.
1012 			 */
1013 
1014 			/* ACK the READ*/
1015 			vgpu_vreg(vgpu, offset + 4) = 0;
1016 			vgpu_vreg(vgpu, offset + 8) = 0;
1017 			vgpu_vreg(vgpu, offset + 12) = 0;
1018 			vgpu_vreg(vgpu, offset + 16) = 0;
1019 			vgpu_vreg(vgpu, offset + 20) = 0;
1020 
1021 			dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2,
1022 					true);
1023 			return 0;
1024 		}
1025 
1026 		for (idx = 1; idx <= 5; idx++) {
1027 			/* clear the data registers */
1028 			vgpu_vreg(vgpu, offset + 4 * idx) = 0;
1029 		}
1030 
1031 		/*
1032 		 * Read reply format: ACK (1 byte) plus (len + 1) bytes of data.
1033 		 */
1034 		if ((len + 2) > AUX_BURST_SIZE) {
1035 			gvt_vgpu_err("dp_aux_header: len %d is too large\n", len);
1036 			return -EINVAL;
1037 		}
1038 
1039 		/* read from virtual DPCD to vreg */
1040 		/* first 4 bytes: [ACK][addr][addr+1][addr+2] */
1041 		if (dpcd && dpcd->data_valid) {
1042 			for (i = 1; i <= (len + 1); i++) {
1043 				int t;
1044 
1045 				t = dpcd->data[addr + i - 1];
1046 				t <<= (24 - 8 * (i % 4));
1047 				ret |= t;
1048 
1049 				if ((i % 4 == 3) || (i == (len + 1))) {
1050 					vgpu_vreg(vgpu, offset +
1051 							(i / 4 + 1) * 4) = ret;
1052 					ret = 0;
1053 				}
1054 			}
1055 		}
1056 		dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2,
1057 				dpcd && dpcd->data_valid);
1058 		return 0;
1059 	}
1060 
1061 	/* i2c transaction starts */
1062 	intel_gvt_i2c_handle_aux_ch_write(vgpu, port_index, offset, p_data);
1063 
1064 	if (data & DP_AUX_CH_CTL_INTERRUPT)
1065 		trigger_aux_channel_interrupt(vgpu, offset);
1066 	return 0;
1067 }
1068 
1069 static int mbctl_write(struct intel_vgpu *vgpu, unsigned int offset,
1070 		void *p_data, unsigned int bytes)
1071 {
1072 	*(u32 *)p_data &= (~GEN6_MBCTL_ENABLE_BOOT_FETCH);
1073 	write_vreg(vgpu, offset, p_data, bytes);
1074 	return 0;
1075 }
1076 
1077 static int vga_control_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1078 		void *p_data, unsigned int bytes)
1079 {
1080 	bool vga_disable;
1081 
1082 	write_vreg(vgpu, offset, p_data, bytes);
1083 	vga_disable = vgpu_vreg(vgpu, offset) & VGA_DISP_DISABLE;
1084 
1085 	gvt_dbg_core("vgpu%d: %s VGA mode\n", vgpu->id,
1086 			vga_disable ? "Disable" : "Enable");
1087 	return 0;
1088 }
1089 
1090 static u32 read_virtual_sbi_register(struct intel_vgpu *vgpu,
1091 		unsigned int sbi_offset)
1092 {
1093 	struct intel_vgpu_display *display = &vgpu->display;
1094 	int num = display->sbi.number;
1095 	int i;
1096 
1097 	for (i = 0; i < num; ++i)
1098 		if (display->sbi.registers[i].offset == sbi_offset)
1099 			break;
1100 
1101 	if (i == num)
1102 		return 0;
1103 
1104 	return display->sbi.registers[i].value;
1105 }
1106 
1107 static void write_virtual_sbi_register(struct intel_vgpu *vgpu,
1108 		unsigned int offset, u32 value)
1109 {
1110 	struct intel_vgpu_display *display = &vgpu->display;
1111 	int num = display->sbi.number;
1112 	int i;
1113 
1114 	for (i = 0; i < num; ++i) {
1115 		if (display->sbi.registers[i].offset == offset)
1116 			break;
1117 	}
1118 
1119 	if (i == num) {
1120 		if (num == SBI_REG_MAX) {
1121 			gvt_vgpu_err("SBI caching meets maximum limits\n");
1122 			return;
1123 		}
1124 		display->sbi.number++;
1125 	}
1126 
1127 	display->sbi.registers[i].offset = offset;
1128 	display->sbi.registers[i].value = value;
1129 }
1130 
1131 static int sbi_data_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
1132 		void *p_data, unsigned int bytes)
1133 {
1134 	if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >>
1135 				SBI_OPCODE_SHIFT) == SBI_CMD_CRRD) {
1136 		unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) &
1137 				SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT;
1138 		vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu,
1139 				sbi_offset);
1140 	}
1141 	read_vreg(vgpu, offset, p_data, bytes);
1142 	return 0;
1143 }
1144 
1145 static int sbi_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1146 		void *p_data, unsigned int bytes)
1147 {
1148 	u32 data;
1149 
1150 	write_vreg(vgpu, offset, p_data, bytes);
1151 	data = vgpu_vreg(vgpu, offset);
1152 
1153 	data &= ~(SBI_STAT_MASK << SBI_STAT_SHIFT);
1154 	data |= SBI_READY;
1155 
1156 	data &= ~(SBI_RESPONSE_MASK << SBI_RESPONSE_SHIFT);
1157 	data |= SBI_RESPONSE_SUCCESS;
1158 
1159 	vgpu_vreg(vgpu, offset) = data;
1160 
1161 	if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >>
1162 				SBI_OPCODE_SHIFT) == SBI_CMD_CRWR) {
1163 		unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) &
1164 				SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT;
1165 
1166 		write_virtual_sbi_register(vgpu, sbi_offset,
1167 					   vgpu_vreg_t(vgpu, SBI_DATA));
1168 	}
1169 	return 0;
1170 }
1171 
1172 #define _vgtif_reg(x) \
1173 	(VGT_PVINFO_PAGE + offsetof(struct vgt_if, x))
1174 
1175 static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
1176 		void *p_data, unsigned int bytes)
1177 {
1178 	bool invalid_read = false;
1179 
1180 	read_vreg(vgpu, offset, p_data, bytes);
1181 
1182 	switch (offset) {
1183 	case _vgtif_reg(magic) ... _vgtif_reg(vgt_id):
1184 		if (offset + bytes > _vgtif_reg(vgt_id) + 4)
1185 			invalid_read = true;
1186 		break;
1187 	case _vgtif_reg(avail_rs.mappable_gmadr.base) ...
1188 		_vgtif_reg(avail_rs.fence_num):
1189 		if (offset + bytes >
1190 			_vgtif_reg(avail_rs.fence_num) + 4)
1191 			invalid_read = true;
1192 		break;
1193 	case 0x78010:	/* vgt_caps */
1194 	case 0x7881c:
1195 		break;
1196 	default:
1197 		invalid_read = true;
1198 		break;
1199 	}
1200 	if (invalid_read)
1201 		gvt_vgpu_err("invalid pvinfo read: [%x:%x] = %x\n",
1202 				offset, bytes, *(u32 *)p_data);
1203 	vgpu->pv_notified = true;
1204 	return 0;
1205 }
1206 
1207 static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification)
1208 {
1209 	enum intel_gvt_gtt_type root_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY;
1210 	struct intel_vgpu_mm *mm;
1211 	u64 *pdps;
1212 
1213 	pdps = (u64 *)&vgpu_vreg64_t(vgpu, vgtif_reg(pdp[0]));
1214 
1215 	switch (notification) {
1216 	case VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE:
1217 		root_entry_type = GTT_TYPE_PPGTT_ROOT_L3_ENTRY;
1218 		/* fall through */
1219 	case VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE:
1220 		mm = intel_vgpu_get_ppgtt_mm(vgpu, root_entry_type, pdps);
1221 		return PTR_ERR_OR_ZERO(mm);
1222 	case VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY:
1223 	case VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY:
1224 		return intel_vgpu_put_ppgtt_mm(vgpu, pdps);
1225 	case VGT_G2V_EXECLIST_CONTEXT_CREATE:
1226 	case VGT_G2V_EXECLIST_CONTEXT_DESTROY:
1227 	case 1:	/* Remove this in guest driver. */
1228 		break;
1229 	default:
1230 		gvt_vgpu_err("Invalid PV notification %d\n", notification);
1231 	}
1232 	return 0;
1233 }
1234 
1235 static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready)
1236 {
1237 	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1238 	struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj;
1239 	char *env[3] = {NULL, NULL, NULL};
1240 	char vmid_str[20];
1241 	char display_ready_str[20];
1242 
1243 	snprintf(display_ready_str, 20, "GVT_DISPLAY_READY=%d", ready);
1244 	env[0] = display_ready_str;
1245 
1246 	snprintf(vmid_str, 20, "VMID=%d", vgpu->id);
1247 	env[1] = vmid_str;
1248 
1249 	return kobject_uevent_env(kobj, KOBJ_ADD, env);
1250 }
1251 
1252 static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1253 		void *p_data, unsigned int bytes)
1254 {
1255 	u32 data;
1256 	int ret;
1257 
1258 	write_vreg(vgpu, offset, p_data, bytes);
1259 	data = vgpu_vreg(vgpu, offset);
1260 
1261 	switch (offset) {
1262 	case _vgtif_reg(display_ready):
1263 		send_display_ready_uevent(vgpu, data ? 1 : 0);
1264 		break;
1265 	case _vgtif_reg(g2v_notify):
1266 		ret = handle_g2v_notification(vgpu, data);
1267 		break;
1268 	/* add xhot and yhot to handled list to avoid error log */
1269 	case _vgtif_reg(cursor_x_hot):
1270 	case _vgtif_reg(cursor_y_hot):
1271 	case _vgtif_reg(pdp[0].lo):
1272 	case _vgtif_reg(pdp[0].hi):
1273 	case _vgtif_reg(pdp[1].lo):
1274 	case _vgtif_reg(pdp[1].hi):
1275 	case _vgtif_reg(pdp[2].lo):
1276 	case _vgtif_reg(pdp[2].hi):
1277 	case _vgtif_reg(pdp[3].lo):
1278 	case _vgtif_reg(pdp[3].hi):
1279 	case _vgtif_reg(execlist_context_descriptor_lo):
1280 	case _vgtif_reg(execlist_context_descriptor_hi):
1281 		break;
1282 	case _vgtif_reg(rsv5[0])..._vgtif_reg(rsv5[3]):
1283 		enter_failsafe_mode(vgpu, GVT_FAILSAFE_INSUFFICIENT_RESOURCE);
1284 		break;
1285 	default:
1286 		gvt_vgpu_err("invalid pvinfo write offset %x bytes %x data %x\n",
1287 				offset, bytes, data);
1288 		break;
1289 	}
1290 	return 0;
1291 }
1292 
1293 static int pf_write(struct intel_vgpu *vgpu,
1294 		unsigned int offset, void *p_data, unsigned int bytes)
1295 {
1296 	u32 val = *(u32 *)p_data;
1297 
1298 	if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL ||
1299 	   offset == _PS_1B_CTRL || offset == _PS_2B_CTRL ||
1300 	   offset == _PS_1C_CTRL) && (val & PS_PLANE_SEL_MASK) != 0) {
1301 		WARN_ONCE(true, "VM(%d): guest is trying to scaling a plane\n",
1302 			  vgpu->id);
1303 		return 0;
1304 	}
1305 
1306 	return intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes);
1307 }
1308 
1309 static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu,
1310 		unsigned int offset, void *p_data, unsigned int bytes)
1311 {
1312 	write_vreg(vgpu, offset, p_data, bytes);
1313 
1314 	if (vgpu_vreg(vgpu, offset) &
1315 	    HSW_PWR_WELL_CTL_REQ(HSW_PW_CTL_IDX_GLOBAL))
1316 		vgpu_vreg(vgpu, offset) |=
1317 			HSW_PWR_WELL_CTL_STATE(HSW_PW_CTL_IDX_GLOBAL);
1318 	else
1319 		vgpu_vreg(vgpu, offset) &=
1320 			~HSW_PWR_WELL_CTL_STATE(HSW_PW_CTL_IDX_GLOBAL);
1321 	return 0;
1322 }
1323 
1324 static int gen9_dbuf_ctl_mmio_write(struct intel_vgpu *vgpu,
1325 		unsigned int offset, void *p_data, unsigned int bytes)
1326 {
1327 	write_vreg(vgpu, offset, p_data, bytes);
1328 
1329 	if (vgpu_vreg(vgpu, offset) & DBUF_POWER_REQUEST)
1330 		vgpu_vreg(vgpu, offset) |= DBUF_POWER_STATE;
1331 	else
1332 		vgpu_vreg(vgpu, offset) &= ~DBUF_POWER_STATE;
1333 
1334 	return 0;
1335 }
1336 
1337 static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu,
1338 	unsigned int offset, void *p_data, unsigned int bytes)
1339 {
1340 	write_vreg(vgpu, offset, p_data, bytes);
1341 
1342 	if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM)
1343 		vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM;
1344 	return 0;
1345 }
1346 
1347 static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset,
1348 		void *p_data, unsigned int bytes)
1349 {
1350 	u32 mode;
1351 
1352 	write_vreg(vgpu, offset, p_data, bytes);
1353 	mode = vgpu_vreg(vgpu, offset);
1354 
1355 	if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) {
1356 		WARN_ONCE(1, "VM(%d): iGVT-g doesn't support GuC\n",
1357 				vgpu->id);
1358 		return 0;
1359 	}
1360 
1361 	return 0;
1362 }
1363 
1364 static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset,
1365 		void *p_data, unsigned int bytes)
1366 {
1367 	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1368 	u32 trtte = *(u32 *)p_data;
1369 
1370 	if ((trtte & 1) && (trtte & (1 << 1)) == 0) {
1371 		WARN(1, "VM(%d): Use physical address for TRTT!\n",
1372 				vgpu->id);
1373 		return -EINVAL;
1374 	}
1375 	write_vreg(vgpu, offset, p_data, bytes);
1376 	/* TRTTE is not per-context */
1377 
1378 	mmio_hw_access_pre(dev_priv);
1379 	I915_WRITE(_MMIO(offset), vgpu_vreg(vgpu, offset));
1380 	mmio_hw_access_post(dev_priv);
1381 
1382 	return 0;
1383 }
1384 
1385 static int gen9_trtt_chicken_write(struct intel_vgpu *vgpu, unsigned int offset,
1386 		void *p_data, unsigned int bytes)
1387 {
1388 	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1389 	u32 val = *(u32 *)p_data;
1390 
1391 	if (val & 1) {
1392 		/* unblock hw logic */
1393 		mmio_hw_access_pre(dev_priv);
1394 		I915_WRITE(_MMIO(offset), val);
1395 		mmio_hw_access_post(dev_priv);
1396 	}
1397 	write_vreg(vgpu, offset, p_data, bytes);
1398 	return 0;
1399 }
1400 
1401 static int dpll_status_read(struct intel_vgpu *vgpu, unsigned int offset,
1402 		void *p_data, unsigned int bytes)
1403 {
1404 	u32 v = 0;
1405 
1406 	if (vgpu_vreg(vgpu, 0x46010) & (1 << 31))
1407 		v |= (1 << 0);
1408 
1409 	if (vgpu_vreg(vgpu, 0x46014) & (1 << 31))
1410 		v |= (1 << 8);
1411 
1412 	if (vgpu_vreg(vgpu, 0x46040) & (1 << 31))
1413 		v |= (1 << 16);
1414 
1415 	if (vgpu_vreg(vgpu, 0x46060) & (1 << 31))
1416 		v |= (1 << 24);
1417 
1418 	vgpu_vreg(vgpu, offset) = v;
1419 
1420 	return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1421 }
1422 
1423 static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset,
1424 		void *p_data, unsigned int bytes)
1425 {
1426 	u32 value = *(u32 *)p_data;
1427 	u32 cmd = value & 0xff;
1428 	u32 *data0 = &vgpu_vreg_t(vgpu, GEN6_PCODE_DATA);
1429 
1430 	switch (cmd) {
1431 	case GEN9_PCODE_READ_MEM_LATENCY:
1432 		if (IS_SKYLAKE(vgpu->gvt->dev_priv)
1433 			 || IS_KABYLAKE(vgpu->gvt->dev_priv)
1434 			 || IS_COFFEELAKE(vgpu->gvt->dev_priv)) {
1435 			/**
1436 			 * "Read memory latency" command on gen9.
1437 			 * Below memory latency values are read
1438 			 * from skylake platform.
1439 			 */
1440 			if (!*data0)
1441 				*data0 = 0x1e1a1100;
1442 			else
1443 				*data0 = 0x61514b3d;
1444 		} else if (IS_BROXTON(vgpu->gvt->dev_priv)) {
1445 			/**
1446 			 * "Read memory latency" command on gen9.
1447 			 * Below memory latency values are read
1448 			 * from Broxton MRB.
1449 			 */
1450 			if (!*data0)
1451 				*data0 = 0x16080707;
1452 			else
1453 				*data0 = 0x16161616;
1454 		}
1455 		break;
1456 	case SKL_PCODE_CDCLK_CONTROL:
1457 		if (IS_SKYLAKE(vgpu->gvt->dev_priv)
1458 			 || IS_KABYLAKE(vgpu->gvt->dev_priv)
1459 			 || IS_COFFEELAKE(vgpu->gvt->dev_priv))
1460 			*data0 = SKL_CDCLK_READY_FOR_CHANGE;
1461 		break;
1462 	case GEN6_PCODE_READ_RC6VIDS:
1463 		*data0 |= 0x1;
1464 		break;
1465 	}
1466 
1467 	gvt_dbg_core("VM(%d) write %x to mailbox, return data0 %x\n",
1468 		     vgpu->id, value, *data0);
1469 	/**
1470 	 * PCODE_READY clear means ready for pcode read/write,
1471 	 * PCODE_ERROR_MASK clear means no error happened. In GVT-g we
1472 	 * always emulate as pcode read/write success and ready for access
1473 	 * anytime, since we don't touch real physical registers here.
1474 	 */
1475 	value &= ~(GEN6_PCODE_READY | GEN6_PCODE_ERROR_MASK);
1476 	return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes);
1477 }
1478 
1479 static int hws_pga_write(struct intel_vgpu *vgpu, unsigned int offset,
1480 		void *p_data, unsigned int bytes)
1481 {
1482 	u32 value = *(u32 *)p_data;
1483 	int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset);
1484 
1485 	if (!intel_gvt_ggtt_validate_range(vgpu, value, I915_GTT_PAGE_SIZE)) {
1486 		gvt_vgpu_err("write invalid HWSP address, reg:0x%x, value:0x%x\n",
1487 			      offset, value);
1488 		return -EINVAL;
1489 	}
1490 	/*
1491 	 * Need to emulate all the HWSP register write to ensure host can
1492 	 * update the VM CSB status correctly. Here listed registers can
1493 	 * support BDW, SKL or other platforms with same HWSP registers.
1494 	 */
1495 	if (unlikely(ring_id < 0 || ring_id >= I915_NUM_ENGINES)) {
1496 		gvt_vgpu_err("access unknown hardware status page register:0x%x\n",
1497 			     offset);
1498 		return -EINVAL;
1499 	}
1500 	vgpu->hws_pga[ring_id] = value;
1501 	gvt_dbg_mmio("VM(%d) write: 0x%x to HWSP: 0x%x\n",
1502 		     vgpu->id, value, offset);
1503 
1504 	return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes);
1505 }
1506 
1507 static int skl_power_well_ctl_write(struct intel_vgpu *vgpu,
1508 		unsigned int offset, void *p_data, unsigned int bytes)
1509 {
1510 	u32 v = *(u32 *)p_data;
1511 
1512 	if (IS_BROXTON(vgpu->gvt->dev_priv))
1513 		v &= (1 << 31) | (1 << 29);
1514 	else
1515 		v &= (1 << 31) | (1 << 29) | (1 << 9) |
1516 			(1 << 7) | (1 << 5) | (1 << 3) | (1 << 1);
1517 	v |= (v >> 1);
1518 
1519 	return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes);
1520 }
1521 
1522 static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset,
1523 		void *p_data, unsigned int bytes)
1524 {
1525 	u32 v = *(u32 *)p_data;
1526 
1527 	/* other bits are MBZ. */
1528 	v &= (1 << 31) | (1 << 30);
1529 	v & (1 << 31) ? (v |= (1 << 30)) : (v &= ~(1 << 30));
1530 
1531 	vgpu_vreg(vgpu, offset) = v;
1532 
1533 	return 0;
1534 }
1535 
1536 static int bxt_de_pll_enable_write(struct intel_vgpu *vgpu,
1537 		unsigned int offset, void *p_data, unsigned int bytes)
1538 {
1539 	u32 v = *(u32 *)p_data;
1540 
1541 	if (v & BXT_DE_PLL_PLL_ENABLE)
1542 		v |= BXT_DE_PLL_LOCK;
1543 
1544 	vgpu_vreg(vgpu, offset) = v;
1545 
1546 	return 0;
1547 }
1548 
1549 static int bxt_port_pll_enable_write(struct intel_vgpu *vgpu,
1550 		unsigned int offset, void *p_data, unsigned int bytes)
1551 {
1552 	u32 v = *(u32 *)p_data;
1553 
1554 	if (v & PORT_PLL_ENABLE)
1555 		v |= PORT_PLL_LOCK;
1556 
1557 	vgpu_vreg(vgpu, offset) = v;
1558 
1559 	return 0;
1560 }
1561 
1562 static int bxt_phy_ctl_family_write(struct intel_vgpu *vgpu,
1563 		unsigned int offset, void *p_data, unsigned int bytes)
1564 {
1565 	u32 v = *(u32 *)p_data;
1566 	u32 data = v & COMMON_RESET_DIS ? BXT_PHY_LANE_ENABLED : 0;
1567 
1568 	switch (offset) {
1569 	case _PHY_CTL_FAMILY_EDP:
1570 		vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_A) = data;
1571 		break;
1572 	case _PHY_CTL_FAMILY_DDI:
1573 		vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_B) = data;
1574 		vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_C) = data;
1575 		break;
1576 	}
1577 
1578 	vgpu_vreg(vgpu, offset) = v;
1579 
1580 	return 0;
1581 }
1582 
1583 static int bxt_port_tx_dw3_read(struct intel_vgpu *vgpu,
1584 		unsigned int offset, void *p_data, unsigned int bytes)
1585 {
1586 	u32 v = vgpu_vreg(vgpu, offset);
1587 
1588 	v &= ~UNIQUE_TRANGE_EN_METHOD;
1589 
1590 	vgpu_vreg(vgpu, offset) = v;
1591 
1592 	return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1593 }
1594 
1595 static int bxt_pcs_dw12_grp_write(struct intel_vgpu *vgpu,
1596 		unsigned int offset, void *p_data, unsigned int bytes)
1597 {
1598 	u32 v = *(u32 *)p_data;
1599 
1600 	if (offset == _PORT_PCS_DW12_GRP_A || offset == _PORT_PCS_DW12_GRP_B) {
1601 		vgpu_vreg(vgpu, offset - 0x600) = v;
1602 		vgpu_vreg(vgpu, offset - 0x800) = v;
1603 	} else {
1604 		vgpu_vreg(vgpu, offset - 0x400) = v;
1605 		vgpu_vreg(vgpu, offset - 0x600) = v;
1606 	}
1607 
1608 	vgpu_vreg(vgpu, offset) = v;
1609 
1610 	return 0;
1611 }
1612 
1613 static int bxt_gt_disp_pwron_write(struct intel_vgpu *vgpu,
1614 		unsigned int offset, void *p_data, unsigned int bytes)
1615 {
1616 	u32 v = *(u32 *)p_data;
1617 
1618 	if (v & BIT(0)) {
1619 		vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=
1620 			~PHY_RESERVED;
1621 		vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=
1622 			PHY_POWER_GOOD;
1623 	}
1624 
1625 	if (v & BIT(1)) {
1626 		vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &=
1627 			~PHY_RESERVED;
1628 		vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |=
1629 			PHY_POWER_GOOD;
1630 	}
1631 
1632 
1633 	vgpu_vreg(vgpu, offset) = v;
1634 
1635 	return 0;
1636 }
1637 
1638 static int edp_psr_imr_iir_write(struct intel_vgpu *vgpu,
1639 		unsigned int offset, void *p_data, unsigned int bytes)
1640 {
1641 	vgpu_vreg(vgpu, offset) = 0;
1642 	return 0;
1643 }
1644 
1645 static int mmio_read_from_hw(struct intel_vgpu *vgpu,
1646 		unsigned int offset, void *p_data, unsigned int bytes)
1647 {
1648 	struct intel_gvt *gvt = vgpu->gvt;
1649 	struct drm_i915_private *dev_priv = gvt->dev_priv;
1650 	int ring_id;
1651 	u32 ring_base;
1652 
1653 	ring_id = intel_gvt_render_mmio_to_ring_id(gvt, offset);
1654 	/**
1655 	 * Read HW reg in following case
1656 	 * a. the offset isn't a ring mmio
1657 	 * b. the offset's ring is running on hw.
1658 	 * c. the offset is ring time stamp mmio
1659 	 */
1660 	if (ring_id >= 0)
1661 		ring_base = dev_priv->engine[ring_id]->mmio_base;
1662 
1663 	if (ring_id < 0 || vgpu  == gvt->scheduler.engine_owner[ring_id] ||
1664 	    offset == i915_mmio_reg_offset(RING_TIMESTAMP(ring_base)) ||
1665 	    offset == i915_mmio_reg_offset(RING_TIMESTAMP_UDW(ring_base))) {
1666 		mmio_hw_access_pre(dev_priv);
1667 		vgpu_vreg(vgpu, offset) = I915_READ(_MMIO(offset));
1668 		mmio_hw_access_post(dev_priv);
1669 	}
1670 
1671 	return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1672 }
1673 
1674 static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1675 		void *p_data, unsigned int bytes)
1676 {
1677 	int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset);
1678 	struct intel_vgpu_execlist *execlist;
1679 	u32 data = *(u32 *)p_data;
1680 	int ret = 0;
1681 
1682 	if (WARN_ON(ring_id < 0 || ring_id >= I915_NUM_ENGINES))
1683 		return -EINVAL;
1684 
1685 	execlist = &vgpu->submission.execlist[ring_id];
1686 
1687 	execlist->elsp_dwords.data[3 - execlist->elsp_dwords.index] = data;
1688 	if (execlist->elsp_dwords.index == 3) {
1689 		ret = intel_vgpu_submit_execlist(vgpu, ring_id);
1690 		if(ret)
1691 			gvt_vgpu_err("fail submit workload on ring %d\n",
1692 				ring_id);
1693 	}
1694 
1695 	++execlist->elsp_dwords.index;
1696 	execlist->elsp_dwords.index &= 0x3;
1697 	return ret;
1698 }
1699 
1700 static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1701 		void *p_data, unsigned int bytes)
1702 {
1703 	u32 data = *(u32 *)p_data;
1704 	int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset);
1705 	bool enable_execlist;
1706 	int ret;
1707 
1708 	write_vreg(vgpu, offset, p_data, bytes);
1709 
1710 	/* when PPGTT mode enabled, we will check if guest has called
1711 	 * pvinfo, if not, we will treat this guest as non-gvtg-aware
1712 	 * guest, and stop emulating its cfg space, mmio, gtt, etc.
1713 	 */
1714 	if (((data & _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)) ||
1715 			(data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)))
1716 			&& !vgpu->pv_notified) {
1717 		enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
1718 		return 0;
1719 	}
1720 	if ((data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE))
1721 			|| (data & _MASKED_BIT_DISABLE(GFX_RUN_LIST_ENABLE))) {
1722 		enable_execlist = !!(data & GFX_RUN_LIST_ENABLE);
1723 
1724 		gvt_dbg_core("EXECLIST %s on ring %d\n",
1725 				(enable_execlist ? "enabling" : "disabling"),
1726 				ring_id);
1727 
1728 		if (!enable_execlist)
1729 			return 0;
1730 
1731 		ret = intel_vgpu_select_submission_ops(vgpu,
1732 			       BIT(ring_id),
1733 			       INTEL_VGPU_EXECLIST_SUBMISSION);
1734 		if (ret)
1735 			return ret;
1736 
1737 		intel_vgpu_start_schedule(vgpu);
1738 	}
1739 	return 0;
1740 }
1741 
1742 static int gvt_reg_tlb_control_handler(struct intel_vgpu *vgpu,
1743 		unsigned int offset, void *p_data, unsigned int bytes)
1744 {
1745 	unsigned int id = 0;
1746 
1747 	write_vreg(vgpu, offset, p_data, bytes);
1748 	vgpu_vreg(vgpu, offset) = 0;
1749 
1750 	switch (offset) {
1751 	case 0x4260:
1752 		id = RCS0;
1753 		break;
1754 	case 0x4264:
1755 		id = VCS0;
1756 		break;
1757 	case 0x4268:
1758 		id = VCS1;
1759 		break;
1760 	case 0x426c:
1761 		id = BCS0;
1762 		break;
1763 	case 0x4270:
1764 		id = VECS0;
1765 		break;
1766 	default:
1767 		return -EINVAL;
1768 	}
1769 	set_bit(id, (void *)vgpu->submission.tlb_handle_pending);
1770 
1771 	return 0;
1772 }
1773 
1774 static int ring_reset_ctl_write(struct intel_vgpu *vgpu,
1775 	unsigned int offset, void *p_data, unsigned int bytes)
1776 {
1777 	u32 data;
1778 
1779 	write_vreg(vgpu, offset, p_data, bytes);
1780 	data = vgpu_vreg(vgpu, offset);
1781 
1782 	if (data & _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET))
1783 		data |= RESET_CTL_READY_TO_RESET;
1784 	else if (data & _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET))
1785 		data &= ~RESET_CTL_READY_TO_RESET;
1786 
1787 	vgpu_vreg(vgpu, offset) = data;
1788 	return 0;
1789 }
1790 
1791 #define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
1792 	ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
1793 		f, s, am, rm, d, r, w); \
1794 	if (ret) \
1795 		return ret; \
1796 } while (0)
1797 
1798 #define MMIO_D(reg, d) \
1799 	MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL)
1800 
1801 #define MMIO_DH(reg, d, r, w) \
1802 	MMIO_F(reg, 4, 0, 0, 0, d, r, w)
1803 
1804 #define MMIO_DFH(reg, d, f, r, w) \
1805 	MMIO_F(reg, 4, f, 0, 0, d, r, w)
1806 
1807 #define MMIO_GM(reg, d, r, w) \
1808 	MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
1809 
1810 #define MMIO_GM_RDR(reg, d, r, w) \
1811 	MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
1812 
1813 #define MMIO_RO(reg, d, f, rm, r, w) \
1814 	MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
1815 
1816 #define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \
1817 	MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
1818 	MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
1819 	MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
1820 	MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
1821 	if (HAS_ENGINE(dev_priv, VCS1)) \
1822 		MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
1823 } while (0)
1824 
1825 #define MMIO_RING_D(prefix, d) \
1826 	MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL)
1827 
1828 #define MMIO_RING_DFH(prefix, d, f, r, w) \
1829 	MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
1830 
1831 #define MMIO_RING_GM(prefix, d, r, w) \
1832 	MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
1833 
1834 #define MMIO_RING_GM_RDR(prefix, d, r, w) \
1835 	MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
1836 
1837 #define MMIO_RING_RO(prefix, d, f, rm, r, w) \
1838 	MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
1839 
1840 static int init_generic_mmio_info(struct intel_gvt *gvt)
1841 {
1842 	struct drm_i915_private *dev_priv = gvt->dev_priv;
1843 	int ret;
1844 
1845 	MMIO_RING_DFH(RING_IMR, D_ALL, F_CMD_ACCESS, NULL,
1846 		intel_vgpu_reg_imr_handler);
1847 
1848 	MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
1849 	MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
1850 	MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
1851 	MMIO_D(SDEISR, D_ALL);
1852 
1853 	MMIO_RING_DFH(RING_HWSTAM, D_ALL, F_CMD_ACCESS, NULL, NULL);
1854 
1855 	MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
1856 		gamw_echo_dev_rw_ia_write);
1857 
1858 	MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
1859 	MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
1860 	MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
1861 
1862 #define RING_REG(base) _MMIO((base) + 0x28)
1863 	MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
1864 #undef RING_REG
1865 
1866 #define RING_REG(base) _MMIO((base) + 0x134)
1867 	MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
1868 #undef RING_REG
1869 
1870 #define RING_REG(base) _MMIO((base) + 0x6c)
1871 	MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
1872 #undef RING_REG
1873 	MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
1874 
1875 	MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);
1876 	MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL);
1877 	MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);
1878 	MMIO_D(GEN7_CXT_SIZE, D_ALL);
1879 
1880 	MMIO_RING_DFH(RING_TAIL, D_ALL, F_CMD_ACCESS, NULL, NULL);
1881 	MMIO_RING_DFH(RING_HEAD, D_ALL, F_CMD_ACCESS, NULL, NULL);
1882 	MMIO_RING_DFH(RING_CTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
1883 	MMIO_RING_DFH(RING_ACTHD, D_ALL, F_CMD_ACCESS, mmio_read_from_hw, NULL);
1884 	MMIO_RING_GM_RDR(RING_START, D_ALL, NULL, NULL);
1885 
1886 	/* RING MODE */
1887 #define RING_REG(base) _MMIO((base) + 0x29c)
1888 	MMIO_RING_DFH(RING_REG, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL,
1889 		ring_mode_mmio_write);
1890 #undef RING_REG
1891 
1892 	MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1893 		NULL, NULL);
1894 	MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1895 			NULL, NULL);
1896 	MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
1897 			mmio_read_from_hw, NULL);
1898 	MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
1899 			mmio_read_from_hw, NULL);
1900 
1901 	MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1902 	MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1903 		NULL, NULL);
1904 	MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1905 	MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1906 	MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1907 
1908 	MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1909 	MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1910 	MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1911 	MMIO_DFH(_MMIO(0x20e4), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1912 	MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1913 	MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
1914 	MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1915 		NULL, NULL);
1916 	MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1917 		 NULL, NULL);
1918 	MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL);
1919 	MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL);
1920 	MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL);
1921 	MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL);
1922 	MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL);
1923 	MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);
1924 	MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);
1925 	MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1926 	MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1927 	MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1928 
1929 	/* display */
1930 	MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL);
1931 	MMIO_D(_MMIO(0x602a0), D_ALL);
1932 
1933 	MMIO_D(_MMIO(0x65050), D_ALL);
1934 	MMIO_D(_MMIO(0x650b4), D_ALL);
1935 
1936 	MMIO_D(_MMIO(0xc4040), D_ALL);
1937 	MMIO_D(DERRMR, D_ALL);
1938 
1939 	MMIO_D(PIPEDSL(PIPE_A), D_ALL);
1940 	MMIO_D(PIPEDSL(PIPE_B), D_ALL);
1941 	MMIO_D(PIPEDSL(PIPE_C), D_ALL);
1942 	MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL);
1943 
1944 	MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
1945 	MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
1946 	MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write);
1947 	MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write);
1948 
1949 	MMIO_D(PIPESTAT(PIPE_A), D_ALL);
1950 	MMIO_D(PIPESTAT(PIPE_B), D_ALL);
1951 	MMIO_D(PIPESTAT(PIPE_C), D_ALL);
1952 	MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL);
1953 
1954 	MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL);
1955 	MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL);
1956 	MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL);
1957 	MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL);
1958 
1959 	MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL);
1960 	MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL);
1961 	MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL);
1962 	MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL);
1963 
1964 	MMIO_D(CURCNTR(PIPE_A), D_ALL);
1965 	MMIO_D(CURCNTR(PIPE_B), D_ALL);
1966 	MMIO_D(CURCNTR(PIPE_C), D_ALL);
1967 
1968 	MMIO_D(CURPOS(PIPE_A), D_ALL);
1969 	MMIO_D(CURPOS(PIPE_B), D_ALL);
1970 	MMIO_D(CURPOS(PIPE_C), D_ALL);
1971 
1972 	MMIO_D(CURBASE(PIPE_A), D_ALL);
1973 	MMIO_D(CURBASE(PIPE_B), D_ALL);
1974 	MMIO_D(CURBASE(PIPE_C), D_ALL);
1975 
1976 	MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL);
1977 	MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL);
1978 	MMIO_D(CUR_FBC_CTL(PIPE_C), D_ALL);
1979 
1980 	MMIO_D(_MMIO(0x700ac), D_ALL);
1981 	MMIO_D(_MMIO(0x710ac), D_ALL);
1982 	MMIO_D(_MMIO(0x720ac), D_ALL);
1983 
1984 	MMIO_D(_MMIO(0x70090), D_ALL);
1985 	MMIO_D(_MMIO(0x70094), D_ALL);
1986 	MMIO_D(_MMIO(0x70098), D_ALL);
1987 	MMIO_D(_MMIO(0x7009c), D_ALL);
1988 
1989 	MMIO_D(DSPCNTR(PIPE_A), D_ALL);
1990 	MMIO_D(DSPADDR(PIPE_A), D_ALL);
1991 	MMIO_D(DSPSTRIDE(PIPE_A), D_ALL);
1992 	MMIO_D(DSPPOS(PIPE_A), D_ALL);
1993 	MMIO_D(DSPSIZE(PIPE_A), D_ALL);
1994 	MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
1995 	MMIO_D(DSPOFFSET(PIPE_A), D_ALL);
1996 	MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL);
1997 	MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL,
1998 		reg50080_mmio_write);
1999 
2000 	MMIO_D(DSPCNTR(PIPE_B), D_ALL);
2001 	MMIO_D(DSPADDR(PIPE_B), D_ALL);
2002 	MMIO_D(DSPSTRIDE(PIPE_B), D_ALL);
2003 	MMIO_D(DSPPOS(PIPE_B), D_ALL);
2004 	MMIO_D(DSPSIZE(PIPE_B), D_ALL);
2005 	MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
2006 	MMIO_D(DSPOFFSET(PIPE_B), D_ALL);
2007 	MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL);
2008 	MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL,
2009 		reg50080_mmio_write);
2010 
2011 	MMIO_D(DSPCNTR(PIPE_C), D_ALL);
2012 	MMIO_D(DSPADDR(PIPE_C), D_ALL);
2013 	MMIO_D(DSPSTRIDE(PIPE_C), D_ALL);
2014 	MMIO_D(DSPPOS(PIPE_C), D_ALL);
2015 	MMIO_D(DSPSIZE(PIPE_C), D_ALL);
2016 	MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
2017 	MMIO_D(DSPOFFSET(PIPE_C), D_ALL);
2018 	MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL);
2019 	MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL,
2020 		reg50080_mmio_write);
2021 
2022 	MMIO_D(SPRCTL(PIPE_A), D_ALL);
2023 	MMIO_D(SPRLINOFF(PIPE_A), D_ALL);
2024 	MMIO_D(SPRSTRIDE(PIPE_A), D_ALL);
2025 	MMIO_D(SPRPOS(PIPE_A), D_ALL);
2026 	MMIO_D(SPRSIZE(PIPE_A), D_ALL);
2027 	MMIO_D(SPRKEYVAL(PIPE_A), D_ALL);
2028 	MMIO_D(SPRKEYMSK(PIPE_A), D_ALL);
2029 	MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
2030 	MMIO_D(SPRKEYMAX(PIPE_A), D_ALL);
2031 	MMIO_D(SPROFFSET(PIPE_A), D_ALL);
2032 	MMIO_D(SPRSCALE(PIPE_A), D_ALL);
2033 	MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL);
2034 	MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL,
2035 		reg50080_mmio_write);
2036 
2037 	MMIO_D(SPRCTL(PIPE_B), D_ALL);
2038 	MMIO_D(SPRLINOFF(PIPE_B), D_ALL);
2039 	MMIO_D(SPRSTRIDE(PIPE_B), D_ALL);
2040 	MMIO_D(SPRPOS(PIPE_B), D_ALL);
2041 	MMIO_D(SPRSIZE(PIPE_B), D_ALL);
2042 	MMIO_D(SPRKEYVAL(PIPE_B), D_ALL);
2043 	MMIO_D(SPRKEYMSK(PIPE_B), D_ALL);
2044 	MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);
2045 	MMIO_D(SPRKEYMAX(PIPE_B), D_ALL);
2046 	MMIO_D(SPROFFSET(PIPE_B), D_ALL);
2047 	MMIO_D(SPRSCALE(PIPE_B), D_ALL);
2048 	MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL);
2049 	MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL,
2050 		reg50080_mmio_write);
2051 
2052 	MMIO_D(SPRCTL(PIPE_C), D_ALL);
2053 	MMIO_D(SPRLINOFF(PIPE_C), D_ALL);
2054 	MMIO_D(SPRSTRIDE(PIPE_C), D_ALL);
2055 	MMIO_D(SPRPOS(PIPE_C), D_ALL);
2056 	MMIO_D(SPRSIZE(PIPE_C), D_ALL);
2057 	MMIO_D(SPRKEYVAL(PIPE_C), D_ALL);
2058 	MMIO_D(SPRKEYMSK(PIPE_C), D_ALL);
2059 	MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
2060 	MMIO_D(SPRKEYMAX(PIPE_C), D_ALL);
2061 	MMIO_D(SPROFFSET(PIPE_C), D_ALL);
2062 	MMIO_D(SPRSCALE(PIPE_C), D_ALL);
2063 	MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL);
2064 	MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL,
2065 		reg50080_mmio_write);
2066 
2067 	MMIO_D(HTOTAL(TRANSCODER_A), D_ALL);
2068 	MMIO_D(HBLANK(TRANSCODER_A), D_ALL);
2069 	MMIO_D(HSYNC(TRANSCODER_A), D_ALL);
2070 	MMIO_D(VTOTAL(TRANSCODER_A), D_ALL);
2071 	MMIO_D(VBLANK(TRANSCODER_A), D_ALL);
2072 	MMIO_D(VSYNC(TRANSCODER_A), D_ALL);
2073 	MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL);
2074 	MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL);
2075 	MMIO_D(PIPESRC(TRANSCODER_A), D_ALL);
2076 
2077 	MMIO_D(HTOTAL(TRANSCODER_B), D_ALL);
2078 	MMIO_D(HBLANK(TRANSCODER_B), D_ALL);
2079 	MMIO_D(HSYNC(TRANSCODER_B), D_ALL);
2080 	MMIO_D(VTOTAL(TRANSCODER_B), D_ALL);
2081 	MMIO_D(VBLANK(TRANSCODER_B), D_ALL);
2082 	MMIO_D(VSYNC(TRANSCODER_B), D_ALL);
2083 	MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL);
2084 	MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL);
2085 	MMIO_D(PIPESRC(TRANSCODER_B), D_ALL);
2086 
2087 	MMIO_D(HTOTAL(TRANSCODER_C), D_ALL);
2088 	MMIO_D(HBLANK(TRANSCODER_C), D_ALL);
2089 	MMIO_D(HSYNC(TRANSCODER_C), D_ALL);
2090 	MMIO_D(VTOTAL(TRANSCODER_C), D_ALL);
2091 	MMIO_D(VBLANK(TRANSCODER_C), D_ALL);
2092 	MMIO_D(VSYNC(TRANSCODER_C), D_ALL);
2093 	MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL);
2094 	MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL);
2095 	MMIO_D(PIPESRC(TRANSCODER_C), D_ALL);
2096 
2097 	MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL);
2098 	MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL);
2099 	MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL);
2100 	MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL);
2101 	MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL);
2102 	MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL);
2103 	MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL);
2104 	MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL);
2105 
2106 	MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL);
2107 	MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL);
2108 	MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL);
2109 	MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL);
2110 	MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL);
2111 	MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL);
2112 	MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL);
2113 	MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL);
2114 
2115 	MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL);
2116 	MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL);
2117 	MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL);
2118 	MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL);
2119 	MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL);
2120 	MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL);
2121 	MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL);
2122 	MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL);
2123 
2124 	MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL);
2125 	MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL);
2126 	MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL);
2127 	MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL);
2128 	MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL);
2129 	MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL);
2130 	MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL);
2131 	MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL);
2132 
2133 	MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL);
2134 	MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL);
2135 	MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL);
2136 	MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL);
2137 	MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL);
2138 	MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL);
2139 	MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL);
2140 	MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL);
2141 
2142 	MMIO_D(PF_CTL(PIPE_A), D_ALL);
2143 	MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL);
2144 	MMIO_D(PF_WIN_POS(PIPE_A), D_ALL);
2145 	MMIO_D(PF_VSCALE(PIPE_A), D_ALL);
2146 	MMIO_D(PF_HSCALE(PIPE_A), D_ALL);
2147 
2148 	MMIO_D(PF_CTL(PIPE_B), D_ALL);
2149 	MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL);
2150 	MMIO_D(PF_WIN_POS(PIPE_B), D_ALL);
2151 	MMIO_D(PF_VSCALE(PIPE_B), D_ALL);
2152 	MMIO_D(PF_HSCALE(PIPE_B), D_ALL);
2153 
2154 	MMIO_D(PF_CTL(PIPE_C), D_ALL);
2155 	MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL);
2156 	MMIO_D(PF_WIN_POS(PIPE_C), D_ALL);
2157 	MMIO_D(PF_VSCALE(PIPE_C), D_ALL);
2158 	MMIO_D(PF_HSCALE(PIPE_C), D_ALL);
2159 
2160 	MMIO_D(WM0_PIPEA_ILK, D_ALL);
2161 	MMIO_D(WM0_PIPEB_ILK, D_ALL);
2162 	MMIO_D(WM0_PIPEC_IVB, D_ALL);
2163 	MMIO_D(WM1_LP_ILK, D_ALL);
2164 	MMIO_D(WM2_LP_ILK, D_ALL);
2165 	MMIO_D(WM3_LP_ILK, D_ALL);
2166 	MMIO_D(WM1S_LP_ILK, D_ALL);
2167 	MMIO_D(WM2S_LP_IVB, D_ALL);
2168 	MMIO_D(WM3S_LP_IVB, D_ALL);
2169 
2170 	MMIO_D(BLC_PWM_CPU_CTL2, D_ALL);
2171 	MMIO_D(BLC_PWM_CPU_CTL, D_ALL);
2172 	MMIO_D(BLC_PWM_PCH_CTL1, D_ALL);
2173 	MMIO_D(BLC_PWM_PCH_CTL2, D_ALL);
2174 
2175 	MMIO_D(_MMIO(0x48268), D_ALL);
2176 
2177 	MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
2178 		gmbus_mmio_write);
2179 	MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
2180 	MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
2181 
2182 	MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
2183 		dp_aux_ch_ctl_mmio_write);
2184 	MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
2185 		dp_aux_ch_ctl_mmio_write);
2186 	MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
2187 		dp_aux_ch_ctl_mmio_write);
2188 
2189 	MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);
2190 
2191 	MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write);
2192 	MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write);
2193 
2194 	MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
2195 	MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
2196 	MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
2197 	MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
2198 	MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
2199 	MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
2200 	MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
2201 	MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
2202 	MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
2203 
2204 	MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A), D_ALL);
2205 	MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A), D_ALL);
2206 	MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A), D_ALL);
2207 	MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A), D_ALL);
2208 	MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A), D_ALL);
2209 	MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A), D_ALL);
2210 	MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A), D_ALL);
2211 
2212 	MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B), D_ALL);
2213 	MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B), D_ALL);
2214 	MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B), D_ALL);
2215 	MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B), D_ALL);
2216 	MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B), D_ALL);
2217 	MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B), D_ALL);
2218 	MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B), D_ALL);
2219 
2220 	MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1), D_ALL);
2221 	MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1), D_ALL);
2222 	MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2), D_ALL);
2223 	MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2), D_ALL);
2224 	MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1), D_ALL);
2225 	MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1), D_ALL);
2226 	MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2), D_ALL);
2227 	MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2), D_ALL);
2228 
2229 	MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL);
2230 	MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL);
2231 	MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL);
2232 
2233 	MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL);
2234 	MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL);
2235 	MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL);
2236 
2237 	MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL);
2238 	MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL);
2239 	MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL);
2240 
2241 	MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL);
2242 	MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL);
2243 	MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL);
2244 
2245 	MMIO_D(_MMIO(_FDI_RXA_MISC), D_ALL);
2246 	MMIO_D(_MMIO(_FDI_RXB_MISC), D_ALL);
2247 	MMIO_D(_MMIO(_FDI_RXA_TUSIZE1), D_ALL);
2248 	MMIO_D(_MMIO(_FDI_RXA_TUSIZE2), D_ALL);
2249 	MMIO_D(_MMIO(_FDI_RXB_TUSIZE1), D_ALL);
2250 	MMIO_D(_MMIO(_FDI_RXB_TUSIZE2), D_ALL);
2251 
2252 	MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
2253 	MMIO_D(PCH_PP_DIVISOR, D_ALL);
2254 	MMIO_D(PCH_PP_STATUS,  D_ALL);
2255 	MMIO_D(PCH_LVDS, D_ALL);
2256 	MMIO_D(_MMIO(_PCH_DPLL_A), D_ALL);
2257 	MMIO_D(_MMIO(_PCH_DPLL_B), D_ALL);
2258 	MMIO_D(_MMIO(_PCH_FPA0), D_ALL);
2259 	MMIO_D(_MMIO(_PCH_FPA1), D_ALL);
2260 	MMIO_D(_MMIO(_PCH_FPB0), D_ALL);
2261 	MMIO_D(_MMIO(_PCH_FPB1), D_ALL);
2262 	MMIO_D(PCH_DREF_CONTROL, D_ALL);
2263 	MMIO_D(PCH_RAWCLK_FREQ, D_ALL);
2264 	MMIO_D(PCH_DPLL_SEL, D_ALL);
2265 
2266 	MMIO_D(_MMIO(0x61208), D_ALL);
2267 	MMIO_D(_MMIO(0x6120c), D_ALL);
2268 	MMIO_D(PCH_PP_ON_DELAYS, D_ALL);
2269 	MMIO_D(PCH_PP_OFF_DELAYS, D_ALL);
2270 
2271 	MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL);
2272 	MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL);
2273 	MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL);
2274 	MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL);
2275 	MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL);
2276 	MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL);
2277 
2278 	MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
2279 		PORTA_HOTPLUG_STATUS_MASK
2280 		| PORTB_HOTPLUG_STATUS_MASK
2281 		| PORTC_HOTPLUG_STATUS_MASK
2282 		| PORTD_HOTPLUG_STATUS_MASK,
2283 		NULL, NULL);
2284 
2285 	MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);
2286 	MMIO_D(FUSE_STRAP, D_ALL);
2287 	MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL);
2288 
2289 	MMIO_D(DISP_ARB_CTL, D_ALL);
2290 	MMIO_D(DISP_ARB_CTL2, D_ALL);
2291 
2292 	MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL);
2293 	MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL);
2294 	MMIO_D(ILK_DSPCLK_GATE_D, D_ALL);
2295 
2296 	MMIO_D(SOUTH_CHICKEN1, D_ALL);
2297 	MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
2298 	MMIO_D(_MMIO(_TRANSA_CHICKEN1), D_ALL);
2299 	MMIO_D(_MMIO(_TRANSB_CHICKEN1), D_ALL);
2300 	MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL);
2301 	MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL);
2302 	MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL);
2303 
2304 	MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
2305 	MMIO_D(ILK_DPFC_CONTROL, D_ALL);
2306 	MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL);
2307 	MMIO_D(ILK_DPFC_STATUS, D_ALL);
2308 	MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL);
2309 	MMIO_D(ILK_DPFC_CHICKEN, D_ALL);
2310 	MMIO_D(ILK_FBC_RT_BASE, D_ALL);
2311 
2312 	MMIO_D(IPS_CTL, D_ALL);
2313 
2314 	MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL);
2315 	MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL);
2316 	MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL);
2317 	MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL);
2318 	MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL);
2319 	MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL);
2320 	MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL);
2321 	MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL);
2322 	MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL);
2323 	MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL);
2324 	MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL);
2325 	MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL);
2326 	MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL);
2327 
2328 	MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL);
2329 	MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL);
2330 	MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL);
2331 	MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL);
2332 	MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL);
2333 	MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL);
2334 	MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL);
2335 	MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL);
2336 	MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL);
2337 	MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL);
2338 	MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL);
2339 	MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL);
2340 	MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL);
2341 
2342 	MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL);
2343 	MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL);
2344 	MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL);
2345 	MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL);
2346 	MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL);
2347 	MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL);
2348 	MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL);
2349 	MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL);
2350 	MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL);
2351 	MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL);
2352 	MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL);
2353 	MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL);
2354 	MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL);
2355 
2356 	MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL);
2357 	MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL);
2358 	MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
2359 
2360 	MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL);
2361 	MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL);
2362 	MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
2363 
2364 	MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL);
2365 	MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL);
2366 	MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
2367 
2368 	MMIO_D(_MMIO(0x60110), D_ALL);
2369 	MMIO_D(_MMIO(0x61110), D_ALL);
2370 	MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
2371 	MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
2372 	MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
2373 	MMIO_F(_MMIO(0x70440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2374 	MMIO_F(_MMIO(0x71440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2375 	MMIO_F(_MMIO(0x72440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2376 	MMIO_F(_MMIO(0x7044c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2377 	MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2378 	MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2379 
2380 	MMIO_D(PIPE_WM_LINETIME(PIPE_A), D_ALL);
2381 	MMIO_D(PIPE_WM_LINETIME(PIPE_B), D_ALL);
2382 	MMIO_D(PIPE_WM_LINETIME(PIPE_C), D_ALL);
2383 	MMIO_D(SPLL_CTL, D_ALL);
2384 	MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL);
2385 	MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL);
2386 	MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL);
2387 	MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL);
2388 	MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL);
2389 	MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL);
2390 	MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL);
2391 	MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL);
2392 	MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL);
2393 	MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL);
2394 
2395 	MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL);
2396 	MMIO_D(_MMIO(0x46508), D_ALL);
2397 
2398 	MMIO_D(_MMIO(0x49080), D_ALL);
2399 	MMIO_D(_MMIO(0x49180), D_ALL);
2400 	MMIO_D(_MMIO(0x49280), D_ALL);
2401 
2402 	MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
2403 	MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
2404 	MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
2405 
2406 	MMIO_D(GAMMA_MODE(PIPE_A), D_ALL);
2407 	MMIO_D(GAMMA_MODE(PIPE_B), D_ALL);
2408 	MMIO_D(GAMMA_MODE(PIPE_C), D_ALL);
2409 
2410 	MMIO_D(PIPE_MULT(PIPE_A), D_ALL);
2411 	MMIO_D(PIPE_MULT(PIPE_B), D_ALL);
2412 	MMIO_D(PIPE_MULT(PIPE_C), D_ALL);
2413 
2414 	MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL);
2415 	MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL);
2416 	MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL);
2417 
2418 	MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
2419 	MMIO_D(SBI_ADDR, D_ALL);
2420 	MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
2421 	MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
2422 	MMIO_D(PIXCLK_GATE, D_ALL);
2423 
2424 	MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL,
2425 		dp_aux_ch_ctl_mmio_write);
2426 
2427 	MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2428 	MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2429 	MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2430 	MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2431 	MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2432 
2433 	MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
2434 	MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
2435 	MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
2436 	MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
2437 	MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
2438 
2439 	MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
2440 	MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
2441 	MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
2442 	MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
2443 	MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
2444 
2445 	MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2446 	MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2447 	MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2448 	MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2449 	MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2450 
2451 	MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL);
2452 	MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL);
2453 	MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A), D_ALL);
2454 
2455 	MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL);
2456 	MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL);
2457 	MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL);
2458 	MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL);
2459 
2460 	MMIO_D(_MMIO(_TRANSA_MSA_MISC), D_ALL);
2461 	MMIO_D(_MMIO(_TRANSB_MSA_MISC), D_ALL);
2462 	MMIO_D(_MMIO(_TRANSC_MSA_MISC), D_ALL);
2463 	MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC), D_ALL);
2464 
2465 	MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);
2466 	MMIO_D(FORCEWAKE_ACK, D_ALL);
2467 	MMIO_D(GEN6_GT_CORE_STATUS, D_ALL);
2468 	MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL);
2469 	MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL);
2470 	MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
2471 	MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);
2472 	MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL);
2473 	MMIO_D(ECOBUS, D_ALL);
2474 	MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);
2475 	MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);
2476 	MMIO_D(GEN6_RPNSWREQ, D_ALL);
2477 	MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL);
2478 	MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL);
2479 	MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL);
2480 	MMIO_D(GEN6_RPSTAT1, D_ALL);
2481 	MMIO_D(GEN6_RP_CONTROL, D_ALL);
2482 	MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL);
2483 	MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL);
2484 	MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL);
2485 	MMIO_D(GEN6_RP_CUR_UP, D_ALL);
2486 	MMIO_D(GEN6_RP_PREV_UP, D_ALL);
2487 	MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL);
2488 	MMIO_D(GEN6_RP_CUR_DOWN, D_ALL);
2489 	MMIO_D(GEN6_RP_PREV_DOWN, D_ALL);
2490 	MMIO_D(GEN6_RP_UP_EI, D_ALL);
2491 	MMIO_D(GEN6_RP_DOWN_EI, D_ALL);
2492 	MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL);
2493 	MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL);
2494 	MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL);
2495 	MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL);
2496 	MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL);
2497 	MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL);
2498 	MMIO_D(GEN6_RC_SLEEP, D_ALL);
2499 	MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL);
2500 	MMIO_D(GEN6_RC6_THRESHOLD, D_ALL);
2501 	MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
2502 	MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
2503 	MMIO_D(GEN6_PMINTRMSK, D_ALL);
2504 	MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write);
2505 	MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write);
2506 	MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write);
2507 	MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write);
2508 	MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);
2509 	MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);
2510 
2511 	MMIO_D(RSTDBYCTL, D_ALL);
2512 
2513 	MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
2514 	MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
2515 	MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
2516 
2517 	MMIO_D(TILECTL, D_ALL);
2518 
2519 	MMIO_D(GEN6_UCGCTL1, D_ALL);
2520 	MMIO_D(GEN6_UCGCTL2, D_ALL);
2521 
2522 	MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL);
2523 
2524 	MMIO_D(GEN6_PCODE_DATA, D_ALL);
2525 	MMIO_D(_MMIO(0x13812c), D_ALL);
2526 	MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
2527 	MMIO_D(HSW_EDRAM_CAP, D_ALL);
2528 	MMIO_D(HSW_IDICR, D_ALL);
2529 	MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);
2530 
2531 	MMIO_D(_MMIO(0x3c), D_ALL);
2532 	MMIO_D(_MMIO(0x860), D_ALL);
2533 	MMIO_D(ECOSKPD, D_ALL);
2534 	MMIO_D(_MMIO(0x121d0), D_ALL);
2535 	MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
2536 	MMIO_D(_MMIO(0x41d0), D_ALL);
2537 	MMIO_D(GAC_ECO_BITS, D_ALL);
2538 	MMIO_D(_MMIO(0x6200), D_ALL);
2539 	MMIO_D(_MMIO(0x6204), D_ALL);
2540 	MMIO_D(_MMIO(0x6208), D_ALL);
2541 	MMIO_D(_MMIO(0x7118), D_ALL);
2542 	MMIO_D(_MMIO(0x7180), D_ALL);
2543 	MMIO_D(_MMIO(0x7408), D_ALL);
2544 	MMIO_D(_MMIO(0x7c00), D_ALL);
2545 	MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
2546 	MMIO_D(_MMIO(0x911c), D_ALL);
2547 	MMIO_D(_MMIO(0x9120), D_ALL);
2548 	MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
2549 
2550 	MMIO_D(GAB_CTL, D_ALL);
2551 	MMIO_D(_MMIO(0x48800), D_ALL);
2552 	MMIO_D(_MMIO(0xce044), D_ALL);
2553 	MMIO_D(_MMIO(0xe6500), D_ALL);
2554 	MMIO_D(_MMIO(0xe6504), D_ALL);
2555 	MMIO_D(_MMIO(0xe6600), D_ALL);
2556 	MMIO_D(_MMIO(0xe6604), D_ALL);
2557 	MMIO_D(_MMIO(0xe6700), D_ALL);
2558 	MMIO_D(_MMIO(0xe6704), D_ALL);
2559 	MMIO_D(_MMIO(0xe6800), D_ALL);
2560 	MMIO_D(_MMIO(0xe6804), D_ALL);
2561 	MMIO_D(PCH_GMBUS4, D_ALL);
2562 	MMIO_D(PCH_GMBUS5, D_ALL);
2563 
2564 	MMIO_D(_MMIO(0x902c), D_ALL);
2565 	MMIO_D(_MMIO(0xec008), D_ALL);
2566 	MMIO_D(_MMIO(0xec00c), D_ALL);
2567 	MMIO_D(_MMIO(0xec008 + 0x18), D_ALL);
2568 	MMIO_D(_MMIO(0xec00c + 0x18), D_ALL);
2569 	MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL);
2570 	MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL);
2571 	MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL);
2572 	MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL);
2573 	MMIO_D(_MMIO(0xec408), D_ALL);
2574 	MMIO_D(_MMIO(0xec40c), D_ALL);
2575 	MMIO_D(_MMIO(0xec408 + 0x18), D_ALL);
2576 	MMIO_D(_MMIO(0xec40c + 0x18), D_ALL);
2577 	MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL);
2578 	MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL);
2579 	MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL);
2580 	MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL);
2581 	MMIO_D(_MMIO(0xfc810), D_ALL);
2582 	MMIO_D(_MMIO(0xfc81c), D_ALL);
2583 	MMIO_D(_MMIO(0xfc828), D_ALL);
2584 	MMIO_D(_MMIO(0xfc834), D_ALL);
2585 	MMIO_D(_MMIO(0xfcc00), D_ALL);
2586 	MMIO_D(_MMIO(0xfcc0c), D_ALL);
2587 	MMIO_D(_MMIO(0xfcc18), D_ALL);
2588 	MMIO_D(_MMIO(0xfcc24), D_ALL);
2589 	MMIO_D(_MMIO(0xfd000), D_ALL);
2590 	MMIO_D(_MMIO(0xfd00c), D_ALL);
2591 	MMIO_D(_MMIO(0xfd018), D_ALL);
2592 	MMIO_D(_MMIO(0xfd024), D_ALL);
2593 	MMIO_D(_MMIO(0xfd034), D_ALL);
2594 
2595 	MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);
2596 	MMIO_D(_MMIO(0x2054), D_ALL);
2597 	MMIO_D(_MMIO(0x12054), D_ALL);
2598 	MMIO_D(_MMIO(0x22054), D_ALL);
2599 	MMIO_D(_MMIO(0x1a054), D_ALL);
2600 
2601 	MMIO_D(_MMIO(0x44070), D_ALL);
2602 	MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2603 	MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL);
2604 	MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
2605 	MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL);
2606 	MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
2607 
2608 	MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
2609 	MMIO_D(_MMIO(0x2b00), D_BDW_PLUS);
2610 	MMIO_D(_MMIO(0x2360), D_BDW_PLUS);
2611 	MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2612 	MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2613 	MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2614 
2615 	MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2616 	MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2617 	MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL);
2618 
2619 	MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2620 	MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2621 	MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2622 	MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2623 	MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2624 	MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2625 	MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2626 	MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2627 	MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2628 	MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2629 	MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2630 	MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2631 	MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2632 	MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2633 	MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2634 	MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2635 	MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2636 
2637 	MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2638 	MMIO_RING_GM_RDR(RING_BBADDR, D_ALL, NULL, NULL);
2639 	MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL);
2640 	MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL);
2641 	MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL);
2642 	MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);
2643 	MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);
2644 	MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2645 	MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2646 	MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2647 	MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2648 
2649 	MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
2650 	MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
2651 	return 0;
2652 }
2653 
2654 static int init_broadwell_mmio_info(struct intel_gvt *gvt)
2655 {
2656 	struct drm_i915_private *dev_priv = gvt->dev_priv;
2657 	int ret;
2658 
2659 	MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2660 	MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2661 	MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2662 	MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS);
2663 
2664 	MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2665 	MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2666 	MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2667 	MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS);
2668 
2669 	MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2670 	MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2671 	MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2672 	MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS);
2673 
2674 	MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2675 	MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2676 	MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2677 	MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS);
2678 
2679 	MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL,
2680 		intel_vgpu_reg_imr_handler);
2681 	MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL,
2682 		intel_vgpu_reg_ier_handler);
2683 	MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL,
2684 		intel_vgpu_reg_iir_handler);
2685 	MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS);
2686 
2687 	MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL,
2688 		intel_vgpu_reg_imr_handler);
2689 	MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL,
2690 		intel_vgpu_reg_ier_handler);
2691 	MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL,
2692 		intel_vgpu_reg_iir_handler);
2693 	MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS);
2694 
2695 	MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL,
2696 		intel_vgpu_reg_imr_handler);
2697 	MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL,
2698 		intel_vgpu_reg_ier_handler);
2699 	MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL,
2700 		intel_vgpu_reg_iir_handler);
2701 	MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS);
2702 
2703 	MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2704 	MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2705 	MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2706 	MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS);
2707 
2708 	MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2709 	MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2710 	MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2711 	MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS);
2712 
2713 	MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2714 	MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2715 	MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2716 	MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS);
2717 
2718 	MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
2719 		intel_vgpu_reg_master_irq_handler);
2720 
2721 	MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, F_CMD_ACCESS,
2722 		mmio_read_from_hw, NULL);
2723 
2724 #define RING_REG(base) _MMIO((base) + 0xd0)
2725 	MMIO_RING_F(RING_REG, 4, F_RO, 0,
2726 		~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
2727 		ring_reset_ctl_write);
2728 #undef RING_REG
2729 
2730 #define RING_REG(base) _MMIO((base) + 0x230)
2731 	MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
2732 #undef RING_REG
2733 
2734 #define RING_REG(base) _MMIO((base) + 0x234)
2735 	MMIO_RING_F(RING_REG, 8, F_RO | F_CMD_ACCESS, 0, ~0, D_BDW_PLUS,
2736 		NULL, NULL);
2737 #undef RING_REG
2738 
2739 #define RING_REG(base) _MMIO((base) + 0x244)
2740 	MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2741 #undef RING_REG
2742 
2743 #define RING_REG(base) _MMIO((base) + 0x370)
2744 	MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
2745 #undef RING_REG
2746 
2747 #define RING_REG(base) _MMIO((base) + 0x3a0)
2748 	MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
2749 #undef RING_REG
2750 
2751 	MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS);
2752 	MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS);
2753 	MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS);
2754 	MMIO_D(_MMIO(0x1c1d0), D_BDW_PLUS);
2755 	MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS);
2756 	MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS);
2757 	MMIO_D(_MMIO(0x1c054), D_BDW_PLUS);
2758 
2759 	MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
2760 
2761 	MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS);
2762 	MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
2763 
2764 	MMIO_D(GAMTARBMODE, D_BDW_PLUS);
2765 
2766 #define RING_REG(base) _MMIO((base) + 0x270)
2767 	MMIO_RING_F(RING_REG, 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL);
2768 #undef RING_REG
2769 
2770 	MMIO_RING_GM_RDR(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write);
2771 
2772 	MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2773 
2774 	MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS);
2775 	MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS);
2776 	MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS);
2777 
2778 	MMIO_D(WM_MISC, D_BDW);
2779 	MMIO_D(_MMIO(BDW_EDP_PSR_BASE), D_BDW);
2780 
2781 	MMIO_D(_MMIO(0x6671c), D_BDW_PLUS);
2782 	MMIO_D(_MMIO(0x66c00), D_BDW_PLUS);
2783 	MMIO_D(_MMIO(0x66c04), D_BDW_PLUS);
2784 
2785 	MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS);
2786 
2787 	MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS);
2788 	MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS);
2789 	MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS);
2790 
2791 	MMIO_D(_MMIO(0xfdc), D_BDW_PLUS);
2792 	MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2793 		NULL, NULL);
2794 	MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2795 		NULL, NULL);
2796 	MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2797 
2798 	MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL);
2799 	MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL);
2800 	MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2801 	MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL);
2802 	MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL);
2803 	MMIO_D(_MMIO(0xb110), D_BDW);
2804 
2805 	MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS, 0, 0, D_BDW_PLUS,
2806 		NULL, force_nonpriv_write);
2807 
2808 	MMIO_D(_MMIO(0x44484), D_BDW_PLUS);
2809 	MMIO_D(_MMIO(0x4448c), D_BDW_PLUS);
2810 
2811 	MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL);
2812 	MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS);
2813 
2814 	MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL);
2815 
2816 	MMIO_D(_MMIO(0x110000), D_BDW_PLUS);
2817 
2818 	MMIO_D(_MMIO(0x48400), D_BDW_PLUS);
2819 
2820 	MMIO_D(_MMIO(0x6e570), D_BDW_PLUS);
2821 	MMIO_D(_MMIO(0x65f10), D_BDW_PLUS);
2822 
2823 	MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2824 	MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2825 	MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2826 	MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2827 
2828 	MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL);
2829 
2830 	MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2831 	MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2832 	MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2833 	MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2834 	MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2835 	MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2836 	MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2837 	MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2838 	MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2839 	MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2840 	return 0;
2841 }
2842 
2843 static int init_skl_mmio_info(struct intel_gvt *gvt)
2844 {
2845 	struct drm_i915_private *dev_priv = gvt->dev_priv;
2846 	int ret;
2847 
2848 	MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2849 	MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
2850 	MMIO_DH(FORCEWAKE_BLITTER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2851 	MMIO_DH(FORCEWAKE_ACK_BLITTER_GEN9, D_SKL_PLUS, NULL, NULL);
2852 	MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2853 	MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);
2854 
2855 	MMIO_F(_MMIO(_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
2856 						dp_aux_ch_ctl_mmio_write);
2857 	MMIO_F(_MMIO(_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
2858 						dp_aux_ch_ctl_mmio_write);
2859 	MMIO_F(_MMIO(_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
2860 						dp_aux_ch_ctl_mmio_write);
2861 
2862 	MMIO_D(HSW_PWR_WELL_CTL1, D_SKL_PLUS);
2863 	MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write);
2864 
2865 	MMIO_DH(DBUF_CTL, D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write);
2866 
2867 	MMIO_D(GEN9_PG_ENABLE, D_SKL_PLUS);
2868 	MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
2869 	MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
2870 	MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2871 	MMIO_DH(MMCD_MISC_CTRL, D_SKL_PLUS, NULL, NULL);
2872 	MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL);
2873 	MMIO_D(DC_STATE_EN, D_SKL_PLUS);
2874 	MMIO_D(DC_STATE_DEBUG, D_SKL_PLUS);
2875 	MMIO_D(CDCLK_CTL, D_SKL_PLUS);
2876 	MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
2877 	MMIO_DH(LCPLL2_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
2878 	MMIO_D(_MMIO(_DPLL1_CFGCR1), D_SKL_PLUS);
2879 	MMIO_D(_MMIO(_DPLL2_CFGCR1), D_SKL_PLUS);
2880 	MMIO_D(_MMIO(_DPLL3_CFGCR1), D_SKL_PLUS);
2881 	MMIO_D(_MMIO(_DPLL1_CFGCR2), D_SKL_PLUS);
2882 	MMIO_D(_MMIO(_DPLL2_CFGCR2), D_SKL_PLUS);
2883 	MMIO_D(_MMIO(_DPLL3_CFGCR2), D_SKL_PLUS);
2884 	MMIO_D(DPLL_CTRL1, D_SKL_PLUS);
2885 	MMIO_D(DPLL_CTRL2, D_SKL_PLUS);
2886 	MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL);
2887 
2888 	MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
2889 	MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
2890 	MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
2891 	MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
2892 	MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
2893 	MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
2894 
2895 	MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
2896 	MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
2897 	MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
2898 	MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
2899 	MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
2900 	MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
2901 
2902 	MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
2903 	MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
2904 	MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
2905 	MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
2906 	MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
2907 	MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
2908 
2909 	MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2910 	MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2911 	MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2912 	MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
2913 
2914 	MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2915 	MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2916 	MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2917 	MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
2918 
2919 	MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
2920 	MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2921 	MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2922 	MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
2923 
2924 	MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL);
2925 	MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL);
2926 	MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL);
2927 
2928 	MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2929 	MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2930 	MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2931 
2932 	MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2933 	MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2934 	MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2935 
2936 	MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2937 	MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2938 	MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2939 
2940 	MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2941 	MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2942 	MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2943 
2944 	MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2945 	MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2946 	MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2947 
2948 	MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2949 	MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2950 	MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2951 
2952 	MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
2953 	MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2954 	MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2955 
2956 	MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL);
2957 	MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL);
2958 	MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL);
2959 
2960 	MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2961 	MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2962 	MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2963 	MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
2964 
2965 	MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2966 	MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2967 	MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2968 	MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
2969 
2970 	MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
2971 	MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2972 	MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2973 	MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
2974 
2975 	MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
2976 	MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
2977 	MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
2978 	MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
2979 
2980 	MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
2981 	MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
2982 	MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
2983 	MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
2984 
2985 	MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
2986 	MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
2987 	MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
2988 	MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
2989 
2990 	MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
2991 	MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
2992 	MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
2993 	MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
2994 
2995 	MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
2996 	MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
2997 	MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
2998 	MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
2999 
3000 	MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
3001 	MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
3002 	MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
3003 	MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
3004 
3005 	MMIO_D(_MMIO(_PLANE_CTL_3_A), D_SKL_PLUS);
3006 	MMIO_D(_MMIO(_PLANE_CTL_3_B), D_SKL_PLUS);
3007 	MMIO_D(_MMIO(0x72380), D_SKL_PLUS);
3008 	MMIO_D(_MMIO(0x7239c), D_SKL_PLUS);
3009 	MMIO_D(_MMIO(_PLANE_SURF_3_A), D_SKL_PLUS);
3010 
3011 	MMIO_D(CSR_SSP_BASE, D_SKL_PLUS);
3012 	MMIO_D(CSR_HTP_SKL, D_SKL_PLUS);
3013 	MMIO_D(CSR_LAST_WRITE, D_SKL_PLUS);
3014 
3015 	MMIO_D(BDW_SCRATCH1, D_SKL_PLUS);
3016 
3017 	MMIO_D(SKL_DFSM, D_SKL_PLUS);
3018 	MMIO_D(DISPIO_CR_TX_BMU_CR0, D_SKL_PLUS);
3019 
3020 	MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
3021 		NULL, NULL);
3022 	MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
3023 		NULL, NULL);
3024 
3025 	MMIO_D(RPM_CONFIG0, D_SKL_PLUS);
3026 	MMIO_D(_MMIO(0xd08), D_SKL_PLUS);
3027 	MMIO_D(RC6_LOCATION, D_SKL_PLUS);
3028 	MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS, F_MODE_MASK,
3029 		NULL, NULL);
3030 	MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
3031 		NULL, NULL);
3032 
3033 	/* TRTT */
3034 	MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
3035 	MMIO_DFH(TRVATTL3PTRDW(1), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
3036 	MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
3037 	MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
3038 	MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
3039 	MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS,
3040 		NULL, gen9_trtte_write);
3041 	MMIO_DH(_MMIO(0x4dfc), D_SKL_PLUS, NULL, gen9_trtt_chicken_write);
3042 
3043 	MMIO_D(_MMIO(0x46430), D_SKL_PLUS);
3044 
3045 	MMIO_D(_MMIO(0x46520), D_SKL_PLUS);
3046 
3047 	MMIO_D(_MMIO(0xc403c), D_SKL_PLUS);
3048 	MMIO_D(_MMIO(0xb004), D_SKL_PLUS);
3049 	MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
3050 
3051 	MMIO_D(_MMIO(0x65900), D_SKL_PLUS);
3052 	MMIO_D(GEN6_STOLEN_RESERVED, D_SKL_PLUS);
3053 	MMIO_D(_MMIO(0x4068), D_SKL_PLUS);
3054 	MMIO_D(_MMIO(0x67054), D_SKL_PLUS);
3055 	MMIO_D(_MMIO(0x6e560), D_SKL_PLUS);
3056 	MMIO_D(_MMIO(0x6e554), D_SKL_PLUS);
3057 	MMIO_D(_MMIO(0x2b20), D_SKL_PLUS);
3058 	MMIO_D(_MMIO(0x65f00), D_SKL_PLUS);
3059 	MMIO_D(_MMIO(0x65f08), D_SKL_PLUS);
3060 	MMIO_D(_MMIO(0x320f0), D_SKL_PLUS);
3061 
3062 	MMIO_D(_MMIO(0x70034), D_SKL_PLUS);
3063 	MMIO_D(_MMIO(0x71034), D_SKL_PLUS);
3064 	MMIO_D(_MMIO(0x72034), D_SKL_PLUS);
3065 
3066 	MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A)), D_SKL_PLUS);
3067 	MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B)), D_SKL_PLUS);
3068 	MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C)), D_SKL_PLUS);
3069 	MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A)), D_SKL_PLUS);
3070 	MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B)), D_SKL_PLUS);
3071 	MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C)), D_SKL_PLUS);
3072 	MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A)), D_SKL_PLUS);
3073 	MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)), D_SKL_PLUS);
3074 	MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)), D_SKL_PLUS);
3075 
3076 	MMIO_D(_MMIO(0x44500), D_SKL_PLUS);
3077 	MMIO_DFH(GEN9_CSFE_CHICKEN1_RCS, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
3078 	MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
3079 		 NULL, NULL);
3080 	MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
3081 		 NULL, NULL);
3082 
3083 	MMIO_D(GAMT_CHKN_BIT_REG, D_KBL);
3084 	MMIO_D(GEN9_CTX_PREEMPT_REG, D_KBL | D_SKL);
3085 
3086 	return 0;
3087 }
3088 
3089 static int init_bxt_mmio_info(struct intel_gvt *gvt)
3090 {
3091 	struct drm_i915_private *dev_priv = gvt->dev_priv;
3092 	int ret;
3093 
3094 	MMIO_F(_MMIO(0x80000), 0x3000, 0, 0, 0, D_BXT, NULL, NULL);
3095 
3096 	MMIO_D(GEN7_SAMPLER_INSTDONE, D_BXT);
3097 	MMIO_D(GEN7_ROW_INSTDONE, D_BXT);
3098 	MMIO_D(GEN8_FAULT_TLB_DATA0, D_BXT);
3099 	MMIO_D(GEN8_FAULT_TLB_DATA1, D_BXT);
3100 	MMIO_D(ERROR_GEN6, D_BXT);
3101 	MMIO_D(DONE_REG, D_BXT);
3102 	MMIO_D(EIR, D_BXT);
3103 	MMIO_D(PGTBL_ER, D_BXT);
3104 	MMIO_D(_MMIO(0x4194), D_BXT);
3105 	MMIO_D(_MMIO(0x4294), D_BXT);
3106 	MMIO_D(_MMIO(0x4494), D_BXT);
3107 
3108 	MMIO_RING_D(RING_PSMI_CTL, D_BXT);
3109 	MMIO_RING_D(RING_DMA_FADD, D_BXT);
3110 	MMIO_RING_D(RING_DMA_FADD_UDW, D_BXT);
3111 	MMIO_RING_D(RING_IPEHR, D_BXT);
3112 	MMIO_RING_D(RING_INSTPS, D_BXT);
3113 	MMIO_RING_D(RING_BBADDR_UDW, D_BXT);
3114 	MMIO_RING_D(RING_BBSTATE, D_BXT);
3115 	MMIO_RING_D(RING_IPEIR, D_BXT);
3116 
3117 	MMIO_F(SOFT_SCRATCH(0), 16 * 4, 0, 0, 0, D_BXT, NULL, NULL);
3118 
3119 	MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write);
3120 	MMIO_D(BXT_RP_STATE_CAP, D_BXT);
3121 	MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT,
3122 		NULL, bxt_phy_ctl_family_write);
3123 	MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT,
3124 		NULL, bxt_phy_ctl_family_write);
3125 	MMIO_D(BXT_PHY_CTL(PORT_A), D_BXT);
3126 	MMIO_D(BXT_PHY_CTL(PORT_B), D_BXT);
3127 	MMIO_D(BXT_PHY_CTL(PORT_C), D_BXT);
3128 	MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT,
3129 		NULL, bxt_port_pll_enable_write);
3130 	MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT,
3131 		NULL, bxt_port_pll_enable_write);
3132 	MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL,
3133 		bxt_port_pll_enable_write);
3134 
3135 	MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY0), D_BXT);
3136 	MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY0), D_BXT);
3137 	MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY0), D_BXT);
3138 	MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY0), D_BXT);
3139 	MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY0), D_BXT);
3140 	MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY0), D_BXT);
3141 	MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY0), D_BXT);
3142 	MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY0), D_BXT);
3143 	MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY0), D_BXT);
3144 
3145 	MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY1), D_BXT);
3146 	MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY1), D_BXT);
3147 	MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY1), D_BXT);
3148 	MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY1), D_BXT);
3149 	MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY1), D_BXT);
3150 	MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY1), D_BXT);
3151 	MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY1), D_BXT);
3152 	MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY1), D_BXT);
3153 	MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY1), D_BXT);
3154 
3155 	MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH0), D_BXT);
3156 	MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH0), D_BXT);
3157 	MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
3158 	MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
3159 	MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
3160 	MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH0), D_BXT);
3161 	MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT,
3162 		NULL, bxt_pcs_dw12_grp_write);
3163 	MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
3164 	MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
3165 	MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT,
3166 		bxt_port_tx_dw3_read, NULL);
3167 	MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
3168 	MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
3169 	MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
3170 	MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
3171 	MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
3172 	MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
3173 	MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
3174 	MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
3175 	MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
3176 	MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
3177 	MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
3178 	MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 6), D_BXT);
3179 	MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 8), D_BXT);
3180 	MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 9), D_BXT);
3181 	MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 10), D_BXT);
3182 
3183 	MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH1), D_BXT);
3184 	MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH1), D_BXT);
3185 	MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
3186 	MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
3187 	MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
3188 	MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH1), D_BXT);
3189 	MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT,
3190 		NULL, bxt_pcs_dw12_grp_write);
3191 	MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
3192 	MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
3193 	MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT,
3194 		bxt_port_tx_dw3_read, NULL);
3195 	MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
3196 	MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
3197 	MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
3198 	MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
3199 	MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
3200 	MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
3201 	MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
3202 	MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
3203 	MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
3204 	MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
3205 	MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
3206 	MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 6), D_BXT);
3207 	MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 8), D_BXT);
3208 	MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 9), D_BXT);
3209 	MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 10), D_BXT);
3210 
3211 	MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY1, DPIO_CH0), D_BXT);
3212 	MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY1, DPIO_CH0), D_BXT);
3213 	MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
3214 	MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
3215 	MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
3216 	MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY1, DPIO_CH0), D_BXT);
3217 	MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT,
3218 		NULL, bxt_pcs_dw12_grp_write);
3219 	MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
3220 	MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
3221 	MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT,
3222 		bxt_port_tx_dw3_read, NULL);
3223 	MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
3224 	MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
3225 	MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
3226 	MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
3227 	MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
3228 	MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
3229 	MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
3230 	MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
3231 	MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
3232 	MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
3233 	MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
3234 	MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 6), D_BXT);
3235 	MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 8), D_BXT);
3236 	MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 9), D_BXT);
3237 	MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 10), D_BXT);
3238 
3239 	MMIO_D(BXT_DE_PLL_CTL, D_BXT);
3240 	MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write);
3241 	MMIO_D(BXT_DSI_PLL_CTL, D_BXT);
3242 	MMIO_D(BXT_DSI_PLL_ENABLE, D_BXT);
3243 
3244 	MMIO_D(GEN9_CLKGATE_DIS_0, D_BXT);
3245 	MMIO_D(GEN9_CLKGATE_DIS_4, D_BXT);
3246 
3247 	MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_A), D_BXT);
3248 	MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT);
3249 	MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C), D_BXT);
3250 
3251 	MMIO_D(RC6_CTX_BASE, D_BXT);
3252 
3253 	MMIO_D(GEN8_PUSHBUS_CONTROL, D_BXT);
3254 	MMIO_D(GEN8_PUSHBUS_ENABLE, D_BXT);
3255 	MMIO_D(GEN8_PUSHBUS_SHIFT, D_BXT);
3256 	MMIO_D(GEN6_GFXPAUSE, D_BXT);
3257 	MMIO_D(GEN8_L3SQCREG1, D_BXT);
3258 
3259 	MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL);
3260 
3261 	return 0;
3262 }
3263 
3264 static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt,
3265 					      unsigned int offset)
3266 {
3267 	unsigned long device = intel_gvt_get_device_type(gvt);
3268 	struct gvt_mmio_block *block = gvt->mmio.mmio_block;
3269 	int num = gvt->mmio.num_mmio_block;
3270 	int i;
3271 
3272 	for (i = 0; i < num; i++, block++) {
3273 		if (!(device & block->device))
3274 			continue;
3275 		if (offset >= i915_mmio_reg_offset(block->offset) &&
3276 		    offset < i915_mmio_reg_offset(block->offset) + block->size)
3277 			return block;
3278 	}
3279 	return NULL;
3280 }
3281 
3282 /**
3283  * intel_gvt_clean_mmio_info - clean up MMIO information table for GVT device
3284  * @gvt: GVT device
3285  *
3286  * This function is called at the driver unloading stage, to clean up the MMIO
3287  * information table of GVT device
3288  *
3289  */
3290 void intel_gvt_clean_mmio_info(struct intel_gvt *gvt)
3291 {
3292 	struct hlist_node *tmp;
3293 	struct intel_gvt_mmio_info *e;
3294 	int i;
3295 
3296 	hash_for_each_safe(gvt->mmio.mmio_info_table, i, tmp, e, node)
3297 		kfree(e);
3298 
3299 	vfree(gvt->mmio.mmio_attribute);
3300 	gvt->mmio.mmio_attribute = NULL;
3301 }
3302 
3303 /* Special MMIO blocks. */
3304 static struct gvt_mmio_block mmio_blocks[] = {
3305 	{D_SKL_PLUS, _MMIO(CSR_MMIO_START_RANGE), 0x3000, NULL, NULL},
3306 	{D_ALL, _MMIO(MCHBAR_MIRROR_BASE_SNB), 0x40000, NULL, NULL},
3307 	{D_ALL, _MMIO(VGT_PVINFO_PAGE), VGT_PVINFO_SIZE,
3308 		pvinfo_mmio_read, pvinfo_mmio_write},
3309 	{D_ALL, LGC_PALETTE(PIPE_A, 0), 1024, NULL, NULL},
3310 	{D_ALL, LGC_PALETTE(PIPE_B, 0), 1024, NULL, NULL},
3311 	{D_ALL, LGC_PALETTE(PIPE_C, 0), 1024, NULL, NULL},
3312 };
3313 
3314 /**
3315  * intel_gvt_setup_mmio_info - setup MMIO information table for GVT device
3316  * @gvt: GVT device
3317  *
3318  * This function is called at the initialization stage, to setup the MMIO
3319  * information table for GVT device
3320  *
3321  * Returns:
3322  * zero on success, negative if failed.
3323  */
3324 int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
3325 {
3326 	struct intel_gvt_device_info *info = &gvt->device_info;
3327 	struct drm_i915_private *dev_priv = gvt->dev_priv;
3328 	int size = info->mmio_size / 4 * sizeof(*gvt->mmio.mmio_attribute);
3329 	int ret;
3330 
3331 	gvt->mmio.mmio_attribute = vzalloc(size);
3332 	if (!gvt->mmio.mmio_attribute)
3333 		return -ENOMEM;
3334 
3335 	ret = init_generic_mmio_info(gvt);
3336 	if (ret)
3337 		goto err;
3338 
3339 	if (IS_BROADWELL(dev_priv)) {
3340 		ret = init_broadwell_mmio_info(gvt);
3341 		if (ret)
3342 			goto err;
3343 	} else if (IS_SKYLAKE(dev_priv)
3344 		|| IS_KABYLAKE(dev_priv)
3345 		|| IS_COFFEELAKE(dev_priv)) {
3346 		ret = init_broadwell_mmio_info(gvt);
3347 		if (ret)
3348 			goto err;
3349 		ret = init_skl_mmio_info(gvt);
3350 		if (ret)
3351 			goto err;
3352 	} else if (IS_BROXTON(dev_priv)) {
3353 		ret = init_broadwell_mmio_info(gvt);
3354 		if (ret)
3355 			goto err;
3356 		ret = init_skl_mmio_info(gvt);
3357 		if (ret)
3358 			goto err;
3359 		ret = init_bxt_mmio_info(gvt);
3360 		if (ret)
3361 			goto err;
3362 	}
3363 
3364 	gvt->mmio.mmio_block = mmio_blocks;
3365 	gvt->mmio.num_mmio_block = ARRAY_SIZE(mmio_blocks);
3366 
3367 	return 0;
3368 err:
3369 	intel_gvt_clean_mmio_info(gvt);
3370 	return ret;
3371 }
3372 
3373 /**
3374  * intel_gvt_for_each_tracked_mmio - iterate each tracked mmio
3375  * @gvt: a GVT device
3376  * @handler: the handler
3377  * @data: private data given to handler
3378  *
3379  * Returns:
3380  * Zero on success, negative error code if failed.
3381  */
3382 int intel_gvt_for_each_tracked_mmio(struct intel_gvt *gvt,
3383 	int (*handler)(struct intel_gvt *gvt, u32 offset, void *data),
3384 	void *data)
3385 {
3386 	struct gvt_mmio_block *block = gvt->mmio.mmio_block;
3387 	struct intel_gvt_mmio_info *e;
3388 	int i, j, ret;
3389 
3390 	hash_for_each(gvt->mmio.mmio_info_table, i, e, node) {
3391 		ret = handler(gvt, e->offset, data);
3392 		if (ret)
3393 			return ret;
3394 	}
3395 
3396 	for (i = 0; i < gvt->mmio.num_mmio_block; i++, block++) {
3397 		for (j = 0; j < block->size; j += 4) {
3398 			ret = handler(gvt,
3399 				      i915_mmio_reg_offset(block->offset) + j,
3400 				      data);
3401 			if (ret)
3402 				return ret;
3403 		}
3404 	}
3405 	return 0;
3406 }
3407 
3408 /**
3409  * intel_vgpu_default_mmio_read - default MMIO read handler
3410  * @vgpu: a vGPU
3411  * @offset: access offset
3412  * @p_data: data return buffer
3413  * @bytes: access data length
3414  *
3415  * Returns:
3416  * Zero on success, negative error code if failed.
3417  */
3418 int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
3419 		void *p_data, unsigned int bytes)
3420 {
3421 	read_vreg(vgpu, offset, p_data, bytes);
3422 	return 0;
3423 }
3424 
3425 /**
3426  * intel_t_default_mmio_write - default MMIO write handler
3427  * @vgpu: a vGPU
3428  * @offset: access offset
3429  * @p_data: write data buffer
3430  * @bytes: access data length
3431  *
3432  * Returns:
3433  * Zero on success, negative error code if failed.
3434  */
3435 int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
3436 		void *p_data, unsigned int bytes)
3437 {
3438 	write_vreg(vgpu, offset, p_data, bytes);
3439 	return 0;
3440 }
3441 
3442 /**
3443  * intel_vgpu_mask_mmio_write - write mask register
3444  * @vgpu: a vGPU
3445  * @offset: access offset
3446  * @p_data: write data buffer
3447  * @bytes: access data length
3448  *
3449  * Returns:
3450  * Zero on success, negative error code if failed.
3451  */
3452 int intel_vgpu_mask_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
3453 		void *p_data, unsigned int bytes)
3454 {
3455 	u32 mask, old_vreg;
3456 
3457 	old_vreg = vgpu_vreg(vgpu, offset);
3458 	write_vreg(vgpu, offset, p_data, bytes);
3459 	mask = vgpu_vreg(vgpu, offset) >> 16;
3460 	vgpu_vreg(vgpu, offset) = (old_vreg & ~mask) |
3461 				(vgpu_vreg(vgpu, offset) & mask);
3462 
3463 	return 0;
3464 }
3465 
3466 /**
3467  * intel_gvt_in_force_nonpriv_whitelist - if a mmio is in whitelist to be
3468  * force-nopriv register
3469  *
3470  * @gvt: a GVT device
3471  * @offset: register offset
3472  *
3473  * Returns:
3474  * True if the register is in force-nonpriv whitelist;
3475  * False if outside;
3476  */
3477 bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt,
3478 					  unsigned int offset)
3479 {
3480 	return in_whitelist(offset);
3481 }
3482 
3483 /**
3484  * intel_vgpu_mmio_reg_rw - emulate tracked mmio registers
3485  * @vgpu: a vGPU
3486  * @offset: register offset
3487  * @pdata: data buffer
3488  * @bytes: data length
3489  * @is_read: read or write
3490  *
3491  * Returns:
3492  * Zero on success, negative error code if failed.
3493  */
3494 int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset,
3495 			   void *pdata, unsigned int bytes, bool is_read)
3496 {
3497 	struct intel_gvt *gvt = vgpu->gvt;
3498 	struct intel_gvt_mmio_info *mmio_info;
3499 	struct gvt_mmio_block *mmio_block;
3500 	gvt_mmio_func func;
3501 	int ret;
3502 
3503 	if (WARN_ON(bytes > 8))
3504 		return -EINVAL;
3505 
3506 	/*
3507 	 * Handle special MMIO blocks.
3508 	 */
3509 	mmio_block = find_mmio_block(gvt, offset);
3510 	if (mmio_block) {
3511 		func = is_read ? mmio_block->read : mmio_block->write;
3512 		if (func)
3513 			return func(vgpu, offset, pdata, bytes);
3514 		goto default_rw;
3515 	}
3516 
3517 	/*
3518 	 * Normal tracked MMIOs.
3519 	 */
3520 	mmio_info = find_mmio_info(gvt, offset);
3521 	if (!mmio_info) {
3522 		gvt_dbg_mmio("untracked MMIO %08x len %d\n", offset, bytes);
3523 		goto default_rw;
3524 	}
3525 
3526 	if (is_read)
3527 		return mmio_info->read(vgpu, offset, pdata, bytes);
3528 	else {
3529 		u64 ro_mask = mmio_info->ro_mask;
3530 		u32 old_vreg = 0;
3531 		u64 data = 0;
3532 
3533 		if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) {
3534 			old_vreg = vgpu_vreg(vgpu, offset);
3535 		}
3536 
3537 		if (likely(!ro_mask))
3538 			ret = mmio_info->write(vgpu, offset, pdata, bytes);
3539 		else if (!~ro_mask) {
3540 			gvt_vgpu_err("try to write RO reg %x\n", offset);
3541 			return 0;
3542 		} else {
3543 			/* keep the RO bits in the virtual register */
3544 			memcpy(&data, pdata, bytes);
3545 			data &= ~ro_mask;
3546 			data |= vgpu_vreg(vgpu, offset) & ro_mask;
3547 			ret = mmio_info->write(vgpu, offset, &data, bytes);
3548 		}
3549 
3550 		/* higher 16bits of mode ctl regs are mask bits for change */
3551 		if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) {
3552 			u32 mask = vgpu_vreg(vgpu, offset) >> 16;
3553 
3554 			vgpu_vreg(vgpu, offset) = (old_vreg & ~mask)
3555 					| (vgpu_vreg(vgpu, offset) & mask);
3556 		}
3557 	}
3558 
3559 	return ret;
3560 
3561 default_rw:
3562 	return is_read ?
3563 		intel_vgpu_default_mmio_read(vgpu, offset, pdata, bytes) :
3564 		intel_vgpu_default_mmio_write(vgpu, offset, pdata, bytes);
3565 }
3566