1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Kevin Tian <kevin.tian@intel.com> 25 * Eddie Dong <eddie.dong@intel.com> 26 * Zhiyuan Lv <zhiyuan.lv@intel.com> 27 * 28 * Contributors: 29 * Min He <min.he@intel.com> 30 * Tina Zhang <tina.zhang@intel.com> 31 * Pei Zhang <pei.zhang@intel.com> 32 * Niu Bing <bing.niu@intel.com> 33 * Ping Gao <ping.a.gao@intel.com> 34 * Zhi Wang <zhi.a.wang@intel.com> 35 * 36 37 */ 38 39 #include "i915_drv.h" 40 #include "gvt.h" 41 #include "i915_pvinfo.h" 42 43 /* XXX FIXME i915 has changed PP_XXX definition */ 44 #define PCH_PP_STATUS _MMIO(0xc7200) 45 #define PCH_PP_CONTROL _MMIO(0xc7204) 46 #define PCH_PP_ON_DELAYS _MMIO(0xc7208) 47 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c) 48 #define PCH_PP_DIVISOR _MMIO(0xc7210) 49 50 unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt) 51 { 52 if (IS_BROADWELL(gvt->dev_priv)) 53 return D_BDW; 54 else if (IS_SKYLAKE(gvt->dev_priv)) 55 return D_SKL; 56 else if (IS_KABYLAKE(gvt->dev_priv)) 57 return D_KBL; 58 else if (IS_BROXTON(gvt->dev_priv)) 59 return D_BXT; 60 else if (IS_COFFEELAKE(gvt->dev_priv)) 61 return D_CFL; 62 63 return 0; 64 } 65 66 bool intel_gvt_match_device(struct intel_gvt *gvt, 67 unsigned long device) 68 { 69 return intel_gvt_get_device_type(gvt) & device; 70 } 71 72 static void read_vreg(struct intel_vgpu *vgpu, unsigned int offset, 73 void *p_data, unsigned int bytes) 74 { 75 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); 76 } 77 78 static void write_vreg(struct intel_vgpu *vgpu, unsigned int offset, 79 void *p_data, unsigned int bytes) 80 { 81 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes); 82 } 83 84 static struct intel_gvt_mmio_info *find_mmio_info(struct intel_gvt *gvt, 85 unsigned int offset) 86 { 87 struct intel_gvt_mmio_info *e; 88 89 hash_for_each_possible(gvt->mmio.mmio_info_table, e, node, offset) { 90 if (e->offset == offset) 91 return e; 92 } 93 return NULL; 94 } 95 96 static int new_mmio_info(struct intel_gvt *gvt, 97 u32 offset, u8 flags, u32 size, 98 u32 addr_mask, u32 ro_mask, u32 device, 99 gvt_mmio_func read, gvt_mmio_func write) 100 { 101 struct intel_gvt_mmio_info *info, *p; 102 u32 start, end, i; 103 104 if (!intel_gvt_match_device(gvt, device)) 105 return 0; 106 107 if (WARN_ON(!IS_ALIGNED(offset, 4))) 108 return -EINVAL; 109 110 start = offset; 111 end = offset + size; 112 113 for (i = start; i < end; i += 4) { 114 info = kzalloc(sizeof(*info), GFP_KERNEL); 115 if (!info) 116 return -ENOMEM; 117 118 info->offset = i; 119 p = find_mmio_info(gvt, info->offset); 120 if (p) { 121 WARN(1, "dup mmio definition offset %x\n", 122 info->offset); 123 kfree(info); 124 125 /* We return -EEXIST here to make GVT-g load fail. 126 * So duplicated MMIO can be found as soon as 127 * possible. 128 */ 129 return -EEXIST; 130 } 131 132 info->ro_mask = ro_mask; 133 info->device = device; 134 info->read = read ? read : intel_vgpu_default_mmio_read; 135 info->write = write ? write : intel_vgpu_default_mmio_write; 136 gvt->mmio.mmio_attribute[info->offset / 4] = flags; 137 INIT_HLIST_NODE(&info->node); 138 hash_add(gvt->mmio.mmio_info_table, &info->node, info->offset); 139 gvt->mmio.num_tracked_mmio++; 140 } 141 return 0; 142 } 143 144 /** 145 * intel_gvt_render_mmio_to_ring_id - convert a mmio offset into ring id 146 * @gvt: a GVT device 147 * @offset: register offset 148 * 149 * Returns: 150 * Ring ID on success, negative error code if failed. 151 */ 152 int intel_gvt_render_mmio_to_ring_id(struct intel_gvt *gvt, 153 unsigned int offset) 154 { 155 enum intel_engine_id id; 156 struct intel_engine_cs *engine; 157 158 offset &= ~GENMASK(11, 0); 159 for_each_engine(engine, gvt->dev_priv, id) { 160 if (engine->mmio_base == offset) 161 return id; 162 } 163 return -ENODEV; 164 } 165 166 #define offset_to_fence_num(offset) \ 167 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3) 168 169 #define fence_num_to_offset(num) \ 170 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) 171 172 173 void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason) 174 { 175 switch (reason) { 176 case GVT_FAILSAFE_UNSUPPORTED_GUEST: 177 pr_err("Detected your guest driver doesn't support GVT-g.\n"); 178 break; 179 case GVT_FAILSAFE_INSUFFICIENT_RESOURCE: 180 pr_err("Graphics resource is not enough for the guest\n"); 181 break; 182 case GVT_FAILSAFE_GUEST_ERR: 183 pr_err("GVT Internal error for the guest\n"); 184 break; 185 default: 186 break; 187 } 188 pr_err("Now vgpu %d will enter failsafe mode.\n", vgpu->id); 189 vgpu->failsafe = true; 190 } 191 192 static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu, 193 unsigned int fence_num, void *p_data, unsigned int bytes) 194 { 195 unsigned int max_fence = vgpu_fence_sz(vgpu); 196 197 if (fence_num >= max_fence) { 198 gvt_vgpu_err("access oob fence reg %d/%d\n", 199 fence_num, max_fence); 200 201 /* When guest access oob fence regs without access 202 * pv_info first, we treat guest not supporting GVT, 203 * and we will let vgpu enter failsafe mode. 204 */ 205 if (!vgpu->pv_notified) 206 enter_failsafe_mode(vgpu, 207 GVT_FAILSAFE_UNSUPPORTED_GUEST); 208 209 memset(p_data, 0, bytes); 210 return -EINVAL; 211 } 212 return 0; 213 } 214 215 static int gamw_echo_dev_rw_ia_write(struct intel_vgpu *vgpu, 216 unsigned int offset, void *p_data, unsigned int bytes) 217 { 218 u32 ips = (*(u32 *)p_data) & GAMW_ECO_ENABLE_64K_IPS_FIELD; 219 220 if (INTEL_GEN(vgpu->gvt->dev_priv) <= 10) { 221 if (ips == GAMW_ECO_ENABLE_64K_IPS_FIELD) 222 gvt_dbg_core("vgpu%d: ips enabled\n", vgpu->id); 223 else if (!ips) 224 gvt_dbg_core("vgpu%d: ips disabled\n", vgpu->id); 225 else { 226 /* All engines must be enabled together for vGPU, 227 * since we don't know which engine the ppgtt will 228 * bind to when shadowing. 229 */ 230 gvt_vgpu_err("Unsupported IPS setting %x, cannot enable 64K gtt.\n", 231 ips); 232 return -EINVAL; 233 } 234 } 235 236 write_vreg(vgpu, offset, p_data, bytes); 237 return 0; 238 } 239 240 static int fence_mmio_read(struct intel_vgpu *vgpu, unsigned int off, 241 void *p_data, unsigned int bytes) 242 { 243 int ret; 244 245 ret = sanitize_fence_mmio_access(vgpu, offset_to_fence_num(off), 246 p_data, bytes); 247 if (ret) 248 return ret; 249 read_vreg(vgpu, off, p_data, bytes); 250 return 0; 251 } 252 253 static int fence_mmio_write(struct intel_vgpu *vgpu, unsigned int off, 254 void *p_data, unsigned int bytes) 255 { 256 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 257 unsigned int fence_num = offset_to_fence_num(off); 258 int ret; 259 260 ret = sanitize_fence_mmio_access(vgpu, fence_num, p_data, bytes); 261 if (ret) 262 return ret; 263 write_vreg(vgpu, off, p_data, bytes); 264 265 mmio_hw_access_pre(dev_priv); 266 intel_vgpu_write_fence(vgpu, fence_num, 267 vgpu_vreg64(vgpu, fence_num_to_offset(fence_num))); 268 mmio_hw_access_post(dev_priv); 269 return 0; 270 } 271 272 #define CALC_MODE_MASK_REG(old, new) \ 273 (((new) & GENMASK(31, 16)) \ 274 | ((((old) & GENMASK(15, 0)) & ~((new) >> 16)) \ 275 | ((new) & ((new) >> 16)))) 276 277 static int mul_force_wake_write(struct intel_vgpu *vgpu, 278 unsigned int offset, void *p_data, unsigned int bytes) 279 { 280 u32 old, new; 281 u32 ack_reg_offset; 282 283 old = vgpu_vreg(vgpu, offset); 284 new = CALC_MODE_MASK_REG(old, *(u32 *)p_data); 285 286 if (INTEL_GEN(vgpu->gvt->dev_priv) >= 9) { 287 switch (offset) { 288 case FORCEWAKE_RENDER_GEN9_REG: 289 ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG; 290 break; 291 case FORCEWAKE_BLITTER_GEN9_REG: 292 ack_reg_offset = FORCEWAKE_ACK_BLITTER_GEN9_REG; 293 break; 294 case FORCEWAKE_MEDIA_GEN9_REG: 295 ack_reg_offset = FORCEWAKE_ACK_MEDIA_GEN9_REG; 296 break; 297 default: 298 /*should not hit here*/ 299 gvt_vgpu_err("invalid forcewake offset 0x%x\n", offset); 300 return -EINVAL; 301 } 302 } else { 303 ack_reg_offset = FORCEWAKE_ACK_HSW_REG; 304 } 305 306 vgpu_vreg(vgpu, offset) = new; 307 vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0)); 308 return 0; 309 } 310 311 static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 312 void *p_data, unsigned int bytes) 313 { 314 intel_engine_mask_t engine_mask = 0; 315 u32 data; 316 317 write_vreg(vgpu, offset, p_data, bytes); 318 data = vgpu_vreg(vgpu, offset); 319 320 if (data & GEN6_GRDOM_FULL) { 321 gvt_dbg_mmio("vgpu%d: request full GPU reset\n", vgpu->id); 322 engine_mask = ALL_ENGINES; 323 } else { 324 if (data & GEN6_GRDOM_RENDER) { 325 gvt_dbg_mmio("vgpu%d: request RCS reset\n", vgpu->id); 326 engine_mask |= BIT(RCS0); 327 } 328 if (data & GEN6_GRDOM_MEDIA) { 329 gvt_dbg_mmio("vgpu%d: request VCS reset\n", vgpu->id); 330 engine_mask |= BIT(VCS0); 331 } 332 if (data & GEN6_GRDOM_BLT) { 333 gvt_dbg_mmio("vgpu%d: request BCS Reset\n", vgpu->id); 334 engine_mask |= BIT(BCS0); 335 } 336 if (data & GEN6_GRDOM_VECS) { 337 gvt_dbg_mmio("vgpu%d: request VECS Reset\n", vgpu->id); 338 engine_mask |= BIT(VECS0); 339 } 340 if (data & GEN8_GRDOM_MEDIA2) { 341 gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id); 342 engine_mask |= BIT(VCS1); 343 } 344 engine_mask &= INTEL_INFO(vgpu->gvt->dev_priv)->engine_mask; 345 } 346 347 /* vgpu_lock already hold by emulate mmio r/w */ 348 intel_gvt_reset_vgpu_locked(vgpu, false, engine_mask); 349 350 /* sw will wait for the device to ack the reset request */ 351 vgpu_vreg(vgpu, offset) = 0; 352 353 return 0; 354 } 355 356 static int gmbus_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 357 void *p_data, unsigned int bytes) 358 { 359 return intel_gvt_i2c_handle_gmbus_read(vgpu, offset, p_data, bytes); 360 } 361 362 static int gmbus_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 363 void *p_data, unsigned int bytes) 364 { 365 return intel_gvt_i2c_handle_gmbus_write(vgpu, offset, p_data, bytes); 366 } 367 368 static int pch_pp_control_mmio_write(struct intel_vgpu *vgpu, 369 unsigned int offset, void *p_data, unsigned int bytes) 370 { 371 write_vreg(vgpu, offset, p_data, bytes); 372 373 if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) { 374 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_ON; 375 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE; 376 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN; 377 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE; 378 379 } else 380 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= 381 ~(PP_ON | PP_SEQUENCE_POWER_DOWN 382 | PP_CYCLE_DELAY_ACTIVE); 383 return 0; 384 } 385 386 static int transconf_mmio_write(struct intel_vgpu *vgpu, 387 unsigned int offset, void *p_data, unsigned int bytes) 388 { 389 write_vreg(vgpu, offset, p_data, bytes); 390 391 if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE) 392 vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE; 393 else 394 vgpu_vreg(vgpu, offset) &= ~TRANS_STATE_ENABLE; 395 return 0; 396 } 397 398 static int lcpll_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 399 void *p_data, unsigned int bytes) 400 { 401 write_vreg(vgpu, offset, p_data, bytes); 402 403 if (vgpu_vreg(vgpu, offset) & LCPLL_PLL_DISABLE) 404 vgpu_vreg(vgpu, offset) &= ~LCPLL_PLL_LOCK; 405 else 406 vgpu_vreg(vgpu, offset) |= LCPLL_PLL_LOCK; 407 408 if (vgpu_vreg(vgpu, offset) & LCPLL_CD_SOURCE_FCLK) 409 vgpu_vreg(vgpu, offset) |= LCPLL_CD_SOURCE_FCLK_DONE; 410 else 411 vgpu_vreg(vgpu, offset) &= ~LCPLL_CD_SOURCE_FCLK_DONE; 412 413 return 0; 414 } 415 416 static int dpy_reg_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 417 void *p_data, unsigned int bytes) 418 { 419 switch (offset) { 420 case 0xe651c: 421 case 0xe661c: 422 case 0xe671c: 423 case 0xe681c: 424 vgpu_vreg(vgpu, offset) = 1 << 17; 425 break; 426 case 0xe6c04: 427 vgpu_vreg(vgpu, offset) = 0x3; 428 break; 429 case 0xe6e1c: 430 vgpu_vreg(vgpu, offset) = 0x2f << 16; 431 break; 432 default: 433 return -EINVAL; 434 } 435 436 read_vreg(vgpu, offset, p_data, bytes); 437 return 0; 438 } 439 440 static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 441 void *p_data, unsigned int bytes) 442 { 443 u32 data; 444 445 write_vreg(vgpu, offset, p_data, bytes); 446 data = vgpu_vreg(vgpu, offset); 447 448 if (data & PIPECONF_ENABLE) 449 vgpu_vreg(vgpu, offset) |= I965_PIPECONF_ACTIVE; 450 else 451 vgpu_vreg(vgpu, offset) &= ~I965_PIPECONF_ACTIVE; 452 /* vgpu_lock already hold by emulate mmio r/w */ 453 mutex_unlock(&vgpu->vgpu_lock); 454 intel_gvt_check_vblank_emulation(vgpu->gvt); 455 mutex_lock(&vgpu->vgpu_lock); 456 return 0; 457 } 458 459 /* ascendingly sorted */ 460 static i915_reg_t force_nonpriv_white_list[] = { 461 GEN9_CS_DEBUG_MODE1, //_MMIO(0x20ec) 462 GEN9_CTX_PREEMPT_REG,//_MMIO(0x2248) 463 GEN8_CS_CHICKEN1,//_MMIO(0x2580) 464 _MMIO(0x2690), 465 _MMIO(0x2694), 466 _MMIO(0x2698), 467 _MMIO(0x2754), 468 _MMIO(0x28a0), 469 _MMIO(0x4de0), 470 _MMIO(0x4de4), 471 _MMIO(0x4dfc), 472 GEN7_COMMON_SLICE_CHICKEN1,//_MMIO(0x7010) 473 _MMIO(0x7014), 474 HDC_CHICKEN0,//_MMIO(0x7300) 475 GEN8_HDC_CHICKEN1,//_MMIO(0x7304) 476 _MMIO(0x7700), 477 _MMIO(0x7704), 478 _MMIO(0x7708), 479 _MMIO(0x770c), 480 _MMIO(0x83a8), 481 _MMIO(0xb110), 482 GEN8_L3SQCREG4,//_MMIO(0xb118) 483 _MMIO(0xe100), 484 _MMIO(0xe18c), 485 _MMIO(0xe48c), 486 _MMIO(0xe5f4), 487 }; 488 489 /* a simple bsearch */ 490 static inline bool in_whitelist(unsigned int reg) 491 { 492 int left = 0, right = ARRAY_SIZE(force_nonpriv_white_list); 493 i915_reg_t *array = force_nonpriv_white_list; 494 495 while (left < right) { 496 int mid = (left + right)/2; 497 498 if (reg > array[mid].reg) 499 left = mid + 1; 500 else if (reg < array[mid].reg) 501 right = mid; 502 else 503 return true; 504 } 505 return false; 506 } 507 508 static int force_nonpriv_write(struct intel_vgpu *vgpu, 509 unsigned int offset, void *p_data, unsigned int bytes) 510 { 511 u32 reg_nonpriv = *(u32 *)p_data; 512 int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset); 513 u32 ring_base; 514 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 515 int ret = -EINVAL; 516 517 if ((bytes != 4) || ((offset & (bytes - 1)) != 0) || ring_id < 0) { 518 gvt_err("vgpu(%d) ring %d Invalid FORCE_NONPRIV offset %x(%dB)\n", 519 vgpu->id, ring_id, offset, bytes); 520 return ret; 521 } 522 523 ring_base = dev_priv->engine[ring_id]->mmio_base; 524 525 if (in_whitelist(reg_nonpriv) || 526 reg_nonpriv == i915_mmio_reg_offset(RING_NOPID(ring_base))) { 527 ret = intel_vgpu_default_mmio_write(vgpu, offset, p_data, 528 bytes); 529 } else 530 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x at offset %x\n", 531 vgpu->id, reg_nonpriv, offset); 532 533 return 0; 534 } 535 536 static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 537 void *p_data, unsigned int bytes) 538 { 539 write_vreg(vgpu, offset, p_data, bytes); 540 541 if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) { 542 vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE; 543 } else { 544 vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE; 545 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E))) 546 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) 547 &= ~DP_TP_STATUS_AUTOTRAIN_DONE; 548 } 549 return 0; 550 } 551 552 static int fdi_rx_iir_mmio_write(struct intel_vgpu *vgpu, 553 unsigned int offset, void *p_data, unsigned int bytes) 554 { 555 vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data; 556 return 0; 557 } 558 559 #define FDI_LINK_TRAIN_PATTERN1 0 560 #define FDI_LINK_TRAIN_PATTERN2 1 561 562 static int fdi_auto_training_started(struct intel_vgpu *vgpu) 563 { 564 u32 ddi_buf_ctl = vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_E)); 565 u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL); 566 u32 tx_ctl = vgpu_vreg_t(vgpu, DP_TP_CTL(PORT_E)); 567 568 if ((ddi_buf_ctl & DDI_BUF_CTL_ENABLE) && 569 (rx_ctl & FDI_RX_ENABLE) && 570 (rx_ctl & FDI_AUTO_TRAINING) && 571 (tx_ctl & DP_TP_CTL_ENABLE) && 572 (tx_ctl & DP_TP_CTL_FDI_AUTOTRAIN)) 573 return 1; 574 else 575 return 0; 576 } 577 578 static int check_fdi_rx_train_status(struct intel_vgpu *vgpu, 579 enum pipe pipe, unsigned int train_pattern) 580 { 581 i915_reg_t fdi_rx_imr, fdi_tx_ctl, fdi_rx_ctl; 582 unsigned int fdi_rx_check_bits, fdi_tx_check_bits; 583 unsigned int fdi_rx_train_bits, fdi_tx_train_bits; 584 unsigned int fdi_iir_check_bits; 585 586 fdi_rx_imr = FDI_RX_IMR(pipe); 587 fdi_tx_ctl = FDI_TX_CTL(pipe); 588 fdi_rx_ctl = FDI_RX_CTL(pipe); 589 590 if (train_pattern == FDI_LINK_TRAIN_PATTERN1) { 591 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_1_CPT; 592 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_1; 593 fdi_iir_check_bits = FDI_RX_BIT_LOCK; 594 } else if (train_pattern == FDI_LINK_TRAIN_PATTERN2) { 595 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_2_CPT; 596 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_2; 597 fdi_iir_check_bits = FDI_RX_SYMBOL_LOCK; 598 } else { 599 gvt_vgpu_err("Invalid train pattern %d\n", train_pattern); 600 return -EINVAL; 601 } 602 603 fdi_rx_check_bits = FDI_RX_ENABLE | fdi_rx_train_bits; 604 fdi_tx_check_bits = FDI_TX_ENABLE | fdi_tx_train_bits; 605 606 /* If imr bit has been masked */ 607 if (vgpu_vreg_t(vgpu, fdi_rx_imr) & fdi_iir_check_bits) 608 return 0; 609 610 if (((vgpu_vreg_t(vgpu, fdi_tx_ctl) & fdi_tx_check_bits) 611 == fdi_tx_check_bits) 612 && ((vgpu_vreg_t(vgpu, fdi_rx_ctl) & fdi_rx_check_bits) 613 == fdi_rx_check_bits)) 614 return 1; 615 else 616 return 0; 617 } 618 619 #define INVALID_INDEX (~0U) 620 621 static unsigned int calc_index(unsigned int offset, unsigned int start, 622 unsigned int next, unsigned int end, i915_reg_t i915_end) 623 { 624 unsigned int range = next - start; 625 626 if (!end) 627 end = i915_mmio_reg_offset(i915_end); 628 if (offset < start || offset > end) 629 return INVALID_INDEX; 630 offset -= start; 631 return offset / range; 632 } 633 634 #define FDI_RX_CTL_TO_PIPE(offset) \ 635 calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, 0, FDI_RX_CTL(PIPE_C)) 636 637 #define FDI_TX_CTL_TO_PIPE(offset) \ 638 calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, 0, FDI_TX_CTL(PIPE_C)) 639 640 #define FDI_RX_IMR_TO_PIPE(offset) \ 641 calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, 0, FDI_RX_IMR(PIPE_C)) 642 643 static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu, 644 unsigned int offset, void *p_data, unsigned int bytes) 645 { 646 i915_reg_t fdi_rx_iir; 647 unsigned int index; 648 int ret; 649 650 if (FDI_RX_CTL_TO_PIPE(offset) != INVALID_INDEX) 651 index = FDI_RX_CTL_TO_PIPE(offset); 652 else if (FDI_TX_CTL_TO_PIPE(offset) != INVALID_INDEX) 653 index = FDI_TX_CTL_TO_PIPE(offset); 654 else if (FDI_RX_IMR_TO_PIPE(offset) != INVALID_INDEX) 655 index = FDI_RX_IMR_TO_PIPE(offset); 656 else { 657 gvt_vgpu_err("Unsupport registers %x\n", offset); 658 return -EINVAL; 659 } 660 661 write_vreg(vgpu, offset, p_data, bytes); 662 663 fdi_rx_iir = FDI_RX_IIR(index); 664 665 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN1); 666 if (ret < 0) 667 return ret; 668 if (ret) 669 vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK; 670 671 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN2); 672 if (ret < 0) 673 return ret; 674 if (ret) 675 vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK; 676 677 if (offset == _FDI_RXA_CTL) 678 if (fdi_auto_training_started(vgpu)) 679 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) |= 680 DP_TP_STATUS_AUTOTRAIN_DONE; 681 return 0; 682 } 683 684 #define DP_TP_CTL_TO_PORT(offset) \ 685 calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, 0, DP_TP_CTL(PORT_E)) 686 687 static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 688 void *p_data, unsigned int bytes) 689 { 690 i915_reg_t status_reg; 691 unsigned int index; 692 u32 data; 693 694 write_vreg(vgpu, offset, p_data, bytes); 695 696 index = DP_TP_CTL_TO_PORT(offset); 697 data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8; 698 if (data == 0x2) { 699 status_reg = DP_TP_STATUS(index); 700 vgpu_vreg_t(vgpu, status_reg) |= (1 << 25); 701 } 702 return 0; 703 } 704 705 static int dp_tp_status_mmio_write(struct intel_vgpu *vgpu, 706 unsigned int offset, void *p_data, unsigned int bytes) 707 { 708 u32 reg_val; 709 u32 sticky_mask; 710 711 reg_val = *((u32 *)p_data); 712 sticky_mask = GENMASK(27, 26) | (1 << 24); 713 714 vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) | 715 (vgpu_vreg(vgpu, offset) & sticky_mask); 716 vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask); 717 return 0; 718 } 719 720 static int pch_adpa_mmio_write(struct intel_vgpu *vgpu, 721 unsigned int offset, void *p_data, unsigned int bytes) 722 { 723 u32 data; 724 725 write_vreg(vgpu, offset, p_data, bytes); 726 data = vgpu_vreg(vgpu, offset); 727 728 if (data & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) 729 vgpu_vreg(vgpu, offset) &= ~ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 730 return 0; 731 } 732 733 static int south_chicken2_mmio_write(struct intel_vgpu *vgpu, 734 unsigned int offset, void *p_data, unsigned int bytes) 735 { 736 u32 data; 737 738 write_vreg(vgpu, offset, p_data, bytes); 739 data = vgpu_vreg(vgpu, offset); 740 741 if (data & FDI_MPHY_IOSFSB_RESET_CTL) 742 vgpu_vreg(vgpu, offset) |= FDI_MPHY_IOSFSB_RESET_STATUS; 743 else 744 vgpu_vreg(vgpu, offset) &= ~FDI_MPHY_IOSFSB_RESET_STATUS; 745 return 0; 746 } 747 748 #define DSPSURF_TO_PIPE(offset) \ 749 calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C)) 750 751 static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 752 void *p_data, unsigned int bytes) 753 { 754 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 755 u32 pipe = DSPSURF_TO_PIPE(offset); 756 int event = SKL_FLIP_EVENT(pipe, PLANE_PRIMARY); 757 758 write_vreg(vgpu, offset, p_data, bytes); 759 vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); 760 761 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++; 762 763 if (vgpu_vreg_t(vgpu, DSPCNTR(pipe)) & PLANE_CTL_ASYNC_FLIP) 764 intel_vgpu_trigger_virtual_event(vgpu, event); 765 else 766 set_bit(event, vgpu->irq.flip_done_event[pipe]); 767 768 return 0; 769 } 770 771 #define SPRSURF_TO_PIPE(offset) \ 772 calc_index(offset, _SPRA_SURF, _SPRB_SURF, 0, SPRSURF(PIPE_C)) 773 774 static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 775 void *p_data, unsigned int bytes) 776 { 777 u32 pipe = SPRSURF_TO_PIPE(offset); 778 int event = SKL_FLIP_EVENT(pipe, PLANE_SPRITE0); 779 780 write_vreg(vgpu, offset, p_data, bytes); 781 vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); 782 783 if (vgpu_vreg_t(vgpu, SPRCTL(pipe)) & PLANE_CTL_ASYNC_FLIP) 784 intel_vgpu_trigger_virtual_event(vgpu, event); 785 else 786 set_bit(event, vgpu->irq.flip_done_event[pipe]); 787 788 return 0; 789 } 790 791 static int reg50080_mmio_write(struct intel_vgpu *vgpu, 792 unsigned int offset, void *p_data, 793 unsigned int bytes) 794 { 795 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 796 enum pipe pipe = REG_50080_TO_PIPE(offset); 797 enum plane_id plane = REG_50080_TO_PLANE(offset); 798 int event = SKL_FLIP_EVENT(pipe, plane); 799 800 write_vreg(vgpu, offset, p_data, bytes); 801 if (plane == PLANE_PRIMARY) { 802 vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); 803 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++; 804 } else { 805 vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); 806 } 807 808 if ((vgpu_vreg(vgpu, offset) & REG50080_FLIP_TYPE_MASK) == REG50080_FLIP_TYPE_ASYNC) 809 intel_vgpu_trigger_virtual_event(vgpu, event); 810 else 811 set_bit(event, vgpu->irq.flip_done_event[pipe]); 812 813 return 0; 814 } 815 816 static int trigger_aux_channel_interrupt(struct intel_vgpu *vgpu, 817 unsigned int reg) 818 { 819 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 820 enum intel_gvt_event_type event; 821 822 if (reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_A))) 823 event = AUX_CHANNEL_A; 824 else if (reg == _PCH_DPB_AUX_CH_CTL || 825 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_B))) 826 event = AUX_CHANNEL_B; 827 else if (reg == _PCH_DPC_AUX_CH_CTL || 828 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_C))) 829 event = AUX_CHANNEL_C; 830 else if (reg == _PCH_DPD_AUX_CH_CTL || 831 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_D))) 832 event = AUX_CHANNEL_D; 833 else { 834 WARN_ON(true); 835 return -EINVAL; 836 } 837 838 intel_vgpu_trigger_virtual_event(vgpu, event); 839 return 0; 840 } 841 842 static int dp_aux_ch_ctl_trans_done(struct intel_vgpu *vgpu, u32 value, 843 unsigned int reg, int len, bool data_valid) 844 { 845 /* mark transaction done */ 846 value |= DP_AUX_CH_CTL_DONE; 847 value &= ~DP_AUX_CH_CTL_SEND_BUSY; 848 value &= ~DP_AUX_CH_CTL_RECEIVE_ERROR; 849 850 if (data_valid) 851 value &= ~DP_AUX_CH_CTL_TIME_OUT_ERROR; 852 else 853 value |= DP_AUX_CH_CTL_TIME_OUT_ERROR; 854 855 /* message size */ 856 value &= ~(0xf << 20); 857 value |= (len << 20); 858 vgpu_vreg(vgpu, reg) = value; 859 860 if (value & DP_AUX_CH_CTL_INTERRUPT) 861 return trigger_aux_channel_interrupt(vgpu, reg); 862 return 0; 863 } 864 865 static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd, 866 u8 t) 867 { 868 if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == DPCD_TRAINING_PATTERN_1) { 869 /* training pattern 1 for CR */ 870 /* set LANE0_CR_DONE, LANE1_CR_DONE */ 871 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_CR_DONE; 872 /* set LANE2_CR_DONE, LANE3_CR_DONE */ 873 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_CR_DONE; 874 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == 875 DPCD_TRAINING_PATTERN_2) { 876 /* training pattern 2 for EQ */ 877 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane0_1 */ 878 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_EQ_DONE; 879 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_SYMBOL_LOCKED; 880 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane2_3 */ 881 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_EQ_DONE; 882 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_SYMBOL_LOCKED; 883 /* set INTERLANE_ALIGN_DONE */ 884 dpcd->data[DPCD_LANE_ALIGN_STATUS_UPDATED] |= 885 DPCD_INTERLANE_ALIGN_DONE; 886 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == 887 DPCD_LINK_TRAINING_DISABLED) { 888 /* finish link training */ 889 /* set sink status as synchronized */ 890 dpcd->data[DPCD_SINK_STATUS] = DPCD_SINK_IN_SYNC; 891 } 892 } 893 894 #define _REG_HSW_DP_AUX_CH_CTL(dp) \ 895 ((dp) ? (_PCH_DPB_AUX_CH_CTL + ((dp)-1)*0x100) : 0x64010) 896 897 #define _REG_SKL_DP_AUX_CH_CTL(dp) (0x64010 + (dp) * 0x100) 898 899 #define OFFSET_TO_DP_AUX_PORT(offset) (((offset) & 0xF00) >> 8) 900 901 #define dpy_is_valid_port(port) \ 902 (((port) >= PORT_A) && ((port) < I915_MAX_PORTS)) 903 904 static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu, 905 unsigned int offset, void *p_data, unsigned int bytes) 906 { 907 struct intel_vgpu_display *display = &vgpu->display; 908 int msg, addr, ctrl, op, len; 909 int port_index = OFFSET_TO_DP_AUX_PORT(offset); 910 struct intel_vgpu_dpcd_data *dpcd = NULL; 911 struct intel_vgpu_port *port = NULL; 912 u32 data; 913 914 if (!dpy_is_valid_port(port_index)) { 915 gvt_vgpu_err("Unsupported DP port access!\n"); 916 return 0; 917 } 918 919 write_vreg(vgpu, offset, p_data, bytes); 920 data = vgpu_vreg(vgpu, offset); 921 922 if ((INTEL_GEN(vgpu->gvt->dev_priv) >= 9) 923 && offset != _REG_SKL_DP_AUX_CH_CTL(port_index)) { 924 /* SKL DPB/C/D aux ctl register changed */ 925 return 0; 926 } else if (IS_BROADWELL(vgpu->gvt->dev_priv) && 927 offset != _REG_HSW_DP_AUX_CH_CTL(port_index)) { 928 /* write to the data registers */ 929 return 0; 930 } 931 932 if (!(data & DP_AUX_CH_CTL_SEND_BUSY)) { 933 /* just want to clear the sticky bits */ 934 vgpu_vreg(vgpu, offset) = 0; 935 return 0; 936 } 937 938 port = &display->ports[port_index]; 939 dpcd = port->dpcd; 940 941 /* read out message from DATA1 register */ 942 msg = vgpu_vreg(vgpu, offset + 4); 943 addr = (msg >> 8) & 0xffff; 944 ctrl = (msg >> 24) & 0xff; 945 len = msg & 0xff; 946 op = ctrl >> 4; 947 948 if (op == GVT_AUX_NATIVE_WRITE) { 949 int t; 950 u8 buf[16]; 951 952 if ((addr + len + 1) >= DPCD_SIZE) { 953 /* 954 * Write request exceeds what we supported, 955 * DCPD spec: When a Source Device is writing a DPCD 956 * address not supported by the Sink Device, the Sink 957 * Device shall reply with AUX NACK and “M” equal to 958 * zero. 959 */ 960 961 /* NAK the write */ 962 vgpu_vreg(vgpu, offset + 4) = AUX_NATIVE_REPLY_NAK; 963 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 2, true); 964 return 0; 965 } 966 967 /* 968 * Write request format: Headr (command + address + size) occupies 969 * 4 bytes, followed by (len + 1) bytes of data. See details at 970 * intel_dp_aux_transfer(). 971 */ 972 if ((len + 1 + 4) > AUX_BURST_SIZE) { 973 gvt_vgpu_err("dp_aux_header: len %d is too large\n", len); 974 return -EINVAL; 975 } 976 977 /* unpack data from vreg to buf */ 978 for (t = 0; t < 4; t++) { 979 u32 r = vgpu_vreg(vgpu, offset + 8 + t * 4); 980 981 buf[t * 4] = (r >> 24) & 0xff; 982 buf[t * 4 + 1] = (r >> 16) & 0xff; 983 buf[t * 4 + 2] = (r >> 8) & 0xff; 984 buf[t * 4 + 3] = r & 0xff; 985 } 986 987 /* write to virtual DPCD */ 988 if (dpcd && dpcd->data_valid) { 989 for (t = 0; t <= len; t++) { 990 int p = addr + t; 991 992 dpcd->data[p] = buf[t]; 993 /* check for link training */ 994 if (p == DPCD_TRAINING_PATTERN_SET) 995 dp_aux_ch_ctl_link_training(dpcd, 996 buf[t]); 997 } 998 } 999 1000 /* ACK the write */ 1001 vgpu_vreg(vgpu, offset + 4) = 0; 1002 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 1, 1003 dpcd && dpcd->data_valid); 1004 return 0; 1005 } 1006 1007 if (op == GVT_AUX_NATIVE_READ) { 1008 int idx, i, ret = 0; 1009 1010 if ((addr + len + 1) >= DPCD_SIZE) { 1011 /* 1012 * read request exceeds what we supported 1013 * DPCD spec: A Sink Device receiving a Native AUX CH 1014 * read request for an unsupported DPCD address must 1015 * reply with an AUX ACK and read data set equal to 1016 * zero instead of replying with AUX NACK. 1017 */ 1018 1019 /* ACK the READ*/ 1020 vgpu_vreg(vgpu, offset + 4) = 0; 1021 vgpu_vreg(vgpu, offset + 8) = 0; 1022 vgpu_vreg(vgpu, offset + 12) = 0; 1023 vgpu_vreg(vgpu, offset + 16) = 0; 1024 vgpu_vreg(vgpu, offset + 20) = 0; 1025 1026 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2, 1027 true); 1028 return 0; 1029 } 1030 1031 for (idx = 1; idx <= 5; idx++) { 1032 /* clear the data registers */ 1033 vgpu_vreg(vgpu, offset + 4 * idx) = 0; 1034 } 1035 1036 /* 1037 * Read reply format: ACK (1 byte) plus (len + 1) bytes of data. 1038 */ 1039 if ((len + 2) > AUX_BURST_SIZE) { 1040 gvt_vgpu_err("dp_aux_header: len %d is too large\n", len); 1041 return -EINVAL; 1042 } 1043 1044 /* read from virtual DPCD to vreg */ 1045 /* first 4 bytes: [ACK][addr][addr+1][addr+2] */ 1046 if (dpcd && dpcd->data_valid) { 1047 for (i = 1; i <= (len + 1); i++) { 1048 int t; 1049 1050 t = dpcd->data[addr + i - 1]; 1051 t <<= (24 - 8 * (i % 4)); 1052 ret |= t; 1053 1054 if ((i % 4 == 3) || (i == (len + 1))) { 1055 vgpu_vreg(vgpu, offset + 1056 (i / 4 + 1) * 4) = ret; 1057 ret = 0; 1058 } 1059 } 1060 } 1061 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2, 1062 dpcd && dpcd->data_valid); 1063 return 0; 1064 } 1065 1066 /* i2c transaction starts */ 1067 intel_gvt_i2c_handle_aux_ch_write(vgpu, port_index, offset, p_data); 1068 1069 if (data & DP_AUX_CH_CTL_INTERRUPT) 1070 trigger_aux_channel_interrupt(vgpu, offset); 1071 return 0; 1072 } 1073 1074 static int mbctl_write(struct intel_vgpu *vgpu, unsigned int offset, 1075 void *p_data, unsigned int bytes) 1076 { 1077 *(u32 *)p_data &= (~GEN6_MBCTL_ENABLE_BOOT_FETCH); 1078 write_vreg(vgpu, offset, p_data, bytes); 1079 return 0; 1080 } 1081 1082 static int vga_control_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1083 void *p_data, unsigned int bytes) 1084 { 1085 bool vga_disable; 1086 1087 write_vreg(vgpu, offset, p_data, bytes); 1088 vga_disable = vgpu_vreg(vgpu, offset) & VGA_DISP_DISABLE; 1089 1090 gvt_dbg_core("vgpu%d: %s VGA mode\n", vgpu->id, 1091 vga_disable ? "Disable" : "Enable"); 1092 return 0; 1093 } 1094 1095 static u32 read_virtual_sbi_register(struct intel_vgpu *vgpu, 1096 unsigned int sbi_offset) 1097 { 1098 struct intel_vgpu_display *display = &vgpu->display; 1099 int num = display->sbi.number; 1100 int i; 1101 1102 for (i = 0; i < num; ++i) 1103 if (display->sbi.registers[i].offset == sbi_offset) 1104 break; 1105 1106 if (i == num) 1107 return 0; 1108 1109 return display->sbi.registers[i].value; 1110 } 1111 1112 static void write_virtual_sbi_register(struct intel_vgpu *vgpu, 1113 unsigned int offset, u32 value) 1114 { 1115 struct intel_vgpu_display *display = &vgpu->display; 1116 int num = display->sbi.number; 1117 int i; 1118 1119 for (i = 0; i < num; ++i) { 1120 if (display->sbi.registers[i].offset == offset) 1121 break; 1122 } 1123 1124 if (i == num) { 1125 if (num == SBI_REG_MAX) { 1126 gvt_vgpu_err("SBI caching meets maximum limits\n"); 1127 return; 1128 } 1129 display->sbi.number++; 1130 } 1131 1132 display->sbi.registers[i].offset = offset; 1133 display->sbi.registers[i].value = value; 1134 } 1135 1136 static int sbi_data_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 1137 void *p_data, unsigned int bytes) 1138 { 1139 if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> 1140 SBI_OPCODE_SHIFT) == SBI_CMD_CRRD) { 1141 unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) & 1142 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; 1143 vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu, 1144 sbi_offset); 1145 } 1146 read_vreg(vgpu, offset, p_data, bytes); 1147 return 0; 1148 } 1149 1150 static int sbi_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1151 void *p_data, unsigned int bytes) 1152 { 1153 u32 data; 1154 1155 write_vreg(vgpu, offset, p_data, bytes); 1156 data = vgpu_vreg(vgpu, offset); 1157 1158 data &= ~(SBI_STAT_MASK << SBI_STAT_SHIFT); 1159 data |= SBI_READY; 1160 1161 data &= ~(SBI_RESPONSE_MASK << SBI_RESPONSE_SHIFT); 1162 data |= SBI_RESPONSE_SUCCESS; 1163 1164 vgpu_vreg(vgpu, offset) = data; 1165 1166 if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> 1167 SBI_OPCODE_SHIFT) == SBI_CMD_CRWR) { 1168 unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) & 1169 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; 1170 1171 write_virtual_sbi_register(vgpu, sbi_offset, 1172 vgpu_vreg_t(vgpu, SBI_DATA)); 1173 } 1174 return 0; 1175 } 1176 1177 #define _vgtif_reg(x) \ 1178 (VGT_PVINFO_PAGE + offsetof(struct vgt_if, x)) 1179 1180 static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 1181 void *p_data, unsigned int bytes) 1182 { 1183 bool invalid_read = false; 1184 1185 read_vreg(vgpu, offset, p_data, bytes); 1186 1187 switch (offset) { 1188 case _vgtif_reg(magic) ... _vgtif_reg(vgt_id): 1189 if (offset + bytes > _vgtif_reg(vgt_id) + 4) 1190 invalid_read = true; 1191 break; 1192 case _vgtif_reg(avail_rs.mappable_gmadr.base) ... 1193 _vgtif_reg(avail_rs.fence_num): 1194 if (offset + bytes > 1195 _vgtif_reg(avail_rs.fence_num) + 4) 1196 invalid_read = true; 1197 break; 1198 case 0x78010: /* vgt_caps */ 1199 case 0x7881c: 1200 break; 1201 default: 1202 invalid_read = true; 1203 break; 1204 } 1205 if (invalid_read) 1206 gvt_vgpu_err("invalid pvinfo read: [%x:%x] = %x\n", 1207 offset, bytes, *(u32 *)p_data); 1208 vgpu->pv_notified = true; 1209 return 0; 1210 } 1211 1212 static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification) 1213 { 1214 enum intel_gvt_gtt_type root_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY; 1215 struct intel_vgpu_mm *mm; 1216 u64 *pdps; 1217 1218 pdps = (u64 *)&vgpu_vreg64_t(vgpu, vgtif_reg(pdp[0])); 1219 1220 switch (notification) { 1221 case VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE: 1222 root_entry_type = GTT_TYPE_PPGTT_ROOT_L3_ENTRY; 1223 /* fall through */ 1224 case VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE: 1225 mm = intel_vgpu_get_ppgtt_mm(vgpu, root_entry_type, pdps); 1226 return PTR_ERR_OR_ZERO(mm); 1227 case VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY: 1228 case VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY: 1229 return intel_vgpu_put_ppgtt_mm(vgpu, pdps); 1230 case VGT_G2V_EXECLIST_CONTEXT_CREATE: 1231 case VGT_G2V_EXECLIST_CONTEXT_DESTROY: 1232 case 1: /* Remove this in guest driver. */ 1233 break; 1234 default: 1235 gvt_vgpu_err("Invalid PV notification %d\n", notification); 1236 } 1237 return 0; 1238 } 1239 1240 static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready) 1241 { 1242 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1243 struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj; 1244 char *env[3] = {NULL, NULL, NULL}; 1245 char vmid_str[20]; 1246 char display_ready_str[20]; 1247 1248 snprintf(display_ready_str, 20, "GVT_DISPLAY_READY=%d", ready); 1249 env[0] = display_ready_str; 1250 1251 snprintf(vmid_str, 20, "VMID=%d", vgpu->id); 1252 env[1] = vmid_str; 1253 1254 return kobject_uevent_env(kobj, KOBJ_ADD, env); 1255 } 1256 1257 static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1258 void *p_data, unsigned int bytes) 1259 { 1260 u32 data = *(u32 *)p_data; 1261 bool invalid_write = false; 1262 1263 switch (offset) { 1264 case _vgtif_reg(display_ready): 1265 send_display_ready_uevent(vgpu, data ? 1 : 0); 1266 break; 1267 case _vgtif_reg(g2v_notify): 1268 handle_g2v_notification(vgpu, data); 1269 break; 1270 /* add xhot and yhot to handled list to avoid error log */ 1271 case _vgtif_reg(cursor_x_hot): 1272 case _vgtif_reg(cursor_y_hot): 1273 case _vgtif_reg(pdp[0].lo): 1274 case _vgtif_reg(pdp[0].hi): 1275 case _vgtif_reg(pdp[1].lo): 1276 case _vgtif_reg(pdp[1].hi): 1277 case _vgtif_reg(pdp[2].lo): 1278 case _vgtif_reg(pdp[2].hi): 1279 case _vgtif_reg(pdp[3].lo): 1280 case _vgtif_reg(pdp[3].hi): 1281 case _vgtif_reg(execlist_context_descriptor_lo): 1282 case _vgtif_reg(execlist_context_descriptor_hi): 1283 break; 1284 case _vgtif_reg(rsv5[0])..._vgtif_reg(rsv5[3]): 1285 invalid_write = true; 1286 enter_failsafe_mode(vgpu, GVT_FAILSAFE_INSUFFICIENT_RESOURCE); 1287 break; 1288 default: 1289 invalid_write = true; 1290 gvt_vgpu_err("invalid pvinfo write offset %x bytes %x data %x\n", 1291 offset, bytes, data); 1292 break; 1293 } 1294 1295 if (!invalid_write) 1296 write_vreg(vgpu, offset, p_data, bytes); 1297 1298 return 0; 1299 } 1300 1301 static int pf_write(struct intel_vgpu *vgpu, 1302 unsigned int offset, void *p_data, unsigned int bytes) 1303 { 1304 u32 val = *(u32 *)p_data; 1305 1306 if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL || 1307 offset == _PS_1B_CTRL || offset == _PS_2B_CTRL || 1308 offset == _PS_1C_CTRL) && (val & PS_PLANE_SEL_MASK) != 0) { 1309 WARN_ONCE(true, "VM(%d): guest is trying to scaling a plane\n", 1310 vgpu->id); 1311 return 0; 1312 } 1313 1314 return intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes); 1315 } 1316 1317 static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu, 1318 unsigned int offset, void *p_data, unsigned int bytes) 1319 { 1320 write_vreg(vgpu, offset, p_data, bytes); 1321 1322 if (vgpu_vreg(vgpu, offset) & 1323 HSW_PWR_WELL_CTL_REQ(HSW_PW_CTL_IDX_GLOBAL)) 1324 vgpu_vreg(vgpu, offset) |= 1325 HSW_PWR_WELL_CTL_STATE(HSW_PW_CTL_IDX_GLOBAL); 1326 else 1327 vgpu_vreg(vgpu, offset) &= 1328 ~HSW_PWR_WELL_CTL_STATE(HSW_PW_CTL_IDX_GLOBAL); 1329 return 0; 1330 } 1331 1332 static int gen9_dbuf_ctl_mmio_write(struct intel_vgpu *vgpu, 1333 unsigned int offset, void *p_data, unsigned int bytes) 1334 { 1335 write_vreg(vgpu, offset, p_data, bytes); 1336 1337 if (vgpu_vreg(vgpu, offset) & DBUF_POWER_REQUEST) 1338 vgpu_vreg(vgpu, offset) |= DBUF_POWER_STATE; 1339 else 1340 vgpu_vreg(vgpu, offset) &= ~DBUF_POWER_STATE; 1341 1342 return 0; 1343 } 1344 1345 static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu, 1346 unsigned int offset, void *p_data, unsigned int bytes) 1347 { 1348 write_vreg(vgpu, offset, p_data, bytes); 1349 1350 if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM) 1351 vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM; 1352 return 0; 1353 } 1354 1355 static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset, 1356 void *p_data, unsigned int bytes) 1357 { 1358 u32 mode; 1359 1360 write_vreg(vgpu, offset, p_data, bytes); 1361 mode = vgpu_vreg(vgpu, offset); 1362 1363 if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) { 1364 WARN_ONCE(1, "VM(%d): iGVT-g doesn't support GuC\n", 1365 vgpu->id); 1366 return 0; 1367 } 1368 1369 return 0; 1370 } 1371 1372 static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset, 1373 void *p_data, unsigned int bytes) 1374 { 1375 u32 trtte = *(u32 *)p_data; 1376 1377 if ((trtte & 1) && (trtte & (1 << 1)) == 0) { 1378 WARN(1, "VM(%d): Use physical address for TRTT!\n", 1379 vgpu->id); 1380 return -EINVAL; 1381 } 1382 write_vreg(vgpu, offset, p_data, bytes); 1383 1384 return 0; 1385 } 1386 1387 static int gen9_trtt_chicken_write(struct intel_vgpu *vgpu, unsigned int offset, 1388 void *p_data, unsigned int bytes) 1389 { 1390 write_vreg(vgpu, offset, p_data, bytes); 1391 return 0; 1392 } 1393 1394 static int dpll_status_read(struct intel_vgpu *vgpu, unsigned int offset, 1395 void *p_data, unsigned int bytes) 1396 { 1397 u32 v = 0; 1398 1399 if (vgpu_vreg(vgpu, 0x46010) & (1 << 31)) 1400 v |= (1 << 0); 1401 1402 if (vgpu_vreg(vgpu, 0x46014) & (1 << 31)) 1403 v |= (1 << 8); 1404 1405 if (vgpu_vreg(vgpu, 0x46040) & (1 << 31)) 1406 v |= (1 << 16); 1407 1408 if (vgpu_vreg(vgpu, 0x46060) & (1 << 31)) 1409 v |= (1 << 24); 1410 1411 vgpu_vreg(vgpu, offset) = v; 1412 1413 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1414 } 1415 1416 static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset, 1417 void *p_data, unsigned int bytes) 1418 { 1419 u32 value = *(u32 *)p_data; 1420 u32 cmd = value & 0xff; 1421 u32 *data0 = &vgpu_vreg_t(vgpu, GEN6_PCODE_DATA); 1422 1423 switch (cmd) { 1424 case GEN9_PCODE_READ_MEM_LATENCY: 1425 if (IS_SKYLAKE(vgpu->gvt->dev_priv) 1426 || IS_KABYLAKE(vgpu->gvt->dev_priv) 1427 || IS_COFFEELAKE(vgpu->gvt->dev_priv)) { 1428 /** 1429 * "Read memory latency" command on gen9. 1430 * Below memory latency values are read 1431 * from skylake platform. 1432 */ 1433 if (!*data0) 1434 *data0 = 0x1e1a1100; 1435 else 1436 *data0 = 0x61514b3d; 1437 } else if (IS_BROXTON(vgpu->gvt->dev_priv)) { 1438 /** 1439 * "Read memory latency" command on gen9. 1440 * Below memory latency values are read 1441 * from Broxton MRB. 1442 */ 1443 if (!*data0) 1444 *data0 = 0x16080707; 1445 else 1446 *data0 = 0x16161616; 1447 } 1448 break; 1449 case SKL_PCODE_CDCLK_CONTROL: 1450 if (IS_SKYLAKE(vgpu->gvt->dev_priv) 1451 || IS_KABYLAKE(vgpu->gvt->dev_priv) 1452 || IS_COFFEELAKE(vgpu->gvt->dev_priv)) 1453 *data0 = SKL_CDCLK_READY_FOR_CHANGE; 1454 break; 1455 case GEN6_PCODE_READ_RC6VIDS: 1456 *data0 |= 0x1; 1457 break; 1458 } 1459 1460 gvt_dbg_core("VM(%d) write %x to mailbox, return data0 %x\n", 1461 vgpu->id, value, *data0); 1462 /** 1463 * PCODE_READY clear means ready for pcode read/write, 1464 * PCODE_ERROR_MASK clear means no error happened. In GVT-g we 1465 * always emulate as pcode read/write success and ready for access 1466 * anytime, since we don't touch real physical registers here. 1467 */ 1468 value &= ~(GEN6_PCODE_READY | GEN6_PCODE_ERROR_MASK); 1469 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes); 1470 } 1471 1472 static int hws_pga_write(struct intel_vgpu *vgpu, unsigned int offset, 1473 void *p_data, unsigned int bytes) 1474 { 1475 u32 value = *(u32 *)p_data; 1476 int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset); 1477 1478 if (!intel_gvt_ggtt_validate_range(vgpu, value, I915_GTT_PAGE_SIZE)) { 1479 gvt_vgpu_err("write invalid HWSP address, reg:0x%x, value:0x%x\n", 1480 offset, value); 1481 return -EINVAL; 1482 } 1483 /* 1484 * Need to emulate all the HWSP register write to ensure host can 1485 * update the VM CSB status correctly. Here listed registers can 1486 * support BDW, SKL or other platforms with same HWSP registers. 1487 */ 1488 if (unlikely(ring_id < 0 || ring_id >= I915_NUM_ENGINES)) { 1489 gvt_vgpu_err("access unknown hardware status page register:0x%x\n", 1490 offset); 1491 return -EINVAL; 1492 } 1493 vgpu->hws_pga[ring_id] = value; 1494 gvt_dbg_mmio("VM(%d) write: 0x%x to HWSP: 0x%x\n", 1495 vgpu->id, value, offset); 1496 1497 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes); 1498 } 1499 1500 static int skl_power_well_ctl_write(struct intel_vgpu *vgpu, 1501 unsigned int offset, void *p_data, unsigned int bytes) 1502 { 1503 u32 v = *(u32 *)p_data; 1504 1505 if (IS_BROXTON(vgpu->gvt->dev_priv)) 1506 v &= (1 << 31) | (1 << 29); 1507 else 1508 v &= (1 << 31) | (1 << 29) | (1 << 9) | 1509 (1 << 7) | (1 << 5) | (1 << 3) | (1 << 1); 1510 v |= (v >> 1); 1511 1512 return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes); 1513 } 1514 1515 static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset, 1516 void *p_data, unsigned int bytes) 1517 { 1518 u32 v = *(u32 *)p_data; 1519 1520 /* other bits are MBZ. */ 1521 v &= (1 << 31) | (1 << 30); 1522 v & (1 << 31) ? (v |= (1 << 30)) : (v &= ~(1 << 30)); 1523 1524 vgpu_vreg(vgpu, offset) = v; 1525 1526 return 0; 1527 } 1528 1529 static int bxt_de_pll_enable_write(struct intel_vgpu *vgpu, 1530 unsigned int offset, void *p_data, unsigned int bytes) 1531 { 1532 u32 v = *(u32 *)p_data; 1533 1534 if (v & BXT_DE_PLL_PLL_ENABLE) 1535 v |= BXT_DE_PLL_LOCK; 1536 1537 vgpu_vreg(vgpu, offset) = v; 1538 1539 return 0; 1540 } 1541 1542 static int bxt_port_pll_enable_write(struct intel_vgpu *vgpu, 1543 unsigned int offset, void *p_data, unsigned int bytes) 1544 { 1545 u32 v = *(u32 *)p_data; 1546 1547 if (v & PORT_PLL_ENABLE) 1548 v |= PORT_PLL_LOCK; 1549 1550 vgpu_vreg(vgpu, offset) = v; 1551 1552 return 0; 1553 } 1554 1555 static int bxt_phy_ctl_family_write(struct intel_vgpu *vgpu, 1556 unsigned int offset, void *p_data, unsigned int bytes) 1557 { 1558 u32 v = *(u32 *)p_data; 1559 u32 data = v & COMMON_RESET_DIS ? BXT_PHY_LANE_ENABLED : 0; 1560 1561 switch (offset) { 1562 case _PHY_CTL_FAMILY_EDP: 1563 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_A) = data; 1564 break; 1565 case _PHY_CTL_FAMILY_DDI: 1566 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_B) = data; 1567 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_C) = data; 1568 break; 1569 } 1570 1571 vgpu_vreg(vgpu, offset) = v; 1572 1573 return 0; 1574 } 1575 1576 static int bxt_port_tx_dw3_read(struct intel_vgpu *vgpu, 1577 unsigned int offset, void *p_data, unsigned int bytes) 1578 { 1579 u32 v = vgpu_vreg(vgpu, offset); 1580 1581 v &= ~UNIQUE_TRANGE_EN_METHOD; 1582 1583 vgpu_vreg(vgpu, offset) = v; 1584 1585 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1586 } 1587 1588 static int bxt_pcs_dw12_grp_write(struct intel_vgpu *vgpu, 1589 unsigned int offset, void *p_data, unsigned int bytes) 1590 { 1591 u32 v = *(u32 *)p_data; 1592 1593 if (offset == _PORT_PCS_DW12_GRP_A || offset == _PORT_PCS_DW12_GRP_B) { 1594 vgpu_vreg(vgpu, offset - 0x600) = v; 1595 vgpu_vreg(vgpu, offset - 0x800) = v; 1596 } else { 1597 vgpu_vreg(vgpu, offset - 0x400) = v; 1598 vgpu_vreg(vgpu, offset - 0x600) = v; 1599 } 1600 1601 vgpu_vreg(vgpu, offset) = v; 1602 1603 return 0; 1604 } 1605 1606 static int bxt_gt_disp_pwron_write(struct intel_vgpu *vgpu, 1607 unsigned int offset, void *p_data, unsigned int bytes) 1608 { 1609 u32 v = *(u32 *)p_data; 1610 1611 if (v & BIT(0)) { 1612 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &= 1613 ~PHY_RESERVED; 1614 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |= 1615 PHY_POWER_GOOD; 1616 } 1617 1618 if (v & BIT(1)) { 1619 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &= 1620 ~PHY_RESERVED; 1621 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |= 1622 PHY_POWER_GOOD; 1623 } 1624 1625 1626 vgpu_vreg(vgpu, offset) = v; 1627 1628 return 0; 1629 } 1630 1631 static int edp_psr_imr_iir_write(struct intel_vgpu *vgpu, 1632 unsigned int offset, void *p_data, unsigned int bytes) 1633 { 1634 vgpu_vreg(vgpu, offset) = 0; 1635 return 0; 1636 } 1637 1638 static int mmio_read_from_hw(struct intel_vgpu *vgpu, 1639 unsigned int offset, void *p_data, unsigned int bytes) 1640 { 1641 struct intel_gvt *gvt = vgpu->gvt; 1642 struct drm_i915_private *dev_priv = gvt->dev_priv; 1643 int ring_id; 1644 u32 ring_base; 1645 1646 ring_id = intel_gvt_render_mmio_to_ring_id(gvt, offset); 1647 /** 1648 * Read HW reg in following case 1649 * a. the offset isn't a ring mmio 1650 * b. the offset's ring is running on hw. 1651 * c. the offset is ring time stamp mmio 1652 */ 1653 if (ring_id >= 0) 1654 ring_base = dev_priv->engine[ring_id]->mmio_base; 1655 1656 if (ring_id < 0 || vgpu == gvt->scheduler.engine_owner[ring_id] || 1657 offset == i915_mmio_reg_offset(RING_TIMESTAMP(ring_base)) || 1658 offset == i915_mmio_reg_offset(RING_TIMESTAMP_UDW(ring_base))) { 1659 mmio_hw_access_pre(dev_priv); 1660 vgpu_vreg(vgpu, offset) = I915_READ(_MMIO(offset)); 1661 mmio_hw_access_post(dev_priv); 1662 } 1663 1664 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1665 } 1666 1667 static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1668 void *p_data, unsigned int bytes) 1669 { 1670 int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset); 1671 struct intel_vgpu_execlist *execlist; 1672 u32 data = *(u32 *)p_data; 1673 int ret = 0; 1674 1675 if (WARN_ON(ring_id < 0 || ring_id >= I915_NUM_ENGINES)) 1676 return -EINVAL; 1677 1678 execlist = &vgpu->submission.execlist[ring_id]; 1679 1680 execlist->elsp_dwords.data[3 - execlist->elsp_dwords.index] = data; 1681 if (execlist->elsp_dwords.index == 3) { 1682 ret = intel_vgpu_submit_execlist(vgpu, ring_id); 1683 if(ret) 1684 gvt_vgpu_err("fail submit workload on ring %d\n", 1685 ring_id); 1686 } 1687 1688 ++execlist->elsp_dwords.index; 1689 execlist->elsp_dwords.index &= 0x3; 1690 return ret; 1691 } 1692 1693 static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1694 void *p_data, unsigned int bytes) 1695 { 1696 u32 data = *(u32 *)p_data; 1697 int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset); 1698 bool enable_execlist; 1699 int ret; 1700 1701 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(1); 1702 if (IS_COFFEELAKE(vgpu->gvt->dev_priv)) 1703 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(2); 1704 write_vreg(vgpu, offset, p_data, bytes); 1705 1706 if (data & _MASKED_BIT_ENABLE(1)) { 1707 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); 1708 return 0; 1709 } 1710 1711 if (IS_COFFEELAKE(vgpu->gvt->dev_priv) && 1712 data & _MASKED_BIT_ENABLE(2)) { 1713 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); 1714 return 0; 1715 } 1716 1717 /* when PPGTT mode enabled, we will check if guest has called 1718 * pvinfo, if not, we will treat this guest as non-gvtg-aware 1719 * guest, and stop emulating its cfg space, mmio, gtt, etc. 1720 */ 1721 if (((data & _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)) || 1722 (data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE))) 1723 && !vgpu->pv_notified) { 1724 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); 1725 return 0; 1726 } 1727 if ((data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)) 1728 || (data & _MASKED_BIT_DISABLE(GFX_RUN_LIST_ENABLE))) { 1729 enable_execlist = !!(data & GFX_RUN_LIST_ENABLE); 1730 1731 gvt_dbg_core("EXECLIST %s on ring %d\n", 1732 (enable_execlist ? "enabling" : "disabling"), 1733 ring_id); 1734 1735 if (!enable_execlist) 1736 return 0; 1737 1738 ret = intel_vgpu_select_submission_ops(vgpu, 1739 BIT(ring_id), 1740 INTEL_VGPU_EXECLIST_SUBMISSION); 1741 if (ret) 1742 return ret; 1743 1744 intel_vgpu_start_schedule(vgpu); 1745 } 1746 return 0; 1747 } 1748 1749 static int gvt_reg_tlb_control_handler(struct intel_vgpu *vgpu, 1750 unsigned int offset, void *p_data, unsigned int bytes) 1751 { 1752 unsigned int id = 0; 1753 1754 write_vreg(vgpu, offset, p_data, bytes); 1755 vgpu_vreg(vgpu, offset) = 0; 1756 1757 switch (offset) { 1758 case 0x4260: 1759 id = RCS0; 1760 break; 1761 case 0x4264: 1762 id = VCS0; 1763 break; 1764 case 0x4268: 1765 id = VCS1; 1766 break; 1767 case 0x426c: 1768 id = BCS0; 1769 break; 1770 case 0x4270: 1771 id = VECS0; 1772 break; 1773 default: 1774 return -EINVAL; 1775 } 1776 set_bit(id, (void *)vgpu->submission.tlb_handle_pending); 1777 1778 return 0; 1779 } 1780 1781 static int ring_reset_ctl_write(struct intel_vgpu *vgpu, 1782 unsigned int offset, void *p_data, unsigned int bytes) 1783 { 1784 u32 data; 1785 1786 write_vreg(vgpu, offset, p_data, bytes); 1787 data = vgpu_vreg(vgpu, offset); 1788 1789 if (data & _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET)) 1790 data |= RESET_CTL_READY_TO_RESET; 1791 else if (data & _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET)) 1792 data &= ~RESET_CTL_READY_TO_RESET; 1793 1794 vgpu_vreg(vgpu, offset) = data; 1795 return 0; 1796 } 1797 1798 static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu, 1799 unsigned int offset, void *p_data, 1800 unsigned int bytes) 1801 { 1802 u32 data = *(u32 *)p_data; 1803 1804 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(0x18); 1805 write_vreg(vgpu, offset, p_data, bytes); 1806 1807 if (data & _MASKED_BIT_ENABLE(0x10) || data & _MASKED_BIT_ENABLE(0x8)) 1808 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); 1809 1810 return 0; 1811 } 1812 1813 #define MMIO_F(reg, s, f, am, rm, d, r, w) do { \ 1814 ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \ 1815 f, s, am, rm, d, r, w); \ 1816 if (ret) \ 1817 return ret; \ 1818 } while (0) 1819 1820 #define MMIO_D(reg, d) \ 1821 MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL) 1822 1823 #define MMIO_DH(reg, d, r, w) \ 1824 MMIO_F(reg, 4, 0, 0, 0, d, r, w) 1825 1826 #define MMIO_DFH(reg, d, f, r, w) \ 1827 MMIO_F(reg, 4, f, 0, 0, d, r, w) 1828 1829 #define MMIO_GM(reg, d, r, w) \ 1830 MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w) 1831 1832 #define MMIO_GM_RDR(reg, d, r, w) \ 1833 MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w) 1834 1835 #define MMIO_RO(reg, d, f, rm, r, w) \ 1836 MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w) 1837 1838 #define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \ 1839 MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \ 1840 MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \ 1841 MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \ 1842 MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \ 1843 if (HAS_ENGINE(dev_priv, VCS1)) \ 1844 MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \ 1845 } while (0) 1846 1847 #define MMIO_RING_D(prefix, d) \ 1848 MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL) 1849 1850 #define MMIO_RING_DFH(prefix, d, f, r, w) \ 1851 MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w) 1852 1853 #define MMIO_RING_GM(prefix, d, r, w) \ 1854 MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w) 1855 1856 #define MMIO_RING_GM_RDR(prefix, d, r, w) \ 1857 MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w) 1858 1859 #define MMIO_RING_RO(prefix, d, f, rm, r, w) \ 1860 MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w) 1861 1862 static int init_generic_mmio_info(struct intel_gvt *gvt) 1863 { 1864 struct drm_i915_private *dev_priv = gvt->dev_priv; 1865 int ret; 1866 1867 MMIO_RING_DFH(RING_IMR, D_ALL, F_CMD_ACCESS, NULL, 1868 intel_vgpu_reg_imr_handler); 1869 1870 MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler); 1871 MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler); 1872 MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler); 1873 MMIO_D(SDEISR, D_ALL); 1874 1875 MMIO_RING_DFH(RING_HWSTAM, D_ALL, F_CMD_ACCESS, NULL, NULL); 1876 1877 MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL, 1878 gamw_echo_dev_rw_ia_write); 1879 1880 MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1881 MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1882 MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1883 1884 #define RING_REG(base) _MMIO((base) + 0x28) 1885 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL); 1886 #undef RING_REG 1887 1888 #define RING_REG(base) _MMIO((base) + 0x134) 1889 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL); 1890 #undef RING_REG 1891 1892 #define RING_REG(base) _MMIO((base) + 0x6c) 1893 MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL); 1894 #undef RING_REG 1895 MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL); 1896 1897 MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL); 1898 MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL); 1899 MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL); 1900 MMIO_D(GEN7_CXT_SIZE, D_ALL); 1901 1902 MMIO_RING_DFH(RING_TAIL, D_ALL, F_CMD_ACCESS, NULL, NULL); 1903 MMIO_RING_DFH(RING_HEAD, D_ALL, F_CMD_ACCESS, NULL, NULL); 1904 MMIO_RING_DFH(RING_CTL, D_ALL, F_CMD_ACCESS, NULL, NULL); 1905 MMIO_RING_DFH(RING_ACTHD, D_ALL, F_CMD_ACCESS, mmio_read_from_hw, NULL); 1906 MMIO_RING_GM_RDR(RING_START, D_ALL, NULL, NULL); 1907 1908 /* RING MODE */ 1909 #define RING_REG(base) _MMIO((base) + 0x29c) 1910 MMIO_RING_DFH(RING_REG, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, 1911 ring_mode_mmio_write); 1912 #undef RING_REG 1913 1914 MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 1915 NULL, NULL); 1916 MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 1917 NULL, NULL); 1918 MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS, 1919 mmio_read_from_hw, NULL); 1920 MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS, 1921 mmio_read_from_hw, NULL); 1922 1923 MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1924 MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 1925 NULL, NULL); 1926 MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1927 MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1928 MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1929 1930 MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1931 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1932 MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1933 MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL, 1934 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1935 MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1936 MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL); 1937 MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 1938 NULL, NULL); 1939 MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 1940 NULL, NULL); 1941 MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL); 1942 MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL); 1943 MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL); 1944 MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL); 1945 MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL); 1946 MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL); 1947 MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL); 1948 MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1949 MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1950 MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1951 1952 /* display */ 1953 MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL); 1954 MMIO_D(_MMIO(0x602a0), D_ALL); 1955 1956 MMIO_D(_MMIO(0x65050), D_ALL); 1957 MMIO_D(_MMIO(0x650b4), D_ALL); 1958 1959 MMIO_D(_MMIO(0xc4040), D_ALL); 1960 MMIO_D(DERRMR, D_ALL); 1961 1962 MMIO_D(PIPEDSL(PIPE_A), D_ALL); 1963 MMIO_D(PIPEDSL(PIPE_B), D_ALL); 1964 MMIO_D(PIPEDSL(PIPE_C), D_ALL); 1965 MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL); 1966 1967 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write); 1968 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write); 1969 MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write); 1970 MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write); 1971 1972 MMIO_D(PIPESTAT(PIPE_A), D_ALL); 1973 MMIO_D(PIPESTAT(PIPE_B), D_ALL); 1974 MMIO_D(PIPESTAT(PIPE_C), D_ALL); 1975 MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL); 1976 1977 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL); 1978 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL); 1979 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL); 1980 MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL); 1981 1982 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL); 1983 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL); 1984 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL); 1985 MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL); 1986 1987 MMIO_D(CURCNTR(PIPE_A), D_ALL); 1988 MMIO_D(CURCNTR(PIPE_B), D_ALL); 1989 MMIO_D(CURCNTR(PIPE_C), D_ALL); 1990 1991 MMIO_D(CURPOS(PIPE_A), D_ALL); 1992 MMIO_D(CURPOS(PIPE_B), D_ALL); 1993 MMIO_D(CURPOS(PIPE_C), D_ALL); 1994 1995 MMIO_D(CURBASE(PIPE_A), D_ALL); 1996 MMIO_D(CURBASE(PIPE_B), D_ALL); 1997 MMIO_D(CURBASE(PIPE_C), D_ALL); 1998 1999 MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL); 2000 MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL); 2001 MMIO_D(CUR_FBC_CTL(PIPE_C), D_ALL); 2002 2003 MMIO_D(_MMIO(0x700ac), D_ALL); 2004 MMIO_D(_MMIO(0x710ac), D_ALL); 2005 MMIO_D(_MMIO(0x720ac), D_ALL); 2006 2007 MMIO_D(_MMIO(0x70090), D_ALL); 2008 MMIO_D(_MMIO(0x70094), D_ALL); 2009 MMIO_D(_MMIO(0x70098), D_ALL); 2010 MMIO_D(_MMIO(0x7009c), D_ALL); 2011 2012 MMIO_D(DSPCNTR(PIPE_A), D_ALL); 2013 MMIO_D(DSPADDR(PIPE_A), D_ALL); 2014 MMIO_D(DSPSTRIDE(PIPE_A), D_ALL); 2015 MMIO_D(DSPPOS(PIPE_A), D_ALL); 2016 MMIO_D(DSPSIZE(PIPE_A), D_ALL); 2017 MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write); 2018 MMIO_D(DSPOFFSET(PIPE_A), D_ALL); 2019 MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL); 2020 MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL, 2021 reg50080_mmio_write); 2022 2023 MMIO_D(DSPCNTR(PIPE_B), D_ALL); 2024 MMIO_D(DSPADDR(PIPE_B), D_ALL); 2025 MMIO_D(DSPSTRIDE(PIPE_B), D_ALL); 2026 MMIO_D(DSPPOS(PIPE_B), D_ALL); 2027 MMIO_D(DSPSIZE(PIPE_B), D_ALL); 2028 MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write); 2029 MMIO_D(DSPOFFSET(PIPE_B), D_ALL); 2030 MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL); 2031 MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL, 2032 reg50080_mmio_write); 2033 2034 MMIO_D(DSPCNTR(PIPE_C), D_ALL); 2035 MMIO_D(DSPADDR(PIPE_C), D_ALL); 2036 MMIO_D(DSPSTRIDE(PIPE_C), D_ALL); 2037 MMIO_D(DSPPOS(PIPE_C), D_ALL); 2038 MMIO_D(DSPSIZE(PIPE_C), D_ALL); 2039 MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write); 2040 MMIO_D(DSPOFFSET(PIPE_C), D_ALL); 2041 MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL); 2042 MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL, 2043 reg50080_mmio_write); 2044 2045 MMIO_D(SPRCTL(PIPE_A), D_ALL); 2046 MMIO_D(SPRLINOFF(PIPE_A), D_ALL); 2047 MMIO_D(SPRSTRIDE(PIPE_A), D_ALL); 2048 MMIO_D(SPRPOS(PIPE_A), D_ALL); 2049 MMIO_D(SPRSIZE(PIPE_A), D_ALL); 2050 MMIO_D(SPRKEYVAL(PIPE_A), D_ALL); 2051 MMIO_D(SPRKEYMSK(PIPE_A), D_ALL); 2052 MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write); 2053 MMIO_D(SPRKEYMAX(PIPE_A), D_ALL); 2054 MMIO_D(SPROFFSET(PIPE_A), D_ALL); 2055 MMIO_D(SPRSCALE(PIPE_A), D_ALL); 2056 MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL); 2057 MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL, 2058 reg50080_mmio_write); 2059 2060 MMIO_D(SPRCTL(PIPE_B), D_ALL); 2061 MMIO_D(SPRLINOFF(PIPE_B), D_ALL); 2062 MMIO_D(SPRSTRIDE(PIPE_B), D_ALL); 2063 MMIO_D(SPRPOS(PIPE_B), D_ALL); 2064 MMIO_D(SPRSIZE(PIPE_B), D_ALL); 2065 MMIO_D(SPRKEYVAL(PIPE_B), D_ALL); 2066 MMIO_D(SPRKEYMSK(PIPE_B), D_ALL); 2067 MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write); 2068 MMIO_D(SPRKEYMAX(PIPE_B), D_ALL); 2069 MMIO_D(SPROFFSET(PIPE_B), D_ALL); 2070 MMIO_D(SPRSCALE(PIPE_B), D_ALL); 2071 MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL); 2072 MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL, 2073 reg50080_mmio_write); 2074 2075 MMIO_D(SPRCTL(PIPE_C), D_ALL); 2076 MMIO_D(SPRLINOFF(PIPE_C), D_ALL); 2077 MMIO_D(SPRSTRIDE(PIPE_C), D_ALL); 2078 MMIO_D(SPRPOS(PIPE_C), D_ALL); 2079 MMIO_D(SPRSIZE(PIPE_C), D_ALL); 2080 MMIO_D(SPRKEYVAL(PIPE_C), D_ALL); 2081 MMIO_D(SPRKEYMSK(PIPE_C), D_ALL); 2082 MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write); 2083 MMIO_D(SPRKEYMAX(PIPE_C), D_ALL); 2084 MMIO_D(SPROFFSET(PIPE_C), D_ALL); 2085 MMIO_D(SPRSCALE(PIPE_C), D_ALL); 2086 MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL); 2087 MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL, 2088 reg50080_mmio_write); 2089 2090 MMIO_D(HTOTAL(TRANSCODER_A), D_ALL); 2091 MMIO_D(HBLANK(TRANSCODER_A), D_ALL); 2092 MMIO_D(HSYNC(TRANSCODER_A), D_ALL); 2093 MMIO_D(VTOTAL(TRANSCODER_A), D_ALL); 2094 MMIO_D(VBLANK(TRANSCODER_A), D_ALL); 2095 MMIO_D(VSYNC(TRANSCODER_A), D_ALL); 2096 MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL); 2097 MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL); 2098 MMIO_D(PIPESRC(TRANSCODER_A), D_ALL); 2099 2100 MMIO_D(HTOTAL(TRANSCODER_B), D_ALL); 2101 MMIO_D(HBLANK(TRANSCODER_B), D_ALL); 2102 MMIO_D(HSYNC(TRANSCODER_B), D_ALL); 2103 MMIO_D(VTOTAL(TRANSCODER_B), D_ALL); 2104 MMIO_D(VBLANK(TRANSCODER_B), D_ALL); 2105 MMIO_D(VSYNC(TRANSCODER_B), D_ALL); 2106 MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL); 2107 MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL); 2108 MMIO_D(PIPESRC(TRANSCODER_B), D_ALL); 2109 2110 MMIO_D(HTOTAL(TRANSCODER_C), D_ALL); 2111 MMIO_D(HBLANK(TRANSCODER_C), D_ALL); 2112 MMIO_D(HSYNC(TRANSCODER_C), D_ALL); 2113 MMIO_D(VTOTAL(TRANSCODER_C), D_ALL); 2114 MMIO_D(VBLANK(TRANSCODER_C), D_ALL); 2115 MMIO_D(VSYNC(TRANSCODER_C), D_ALL); 2116 MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL); 2117 MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL); 2118 MMIO_D(PIPESRC(TRANSCODER_C), D_ALL); 2119 2120 MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL); 2121 MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL); 2122 MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL); 2123 MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL); 2124 MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL); 2125 MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL); 2126 MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL); 2127 MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL); 2128 2129 MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL); 2130 MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL); 2131 MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL); 2132 MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL); 2133 MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL); 2134 MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL); 2135 MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL); 2136 MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL); 2137 2138 MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL); 2139 MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL); 2140 MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL); 2141 MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL); 2142 MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL); 2143 MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL); 2144 MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL); 2145 MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL); 2146 2147 MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL); 2148 MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL); 2149 MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL); 2150 MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL); 2151 MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL); 2152 MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL); 2153 MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL); 2154 MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL); 2155 2156 MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL); 2157 MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL); 2158 MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL); 2159 MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL); 2160 MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL); 2161 MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL); 2162 MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL); 2163 MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL); 2164 2165 MMIO_D(PF_CTL(PIPE_A), D_ALL); 2166 MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL); 2167 MMIO_D(PF_WIN_POS(PIPE_A), D_ALL); 2168 MMIO_D(PF_VSCALE(PIPE_A), D_ALL); 2169 MMIO_D(PF_HSCALE(PIPE_A), D_ALL); 2170 2171 MMIO_D(PF_CTL(PIPE_B), D_ALL); 2172 MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL); 2173 MMIO_D(PF_WIN_POS(PIPE_B), D_ALL); 2174 MMIO_D(PF_VSCALE(PIPE_B), D_ALL); 2175 MMIO_D(PF_HSCALE(PIPE_B), D_ALL); 2176 2177 MMIO_D(PF_CTL(PIPE_C), D_ALL); 2178 MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL); 2179 MMIO_D(PF_WIN_POS(PIPE_C), D_ALL); 2180 MMIO_D(PF_VSCALE(PIPE_C), D_ALL); 2181 MMIO_D(PF_HSCALE(PIPE_C), D_ALL); 2182 2183 MMIO_D(WM0_PIPEA_ILK, D_ALL); 2184 MMIO_D(WM0_PIPEB_ILK, D_ALL); 2185 MMIO_D(WM0_PIPEC_IVB, D_ALL); 2186 MMIO_D(WM1_LP_ILK, D_ALL); 2187 MMIO_D(WM2_LP_ILK, D_ALL); 2188 MMIO_D(WM3_LP_ILK, D_ALL); 2189 MMIO_D(WM1S_LP_ILK, D_ALL); 2190 MMIO_D(WM2S_LP_IVB, D_ALL); 2191 MMIO_D(WM3S_LP_IVB, D_ALL); 2192 2193 MMIO_D(BLC_PWM_CPU_CTL2, D_ALL); 2194 MMIO_D(BLC_PWM_CPU_CTL, D_ALL); 2195 MMIO_D(BLC_PWM_PCH_CTL1, D_ALL); 2196 MMIO_D(BLC_PWM_PCH_CTL2, D_ALL); 2197 2198 MMIO_D(_MMIO(0x48268), D_ALL); 2199 2200 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read, 2201 gmbus_mmio_write); 2202 MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL); 2203 MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL); 2204 2205 MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 2206 dp_aux_ch_ctl_mmio_write); 2207 MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 2208 dp_aux_ch_ctl_mmio_write); 2209 MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 2210 dp_aux_ch_ctl_mmio_write); 2211 2212 MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write); 2213 2214 MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write); 2215 MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write); 2216 2217 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write); 2218 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write); 2219 MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write); 2220 MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); 2221 MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); 2222 MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); 2223 MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); 2224 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); 2225 MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); 2226 2227 MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A), D_ALL); 2228 MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A), D_ALL); 2229 MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A), D_ALL); 2230 MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A), D_ALL); 2231 MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A), D_ALL); 2232 MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A), D_ALL); 2233 MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A), D_ALL); 2234 2235 MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B), D_ALL); 2236 MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B), D_ALL); 2237 MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B), D_ALL); 2238 MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B), D_ALL); 2239 MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B), D_ALL); 2240 MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B), D_ALL); 2241 MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B), D_ALL); 2242 2243 MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1), D_ALL); 2244 MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1), D_ALL); 2245 MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2), D_ALL); 2246 MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2), D_ALL); 2247 MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1), D_ALL); 2248 MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1), D_ALL); 2249 MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2), D_ALL); 2250 MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2), D_ALL); 2251 2252 MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL); 2253 MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL); 2254 MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL); 2255 2256 MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL); 2257 MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL); 2258 MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL); 2259 2260 MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL); 2261 MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL); 2262 MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL); 2263 2264 MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL); 2265 MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL); 2266 MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL); 2267 2268 MMIO_D(_MMIO(_FDI_RXA_MISC), D_ALL); 2269 MMIO_D(_MMIO(_FDI_RXB_MISC), D_ALL); 2270 MMIO_D(_MMIO(_FDI_RXA_TUSIZE1), D_ALL); 2271 MMIO_D(_MMIO(_FDI_RXA_TUSIZE2), D_ALL); 2272 MMIO_D(_MMIO(_FDI_RXB_TUSIZE1), D_ALL); 2273 MMIO_D(_MMIO(_FDI_RXB_TUSIZE2), D_ALL); 2274 2275 MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write); 2276 MMIO_D(PCH_PP_DIVISOR, D_ALL); 2277 MMIO_D(PCH_PP_STATUS, D_ALL); 2278 MMIO_D(PCH_LVDS, D_ALL); 2279 MMIO_D(_MMIO(_PCH_DPLL_A), D_ALL); 2280 MMIO_D(_MMIO(_PCH_DPLL_B), D_ALL); 2281 MMIO_D(_MMIO(_PCH_FPA0), D_ALL); 2282 MMIO_D(_MMIO(_PCH_FPA1), D_ALL); 2283 MMIO_D(_MMIO(_PCH_FPB0), D_ALL); 2284 MMIO_D(_MMIO(_PCH_FPB1), D_ALL); 2285 MMIO_D(PCH_DREF_CONTROL, D_ALL); 2286 MMIO_D(PCH_RAWCLK_FREQ, D_ALL); 2287 MMIO_D(PCH_DPLL_SEL, D_ALL); 2288 2289 MMIO_D(_MMIO(0x61208), D_ALL); 2290 MMIO_D(_MMIO(0x6120c), D_ALL); 2291 MMIO_D(PCH_PP_ON_DELAYS, D_ALL); 2292 MMIO_D(PCH_PP_OFF_DELAYS, D_ALL); 2293 2294 MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL); 2295 MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL); 2296 MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL); 2297 MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL); 2298 MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL); 2299 MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL); 2300 2301 MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0, 2302 PORTA_HOTPLUG_STATUS_MASK 2303 | PORTB_HOTPLUG_STATUS_MASK 2304 | PORTC_HOTPLUG_STATUS_MASK 2305 | PORTD_HOTPLUG_STATUS_MASK, 2306 NULL, NULL); 2307 2308 MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write); 2309 MMIO_D(FUSE_STRAP, D_ALL); 2310 MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL); 2311 2312 MMIO_D(DISP_ARB_CTL, D_ALL); 2313 MMIO_D(DISP_ARB_CTL2, D_ALL); 2314 2315 MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL); 2316 MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL); 2317 MMIO_D(ILK_DSPCLK_GATE_D, D_ALL); 2318 2319 MMIO_D(SOUTH_CHICKEN1, D_ALL); 2320 MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write); 2321 MMIO_D(_MMIO(_TRANSA_CHICKEN1), D_ALL); 2322 MMIO_D(_MMIO(_TRANSB_CHICKEN1), D_ALL); 2323 MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL); 2324 MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL); 2325 MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL); 2326 2327 MMIO_D(ILK_DPFC_CB_BASE, D_ALL); 2328 MMIO_D(ILK_DPFC_CONTROL, D_ALL); 2329 MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL); 2330 MMIO_D(ILK_DPFC_STATUS, D_ALL); 2331 MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL); 2332 MMIO_D(ILK_DPFC_CHICKEN, D_ALL); 2333 MMIO_D(ILK_FBC_RT_BASE, D_ALL); 2334 2335 MMIO_D(IPS_CTL, D_ALL); 2336 2337 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL); 2338 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL); 2339 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL); 2340 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL); 2341 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL); 2342 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL); 2343 MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL); 2344 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL); 2345 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL); 2346 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL); 2347 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL); 2348 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL); 2349 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL); 2350 2351 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL); 2352 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL); 2353 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL); 2354 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL); 2355 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL); 2356 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL); 2357 MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL); 2358 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL); 2359 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL); 2360 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL); 2361 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL); 2362 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL); 2363 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL); 2364 2365 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL); 2366 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL); 2367 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL); 2368 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL); 2369 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL); 2370 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL); 2371 MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL); 2372 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL); 2373 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL); 2374 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL); 2375 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL); 2376 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL); 2377 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL); 2378 2379 MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL); 2380 MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL); 2381 MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 2382 2383 MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL); 2384 MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL); 2385 MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 2386 2387 MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL); 2388 MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL); 2389 MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 2390 2391 MMIO_D(_MMIO(0x60110), D_ALL); 2392 MMIO_D(_MMIO(0x61110), D_ALL); 2393 MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL); 2394 MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL); 2395 MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL); 2396 MMIO_F(_MMIO(0x70440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2397 MMIO_F(_MMIO(0x71440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2398 MMIO_F(_MMIO(0x72440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2399 MMIO_F(_MMIO(0x7044c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2400 MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2401 MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2402 2403 MMIO_D(PIPE_WM_LINETIME(PIPE_A), D_ALL); 2404 MMIO_D(PIPE_WM_LINETIME(PIPE_B), D_ALL); 2405 MMIO_D(PIPE_WM_LINETIME(PIPE_C), D_ALL); 2406 MMIO_D(SPLL_CTL, D_ALL); 2407 MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL); 2408 MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL); 2409 MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL); 2410 MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL); 2411 MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL); 2412 MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL); 2413 MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL); 2414 MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL); 2415 MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL); 2416 MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL); 2417 2418 MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL); 2419 MMIO_D(_MMIO(0x46508), D_ALL); 2420 2421 MMIO_D(_MMIO(0x49080), D_ALL); 2422 MMIO_D(_MMIO(0x49180), D_ALL); 2423 MMIO_D(_MMIO(0x49280), D_ALL); 2424 2425 MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL); 2426 MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL); 2427 MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL); 2428 2429 MMIO_D(GAMMA_MODE(PIPE_A), D_ALL); 2430 MMIO_D(GAMMA_MODE(PIPE_B), D_ALL); 2431 MMIO_D(GAMMA_MODE(PIPE_C), D_ALL); 2432 2433 MMIO_D(PIPE_MULT(PIPE_A), D_ALL); 2434 MMIO_D(PIPE_MULT(PIPE_B), D_ALL); 2435 MMIO_D(PIPE_MULT(PIPE_C), D_ALL); 2436 2437 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL); 2438 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL); 2439 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL); 2440 2441 MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL); 2442 MMIO_D(SBI_ADDR, D_ALL); 2443 MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL); 2444 MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write); 2445 MMIO_D(PIXCLK_GATE, D_ALL); 2446 2447 MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL, 2448 dp_aux_ch_ctl_mmio_write); 2449 2450 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2451 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2452 MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2453 MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2454 MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2455 2456 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write); 2457 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write); 2458 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write); 2459 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write); 2460 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write); 2461 2462 MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write); 2463 MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write); 2464 MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write); 2465 MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write); 2466 MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL); 2467 2468 MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2469 MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2470 MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2471 MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2472 MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2473 2474 MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL); 2475 MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL); 2476 MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A), D_ALL); 2477 2478 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL); 2479 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL); 2480 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL); 2481 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL); 2482 2483 MMIO_D(_MMIO(_TRANSA_MSA_MISC), D_ALL); 2484 MMIO_D(_MMIO(_TRANSB_MSA_MISC), D_ALL); 2485 MMIO_D(_MMIO(_TRANSC_MSA_MISC), D_ALL); 2486 MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC), D_ALL); 2487 2488 MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL); 2489 MMIO_D(FORCEWAKE_ACK, D_ALL); 2490 MMIO_D(GEN6_GT_CORE_STATUS, D_ALL); 2491 MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL); 2492 MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL); 2493 MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL); 2494 MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write); 2495 MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL); 2496 MMIO_D(ECOBUS, D_ALL); 2497 MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL); 2498 MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL); 2499 MMIO_D(GEN6_RPNSWREQ, D_ALL); 2500 MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL); 2501 MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL); 2502 MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL); 2503 MMIO_D(GEN6_RPSTAT1, D_ALL); 2504 MMIO_D(GEN6_RP_CONTROL, D_ALL); 2505 MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL); 2506 MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL); 2507 MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL); 2508 MMIO_D(GEN6_RP_CUR_UP, D_ALL); 2509 MMIO_D(GEN6_RP_PREV_UP, D_ALL); 2510 MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL); 2511 MMIO_D(GEN6_RP_CUR_DOWN, D_ALL); 2512 MMIO_D(GEN6_RP_PREV_DOWN, D_ALL); 2513 MMIO_D(GEN6_RP_UP_EI, D_ALL); 2514 MMIO_D(GEN6_RP_DOWN_EI, D_ALL); 2515 MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL); 2516 MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL); 2517 MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL); 2518 MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL); 2519 MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL); 2520 MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL); 2521 MMIO_D(GEN6_RC_SLEEP, D_ALL); 2522 MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL); 2523 MMIO_D(GEN6_RC6_THRESHOLD, D_ALL); 2524 MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL); 2525 MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL); 2526 MMIO_D(GEN6_PMINTRMSK, D_ALL); 2527 MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write); 2528 MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write); 2529 MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write); 2530 MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write); 2531 MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write); 2532 MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write); 2533 2534 MMIO_D(RSTDBYCTL, D_ALL); 2535 2536 MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write); 2537 MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write); 2538 MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write); 2539 2540 MMIO_D(TILECTL, D_ALL); 2541 2542 MMIO_D(GEN6_UCGCTL1, D_ALL); 2543 MMIO_D(GEN6_UCGCTL2, D_ALL); 2544 2545 MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL); 2546 2547 MMIO_D(GEN6_PCODE_DATA, D_ALL); 2548 MMIO_D(_MMIO(0x13812c), D_ALL); 2549 MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL); 2550 MMIO_D(HSW_EDRAM_CAP, D_ALL); 2551 MMIO_D(HSW_IDICR, D_ALL); 2552 MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL); 2553 2554 MMIO_D(_MMIO(0x3c), D_ALL); 2555 MMIO_D(_MMIO(0x860), D_ALL); 2556 MMIO_D(ECOSKPD, D_ALL); 2557 MMIO_D(_MMIO(0x121d0), D_ALL); 2558 MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL); 2559 MMIO_D(_MMIO(0x41d0), D_ALL); 2560 MMIO_D(GAC_ECO_BITS, D_ALL); 2561 MMIO_D(_MMIO(0x6200), D_ALL); 2562 MMIO_D(_MMIO(0x6204), D_ALL); 2563 MMIO_D(_MMIO(0x6208), D_ALL); 2564 MMIO_D(_MMIO(0x7118), D_ALL); 2565 MMIO_D(_MMIO(0x7180), D_ALL); 2566 MMIO_D(_MMIO(0x7408), D_ALL); 2567 MMIO_D(_MMIO(0x7c00), D_ALL); 2568 MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write); 2569 MMIO_D(_MMIO(0x911c), D_ALL); 2570 MMIO_D(_MMIO(0x9120), D_ALL); 2571 MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL); 2572 2573 MMIO_D(GAB_CTL, D_ALL); 2574 MMIO_D(_MMIO(0x48800), D_ALL); 2575 MMIO_D(_MMIO(0xce044), D_ALL); 2576 MMIO_D(_MMIO(0xe6500), D_ALL); 2577 MMIO_D(_MMIO(0xe6504), D_ALL); 2578 MMIO_D(_MMIO(0xe6600), D_ALL); 2579 MMIO_D(_MMIO(0xe6604), D_ALL); 2580 MMIO_D(_MMIO(0xe6700), D_ALL); 2581 MMIO_D(_MMIO(0xe6704), D_ALL); 2582 MMIO_D(_MMIO(0xe6800), D_ALL); 2583 MMIO_D(_MMIO(0xe6804), D_ALL); 2584 MMIO_D(PCH_GMBUS4, D_ALL); 2585 MMIO_D(PCH_GMBUS5, D_ALL); 2586 2587 MMIO_D(_MMIO(0x902c), D_ALL); 2588 MMIO_D(_MMIO(0xec008), D_ALL); 2589 MMIO_D(_MMIO(0xec00c), D_ALL); 2590 MMIO_D(_MMIO(0xec008 + 0x18), D_ALL); 2591 MMIO_D(_MMIO(0xec00c + 0x18), D_ALL); 2592 MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL); 2593 MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL); 2594 MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL); 2595 MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL); 2596 MMIO_D(_MMIO(0xec408), D_ALL); 2597 MMIO_D(_MMIO(0xec40c), D_ALL); 2598 MMIO_D(_MMIO(0xec408 + 0x18), D_ALL); 2599 MMIO_D(_MMIO(0xec40c + 0x18), D_ALL); 2600 MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL); 2601 MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL); 2602 MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL); 2603 MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL); 2604 MMIO_D(_MMIO(0xfc810), D_ALL); 2605 MMIO_D(_MMIO(0xfc81c), D_ALL); 2606 MMIO_D(_MMIO(0xfc828), D_ALL); 2607 MMIO_D(_MMIO(0xfc834), D_ALL); 2608 MMIO_D(_MMIO(0xfcc00), D_ALL); 2609 MMIO_D(_MMIO(0xfcc0c), D_ALL); 2610 MMIO_D(_MMIO(0xfcc18), D_ALL); 2611 MMIO_D(_MMIO(0xfcc24), D_ALL); 2612 MMIO_D(_MMIO(0xfd000), D_ALL); 2613 MMIO_D(_MMIO(0xfd00c), D_ALL); 2614 MMIO_D(_MMIO(0xfd018), D_ALL); 2615 MMIO_D(_MMIO(0xfd024), D_ALL); 2616 MMIO_D(_MMIO(0xfd034), D_ALL); 2617 2618 MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write); 2619 MMIO_D(_MMIO(0x2054), D_ALL); 2620 MMIO_D(_MMIO(0x12054), D_ALL); 2621 MMIO_D(_MMIO(0x22054), D_ALL); 2622 MMIO_D(_MMIO(0x1a054), D_ALL); 2623 2624 MMIO_D(_MMIO(0x44070), D_ALL); 2625 MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2626 MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL); 2627 MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL); 2628 MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL); 2629 MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL); 2630 2631 MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL); 2632 MMIO_D(_MMIO(0x2b00), D_BDW_PLUS); 2633 MMIO_D(_MMIO(0x2360), D_BDW_PLUS); 2634 MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2635 MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2636 MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2637 2638 MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2639 MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2640 MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL); 2641 2642 MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2643 MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2644 MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2645 MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2646 MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2647 MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2648 MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2649 MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2650 MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2651 MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2652 MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2653 MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2654 MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2655 MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2656 MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2657 MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2658 MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2659 2660 MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2661 MMIO_RING_GM_RDR(RING_BBADDR, D_ALL, NULL, NULL); 2662 MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL); 2663 MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL); 2664 MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL); 2665 MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL); 2666 MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL); 2667 MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2668 MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2669 MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2670 MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2671 2672 MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write); 2673 MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write); 2674 return 0; 2675 } 2676 2677 static int init_broadwell_mmio_info(struct intel_gvt *gvt) 2678 { 2679 struct drm_i915_private *dev_priv = gvt->dev_priv; 2680 int ret; 2681 2682 MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2683 MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2684 MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2685 MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS); 2686 2687 MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2688 MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2689 MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2690 MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS); 2691 2692 MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2693 MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2694 MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2695 MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS); 2696 2697 MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2698 MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2699 MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2700 MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS); 2701 2702 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL, 2703 intel_vgpu_reg_imr_handler); 2704 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL, 2705 intel_vgpu_reg_ier_handler); 2706 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL, 2707 intel_vgpu_reg_iir_handler); 2708 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS); 2709 2710 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL, 2711 intel_vgpu_reg_imr_handler); 2712 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL, 2713 intel_vgpu_reg_ier_handler); 2714 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL, 2715 intel_vgpu_reg_iir_handler); 2716 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS); 2717 2718 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL, 2719 intel_vgpu_reg_imr_handler); 2720 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL, 2721 intel_vgpu_reg_ier_handler); 2722 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL, 2723 intel_vgpu_reg_iir_handler); 2724 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS); 2725 2726 MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2727 MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2728 MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2729 MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS); 2730 2731 MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2732 MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2733 MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2734 MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS); 2735 2736 MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2737 MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2738 MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2739 MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS); 2740 2741 MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL, 2742 intel_vgpu_reg_master_irq_handler); 2743 2744 MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, F_CMD_ACCESS, 2745 mmio_read_from_hw, NULL); 2746 2747 #define RING_REG(base) _MMIO((base) + 0xd0) 2748 MMIO_RING_F(RING_REG, 4, F_RO, 0, 2749 ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL, 2750 ring_reset_ctl_write); 2751 #undef RING_REG 2752 2753 #define RING_REG(base) _MMIO((base) + 0x230) 2754 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write); 2755 #undef RING_REG 2756 2757 #define RING_REG(base) _MMIO((base) + 0x234) 2758 MMIO_RING_F(RING_REG, 8, F_RO | F_CMD_ACCESS, 0, ~0, D_BDW_PLUS, 2759 NULL, NULL); 2760 #undef RING_REG 2761 2762 #define RING_REG(base) _MMIO((base) + 0x244) 2763 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2764 #undef RING_REG 2765 2766 #define RING_REG(base) _MMIO((base) + 0x370) 2767 MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL); 2768 #undef RING_REG 2769 2770 #define RING_REG(base) _MMIO((base) + 0x3a0) 2771 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2772 #undef RING_REG 2773 2774 MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS); 2775 MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS); 2776 MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS); 2777 MMIO_D(_MMIO(0x1c1d0), D_BDW_PLUS); 2778 MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS); 2779 MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS); 2780 MMIO_D(_MMIO(0x1c054), D_BDW_PLUS); 2781 2782 MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write); 2783 2784 MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS); 2785 MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS); 2786 2787 MMIO_D(GAMTARBMODE, D_BDW_PLUS); 2788 2789 #define RING_REG(base) _MMIO((base) + 0x270) 2790 MMIO_RING_F(RING_REG, 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL); 2791 #undef RING_REG 2792 2793 MMIO_RING_GM_RDR(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write); 2794 2795 MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2796 2797 MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS); 2798 MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS); 2799 MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS); 2800 2801 MMIO_D(WM_MISC, D_BDW); 2802 MMIO_D(_MMIO(_SRD_CTL_EDP), D_BDW); 2803 2804 MMIO_D(_MMIO(0x6671c), D_BDW_PLUS); 2805 MMIO_D(_MMIO(0x66c00), D_BDW_PLUS); 2806 MMIO_D(_MMIO(0x66c04), D_BDW_PLUS); 2807 2808 MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS); 2809 2810 MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS); 2811 MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS); 2812 MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS); 2813 2814 MMIO_D(_MMIO(0xfdc), D_BDW_PLUS); 2815 MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2816 NULL, NULL); 2817 MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2818 NULL, NULL); 2819 MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2820 2821 MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL); 2822 MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL); 2823 MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2824 MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL); 2825 MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL); 2826 MMIO_D(_MMIO(0xb110), D_BDW); 2827 2828 MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, 2829 NULL, force_nonpriv_write); 2830 2831 MMIO_D(_MMIO(0x44484), D_BDW_PLUS); 2832 MMIO_D(_MMIO(0x4448c), D_BDW_PLUS); 2833 2834 MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL); 2835 MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS); 2836 2837 MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL); 2838 2839 MMIO_D(_MMIO(0x110000), D_BDW_PLUS); 2840 2841 MMIO_D(_MMIO(0x48400), D_BDW_PLUS); 2842 2843 MMIO_D(_MMIO(0x6e570), D_BDW_PLUS); 2844 MMIO_D(_MMIO(0x65f10), D_BDW_PLUS); 2845 2846 MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2847 MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2848 MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2849 MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2850 2851 MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL); 2852 2853 MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2854 MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2855 MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2856 MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2857 MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2858 MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2859 MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2860 MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2861 MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2862 MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2863 return 0; 2864 } 2865 2866 static int init_skl_mmio_info(struct intel_gvt *gvt) 2867 { 2868 struct drm_i915_private *dev_priv = gvt->dev_priv; 2869 int ret; 2870 2871 MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2872 MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL); 2873 MMIO_DH(FORCEWAKE_BLITTER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2874 MMIO_DH(FORCEWAKE_ACK_BLITTER_GEN9, D_SKL_PLUS, NULL, NULL); 2875 MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2876 MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL); 2877 2878 MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 2879 dp_aux_ch_ctl_mmio_write); 2880 MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 2881 dp_aux_ch_ctl_mmio_write); 2882 MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 2883 dp_aux_ch_ctl_mmio_write); 2884 2885 MMIO_D(HSW_PWR_WELL_CTL1, D_SKL_PLUS); 2886 MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write); 2887 2888 MMIO_DH(DBUF_CTL, D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write); 2889 2890 MMIO_D(GEN9_PG_ENABLE, D_SKL_PLUS); 2891 MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS); 2892 MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS); 2893 MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2894 MMIO_DH(MMCD_MISC_CTRL, D_SKL_PLUS, NULL, NULL); 2895 MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL); 2896 MMIO_D(DC_STATE_EN, D_SKL_PLUS); 2897 MMIO_D(DC_STATE_DEBUG, D_SKL_PLUS); 2898 MMIO_D(CDCLK_CTL, D_SKL_PLUS); 2899 MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write); 2900 MMIO_DH(LCPLL2_CTL, D_SKL_PLUS, NULL, skl_lcpll_write); 2901 MMIO_D(_MMIO(_DPLL1_CFGCR1), D_SKL_PLUS); 2902 MMIO_D(_MMIO(_DPLL2_CFGCR1), D_SKL_PLUS); 2903 MMIO_D(_MMIO(_DPLL3_CFGCR1), D_SKL_PLUS); 2904 MMIO_D(_MMIO(_DPLL1_CFGCR2), D_SKL_PLUS); 2905 MMIO_D(_MMIO(_DPLL2_CFGCR2), D_SKL_PLUS); 2906 MMIO_D(_MMIO(_DPLL3_CFGCR2), D_SKL_PLUS); 2907 MMIO_D(DPLL_CTRL1, D_SKL_PLUS); 2908 MMIO_D(DPLL_CTRL2, D_SKL_PLUS); 2909 MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL); 2910 2911 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); 2912 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); 2913 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); 2914 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); 2915 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); 2916 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); 2917 2918 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); 2919 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); 2920 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); 2921 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); 2922 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); 2923 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); 2924 2925 MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); 2926 MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); 2927 MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); 2928 MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); 2929 MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); 2930 MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); 2931 2932 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 2933 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 2934 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 2935 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); 2936 2937 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 2938 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 2939 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 2940 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); 2941 2942 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 2943 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 2944 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2945 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); 2946 2947 MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL); 2948 MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL); 2949 MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL); 2950 2951 MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2952 MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2953 MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2954 2955 MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2956 MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2957 MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2958 2959 MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2960 MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2961 MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2962 2963 MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2964 MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2965 MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2966 2967 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 2968 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 2969 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 2970 2971 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 2972 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 2973 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 2974 2975 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 2976 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 2977 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2978 2979 MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL); 2980 MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL); 2981 MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL); 2982 2983 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 2984 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 2985 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 2986 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); 2987 2988 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 2989 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 2990 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 2991 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); 2992 2993 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 2994 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 2995 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2996 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); 2997 2998 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL); 2999 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL); 3000 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL); 3001 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL); 3002 3003 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL); 3004 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL); 3005 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL); 3006 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL); 3007 3008 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL); 3009 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL); 3010 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL); 3011 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL); 3012 3013 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL); 3014 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL); 3015 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL); 3016 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL); 3017 3018 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL); 3019 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL); 3020 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL); 3021 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL); 3022 3023 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL); 3024 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL); 3025 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL); 3026 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL); 3027 3028 MMIO_D(_MMIO(_PLANE_CTL_3_A), D_SKL_PLUS); 3029 MMIO_D(_MMIO(_PLANE_CTL_3_B), D_SKL_PLUS); 3030 MMIO_D(_MMIO(0x72380), D_SKL_PLUS); 3031 MMIO_D(_MMIO(0x7239c), D_SKL_PLUS); 3032 MMIO_D(_MMIO(_PLANE_SURF_3_A), D_SKL_PLUS); 3033 3034 MMIO_D(CSR_SSP_BASE, D_SKL_PLUS); 3035 MMIO_D(CSR_HTP_SKL, D_SKL_PLUS); 3036 MMIO_D(CSR_LAST_WRITE, D_SKL_PLUS); 3037 3038 MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 3039 3040 MMIO_D(SKL_DFSM, D_SKL_PLUS); 3041 MMIO_D(DISPIO_CR_TX_BMU_CR0, D_SKL_PLUS); 3042 3043 MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS, 3044 NULL, NULL); 3045 MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS, 3046 NULL, NULL); 3047 3048 MMIO_D(RPM_CONFIG0, D_SKL_PLUS); 3049 MMIO_D(_MMIO(0xd08), D_SKL_PLUS); 3050 MMIO_D(RC6_LOCATION, D_SKL_PLUS); 3051 MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS, 3052 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 3053 MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, 3054 NULL, NULL); 3055 3056 /* TRTT */ 3057 MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 3058 MMIO_DFH(TRVATTL3PTRDW(1), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 3059 MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 3060 MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 3061 MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 3062 MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS, 3063 NULL, gen9_trtte_write); 3064 MMIO_DH(_MMIO(0x4dfc), D_SKL_PLUS, NULL, gen9_trtt_chicken_write); 3065 3066 MMIO_D(_MMIO(0x46430), D_SKL_PLUS); 3067 3068 MMIO_D(_MMIO(0x46520), D_SKL_PLUS); 3069 3070 MMIO_D(_MMIO(0xc403c), D_SKL_PLUS); 3071 MMIO_DFH(GEN8_GARBCNTL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 3072 MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write); 3073 3074 MMIO_D(_MMIO(0x65900), D_SKL_PLUS); 3075 MMIO_D(GEN6_STOLEN_RESERVED, D_SKL_PLUS); 3076 MMIO_D(_MMIO(0x4068), D_SKL_PLUS); 3077 MMIO_D(_MMIO(0x67054), D_SKL_PLUS); 3078 MMIO_D(_MMIO(0x6e560), D_SKL_PLUS); 3079 MMIO_D(_MMIO(0x6e554), D_SKL_PLUS); 3080 MMIO_D(_MMIO(0x2b20), D_SKL_PLUS); 3081 MMIO_D(_MMIO(0x65f00), D_SKL_PLUS); 3082 MMIO_D(_MMIO(0x65f08), D_SKL_PLUS); 3083 MMIO_D(_MMIO(0x320f0), D_SKL_PLUS); 3084 3085 MMIO_D(_MMIO(0x70034), D_SKL_PLUS); 3086 MMIO_D(_MMIO(0x71034), D_SKL_PLUS); 3087 MMIO_D(_MMIO(0x72034), D_SKL_PLUS); 3088 3089 MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A)), D_SKL_PLUS); 3090 MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B)), D_SKL_PLUS); 3091 MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C)), D_SKL_PLUS); 3092 MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A)), D_SKL_PLUS); 3093 MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B)), D_SKL_PLUS); 3094 MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C)), D_SKL_PLUS); 3095 MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A)), D_SKL_PLUS); 3096 MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)), D_SKL_PLUS); 3097 MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)), D_SKL_PLUS); 3098 3099 MMIO_D(_MMIO(0x44500), D_SKL_PLUS); 3100 #define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4) 3101 MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, 3102 NULL, csfe_chicken1_mmio_write); 3103 #undef CSFE_CHICKEN1_REG 3104 MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, 3105 NULL, NULL); 3106 MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, 3107 NULL, NULL); 3108 3109 MMIO_D(GAMT_CHKN_BIT_REG, D_KBL); 3110 MMIO_D(GEN9_CTX_PREEMPT_REG, D_KBL | D_SKL); 3111 3112 return 0; 3113 } 3114 3115 static int init_bxt_mmio_info(struct intel_gvt *gvt) 3116 { 3117 struct drm_i915_private *dev_priv = gvt->dev_priv; 3118 int ret; 3119 3120 MMIO_F(_MMIO(0x80000), 0x3000, 0, 0, 0, D_BXT, NULL, NULL); 3121 3122 MMIO_D(GEN7_SAMPLER_INSTDONE, D_BXT); 3123 MMIO_D(GEN7_ROW_INSTDONE, D_BXT); 3124 MMIO_D(GEN8_FAULT_TLB_DATA0, D_BXT); 3125 MMIO_D(GEN8_FAULT_TLB_DATA1, D_BXT); 3126 MMIO_D(ERROR_GEN6, D_BXT); 3127 MMIO_D(DONE_REG, D_BXT); 3128 MMIO_D(EIR, D_BXT); 3129 MMIO_D(PGTBL_ER, D_BXT); 3130 MMIO_D(_MMIO(0x4194), D_BXT); 3131 MMIO_D(_MMIO(0x4294), D_BXT); 3132 MMIO_D(_MMIO(0x4494), D_BXT); 3133 3134 MMIO_RING_D(RING_PSMI_CTL, D_BXT); 3135 MMIO_RING_D(RING_DMA_FADD, D_BXT); 3136 MMIO_RING_D(RING_DMA_FADD_UDW, D_BXT); 3137 MMIO_RING_D(RING_IPEHR, D_BXT); 3138 MMIO_RING_D(RING_INSTPS, D_BXT); 3139 MMIO_RING_D(RING_BBADDR_UDW, D_BXT); 3140 MMIO_RING_D(RING_BBSTATE, D_BXT); 3141 MMIO_RING_D(RING_IPEIR, D_BXT); 3142 3143 MMIO_F(SOFT_SCRATCH(0), 16 * 4, 0, 0, 0, D_BXT, NULL, NULL); 3144 3145 MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write); 3146 MMIO_D(BXT_RP_STATE_CAP, D_BXT); 3147 MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT, 3148 NULL, bxt_phy_ctl_family_write); 3149 MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT, 3150 NULL, bxt_phy_ctl_family_write); 3151 MMIO_D(BXT_PHY_CTL(PORT_A), D_BXT); 3152 MMIO_D(BXT_PHY_CTL(PORT_B), D_BXT); 3153 MMIO_D(BXT_PHY_CTL(PORT_C), D_BXT); 3154 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT, 3155 NULL, bxt_port_pll_enable_write); 3156 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT, 3157 NULL, bxt_port_pll_enable_write); 3158 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL, 3159 bxt_port_pll_enable_write); 3160 3161 MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY0), D_BXT); 3162 MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY0), D_BXT); 3163 MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY0), D_BXT); 3164 MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY0), D_BXT); 3165 MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY0), D_BXT); 3166 MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY0), D_BXT); 3167 MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY0), D_BXT); 3168 MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY0), D_BXT); 3169 MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY0), D_BXT); 3170 3171 MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY1), D_BXT); 3172 MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY1), D_BXT); 3173 MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY1), D_BXT); 3174 MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY1), D_BXT); 3175 MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY1), D_BXT); 3176 MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY1), D_BXT); 3177 MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY1), D_BXT); 3178 MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY1), D_BXT); 3179 MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY1), D_BXT); 3180 3181 MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH0), D_BXT); 3182 MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH0), D_BXT); 3183 MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH0), D_BXT); 3184 MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH0), D_BXT); 3185 MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH0), D_BXT); 3186 MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH0), D_BXT); 3187 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT, 3188 NULL, bxt_pcs_dw12_grp_write); 3189 MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH0), D_BXT); 3190 MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH0), D_BXT); 3191 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT, 3192 bxt_port_tx_dw3_read, NULL); 3193 MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH0), D_BXT); 3194 MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH0), D_BXT); 3195 MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH0), D_BXT); 3196 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT); 3197 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 1), D_BXT); 3198 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 2), D_BXT); 3199 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 3), D_BXT); 3200 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 0), D_BXT); 3201 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 1), D_BXT); 3202 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 2), D_BXT); 3203 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 3), D_BXT); 3204 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 6), D_BXT); 3205 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 8), D_BXT); 3206 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 9), D_BXT); 3207 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 10), D_BXT); 3208 3209 MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH1), D_BXT); 3210 MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH1), D_BXT); 3211 MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH1), D_BXT); 3212 MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH1), D_BXT); 3213 MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH1), D_BXT); 3214 MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH1), D_BXT); 3215 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT, 3216 NULL, bxt_pcs_dw12_grp_write); 3217 MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH1), D_BXT); 3218 MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH1), D_BXT); 3219 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT, 3220 bxt_port_tx_dw3_read, NULL); 3221 MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH1), D_BXT); 3222 MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH1), D_BXT); 3223 MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH1), D_BXT); 3224 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT); 3225 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 1), D_BXT); 3226 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 2), D_BXT); 3227 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 3), D_BXT); 3228 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 0), D_BXT); 3229 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 1), D_BXT); 3230 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 2), D_BXT); 3231 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 3), D_BXT); 3232 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 6), D_BXT); 3233 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 8), D_BXT); 3234 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 9), D_BXT); 3235 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 10), D_BXT); 3236 3237 MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY1, DPIO_CH0), D_BXT); 3238 MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY1, DPIO_CH0), D_BXT); 3239 MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY1, DPIO_CH0), D_BXT); 3240 MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY1, DPIO_CH0), D_BXT); 3241 MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY1, DPIO_CH0), D_BXT); 3242 MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY1, DPIO_CH0), D_BXT); 3243 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT, 3244 NULL, bxt_pcs_dw12_grp_write); 3245 MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY1, DPIO_CH0), D_BXT); 3246 MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY1, DPIO_CH0), D_BXT); 3247 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT, 3248 bxt_port_tx_dw3_read, NULL); 3249 MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY1, DPIO_CH0), D_BXT); 3250 MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY1, DPIO_CH0), D_BXT); 3251 MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY1, DPIO_CH0), D_BXT); 3252 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT); 3253 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 1), D_BXT); 3254 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 2), D_BXT); 3255 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 3), D_BXT); 3256 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 0), D_BXT); 3257 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 1), D_BXT); 3258 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 2), D_BXT); 3259 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 3), D_BXT); 3260 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 6), D_BXT); 3261 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 8), D_BXT); 3262 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 9), D_BXT); 3263 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 10), D_BXT); 3264 3265 MMIO_D(BXT_DE_PLL_CTL, D_BXT); 3266 MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write); 3267 MMIO_D(BXT_DSI_PLL_CTL, D_BXT); 3268 MMIO_D(BXT_DSI_PLL_ENABLE, D_BXT); 3269 3270 MMIO_D(GEN9_CLKGATE_DIS_0, D_BXT); 3271 MMIO_D(GEN9_CLKGATE_DIS_4, D_BXT); 3272 3273 MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_A), D_BXT); 3274 MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT); 3275 MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C), D_BXT); 3276 3277 MMIO_D(RC6_CTX_BASE, D_BXT); 3278 3279 MMIO_D(GEN8_PUSHBUS_CONTROL, D_BXT); 3280 MMIO_D(GEN8_PUSHBUS_ENABLE, D_BXT); 3281 MMIO_D(GEN8_PUSHBUS_SHIFT, D_BXT); 3282 MMIO_D(GEN6_GFXPAUSE, D_BXT); 3283 MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL); 3284 3285 MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL); 3286 3287 return 0; 3288 } 3289 3290 static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt, 3291 unsigned int offset) 3292 { 3293 unsigned long device = intel_gvt_get_device_type(gvt); 3294 struct gvt_mmio_block *block = gvt->mmio.mmio_block; 3295 int num = gvt->mmio.num_mmio_block; 3296 int i; 3297 3298 for (i = 0; i < num; i++, block++) { 3299 if (!(device & block->device)) 3300 continue; 3301 if (offset >= i915_mmio_reg_offset(block->offset) && 3302 offset < i915_mmio_reg_offset(block->offset) + block->size) 3303 return block; 3304 } 3305 return NULL; 3306 } 3307 3308 /** 3309 * intel_gvt_clean_mmio_info - clean up MMIO information table for GVT device 3310 * @gvt: GVT device 3311 * 3312 * This function is called at the driver unloading stage, to clean up the MMIO 3313 * information table of GVT device 3314 * 3315 */ 3316 void intel_gvt_clean_mmio_info(struct intel_gvt *gvt) 3317 { 3318 struct hlist_node *tmp; 3319 struct intel_gvt_mmio_info *e; 3320 int i; 3321 3322 hash_for_each_safe(gvt->mmio.mmio_info_table, i, tmp, e, node) 3323 kfree(e); 3324 3325 vfree(gvt->mmio.mmio_attribute); 3326 gvt->mmio.mmio_attribute = NULL; 3327 } 3328 3329 /* Special MMIO blocks. */ 3330 static struct gvt_mmio_block mmio_blocks[] = { 3331 {D_SKL_PLUS, _MMIO(CSR_MMIO_START_RANGE), 0x3000, NULL, NULL}, 3332 {D_ALL, _MMIO(MCHBAR_MIRROR_BASE_SNB), 0x40000, NULL, NULL}, 3333 {D_ALL, _MMIO(VGT_PVINFO_PAGE), VGT_PVINFO_SIZE, 3334 pvinfo_mmio_read, pvinfo_mmio_write}, 3335 {D_ALL, LGC_PALETTE(PIPE_A, 0), 1024, NULL, NULL}, 3336 {D_ALL, LGC_PALETTE(PIPE_B, 0), 1024, NULL, NULL}, 3337 {D_ALL, LGC_PALETTE(PIPE_C, 0), 1024, NULL, NULL}, 3338 }; 3339 3340 /** 3341 * intel_gvt_setup_mmio_info - setup MMIO information table for GVT device 3342 * @gvt: GVT device 3343 * 3344 * This function is called at the initialization stage, to setup the MMIO 3345 * information table for GVT device 3346 * 3347 * Returns: 3348 * zero on success, negative if failed. 3349 */ 3350 int intel_gvt_setup_mmio_info(struct intel_gvt *gvt) 3351 { 3352 struct intel_gvt_device_info *info = &gvt->device_info; 3353 struct drm_i915_private *dev_priv = gvt->dev_priv; 3354 int size = info->mmio_size / 4 * sizeof(*gvt->mmio.mmio_attribute); 3355 int ret; 3356 3357 gvt->mmio.mmio_attribute = vzalloc(size); 3358 if (!gvt->mmio.mmio_attribute) 3359 return -ENOMEM; 3360 3361 ret = init_generic_mmio_info(gvt); 3362 if (ret) 3363 goto err; 3364 3365 if (IS_BROADWELL(dev_priv)) { 3366 ret = init_broadwell_mmio_info(gvt); 3367 if (ret) 3368 goto err; 3369 } else if (IS_SKYLAKE(dev_priv) 3370 || IS_KABYLAKE(dev_priv) 3371 || IS_COFFEELAKE(dev_priv)) { 3372 ret = init_broadwell_mmio_info(gvt); 3373 if (ret) 3374 goto err; 3375 ret = init_skl_mmio_info(gvt); 3376 if (ret) 3377 goto err; 3378 } else if (IS_BROXTON(dev_priv)) { 3379 ret = init_broadwell_mmio_info(gvt); 3380 if (ret) 3381 goto err; 3382 ret = init_skl_mmio_info(gvt); 3383 if (ret) 3384 goto err; 3385 ret = init_bxt_mmio_info(gvt); 3386 if (ret) 3387 goto err; 3388 } 3389 3390 gvt->mmio.mmio_block = mmio_blocks; 3391 gvt->mmio.num_mmio_block = ARRAY_SIZE(mmio_blocks); 3392 3393 return 0; 3394 err: 3395 intel_gvt_clean_mmio_info(gvt); 3396 return ret; 3397 } 3398 3399 /** 3400 * intel_gvt_for_each_tracked_mmio - iterate each tracked mmio 3401 * @gvt: a GVT device 3402 * @handler: the handler 3403 * @data: private data given to handler 3404 * 3405 * Returns: 3406 * Zero on success, negative error code if failed. 3407 */ 3408 int intel_gvt_for_each_tracked_mmio(struct intel_gvt *gvt, 3409 int (*handler)(struct intel_gvt *gvt, u32 offset, void *data), 3410 void *data) 3411 { 3412 struct gvt_mmio_block *block = gvt->mmio.mmio_block; 3413 struct intel_gvt_mmio_info *e; 3414 int i, j, ret; 3415 3416 hash_for_each(gvt->mmio.mmio_info_table, i, e, node) { 3417 ret = handler(gvt, e->offset, data); 3418 if (ret) 3419 return ret; 3420 } 3421 3422 for (i = 0; i < gvt->mmio.num_mmio_block; i++, block++) { 3423 /* pvinfo data doesn't come from hw mmio */ 3424 if (i915_mmio_reg_offset(block->offset) == VGT_PVINFO_PAGE) 3425 continue; 3426 3427 for (j = 0; j < block->size; j += 4) { 3428 ret = handler(gvt, 3429 i915_mmio_reg_offset(block->offset) + j, 3430 data); 3431 if (ret) 3432 return ret; 3433 } 3434 } 3435 return 0; 3436 } 3437 3438 /** 3439 * intel_vgpu_default_mmio_read - default MMIO read handler 3440 * @vgpu: a vGPU 3441 * @offset: access offset 3442 * @p_data: data return buffer 3443 * @bytes: access data length 3444 * 3445 * Returns: 3446 * Zero on success, negative error code if failed. 3447 */ 3448 int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 3449 void *p_data, unsigned int bytes) 3450 { 3451 read_vreg(vgpu, offset, p_data, bytes); 3452 return 0; 3453 } 3454 3455 /** 3456 * intel_t_default_mmio_write - default MMIO write handler 3457 * @vgpu: a vGPU 3458 * @offset: access offset 3459 * @p_data: write data buffer 3460 * @bytes: access data length 3461 * 3462 * Returns: 3463 * Zero on success, negative error code if failed. 3464 */ 3465 int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 3466 void *p_data, unsigned int bytes) 3467 { 3468 write_vreg(vgpu, offset, p_data, bytes); 3469 return 0; 3470 } 3471 3472 /** 3473 * intel_vgpu_mask_mmio_write - write mask register 3474 * @vgpu: a vGPU 3475 * @offset: access offset 3476 * @p_data: write data buffer 3477 * @bytes: access data length 3478 * 3479 * Returns: 3480 * Zero on success, negative error code if failed. 3481 */ 3482 int intel_vgpu_mask_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 3483 void *p_data, unsigned int bytes) 3484 { 3485 u32 mask, old_vreg; 3486 3487 old_vreg = vgpu_vreg(vgpu, offset); 3488 write_vreg(vgpu, offset, p_data, bytes); 3489 mask = vgpu_vreg(vgpu, offset) >> 16; 3490 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask) | 3491 (vgpu_vreg(vgpu, offset) & mask); 3492 3493 return 0; 3494 } 3495 3496 /** 3497 * intel_gvt_in_force_nonpriv_whitelist - if a mmio is in whitelist to be 3498 * force-nopriv register 3499 * 3500 * @gvt: a GVT device 3501 * @offset: register offset 3502 * 3503 * Returns: 3504 * True if the register is in force-nonpriv whitelist; 3505 * False if outside; 3506 */ 3507 bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt, 3508 unsigned int offset) 3509 { 3510 return in_whitelist(offset); 3511 } 3512 3513 /** 3514 * intel_vgpu_mmio_reg_rw - emulate tracked mmio registers 3515 * @vgpu: a vGPU 3516 * @offset: register offset 3517 * @pdata: data buffer 3518 * @bytes: data length 3519 * @is_read: read or write 3520 * 3521 * Returns: 3522 * Zero on success, negative error code if failed. 3523 */ 3524 int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset, 3525 void *pdata, unsigned int bytes, bool is_read) 3526 { 3527 struct intel_gvt *gvt = vgpu->gvt; 3528 struct intel_gvt_mmio_info *mmio_info; 3529 struct gvt_mmio_block *mmio_block; 3530 gvt_mmio_func func; 3531 int ret; 3532 3533 if (WARN_ON(bytes > 8)) 3534 return -EINVAL; 3535 3536 /* 3537 * Handle special MMIO blocks. 3538 */ 3539 mmio_block = find_mmio_block(gvt, offset); 3540 if (mmio_block) { 3541 func = is_read ? mmio_block->read : mmio_block->write; 3542 if (func) 3543 return func(vgpu, offset, pdata, bytes); 3544 goto default_rw; 3545 } 3546 3547 /* 3548 * Normal tracked MMIOs. 3549 */ 3550 mmio_info = find_mmio_info(gvt, offset); 3551 if (!mmio_info) { 3552 gvt_dbg_mmio("untracked MMIO %08x len %d\n", offset, bytes); 3553 goto default_rw; 3554 } 3555 3556 if (is_read) 3557 return mmio_info->read(vgpu, offset, pdata, bytes); 3558 else { 3559 u64 ro_mask = mmio_info->ro_mask; 3560 u32 old_vreg = 0; 3561 u64 data = 0; 3562 3563 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) { 3564 old_vreg = vgpu_vreg(vgpu, offset); 3565 } 3566 3567 if (likely(!ro_mask)) 3568 ret = mmio_info->write(vgpu, offset, pdata, bytes); 3569 else if (!~ro_mask) { 3570 gvt_vgpu_err("try to write RO reg %x\n", offset); 3571 return 0; 3572 } else { 3573 /* keep the RO bits in the virtual register */ 3574 memcpy(&data, pdata, bytes); 3575 data &= ~ro_mask; 3576 data |= vgpu_vreg(vgpu, offset) & ro_mask; 3577 ret = mmio_info->write(vgpu, offset, &data, bytes); 3578 } 3579 3580 /* higher 16bits of mode ctl regs are mask bits for change */ 3581 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) { 3582 u32 mask = vgpu_vreg(vgpu, offset) >> 16; 3583 3584 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask) 3585 | (vgpu_vreg(vgpu, offset) & mask); 3586 } 3587 } 3588 3589 return ret; 3590 3591 default_rw: 3592 return is_read ? 3593 intel_vgpu_default_mmio_read(vgpu, offset, pdata, bytes) : 3594 intel_vgpu_default_mmio_write(vgpu, offset, pdata, bytes); 3595 } 3596