1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Kevin Tian <kevin.tian@intel.com> 25 * Eddie Dong <eddie.dong@intel.com> 26 * 27 * Contributors: 28 * Niu Bing <bing.niu@intel.com> 29 * Zhi Wang <zhi.a.wang@intel.com> 30 * 31 */ 32 33 #ifndef _GVT_H_ 34 #define _GVT_H_ 35 36 #include "debug.h" 37 #include "hypercall.h" 38 #include "mmio.h" 39 #include "reg.h" 40 #include "interrupt.h" 41 #include "gtt.h" 42 #include "display.h" 43 #include "edid.h" 44 #include "execlist.h" 45 #include "scheduler.h" 46 #include "sched_policy.h" 47 #include "render.h" 48 #include "cmd_parser.h" 49 50 #define GVT_MAX_VGPU 8 51 52 enum { 53 INTEL_GVT_HYPERVISOR_XEN = 0, 54 INTEL_GVT_HYPERVISOR_KVM, 55 }; 56 57 struct intel_gvt_host { 58 bool initialized; 59 int hypervisor_type; 60 struct intel_gvt_mpt *mpt; 61 }; 62 63 extern struct intel_gvt_host intel_gvt_host; 64 65 /* Describe per-platform limitations. */ 66 struct intel_gvt_device_info { 67 u32 max_support_vgpus; 68 u32 cfg_space_size; 69 u32 mmio_size; 70 u32 mmio_bar; 71 unsigned long msi_cap_offset; 72 u32 gtt_start_offset; 73 u32 gtt_entry_size; 74 u32 gtt_entry_size_shift; 75 int gmadr_bytes_in_cmd; 76 u32 max_surface_size; 77 }; 78 79 /* GM resources owned by a vGPU */ 80 struct intel_vgpu_gm { 81 u64 aperture_sz; 82 u64 hidden_sz; 83 struct drm_mm_node low_gm_node; 84 struct drm_mm_node high_gm_node; 85 }; 86 87 #define INTEL_GVT_MAX_NUM_FENCES 32 88 89 /* Fences owned by a vGPU */ 90 struct intel_vgpu_fence { 91 struct drm_i915_fence_reg *regs[INTEL_GVT_MAX_NUM_FENCES]; 92 u32 base; 93 u32 size; 94 }; 95 96 struct intel_vgpu_mmio { 97 void *vreg; 98 void *sreg; 99 bool disable_warn_untrack; 100 }; 101 102 #define INTEL_GVT_MAX_CFG_SPACE_SZ 256 103 #define INTEL_GVT_MAX_BAR_NUM 4 104 105 struct intel_vgpu_pci_bar { 106 u64 size; 107 bool tracked; 108 }; 109 110 struct intel_vgpu_cfg_space { 111 unsigned char virtual_cfg_space[INTEL_GVT_MAX_CFG_SPACE_SZ]; 112 struct intel_vgpu_pci_bar bar[INTEL_GVT_MAX_BAR_NUM]; 113 }; 114 115 #define vgpu_cfg_space(vgpu) ((vgpu)->cfg_space.virtual_cfg_space) 116 117 #define INTEL_GVT_MAX_PIPE 4 118 119 struct intel_vgpu_irq { 120 bool irq_warn_once[INTEL_GVT_EVENT_MAX]; 121 DECLARE_BITMAP(flip_done_event[INTEL_GVT_MAX_PIPE], 122 INTEL_GVT_EVENT_MAX); 123 }; 124 125 struct intel_vgpu_opregion { 126 void *va; 127 u32 gfn[INTEL_GVT_OPREGION_PAGES]; 128 struct page *pages[INTEL_GVT_OPREGION_PAGES]; 129 }; 130 131 #define vgpu_opregion(vgpu) (&(vgpu->opregion)) 132 133 #define INTEL_GVT_MAX_PORT 5 134 135 struct intel_vgpu_display { 136 struct intel_vgpu_i2c_edid i2c_edid; 137 struct intel_vgpu_port ports[INTEL_GVT_MAX_PORT]; 138 struct intel_vgpu_sbi sbi; 139 }; 140 141 struct intel_vgpu { 142 struct intel_gvt *gvt; 143 int id; 144 unsigned long handle; /* vGPU handle used by hypervisor MPT modules */ 145 bool active; 146 bool pv_notified; 147 bool failsafe; 148 bool resetting; 149 void *sched_data; 150 151 struct intel_vgpu_fence fence; 152 struct intel_vgpu_gm gm; 153 struct intel_vgpu_cfg_space cfg_space; 154 struct intel_vgpu_mmio mmio; 155 struct intel_vgpu_irq irq; 156 struct intel_vgpu_gtt gtt; 157 struct intel_vgpu_opregion opregion; 158 struct intel_vgpu_display display; 159 struct intel_vgpu_execlist execlist[I915_NUM_ENGINES]; 160 struct list_head workload_q_head[I915_NUM_ENGINES]; 161 struct kmem_cache *workloads; 162 atomic_t running_workload_num; 163 DECLARE_BITMAP(tlb_handle_pending, I915_NUM_ENGINES); 164 struct i915_gem_context *shadow_ctx; 165 166 #if IS_ENABLED(CONFIG_DRM_I915_GVT_KVMGT) 167 struct { 168 struct mdev_device *mdev; 169 struct vfio_region *region; 170 int num_regions; 171 struct eventfd_ctx *intx_trigger; 172 struct eventfd_ctx *msi_trigger; 173 struct rb_root cache; 174 struct mutex cache_lock; 175 struct notifier_block iommu_notifier; 176 struct notifier_block group_notifier; 177 struct kvm *kvm; 178 struct work_struct release_work; 179 atomic_t released; 180 } vdev; 181 #endif 182 }; 183 184 struct intel_gvt_gm { 185 unsigned long vgpu_allocated_low_gm_size; 186 unsigned long vgpu_allocated_high_gm_size; 187 }; 188 189 struct intel_gvt_fence { 190 unsigned long vgpu_allocated_fence_num; 191 }; 192 193 #define INTEL_GVT_MMIO_HASH_BITS 9 194 195 struct intel_gvt_mmio { 196 u32 *mmio_attribute; 197 DECLARE_HASHTABLE(mmio_info_table, INTEL_GVT_MMIO_HASH_BITS); 198 }; 199 200 struct intel_gvt_firmware { 201 void *cfg_space; 202 void *mmio; 203 bool firmware_loaded; 204 }; 205 206 struct intel_gvt_opregion { 207 void *opregion_va; 208 u32 opregion_pa; 209 }; 210 211 #define NR_MAX_INTEL_VGPU_TYPES 20 212 struct intel_vgpu_type { 213 char name[16]; 214 unsigned int avail_instance; 215 unsigned int low_gm_size; 216 unsigned int high_gm_size; 217 unsigned int fence; 218 enum intel_vgpu_edid resolution; 219 }; 220 221 struct intel_gvt { 222 struct mutex lock; 223 struct drm_i915_private *dev_priv; 224 struct idr vgpu_idr; /* vGPU IDR pool */ 225 226 struct intel_gvt_device_info device_info; 227 struct intel_gvt_gm gm; 228 struct intel_gvt_fence fence; 229 struct intel_gvt_mmio mmio; 230 struct intel_gvt_firmware firmware; 231 struct intel_gvt_irq irq; 232 struct intel_gvt_gtt gtt; 233 struct intel_gvt_opregion opregion; 234 struct intel_gvt_workload_scheduler scheduler; 235 struct notifier_block shadow_ctx_notifier_block[I915_NUM_ENGINES]; 236 DECLARE_HASHTABLE(cmd_table, GVT_CMD_HASH_BITS); 237 struct intel_vgpu_type *types; 238 unsigned int num_types; 239 240 struct task_struct *service_thread; 241 wait_queue_head_t service_thread_wq; 242 unsigned long service_request; 243 }; 244 245 static inline struct intel_gvt *to_gvt(struct drm_i915_private *i915) 246 { 247 return i915->gvt; 248 } 249 250 enum { 251 INTEL_GVT_REQUEST_EMULATE_VBLANK = 0, 252 }; 253 254 static inline void intel_gvt_request_service(struct intel_gvt *gvt, 255 int service) 256 { 257 set_bit(service, (void *)&gvt->service_request); 258 wake_up(&gvt->service_thread_wq); 259 } 260 261 void intel_gvt_free_firmware(struct intel_gvt *gvt); 262 int intel_gvt_load_firmware(struct intel_gvt *gvt); 263 264 /* Aperture/GM space definitions for GVT device */ 265 #define MB_TO_BYTES(mb) ((mb) << 20ULL) 266 #define BYTES_TO_MB(b) ((b) >> 20ULL) 267 268 #define HOST_LOW_GM_SIZE MB_TO_BYTES(128) 269 #define HOST_HIGH_GM_SIZE MB_TO_BYTES(384) 270 #define HOST_FENCE 4 271 272 /* Aperture/GM space definitions for GVT device */ 273 #define gvt_aperture_sz(gvt) (gvt->dev_priv->ggtt.mappable_end) 274 #define gvt_aperture_pa_base(gvt) (gvt->dev_priv->ggtt.mappable_base) 275 276 #define gvt_ggtt_gm_sz(gvt) (gvt->dev_priv->ggtt.base.total) 277 #define gvt_ggtt_sz(gvt) \ 278 ((gvt->dev_priv->ggtt.base.total >> PAGE_SHIFT) << 3) 279 #define gvt_hidden_sz(gvt) (gvt_ggtt_gm_sz(gvt) - gvt_aperture_sz(gvt)) 280 281 #define gvt_aperture_gmadr_base(gvt) (0) 282 #define gvt_aperture_gmadr_end(gvt) (gvt_aperture_gmadr_base(gvt) \ 283 + gvt_aperture_sz(gvt) - 1) 284 285 #define gvt_hidden_gmadr_base(gvt) (gvt_aperture_gmadr_base(gvt) \ 286 + gvt_aperture_sz(gvt)) 287 #define gvt_hidden_gmadr_end(gvt) (gvt_hidden_gmadr_base(gvt) \ 288 + gvt_hidden_sz(gvt) - 1) 289 290 #define gvt_fence_sz(gvt) (gvt->dev_priv->num_fence_regs) 291 292 /* Aperture/GM space definitions for vGPU */ 293 #define vgpu_aperture_offset(vgpu) ((vgpu)->gm.low_gm_node.start) 294 #define vgpu_hidden_offset(vgpu) ((vgpu)->gm.high_gm_node.start) 295 #define vgpu_aperture_sz(vgpu) ((vgpu)->gm.aperture_sz) 296 #define vgpu_hidden_sz(vgpu) ((vgpu)->gm.hidden_sz) 297 298 #define vgpu_aperture_pa_base(vgpu) \ 299 (gvt_aperture_pa_base(vgpu->gvt) + vgpu_aperture_offset(vgpu)) 300 301 #define vgpu_ggtt_gm_sz(vgpu) ((vgpu)->gm.aperture_sz + (vgpu)->gm.hidden_sz) 302 303 #define vgpu_aperture_pa_end(vgpu) \ 304 (vgpu_aperture_pa_base(vgpu) + vgpu_aperture_sz(vgpu) - 1) 305 306 #define vgpu_aperture_gmadr_base(vgpu) (vgpu_aperture_offset(vgpu)) 307 #define vgpu_aperture_gmadr_end(vgpu) \ 308 (vgpu_aperture_gmadr_base(vgpu) + vgpu_aperture_sz(vgpu) - 1) 309 310 #define vgpu_hidden_gmadr_base(vgpu) (vgpu_hidden_offset(vgpu)) 311 #define vgpu_hidden_gmadr_end(vgpu) \ 312 (vgpu_hidden_gmadr_base(vgpu) + vgpu_hidden_sz(vgpu) - 1) 313 314 #define vgpu_fence_base(vgpu) (vgpu->fence.base) 315 #define vgpu_fence_sz(vgpu) (vgpu->fence.size) 316 317 struct intel_vgpu_creation_params { 318 __u64 handle; 319 __u64 low_gm_sz; /* in MB */ 320 __u64 high_gm_sz; /* in MB */ 321 __u64 fence_sz; 322 __u64 resolution; 323 __s32 primary; 324 __u64 vgpu_id; 325 }; 326 327 int intel_vgpu_alloc_resource(struct intel_vgpu *vgpu, 328 struct intel_vgpu_creation_params *param); 329 void intel_vgpu_reset_resource(struct intel_vgpu *vgpu); 330 void intel_vgpu_free_resource(struct intel_vgpu *vgpu); 331 void intel_vgpu_write_fence(struct intel_vgpu *vgpu, 332 u32 fence, u64 value); 333 334 /* Macros for easily accessing vGPU virtual/shadow register */ 335 #define vgpu_vreg(vgpu, reg) \ 336 (*(u32 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg))) 337 #define vgpu_vreg8(vgpu, reg) \ 338 (*(u8 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg))) 339 #define vgpu_vreg16(vgpu, reg) \ 340 (*(u16 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg))) 341 #define vgpu_vreg64(vgpu, reg) \ 342 (*(u64 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg))) 343 #define vgpu_sreg(vgpu, reg) \ 344 (*(u32 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg))) 345 #define vgpu_sreg8(vgpu, reg) \ 346 (*(u8 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg))) 347 #define vgpu_sreg16(vgpu, reg) \ 348 (*(u16 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg))) 349 #define vgpu_sreg64(vgpu, reg) \ 350 (*(u64 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg))) 351 352 #define for_each_active_vgpu(gvt, vgpu, id) \ 353 idr_for_each_entry((&(gvt)->vgpu_idr), (vgpu), (id)) \ 354 for_each_if(vgpu->active) 355 356 static inline void intel_vgpu_write_pci_bar(struct intel_vgpu *vgpu, 357 u32 offset, u32 val, bool low) 358 { 359 u32 *pval; 360 361 /* BAR offset should be 32 bits algiend */ 362 offset = rounddown(offset, 4); 363 pval = (u32 *)(vgpu_cfg_space(vgpu) + offset); 364 365 if (low) { 366 /* 367 * only update bit 31 - bit 4, 368 * leave the bit 3 - bit 0 unchanged. 369 */ 370 *pval = (val & GENMASK(31, 4)) | (*pval & GENMASK(3, 0)); 371 } else { 372 *pval = val; 373 } 374 } 375 376 int intel_gvt_init_vgpu_types(struct intel_gvt *gvt); 377 void intel_gvt_clean_vgpu_types(struct intel_gvt *gvt); 378 379 struct intel_vgpu *intel_gvt_create_vgpu(struct intel_gvt *gvt, 380 struct intel_vgpu_type *type); 381 void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu); 382 void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr, 383 unsigned int engine_mask); 384 void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu); 385 386 387 /* validating GM functions */ 388 #define vgpu_gmadr_is_aperture(vgpu, gmadr) \ 389 ((gmadr >= vgpu_aperture_gmadr_base(vgpu)) && \ 390 (gmadr <= vgpu_aperture_gmadr_end(vgpu))) 391 392 #define vgpu_gmadr_is_hidden(vgpu, gmadr) \ 393 ((gmadr >= vgpu_hidden_gmadr_base(vgpu)) && \ 394 (gmadr <= vgpu_hidden_gmadr_end(vgpu))) 395 396 #define vgpu_gmadr_is_valid(vgpu, gmadr) \ 397 ((vgpu_gmadr_is_aperture(vgpu, gmadr) || \ 398 (vgpu_gmadr_is_hidden(vgpu, gmadr)))) 399 400 #define gvt_gmadr_is_aperture(gvt, gmadr) \ 401 ((gmadr >= gvt_aperture_gmadr_base(gvt)) && \ 402 (gmadr <= gvt_aperture_gmadr_end(gvt))) 403 404 #define gvt_gmadr_is_hidden(gvt, gmadr) \ 405 ((gmadr >= gvt_hidden_gmadr_base(gvt)) && \ 406 (gmadr <= gvt_hidden_gmadr_end(gvt))) 407 408 #define gvt_gmadr_is_valid(gvt, gmadr) \ 409 (gvt_gmadr_is_aperture(gvt, gmadr) || \ 410 gvt_gmadr_is_hidden(gvt, gmadr)) 411 412 bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size); 413 int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr); 414 int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u64 h_addr, u64 *g_addr); 415 int intel_gvt_ggtt_index_g2h(struct intel_vgpu *vgpu, unsigned long g_index, 416 unsigned long *h_index); 417 int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_index, 418 unsigned long *g_index); 419 420 void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu, 421 bool primary); 422 void intel_vgpu_reset_cfg_space(struct intel_vgpu *vgpu); 423 424 int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset, 425 void *p_data, unsigned int bytes); 426 427 int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset, 428 void *p_data, unsigned int bytes); 429 430 void intel_gvt_clean_opregion(struct intel_gvt *gvt); 431 int intel_gvt_init_opregion(struct intel_gvt *gvt); 432 433 void intel_vgpu_clean_opregion(struct intel_vgpu *vgpu); 434 int intel_vgpu_init_opregion(struct intel_vgpu *vgpu, u32 gpa); 435 436 int intel_vgpu_emulate_opregion_request(struct intel_vgpu *vgpu, u32 swsci); 437 void populate_pvinfo_page(struct intel_vgpu *vgpu); 438 439 struct intel_gvt_ops { 440 int (*emulate_cfg_read)(struct intel_vgpu *, unsigned int, void *, 441 unsigned int); 442 int (*emulate_cfg_write)(struct intel_vgpu *, unsigned int, void *, 443 unsigned int); 444 int (*emulate_mmio_read)(struct intel_vgpu *, u64, void *, 445 unsigned int); 446 int (*emulate_mmio_write)(struct intel_vgpu *, u64, void *, 447 unsigned int); 448 struct intel_vgpu *(*vgpu_create)(struct intel_gvt *, 449 struct intel_vgpu_type *); 450 void (*vgpu_destroy)(struct intel_vgpu *); 451 void (*vgpu_reset)(struct intel_vgpu *); 452 }; 453 454 455 enum { 456 GVT_FAILSAFE_UNSUPPORTED_GUEST, 457 GVT_FAILSAFE_INSUFFICIENT_RESOURCE, 458 }; 459 460 #include "mpt.h" 461 462 #endif 463