1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Kevin Tian <kevin.tian@intel.com> 25 * Eddie Dong <eddie.dong@intel.com> 26 * 27 * Contributors: 28 * Niu Bing <bing.niu@intel.com> 29 * Zhi Wang <zhi.a.wang@intel.com> 30 * 31 */ 32 33 #ifndef _GVT_H_ 34 #define _GVT_H_ 35 36 #include "debug.h" 37 #include "hypercall.h" 38 #include "mmio.h" 39 #include "reg.h" 40 #include "interrupt.h" 41 #include "gtt.h" 42 #include "display.h" 43 #include "edid.h" 44 #include "execlist.h" 45 #include "scheduler.h" 46 #include "sched_policy.h" 47 #include "mmio_context.h" 48 #include "cmd_parser.h" 49 #include "fb_decoder.h" 50 #include "dmabuf.h" 51 #include "page_track.h" 52 53 #define GVT_MAX_VGPU 8 54 55 enum { 56 INTEL_GVT_HYPERVISOR_XEN = 0, 57 INTEL_GVT_HYPERVISOR_KVM, 58 }; 59 60 struct intel_gvt_host { 61 bool initialized; 62 int hypervisor_type; 63 struct intel_gvt_mpt *mpt; 64 }; 65 66 extern struct intel_gvt_host intel_gvt_host; 67 68 /* Describe per-platform limitations. */ 69 struct intel_gvt_device_info { 70 u32 max_support_vgpus; 71 u32 cfg_space_size; 72 u32 mmio_size; 73 u32 mmio_bar; 74 unsigned long msi_cap_offset; 75 u32 gtt_start_offset; 76 u32 gtt_entry_size; 77 u32 gtt_entry_size_shift; 78 int gmadr_bytes_in_cmd; 79 u32 max_surface_size; 80 }; 81 82 /* GM resources owned by a vGPU */ 83 struct intel_vgpu_gm { 84 u64 aperture_sz; 85 u64 hidden_sz; 86 struct drm_mm_node low_gm_node; 87 struct drm_mm_node high_gm_node; 88 }; 89 90 #define INTEL_GVT_MAX_NUM_FENCES 32 91 92 /* Fences owned by a vGPU */ 93 struct intel_vgpu_fence { 94 struct drm_i915_fence_reg *regs[INTEL_GVT_MAX_NUM_FENCES]; 95 u32 base; 96 u32 size; 97 }; 98 99 struct intel_vgpu_mmio { 100 void *vreg; 101 void *sreg; 102 }; 103 104 #define INTEL_GVT_MAX_BAR_NUM 4 105 106 struct intel_vgpu_pci_bar { 107 u64 size; 108 bool tracked; 109 }; 110 111 struct intel_vgpu_cfg_space { 112 unsigned char virtual_cfg_space[PCI_CFG_SPACE_EXP_SIZE]; 113 struct intel_vgpu_pci_bar bar[INTEL_GVT_MAX_BAR_NUM]; 114 }; 115 116 #define vgpu_cfg_space(vgpu) ((vgpu)->cfg_space.virtual_cfg_space) 117 118 #define INTEL_GVT_MAX_PIPE 4 119 120 struct intel_vgpu_irq { 121 bool irq_warn_once[INTEL_GVT_EVENT_MAX]; 122 DECLARE_BITMAP(flip_done_event[INTEL_GVT_MAX_PIPE], 123 INTEL_GVT_EVENT_MAX); 124 }; 125 126 struct intel_vgpu_opregion { 127 bool mapped; 128 void *va; 129 u32 gfn[INTEL_GVT_OPREGION_PAGES]; 130 }; 131 132 #define vgpu_opregion(vgpu) (&(vgpu->opregion)) 133 134 struct intel_vgpu_display { 135 struct intel_vgpu_i2c_edid i2c_edid; 136 struct intel_vgpu_port ports[I915_MAX_PORTS]; 137 struct intel_vgpu_sbi sbi; 138 }; 139 140 struct vgpu_sched_ctl { 141 int weight; 142 }; 143 144 enum { 145 INTEL_VGPU_EXECLIST_SUBMISSION = 1, 146 INTEL_VGPU_GUC_SUBMISSION, 147 }; 148 149 struct intel_vgpu_submission_ops { 150 const char *name; 151 int (*init)(struct intel_vgpu *vgpu, unsigned long engine_mask); 152 void (*clean)(struct intel_vgpu *vgpu, unsigned long engine_mask); 153 void (*reset)(struct intel_vgpu *vgpu, unsigned long engine_mask); 154 }; 155 156 struct intel_vgpu_submission { 157 struct intel_vgpu_execlist execlist[I915_NUM_ENGINES]; 158 struct list_head workload_q_head[I915_NUM_ENGINES]; 159 struct kmem_cache *workloads; 160 atomic_t running_workload_num; 161 struct i915_gem_context *shadow_ctx; 162 union { 163 u64 i915_context_pml4; 164 u64 i915_context_pdps[GEN8_3LVL_PDPES]; 165 }; 166 DECLARE_BITMAP(shadow_ctx_desc_updated, I915_NUM_ENGINES); 167 DECLARE_BITMAP(tlb_handle_pending, I915_NUM_ENGINES); 168 void *ring_scan_buffer[I915_NUM_ENGINES]; 169 int ring_scan_buffer_size[I915_NUM_ENGINES]; 170 const struct intel_vgpu_submission_ops *ops; 171 int virtual_submission_interface; 172 bool active; 173 }; 174 175 struct intel_vgpu { 176 struct intel_gvt *gvt; 177 struct mutex vgpu_lock; 178 int id; 179 unsigned long handle; /* vGPU handle used by hypervisor MPT modules */ 180 bool active; 181 bool pv_notified; 182 bool failsafe; 183 unsigned int resetting_eng; 184 185 /* Both sched_data and sched_ctl can be seen a part of the global gvt 186 * scheduler structure. So below 2 vgpu data are protected 187 * by sched_lock, not vgpu_lock. 188 */ 189 void *sched_data; 190 struct vgpu_sched_ctl sched_ctl; 191 192 struct intel_vgpu_fence fence; 193 struct intel_vgpu_gm gm; 194 struct intel_vgpu_cfg_space cfg_space; 195 struct intel_vgpu_mmio mmio; 196 struct intel_vgpu_irq irq; 197 struct intel_vgpu_gtt gtt; 198 struct intel_vgpu_opregion opregion; 199 struct intel_vgpu_display display; 200 struct intel_vgpu_submission submission; 201 struct radix_tree_root page_track_tree; 202 u32 hws_pga[I915_NUM_ENGINES]; 203 204 struct dentry *debugfs; 205 206 #if IS_ENABLED(CONFIG_DRM_I915_GVT_KVMGT) 207 struct { 208 struct mdev_device *mdev; 209 struct vfio_region *region; 210 int num_regions; 211 struct eventfd_ctx *intx_trigger; 212 struct eventfd_ctx *msi_trigger; 213 214 /* 215 * Two caches are used to avoid mapping duplicated pages (eg. 216 * scratch pages). This help to reduce dma setup overhead. 217 */ 218 struct rb_root gfn_cache; 219 struct rb_root dma_addr_cache; 220 unsigned long nr_cache_entries; 221 struct mutex cache_lock; 222 223 struct notifier_block iommu_notifier; 224 struct notifier_block group_notifier; 225 struct kvm *kvm; 226 struct work_struct release_work; 227 atomic_t released; 228 struct vfio_device *vfio_device; 229 } vdev; 230 #endif 231 232 struct list_head dmabuf_obj_list_head; 233 struct mutex dmabuf_lock; 234 struct idr object_idr; 235 236 struct completion vblank_done; 237 238 u32 scan_nonprivbb; 239 }; 240 241 /* validating GM healthy status*/ 242 #define vgpu_is_vm_unhealthy(ret_val) \ 243 (((ret_val) == -EBADRQC) || ((ret_val) == -EFAULT)) 244 245 struct intel_gvt_gm { 246 unsigned long vgpu_allocated_low_gm_size; 247 unsigned long vgpu_allocated_high_gm_size; 248 }; 249 250 struct intel_gvt_fence { 251 unsigned long vgpu_allocated_fence_num; 252 }; 253 254 /* Special MMIO blocks. */ 255 struct gvt_mmio_block { 256 unsigned int device; 257 i915_reg_t offset; 258 unsigned int size; 259 gvt_mmio_func read; 260 gvt_mmio_func write; 261 }; 262 263 #define INTEL_GVT_MMIO_HASH_BITS 11 264 265 struct intel_gvt_mmio { 266 u8 *mmio_attribute; 267 /* Register contains RO bits */ 268 #define F_RO (1 << 0) 269 /* Register contains graphics address */ 270 #define F_GMADR (1 << 1) 271 /* Mode mask registers with high 16 bits as the mask bits */ 272 #define F_MODE_MASK (1 << 2) 273 /* This reg can be accessed by GPU commands */ 274 #define F_CMD_ACCESS (1 << 3) 275 /* This reg has been accessed by a VM */ 276 #define F_ACCESSED (1 << 4) 277 /* This reg has been accessed through GPU commands */ 278 #define F_CMD_ACCESSED (1 << 5) 279 /* This reg could be accessed by unaligned address */ 280 #define F_UNALIGN (1 << 6) 281 /* This reg is saved/restored in context */ 282 #define F_IN_CTX (1 << 7) 283 284 struct gvt_mmio_block *mmio_block; 285 unsigned int num_mmio_block; 286 287 DECLARE_HASHTABLE(mmio_info_table, INTEL_GVT_MMIO_HASH_BITS); 288 unsigned long num_tracked_mmio; 289 }; 290 291 struct intel_gvt_firmware { 292 void *cfg_space; 293 void *mmio; 294 bool firmware_loaded; 295 }; 296 297 #define NR_MAX_INTEL_VGPU_TYPES 20 298 struct intel_vgpu_type { 299 char name[16]; 300 unsigned int avail_instance; 301 unsigned int low_gm_size; 302 unsigned int high_gm_size; 303 unsigned int fence; 304 unsigned int weight; 305 enum intel_vgpu_edid resolution; 306 }; 307 308 struct intel_gvt { 309 /* GVT scope lock, protect GVT itself, and all resource currently 310 * not yet protected by special locks(vgpu and scheduler lock). 311 */ 312 struct mutex lock; 313 /* scheduler scope lock, protect gvt and vgpu schedule related data */ 314 struct mutex sched_lock; 315 316 struct drm_i915_private *dev_priv; 317 struct idr vgpu_idr; /* vGPU IDR pool */ 318 319 struct intel_gvt_device_info device_info; 320 struct intel_gvt_gm gm; 321 struct intel_gvt_fence fence; 322 struct intel_gvt_mmio mmio; 323 struct intel_gvt_firmware firmware; 324 struct intel_gvt_irq irq; 325 struct intel_gvt_gtt gtt; 326 struct intel_gvt_workload_scheduler scheduler; 327 struct notifier_block shadow_ctx_notifier_block[I915_NUM_ENGINES]; 328 DECLARE_HASHTABLE(cmd_table, GVT_CMD_HASH_BITS); 329 struct intel_vgpu_type *types; 330 unsigned int num_types; 331 struct intel_vgpu *idle_vgpu; 332 333 struct task_struct *service_thread; 334 wait_queue_head_t service_thread_wq; 335 336 /* service_request is always used in bit operation, we should always 337 * use it with atomic bit ops so that no need to use gvt big lock. 338 */ 339 unsigned long service_request; 340 341 struct { 342 struct engine_mmio *mmio; 343 int ctx_mmio_count[I915_NUM_ENGINES]; 344 } engine_mmio_list; 345 346 struct dentry *debugfs_root; 347 }; 348 349 static inline struct intel_gvt *to_gvt(struct drm_i915_private *i915) 350 { 351 return i915->gvt; 352 } 353 354 enum { 355 INTEL_GVT_REQUEST_EMULATE_VBLANK = 0, 356 357 /* Scheduling trigger by timer */ 358 INTEL_GVT_REQUEST_SCHED = 1, 359 360 /* Scheduling trigger by event */ 361 INTEL_GVT_REQUEST_EVENT_SCHED = 2, 362 }; 363 364 static inline void intel_gvt_request_service(struct intel_gvt *gvt, 365 int service) 366 { 367 set_bit(service, (void *)&gvt->service_request); 368 wake_up(&gvt->service_thread_wq); 369 } 370 371 void intel_gvt_free_firmware(struct intel_gvt *gvt); 372 int intel_gvt_load_firmware(struct intel_gvt *gvt); 373 374 /* Aperture/GM space definitions for GVT device */ 375 #define MB_TO_BYTES(mb) ((mb) << 20ULL) 376 #define BYTES_TO_MB(b) ((b) >> 20ULL) 377 378 #define HOST_LOW_GM_SIZE MB_TO_BYTES(128) 379 #define HOST_HIGH_GM_SIZE MB_TO_BYTES(384) 380 #define HOST_FENCE 4 381 382 /* Aperture/GM space definitions for GVT device */ 383 #define gvt_aperture_sz(gvt) (gvt->dev_priv->ggtt.mappable_end) 384 #define gvt_aperture_pa_base(gvt) (gvt->dev_priv->ggtt.gmadr.start) 385 386 #define gvt_ggtt_gm_sz(gvt) (gvt->dev_priv->ggtt.vm.total) 387 #define gvt_ggtt_sz(gvt) \ 388 ((gvt->dev_priv->ggtt.vm.total >> PAGE_SHIFT) << 3) 389 #define gvt_hidden_sz(gvt) (gvt_ggtt_gm_sz(gvt) - gvt_aperture_sz(gvt)) 390 391 #define gvt_aperture_gmadr_base(gvt) (0) 392 #define gvt_aperture_gmadr_end(gvt) (gvt_aperture_gmadr_base(gvt) \ 393 + gvt_aperture_sz(gvt) - 1) 394 395 #define gvt_hidden_gmadr_base(gvt) (gvt_aperture_gmadr_base(gvt) \ 396 + gvt_aperture_sz(gvt)) 397 #define gvt_hidden_gmadr_end(gvt) (gvt_hidden_gmadr_base(gvt) \ 398 + gvt_hidden_sz(gvt) - 1) 399 400 #define gvt_fence_sz(gvt) (gvt->dev_priv->num_fence_regs) 401 402 /* Aperture/GM space definitions for vGPU */ 403 #define vgpu_aperture_offset(vgpu) ((vgpu)->gm.low_gm_node.start) 404 #define vgpu_hidden_offset(vgpu) ((vgpu)->gm.high_gm_node.start) 405 #define vgpu_aperture_sz(vgpu) ((vgpu)->gm.aperture_sz) 406 #define vgpu_hidden_sz(vgpu) ((vgpu)->gm.hidden_sz) 407 408 #define vgpu_aperture_pa_base(vgpu) \ 409 (gvt_aperture_pa_base(vgpu->gvt) + vgpu_aperture_offset(vgpu)) 410 411 #define vgpu_ggtt_gm_sz(vgpu) ((vgpu)->gm.aperture_sz + (vgpu)->gm.hidden_sz) 412 413 #define vgpu_aperture_pa_end(vgpu) \ 414 (vgpu_aperture_pa_base(vgpu) + vgpu_aperture_sz(vgpu) - 1) 415 416 #define vgpu_aperture_gmadr_base(vgpu) (vgpu_aperture_offset(vgpu)) 417 #define vgpu_aperture_gmadr_end(vgpu) \ 418 (vgpu_aperture_gmadr_base(vgpu) + vgpu_aperture_sz(vgpu) - 1) 419 420 #define vgpu_hidden_gmadr_base(vgpu) (vgpu_hidden_offset(vgpu)) 421 #define vgpu_hidden_gmadr_end(vgpu) \ 422 (vgpu_hidden_gmadr_base(vgpu) + vgpu_hidden_sz(vgpu) - 1) 423 424 #define vgpu_fence_base(vgpu) (vgpu->fence.base) 425 #define vgpu_fence_sz(vgpu) (vgpu->fence.size) 426 427 struct intel_vgpu_creation_params { 428 __u64 handle; 429 __u64 low_gm_sz; /* in MB */ 430 __u64 high_gm_sz; /* in MB */ 431 __u64 fence_sz; 432 __u64 resolution; 433 __s32 primary; 434 __u64 vgpu_id; 435 436 __u32 weight; 437 }; 438 439 int intel_vgpu_alloc_resource(struct intel_vgpu *vgpu, 440 struct intel_vgpu_creation_params *param); 441 void intel_vgpu_reset_resource(struct intel_vgpu *vgpu); 442 void intel_vgpu_free_resource(struct intel_vgpu *vgpu); 443 void intel_vgpu_write_fence(struct intel_vgpu *vgpu, 444 u32 fence, u64 value); 445 446 /* Macros for easily accessing vGPU virtual/shadow register. 447 Explicitly seperate use for typed MMIO reg or real offset.*/ 448 #define vgpu_vreg_t(vgpu, reg) \ 449 (*(u32 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg))) 450 #define vgpu_vreg(vgpu, offset) \ 451 (*(u32 *)(vgpu->mmio.vreg + (offset))) 452 #define vgpu_vreg64_t(vgpu, reg) \ 453 (*(u64 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg))) 454 #define vgpu_vreg64(vgpu, offset) \ 455 (*(u64 *)(vgpu->mmio.vreg + (offset))) 456 #define vgpu_sreg_t(vgpu, reg) \ 457 (*(u32 *)(vgpu->mmio.sreg + i915_mmio_reg_offset(reg))) 458 #define vgpu_sreg(vgpu, offset) \ 459 (*(u32 *)(vgpu->mmio.sreg + (offset))) 460 461 #define for_each_active_vgpu(gvt, vgpu, id) \ 462 idr_for_each_entry((&(gvt)->vgpu_idr), (vgpu), (id)) \ 463 for_each_if(vgpu->active) 464 465 static inline void intel_vgpu_write_pci_bar(struct intel_vgpu *vgpu, 466 u32 offset, u32 val, bool low) 467 { 468 u32 *pval; 469 470 /* BAR offset should be 32 bits algiend */ 471 offset = rounddown(offset, 4); 472 pval = (u32 *)(vgpu_cfg_space(vgpu) + offset); 473 474 if (low) { 475 /* 476 * only update bit 31 - bit 4, 477 * leave the bit 3 - bit 0 unchanged. 478 */ 479 *pval = (val & GENMASK(31, 4)) | (*pval & GENMASK(3, 0)); 480 } else { 481 *pval = val; 482 } 483 } 484 485 int intel_gvt_init_vgpu_types(struct intel_gvt *gvt); 486 void intel_gvt_clean_vgpu_types(struct intel_gvt *gvt); 487 488 struct intel_vgpu *intel_gvt_create_idle_vgpu(struct intel_gvt *gvt); 489 void intel_gvt_destroy_idle_vgpu(struct intel_vgpu *vgpu); 490 struct intel_vgpu *intel_gvt_create_vgpu(struct intel_gvt *gvt, 491 struct intel_vgpu_type *type); 492 void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu); 493 void intel_gvt_release_vgpu(struct intel_vgpu *vgpu); 494 void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr, 495 unsigned int engine_mask); 496 void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu); 497 void intel_gvt_activate_vgpu(struct intel_vgpu *vgpu); 498 void intel_gvt_deactivate_vgpu(struct intel_vgpu *vgpu); 499 500 /* validating GM functions */ 501 #define vgpu_gmadr_is_aperture(vgpu, gmadr) \ 502 ((gmadr >= vgpu_aperture_gmadr_base(vgpu)) && \ 503 (gmadr <= vgpu_aperture_gmadr_end(vgpu))) 504 505 #define vgpu_gmadr_is_hidden(vgpu, gmadr) \ 506 ((gmadr >= vgpu_hidden_gmadr_base(vgpu)) && \ 507 (gmadr <= vgpu_hidden_gmadr_end(vgpu))) 508 509 #define vgpu_gmadr_is_valid(vgpu, gmadr) \ 510 ((vgpu_gmadr_is_aperture(vgpu, gmadr) || \ 511 (vgpu_gmadr_is_hidden(vgpu, gmadr)))) 512 513 #define gvt_gmadr_is_aperture(gvt, gmadr) \ 514 ((gmadr >= gvt_aperture_gmadr_base(gvt)) && \ 515 (gmadr <= gvt_aperture_gmadr_end(gvt))) 516 517 #define gvt_gmadr_is_hidden(gvt, gmadr) \ 518 ((gmadr >= gvt_hidden_gmadr_base(gvt)) && \ 519 (gmadr <= gvt_hidden_gmadr_end(gvt))) 520 521 #define gvt_gmadr_is_valid(gvt, gmadr) \ 522 (gvt_gmadr_is_aperture(gvt, gmadr) || \ 523 gvt_gmadr_is_hidden(gvt, gmadr)) 524 525 bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size); 526 int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr); 527 int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u64 h_addr, u64 *g_addr); 528 int intel_gvt_ggtt_index_g2h(struct intel_vgpu *vgpu, unsigned long g_index, 529 unsigned long *h_index); 530 int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_index, 531 unsigned long *g_index); 532 533 void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu, 534 bool primary); 535 void intel_vgpu_reset_cfg_space(struct intel_vgpu *vgpu); 536 537 int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset, 538 void *p_data, unsigned int bytes); 539 540 int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset, 541 void *p_data, unsigned int bytes); 542 543 static inline u64 intel_vgpu_get_bar_gpa(struct intel_vgpu *vgpu, int bar) 544 { 545 /* We are 64bit bar. */ 546 return (*(u64 *)(vgpu->cfg_space.virtual_cfg_space + bar)) & 547 PCI_BASE_ADDRESS_MEM_MASK; 548 } 549 550 void intel_vgpu_clean_opregion(struct intel_vgpu *vgpu); 551 int intel_vgpu_init_opregion(struct intel_vgpu *vgpu); 552 int intel_vgpu_opregion_base_write_handler(struct intel_vgpu *vgpu, u32 gpa); 553 554 int intel_vgpu_emulate_opregion_request(struct intel_vgpu *vgpu, u32 swsci); 555 void populate_pvinfo_page(struct intel_vgpu *vgpu); 556 557 int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload); 558 void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason); 559 560 struct intel_gvt_ops { 561 int (*emulate_cfg_read)(struct intel_vgpu *, unsigned int, void *, 562 unsigned int); 563 int (*emulate_cfg_write)(struct intel_vgpu *, unsigned int, void *, 564 unsigned int); 565 int (*emulate_mmio_read)(struct intel_vgpu *, u64, void *, 566 unsigned int); 567 int (*emulate_mmio_write)(struct intel_vgpu *, u64, void *, 568 unsigned int); 569 struct intel_vgpu *(*vgpu_create)(struct intel_gvt *, 570 struct intel_vgpu_type *); 571 void (*vgpu_destroy)(struct intel_vgpu *vgpu); 572 void (*vgpu_release)(struct intel_vgpu *vgpu); 573 void (*vgpu_reset)(struct intel_vgpu *); 574 void (*vgpu_activate)(struct intel_vgpu *); 575 void (*vgpu_deactivate)(struct intel_vgpu *); 576 struct intel_vgpu_type *(*gvt_find_vgpu_type)(struct intel_gvt *gvt, 577 const char *name); 578 bool (*get_gvt_attrs)(struct attribute ***type_attrs, 579 struct attribute_group ***intel_vgpu_type_groups); 580 int (*vgpu_query_plane)(struct intel_vgpu *vgpu, void *); 581 int (*vgpu_get_dmabuf)(struct intel_vgpu *vgpu, unsigned int); 582 int (*write_protect_handler)(struct intel_vgpu *, u64, void *, 583 unsigned int); 584 }; 585 586 587 enum { 588 GVT_FAILSAFE_UNSUPPORTED_GUEST, 589 GVT_FAILSAFE_INSUFFICIENT_RESOURCE, 590 GVT_FAILSAFE_GUEST_ERR, 591 }; 592 593 static inline void mmio_hw_access_pre(struct drm_i915_private *dev_priv) 594 { 595 intel_runtime_pm_get(dev_priv); 596 } 597 598 static inline void mmio_hw_access_post(struct drm_i915_private *dev_priv) 599 { 600 intel_runtime_pm_put(dev_priv); 601 } 602 603 /** 604 * intel_gvt_mmio_set_accessed - mark a MMIO has been accessed 605 * @gvt: a GVT device 606 * @offset: register offset 607 * 608 */ 609 static inline void intel_gvt_mmio_set_accessed( 610 struct intel_gvt *gvt, unsigned int offset) 611 { 612 gvt->mmio.mmio_attribute[offset >> 2] |= F_ACCESSED; 613 } 614 615 /** 616 * intel_gvt_mmio_is_cmd_accessed - mark a MMIO could be accessed by command 617 * @gvt: a GVT device 618 * @offset: register offset 619 * 620 */ 621 static inline bool intel_gvt_mmio_is_cmd_access( 622 struct intel_gvt *gvt, unsigned int offset) 623 { 624 return gvt->mmio.mmio_attribute[offset >> 2] & F_CMD_ACCESS; 625 } 626 627 /** 628 * intel_gvt_mmio_is_unalign - mark a MMIO could be accessed unaligned 629 * @gvt: a GVT device 630 * @offset: register offset 631 * 632 */ 633 static inline bool intel_gvt_mmio_is_unalign( 634 struct intel_gvt *gvt, unsigned int offset) 635 { 636 return gvt->mmio.mmio_attribute[offset >> 2] & F_UNALIGN; 637 } 638 639 /** 640 * intel_gvt_mmio_set_cmd_accessed - mark a MMIO has been accessed by command 641 * @gvt: a GVT device 642 * @offset: register offset 643 * 644 */ 645 static inline void intel_gvt_mmio_set_cmd_accessed( 646 struct intel_gvt *gvt, unsigned int offset) 647 { 648 gvt->mmio.mmio_attribute[offset >> 2] |= F_CMD_ACCESSED; 649 } 650 651 /** 652 * intel_gvt_mmio_has_mode_mask - if a MMIO has a mode mask 653 * @gvt: a GVT device 654 * @offset: register offset 655 * 656 * Returns: 657 * True if a MMIO has a mode mask in its higher 16 bits, false if it isn't. 658 * 659 */ 660 static inline bool intel_gvt_mmio_has_mode_mask( 661 struct intel_gvt *gvt, unsigned int offset) 662 { 663 return gvt->mmio.mmio_attribute[offset >> 2] & F_MODE_MASK; 664 } 665 666 /** 667 * intel_gvt_mmio_is_in_ctx - check if a MMIO has in-ctx mask 668 * @gvt: a GVT device 669 * @offset: register offset 670 * 671 * Returns: 672 * True if a MMIO has a in-context mask, false if it isn't. 673 * 674 */ 675 static inline bool intel_gvt_mmio_is_in_ctx( 676 struct intel_gvt *gvt, unsigned int offset) 677 { 678 return gvt->mmio.mmio_attribute[offset >> 2] & F_IN_CTX; 679 } 680 681 /** 682 * intel_gvt_mmio_set_in_ctx - mask a MMIO in logical context 683 * @gvt: a GVT device 684 * @offset: register offset 685 * 686 */ 687 static inline void intel_gvt_mmio_set_in_ctx( 688 struct intel_gvt *gvt, unsigned int offset) 689 { 690 gvt->mmio.mmio_attribute[offset >> 2] |= F_IN_CTX; 691 } 692 693 int intel_gvt_debugfs_add_vgpu(struct intel_vgpu *vgpu); 694 void intel_gvt_debugfs_remove_vgpu(struct intel_vgpu *vgpu); 695 int intel_gvt_debugfs_init(struct intel_gvt *gvt); 696 void intel_gvt_debugfs_clean(struct intel_gvt *gvt); 697 698 699 #include "trace.h" 700 #include "mpt.h" 701 702 #endif 703