1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Kevin Tian <kevin.tian@intel.com> 25 * Eddie Dong <eddie.dong@intel.com> 26 * 27 * Contributors: 28 * Niu Bing <bing.niu@intel.com> 29 * Zhi Wang <zhi.a.wang@intel.com> 30 * 31 */ 32 33 #ifndef _GVT_H_ 34 #define _GVT_H_ 35 36 #include <uapi/linux/pci_regs.h> 37 #include <linux/kvm_host.h> 38 #include <linux/vfio.h> 39 40 #include "i915_drv.h" 41 #include "intel_gvt.h" 42 43 #include "debug.h" 44 #include "mmio.h" 45 #include "reg.h" 46 #include "interrupt.h" 47 #include "gtt.h" 48 #include "display.h" 49 #include "edid.h" 50 #include "execlist.h" 51 #include "scheduler.h" 52 #include "sched_policy.h" 53 #include "mmio_context.h" 54 #include "cmd_parser.h" 55 #include "fb_decoder.h" 56 #include "dmabuf.h" 57 #include "page_track.h" 58 59 #define GVT_MAX_VGPU 8 60 61 /* Describe per-platform limitations. */ 62 struct intel_gvt_device_info { 63 u32 max_support_vgpus; 64 u32 cfg_space_size; 65 u32 mmio_size; 66 u32 mmio_bar; 67 unsigned long msi_cap_offset; 68 u32 gtt_start_offset; 69 u32 gtt_entry_size; 70 u32 gtt_entry_size_shift; 71 int gmadr_bytes_in_cmd; 72 u32 max_surface_size; 73 }; 74 75 /* GM resources owned by a vGPU */ 76 struct intel_vgpu_gm { 77 u64 aperture_sz; 78 u64 hidden_sz; 79 struct drm_mm_node low_gm_node; 80 struct drm_mm_node high_gm_node; 81 }; 82 83 #define INTEL_GVT_MAX_NUM_FENCES 32 84 85 /* Fences owned by a vGPU */ 86 struct intel_vgpu_fence { 87 struct i915_fence_reg *regs[INTEL_GVT_MAX_NUM_FENCES]; 88 u32 base; 89 u32 size; 90 }; 91 92 struct intel_vgpu_mmio { 93 void *vreg; 94 }; 95 96 #define INTEL_GVT_MAX_BAR_NUM 4 97 98 struct intel_vgpu_pci_bar { 99 u64 size; 100 bool tracked; 101 }; 102 103 struct intel_vgpu_cfg_space { 104 unsigned char virtual_cfg_space[PCI_CFG_SPACE_EXP_SIZE]; 105 struct intel_vgpu_pci_bar bar[INTEL_GVT_MAX_BAR_NUM]; 106 u32 pmcsr_off; 107 }; 108 109 #define vgpu_cfg_space(vgpu) ((vgpu)->cfg_space.virtual_cfg_space) 110 111 struct intel_vgpu_irq { 112 bool irq_warn_once[INTEL_GVT_EVENT_MAX]; 113 DECLARE_BITMAP(flip_done_event[I915_MAX_PIPES], 114 INTEL_GVT_EVENT_MAX); 115 }; 116 117 struct intel_vgpu_opregion { 118 bool mapped; 119 void *va; 120 u32 gfn[INTEL_GVT_OPREGION_PAGES]; 121 }; 122 123 #define vgpu_opregion(vgpu) (&(vgpu->opregion)) 124 125 struct intel_vgpu_display { 126 struct intel_vgpu_i2c_edid i2c_edid; 127 struct intel_vgpu_port ports[I915_MAX_PORTS]; 128 struct intel_vgpu_sbi sbi; 129 enum port port_num; 130 }; 131 132 struct vgpu_sched_ctl { 133 int weight; 134 }; 135 136 enum { 137 INTEL_VGPU_EXECLIST_SUBMISSION = 1, 138 INTEL_VGPU_GUC_SUBMISSION, 139 }; 140 141 struct intel_vgpu_submission_ops { 142 const char *name; 143 int (*init)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask); 144 void (*clean)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask); 145 void (*reset)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask); 146 }; 147 148 struct intel_vgpu_submission { 149 struct intel_vgpu_execlist execlist[I915_NUM_ENGINES]; 150 struct list_head workload_q_head[I915_NUM_ENGINES]; 151 struct intel_context *shadow[I915_NUM_ENGINES]; 152 struct kmem_cache *workloads; 153 atomic_t running_workload_num; 154 union { 155 u64 i915_context_pml4; 156 u64 i915_context_pdps[GEN8_3LVL_PDPES]; 157 }; 158 DECLARE_BITMAP(shadow_ctx_desc_updated, I915_NUM_ENGINES); 159 DECLARE_BITMAP(tlb_handle_pending, I915_NUM_ENGINES); 160 void *ring_scan_buffer[I915_NUM_ENGINES]; 161 int ring_scan_buffer_size[I915_NUM_ENGINES]; 162 const struct intel_vgpu_submission_ops *ops; 163 int virtual_submission_interface; 164 bool active; 165 struct { 166 u32 lrca; 167 bool valid; 168 u64 ring_context_gpa; 169 } last_ctx[I915_NUM_ENGINES]; 170 }; 171 172 #define KVMGT_DEBUGFS_FILENAME "kvmgt_nr_cache_entries" 173 174 struct intel_vgpu { 175 struct intel_gvt *gvt; 176 struct mutex vgpu_lock; 177 int id; 178 bool active; 179 bool attached; 180 bool pv_notified; 181 bool failsafe; 182 unsigned int resetting_eng; 183 184 /* Both sched_data and sched_ctl can be seen a part of the global gvt 185 * scheduler structure. So below 2 vgpu data are protected 186 * by sched_lock, not vgpu_lock. 187 */ 188 void *sched_data; 189 struct vgpu_sched_ctl sched_ctl; 190 191 struct intel_vgpu_fence fence; 192 struct intel_vgpu_gm gm; 193 struct intel_vgpu_cfg_space cfg_space; 194 struct intel_vgpu_mmio mmio; 195 struct intel_vgpu_irq irq; 196 struct intel_vgpu_gtt gtt; 197 struct intel_vgpu_opregion opregion; 198 struct intel_vgpu_display display; 199 struct intel_vgpu_submission submission; 200 struct radix_tree_root page_track_tree; 201 u32 hws_pga[I915_NUM_ENGINES]; 202 /* Set on PCI_D3, reset on DMLR, not reflecting the actual PM state */ 203 bool d3_entered; 204 205 struct dentry *debugfs; 206 207 struct list_head dmabuf_obj_list_head; 208 struct mutex dmabuf_lock; 209 struct idr object_idr; 210 struct intel_vgpu_vblank_timer vblank_timer; 211 212 u32 scan_nonprivbb; 213 214 struct vfio_device vfio_device; 215 struct vfio_region *region; 216 int num_regions; 217 struct eventfd_ctx *intx_trigger; 218 struct eventfd_ctx *msi_trigger; 219 220 /* 221 * Two caches are used to avoid mapping duplicated pages (eg. 222 * scratch pages). This help to reduce dma setup overhead. 223 */ 224 struct rb_root gfn_cache; 225 struct rb_root dma_addr_cache; 226 unsigned long nr_cache_entries; 227 struct mutex cache_lock; 228 229 struct notifier_block iommu_notifier; 230 struct notifier_block group_notifier; 231 struct kvm *kvm; 232 struct work_struct release_work; 233 atomic_t released; 234 struct vfio_group *vfio_group; 235 236 struct kvm_page_track_notifier_node track_node; 237 #define NR_BKT (1 << 18) 238 struct hlist_head ptable[NR_BKT]; 239 #undef NR_BKT 240 }; 241 242 /* validating GM healthy status*/ 243 #define vgpu_is_vm_unhealthy(ret_val) \ 244 (((ret_val) == -EBADRQC) || ((ret_val) == -EFAULT)) 245 246 struct intel_gvt_gm { 247 unsigned long vgpu_allocated_low_gm_size; 248 unsigned long vgpu_allocated_high_gm_size; 249 }; 250 251 struct intel_gvt_fence { 252 unsigned long vgpu_allocated_fence_num; 253 }; 254 255 /* Special MMIO blocks. */ 256 struct gvt_mmio_block { 257 unsigned int device; 258 i915_reg_t offset; 259 unsigned int size; 260 gvt_mmio_func read; 261 gvt_mmio_func write; 262 }; 263 264 #define INTEL_GVT_MMIO_HASH_BITS 11 265 266 struct intel_gvt_mmio { 267 u16 *mmio_attribute; 268 /* Register contains RO bits */ 269 #define F_RO (1 << 0) 270 /* Register contains graphics address */ 271 #define F_GMADR (1 << 1) 272 /* Mode mask registers with high 16 bits as the mask bits */ 273 #define F_MODE_MASK (1 << 2) 274 /* This reg can be accessed by GPU commands */ 275 #define F_CMD_ACCESS (1 << 3) 276 /* This reg has been accessed by a VM */ 277 #define F_ACCESSED (1 << 4) 278 /* This reg requires save & restore during host PM suspend/resume */ 279 #define F_PM_SAVE (1 << 5) 280 /* This reg could be accessed by unaligned address */ 281 #define F_UNALIGN (1 << 6) 282 /* This reg is in GVT's mmio save-restor list and in hardware 283 * logical context image 284 */ 285 #define F_SR_IN_CTX (1 << 7) 286 /* Value of command write of this reg needs to be patched */ 287 #define F_CMD_WRITE_PATCH (1 << 8) 288 289 struct gvt_mmio_block *mmio_block; 290 unsigned int num_mmio_block; 291 292 DECLARE_HASHTABLE(mmio_info_table, INTEL_GVT_MMIO_HASH_BITS); 293 unsigned long num_tracked_mmio; 294 }; 295 296 struct intel_gvt_firmware { 297 void *cfg_space; 298 void *mmio; 299 bool firmware_loaded; 300 }; 301 302 #define NR_MAX_INTEL_VGPU_TYPES 20 303 struct intel_vgpu_type { 304 char name[16]; 305 unsigned int avail_instance; 306 unsigned int low_gm_size; 307 unsigned int high_gm_size; 308 unsigned int fence; 309 unsigned int weight; 310 enum intel_vgpu_edid resolution; 311 }; 312 313 struct intel_gvt { 314 /* GVT scope lock, protect GVT itself, and all resource currently 315 * not yet protected by special locks(vgpu and scheduler lock). 316 */ 317 struct mutex lock; 318 /* scheduler scope lock, protect gvt and vgpu schedule related data */ 319 struct mutex sched_lock; 320 321 struct intel_gt *gt; 322 struct idr vgpu_idr; /* vGPU IDR pool */ 323 324 struct intel_gvt_device_info device_info; 325 struct intel_gvt_gm gm; 326 struct intel_gvt_fence fence; 327 struct intel_gvt_mmio mmio; 328 struct intel_gvt_firmware firmware; 329 struct intel_gvt_irq irq; 330 struct intel_gvt_gtt gtt; 331 struct intel_gvt_workload_scheduler scheduler; 332 struct notifier_block shadow_ctx_notifier_block[I915_NUM_ENGINES]; 333 DECLARE_HASHTABLE(cmd_table, GVT_CMD_HASH_BITS); 334 struct intel_vgpu_type *types; 335 unsigned int num_types; 336 struct intel_vgpu *idle_vgpu; 337 338 struct task_struct *service_thread; 339 wait_queue_head_t service_thread_wq; 340 341 /* service_request is always used in bit operation, we should always 342 * use it with atomic bit ops so that no need to use gvt big lock. 343 */ 344 unsigned long service_request; 345 346 struct { 347 struct engine_mmio *mmio; 348 int ctx_mmio_count[I915_NUM_ENGINES]; 349 u32 *tlb_mmio_offset_list; 350 u32 tlb_mmio_offset_list_cnt; 351 u32 *mocs_mmio_offset_list; 352 u32 mocs_mmio_offset_list_cnt; 353 } engine_mmio_list; 354 bool is_reg_whitelist_updated; 355 356 struct dentry *debugfs_root; 357 }; 358 359 static inline struct intel_gvt *to_gvt(struct drm_i915_private *i915) 360 { 361 return i915->gvt; 362 } 363 364 enum { 365 /* Scheduling trigger by timer */ 366 INTEL_GVT_REQUEST_SCHED = 0, 367 368 /* Scheduling trigger by event */ 369 INTEL_GVT_REQUEST_EVENT_SCHED = 1, 370 371 /* per-vGPU vblank emulation request */ 372 INTEL_GVT_REQUEST_EMULATE_VBLANK = 2, 373 INTEL_GVT_REQUEST_EMULATE_VBLANK_MAX = INTEL_GVT_REQUEST_EMULATE_VBLANK 374 + GVT_MAX_VGPU, 375 }; 376 377 static inline void intel_gvt_request_service(struct intel_gvt *gvt, 378 int service) 379 { 380 set_bit(service, (void *)&gvt->service_request); 381 wake_up(&gvt->service_thread_wq); 382 } 383 384 void intel_gvt_free_firmware(struct intel_gvt *gvt); 385 int intel_gvt_load_firmware(struct intel_gvt *gvt); 386 387 /* Aperture/GM space definitions for GVT device */ 388 #define MB_TO_BYTES(mb) ((mb) << 20ULL) 389 #define BYTES_TO_MB(b) ((b) >> 20ULL) 390 391 #define HOST_LOW_GM_SIZE MB_TO_BYTES(128) 392 #define HOST_HIGH_GM_SIZE MB_TO_BYTES(384) 393 #define HOST_FENCE 4 394 395 #define gvt_to_ggtt(gvt) ((gvt)->gt->ggtt) 396 397 /* Aperture/GM space definitions for GVT device */ 398 #define gvt_aperture_sz(gvt) gvt_to_ggtt(gvt)->mappable_end 399 #define gvt_aperture_pa_base(gvt) gvt_to_ggtt(gvt)->gmadr.start 400 401 #define gvt_ggtt_gm_sz(gvt) gvt_to_ggtt(gvt)->vm.total 402 #define gvt_ggtt_sz(gvt) (gvt_to_ggtt(gvt)->vm.total >> PAGE_SHIFT << 3) 403 #define gvt_hidden_sz(gvt) (gvt_ggtt_gm_sz(gvt) - gvt_aperture_sz(gvt)) 404 405 #define gvt_aperture_gmadr_base(gvt) (0) 406 #define gvt_aperture_gmadr_end(gvt) (gvt_aperture_gmadr_base(gvt) \ 407 + gvt_aperture_sz(gvt) - 1) 408 409 #define gvt_hidden_gmadr_base(gvt) (gvt_aperture_gmadr_base(gvt) \ 410 + gvt_aperture_sz(gvt)) 411 #define gvt_hidden_gmadr_end(gvt) (gvt_hidden_gmadr_base(gvt) \ 412 + gvt_hidden_sz(gvt) - 1) 413 414 #define gvt_fence_sz(gvt) (gvt_to_ggtt(gvt)->num_fences) 415 416 /* Aperture/GM space definitions for vGPU */ 417 #define vgpu_aperture_offset(vgpu) ((vgpu)->gm.low_gm_node.start) 418 #define vgpu_hidden_offset(vgpu) ((vgpu)->gm.high_gm_node.start) 419 #define vgpu_aperture_sz(vgpu) ((vgpu)->gm.aperture_sz) 420 #define vgpu_hidden_sz(vgpu) ((vgpu)->gm.hidden_sz) 421 422 #define vgpu_aperture_pa_base(vgpu) \ 423 (gvt_aperture_pa_base(vgpu->gvt) + vgpu_aperture_offset(vgpu)) 424 425 #define vgpu_ggtt_gm_sz(vgpu) ((vgpu)->gm.aperture_sz + (vgpu)->gm.hidden_sz) 426 427 #define vgpu_aperture_pa_end(vgpu) \ 428 (vgpu_aperture_pa_base(vgpu) + vgpu_aperture_sz(vgpu) - 1) 429 430 #define vgpu_aperture_gmadr_base(vgpu) (vgpu_aperture_offset(vgpu)) 431 #define vgpu_aperture_gmadr_end(vgpu) \ 432 (vgpu_aperture_gmadr_base(vgpu) + vgpu_aperture_sz(vgpu) - 1) 433 434 #define vgpu_hidden_gmadr_base(vgpu) (vgpu_hidden_offset(vgpu)) 435 #define vgpu_hidden_gmadr_end(vgpu) \ 436 (vgpu_hidden_gmadr_base(vgpu) + vgpu_hidden_sz(vgpu) - 1) 437 438 #define vgpu_fence_base(vgpu) (vgpu->fence.base) 439 #define vgpu_fence_sz(vgpu) (vgpu->fence.size) 440 441 /* ring context size i.e. the first 0x50 dwords*/ 442 #define RING_CTX_SIZE 320 443 444 struct intel_vgpu_creation_params { 445 __u64 low_gm_sz; /* in MB */ 446 __u64 high_gm_sz; /* in MB */ 447 __u64 fence_sz; 448 __u64 resolution; 449 __s32 primary; 450 __u64 vgpu_id; 451 452 __u32 weight; 453 }; 454 455 int intel_vgpu_alloc_resource(struct intel_vgpu *vgpu, 456 struct intel_vgpu_creation_params *param); 457 void intel_vgpu_reset_resource(struct intel_vgpu *vgpu); 458 void intel_vgpu_free_resource(struct intel_vgpu *vgpu); 459 void intel_vgpu_write_fence(struct intel_vgpu *vgpu, 460 u32 fence, u64 value); 461 462 /* Macros for easily accessing vGPU virtual/shadow register. 463 Explicitly seperate use for typed MMIO reg or real offset.*/ 464 #define vgpu_vreg_t(vgpu, reg) \ 465 (*(u32 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg))) 466 #define vgpu_vreg(vgpu, offset) \ 467 (*(u32 *)(vgpu->mmio.vreg + (offset))) 468 #define vgpu_vreg64_t(vgpu, reg) \ 469 (*(u64 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg))) 470 #define vgpu_vreg64(vgpu, offset) \ 471 (*(u64 *)(vgpu->mmio.vreg + (offset))) 472 473 #define for_each_active_vgpu(gvt, vgpu, id) \ 474 idr_for_each_entry((&(gvt)->vgpu_idr), (vgpu), (id)) \ 475 for_each_if(vgpu->active) 476 477 static inline void intel_vgpu_write_pci_bar(struct intel_vgpu *vgpu, 478 u32 offset, u32 val, bool low) 479 { 480 u32 *pval; 481 482 /* BAR offset should be 32 bits algiend */ 483 offset = rounddown(offset, 4); 484 pval = (u32 *)(vgpu_cfg_space(vgpu) + offset); 485 486 if (low) { 487 /* 488 * only update bit 31 - bit 4, 489 * leave the bit 3 - bit 0 unchanged. 490 */ 491 *pval = (val & GENMASK(31, 4)) | (*pval & GENMASK(3, 0)); 492 } else { 493 *pval = val; 494 } 495 } 496 497 int intel_gvt_init_vgpu_types(struct intel_gvt *gvt); 498 void intel_gvt_clean_vgpu_types(struct intel_gvt *gvt); 499 500 struct intel_vgpu *intel_gvt_create_idle_vgpu(struct intel_gvt *gvt); 501 void intel_gvt_destroy_idle_vgpu(struct intel_vgpu *vgpu); 502 struct intel_vgpu *intel_gvt_create_vgpu(struct intel_gvt *gvt, 503 struct intel_vgpu_type *type); 504 void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu); 505 void intel_gvt_release_vgpu(struct intel_vgpu *vgpu); 506 void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr, 507 intel_engine_mask_t engine_mask); 508 void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu); 509 void intel_gvt_activate_vgpu(struct intel_vgpu *vgpu); 510 void intel_gvt_deactivate_vgpu(struct intel_vgpu *vgpu); 511 512 int intel_gvt_set_opregion(struct intel_vgpu *vgpu); 513 int intel_gvt_set_edid(struct intel_vgpu *vgpu, int port_num); 514 515 /* validating GM functions */ 516 #define vgpu_gmadr_is_aperture(vgpu, gmadr) \ 517 ((gmadr >= vgpu_aperture_gmadr_base(vgpu)) && \ 518 (gmadr <= vgpu_aperture_gmadr_end(vgpu))) 519 520 #define vgpu_gmadr_is_hidden(vgpu, gmadr) \ 521 ((gmadr >= vgpu_hidden_gmadr_base(vgpu)) && \ 522 (gmadr <= vgpu_hidden_gmadr_end(vgpu))) 523 524 #define vgpu_gmadr_is_valid(vgpu, gmadr) \ 525 ((vgpu_gmadr_is_aperture(vgpu, gmadr) || \ 526 (vgpu_gmadr_is_hidden(vgpu, gmadr)))) 527 528 #define gvt_gmadr_is_aperture(gvt, gmadr) \ 529 ((gmadr >= gvt_aperture_gmadr_base(gvt)) && \ 530 (gmadr <= gvt_aperture_gmadr_end(gvt))) 531 532 #define gvt_gmadr_is_hidden(gvt, gmadr) \ 533 ((gmadr >= gvt_hidden_gmadr_base(gvt)) && \ 534 (gmadr <= gvt_hidden_gmadr_end(gvt))) 535 536 #define gvt_gmadr_is_valid(gvt, gmadr) \ 537 (gvt_gmadr_is_aperture(gvt, gmadr) || \ 538 gvt_gmadr_is_hidden(gvt, gmadr)) 539 540 bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size); 541 int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr); 542 int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u64 h_addr, u64 *g_addr); 543 int intel_gvt_ggtt_index_g2h(struct intel_vgpu *vgpu, unsigned long g_index, 544 unsigned long *h_index); 545 int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_index, 546 unsigned long *g_index); 547 548 void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu, 549 bool primary); 550 void intel_vgpu_reset_cfg_space(struct intel_vgpu *vgpu); 551 552 int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset, 553 void *p_data, unsigned int bytes); 554 555 int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset, 556 void *p_data, unsigned int bytes); 557 558 void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected); 559 560 static inline u64 intel_vgpu_get_bar_gpa(struct intel_vgpu *vgpu, int bar) 561 { 562 /* We are 64bit bar. */ 563 return (*(u64 *)(vgpu->cfg_space.virtual_cfg_space + bar)) & 564 PCI_BASE_ADDRESS_MEM_MASK; 565 } 566 567 void intel_vgpu_clean_opregion(struct intel_vgpu *vgpu); 568 int intel_vgpu_init_opregion(struct intel_vgpu *vgpu); 569 int intel_vgpu_opregion_base_write_handler(struct intel_vgpu *vgpu, u32 gpa); 570 571 int intel_vgpu_emulate_opregion_request(struct intel_vgpu *vgpu, u32 swsci); 572 void populate_pvinfo_page(struct intel_vgpu *vgpu); 573 574 int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload); 575 void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason); 576 void intel_vgpu_detach_regions(struct intel_vgpu *vgpu); 577 578 enum { 579 GVT_FAILSAFE_UNSUPPORTED_GUEST, 580 GVT_FAILSAFE_INSUFFICIENT_RESOURCE, 581 GVT_FAILSAFE_GUEST_ERR, 582 }; 583 584 static inline void mmio_hw_access_pre(struct intel_gt *gt) 585 { 586 intel_runtime_pm_get(gt->uncore->rpm); 587 } 588 589 static inline void mmio_hw_access_post(struct intel_gt *gt) 590 { 591 intel_runtime_pm_put_unchecked(gt->uncore->rpm); 592 } 593 594 /** 595 * intel_gvt_mmio_set_accessed - mark a MMIO has been accessed 596 * @gvt: a GVT device 597 * @offset: register offset 598 * 599 */ 600 static inline void intel_gvt_mmio_set_accessed( 601 struct intel_gvt *gvt, unsigned int offset) 602 { 603 gvt->mmio.mmio_attribute[offset >> 2] |= F_ACCESSED; 604 } 605 606 /** 607 * intel_gvt_mmio_is_cmd_accessible - if a MMIO could be accessed by command 608 * @gvt: a GVT device 609 * @offset: register offset 610 * 611 * Returns: 612 * True if an MMIO is able to be accessed by GPU commands 613 */ 614 static inline bool intel_gvt_mmio_is_cmd_accessible( 615 struct intel_gvt *gvt, unsigned int offset) 616 { 617 return gvt->mmio.mmio_attribute[offset >> 2] & F_CMD_ACCESS; 618 } 619 620 /** 621 * intel_gvt_mmio_set_cmd_accessible - 622 * mark a MMIO could be accessible by command 623 * @gvt: a GVT device 624 * @offset: register offset 625 * 626 */ 627 static inline void intel_gvt_mmio_set_cmd_accessible( 628 struct intel_gvt *gvt, unsigned int offset) 629 { 630 gvt->mmio.mmio_attribute[offset >> 2] |= F_CMD_ACCESS; 631 } 632 633 /** 634 * intel_gvt_mmio_is_unalign - mark a MMIO could be accessed unaligned 635 * @gvt: a GVT device 636 * @offset: register offset 637 * 638 */ 639 static inline bool intel_gvt_mmio_is_unalign( 640 struct intel_gvt *gvt, unsigned int offset) 641 { 642 return gvt->mmio.mmio_attribute[offset >> 2] & F_UNALIGN; 643 } 644 645 /** 646 * intel_gvt_mmio_has_mode_mask - if a MMIO has a mode mask 647 * @gvt: a GVT device 648 * @offset: register offset 649 * 650 * Returns: 651 * True if a MMIO has a mode mask in its higher 16 bits, false if it isn't. 652 * 653 */ 654 static inline bool intel_gvt_mmio_has_mode_mask( 655 struct intel_gvt *gvt, unsigned int offset) 656 { 657 return gvt->mmio.mmio_attribute[offset >> 2] & F_MODE_MASK; 658 } 659 660 /** 661 * intel_gvt_mmio_is_sr_in_ctx - 662 * check if an MMIO has F_SR_IN_CTX mask 663 * @gvt: a GVT device 664 * @offset: register offset 665 * 666 * Returns: 667 * True if an MMIO has an F_SR_IN_CTX mask, false if it isn't. 668 * 669 */ 670 static inline bool intel_gvt_mmio_is_sr_in_ctx( 671 struct intel_gvt *gvt, unsigned int offset) 672 { 673 return gvt->mmio.mmio_attribute[offset >> 2] & F_SR_IN_CTX; 674 } 675 676 /** 677 * intel_gvt_mmio_set_sr_in_ctx - 678 * mask an MMIO in GVT's mmio save-restore list and also 679 * in hardware logical context image 680 * @gvt: a GVT device 681 * @offset: register offset 682 * 683 */ 684 static inline void intel_gvt_mmio_set_sr_in_ctx( 685 struct intel_gvt *gvt, unsigned int offset) 686 { 687 gvt->mmio.mmio_attribute[offset >> 2] |= F_SR_IN_CTX; 688 } 689 690 void intel_gvt_debugfs_add_vgpu(struct intel_vgpu *vgpu); 691 /** 692 * intel_gvt_mmio_set_cmd_write_patch - 693 * mark an MMIO if its cmd write needs to be 694 * patched 695 * @gvt: a GVT device 696 * @offset: register offset 697 * 698 */ 699 static inline void intel_gvt_mmio_set_cmd_write_patch( 700 struct intel_gvt *gvt, unsigned int offset) 701 { 702 gvt->mmio.mmio_attribute[offset >> 2] |= F_CMD_WRITE_PATCH; 703 } 704 705 /** 706 * intel_gvt_mmio_is_cmd_write_patch - check if an mmio's cmd access needs to 707 * be patched 708 * @gvt: a GVT device 709 * @offset: register offset 710 * 711 * Returns: 712 * True if GPU commmand write to an MMIO should be patched 713 */ 714 static inline bool intel_gvt_mmio_is_cmd_write_patch( 715 struct intel_gvt *gvt, unsigned int offset) 716 { 717 return gvt->mmio.mmio_attribute[offset >> 2] & F_CMD_WRITE_PATCH; 718 } 719 720 /** 721 * intel_gvt_read_gpa - copy data from GPA to host data buffer 722 * @vgpu: a vGPU 723 * @gpa: guest physical address 724 * @buf: host data buffer 725 * @len: data length 726 * 727 * Returns: 728 * Zero on success, negative error code if failed. 729 */ 730 static inline int intel_gvt_read_gpa(struct intel_vgpu *vgpu, unsigned long gpa, 731 void *buf, unsigned long len) 732 { 733 if (!vgpu->attached) 734 return -ESRCH; 735 return vfio_dma_rw(vgpu->vfio_group, gpa, buf, len, false); 736 } 737 738 /** 739 * intel_gvt_write_gpa - copy data from host data buffer to GPA 740 * @vgpu: a vGPU 741 * @gpa: guest physical address 742 * @buf: host data buffer 743 * @len: data length 744 * 745 * Returns: 746 * Zero on success, negative error code if failed. 747 */ 748 static inline int intel_gvt_write_gpa(struct intel_vgpu *vgpu, 749 unsigned long gpa, void *buf, unsigned long len) 750 { 751 if (!vgpu->attached) 752 return -ESRCH; 753 return vfio_dma_rw(vgpu->vfio_group, gpa, buf, len, true); 754 } 755 756 void intel_gvt_debugfs_remove_vgpu(struct intel_vgpu *vgpu); 757 void intel_gvt_debugfs_init(struct intel_gvt *gvt); 758 void intel_gvt_debugfs_clean(struct intel_gvt *gvt); 759 760 int intel_gvt_page_track_add(struct intel_vgpu *info, u64 gfn); 761 int intel_gvt_page_track_remove(struct intel_vgpu *info, u64 gfn); 762 int intel_gvt_dma_pin_guest_page(struct intel_vgpu *vgpu, dma_addr_t dma_addr); 763 int intel_gvt_dma_map_guest_page(struct intel_vgpu *vgpu, unsigned long gfn, 764 unsigned long size, dma_addr_t *dma_addr); 765 void intel_gvt_dma_unmap_guest_page(struct intel_vgpu *vgpu, 766 dma_addr_t dma_addr); 767 768 #include "trace.h" 769 770 #endif 771