1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Kevin Tian <kevin.tian@intel.com> 25 * Eddie Dong <eddie.dong@intel.com> 26 * 27 * Contributors: 28 * Niu Bing <bing.niu@intel.com> 29 * Zhi Wang <zhi.a.wang@intel.com> 30 * 31 */ 32 33 #ifndef _GVT_H_ 34 #define _GVT_H_ 35 36 #include "debug.h" 37 #include "hypercall.h" 38 #include "mmio.h" 39 #include "reg.h" 40 #include "interrupt.h" 41 #include "gtt.h" 42 #include "display.h" 43 #include "edid.h" 44 #include "execlist.h" 45 #include "scheduler.h" 46 #include "sched_policy.h" 47 #include "mmio_context.h" 48 #include "cmd_parser.h" 49 #include "fb_decoder.h" 50 #include "dmabuf.h" 51 #include "page_track.h" 52 53 #define GVT_MAX_VGPU 8 54 55 enum { 56 INTEL_GVT_HYPERVISOR_XEN = 0, 57 INTEL_GVT_HYPERVISOR_KVM, 58 }; 59 60 struct intel_gvt_host { 61 bool initialized; 62 int hypervisor_type; 63 struct intel_gvt_mpt *mpt; 64 }; 65 66 extern struct intel_gvt_host intel_gvt_host; 67 68 /* Describe per-platform limitations. */ 69 struct intel_gvt_device_info { 70 u32 max_support_vgpus; 71 u32 cfg_space_size; 72 u32 mmio_size; 73 u32 mmio_bar; 74 unsigned long msi_cap_offset; 75 u32 gtt_start_offset; 76 u32 gtt_entry_size; 77 u32 gtt_entry_size_shift; 78 int gmadr_bytes_in_cmd; 79 u32 max_surface_size; 80 }; 81 82 /* GM resources owned by a vGPU */ 83 struct intel_vgpu_gm { 84 u64 aperture_sz; 85 u64 hidden_sz; 86 struct drm_mm_node low_gm_node; 87 struct drm_mm_node high_gm_node; 88 }; 89 90 #define INTEL_GVT_MAX_NUM_FENCES 32 91 92 /* Fences owned by a vGPU */ 93 struct intel_vgpu_fence { 94 struct drm_i915_fence_reg *regs[INTEL_GVT_MAX_NUM_FENCES]; 95 u32 base; 96 u32 size; 97 }; 98 99 struct intel_vgpu_mmio { 100 void *vreg; 101 void *sreg; 102 }; 103 104 #define INTEL_GVT_MAX_BAR_NUM 4 105 106 struct intel_vgpu_pci_bar { 107 u64 size; 108 bool tracked; 109 }; 110 111 struct intel_vgpu_cfg_space { 112 unsigned char virtual_cfg_space[PCI_CFG_SPACE_EXP_SIZE]; 113 struct intel_vgpu_pci_bar bar[INTEL_GVT_MAX_BAR_NUM]; 114 }; 115 116 #define vgpu_cfg_space(vgpu) ((vgpu)->cfg_space.virtual_cfg_space) 117 118 #define INTEL_GVT_MAX_PIPE 4 119 120 struct intel_vgpu_irq { 121 bool irq_warn_once[INTEL_GVT_EVENT_MAX]; 122 DECLARE_BITMAP(flip_done_event[INTEL_GVT_MAX_PIPE], 123 INTEL_GVT_EVENT_MAX); 124 }; 125 126 struct intel_vgpu_opregion { 127 bool mapped; 128 void *va; 129 u32 gfn[INTEL_GVT_OPREGION_PAGES]; 130 }; 131 132 #define vgpu_opregion(vgpu) (&(vgpu->opregion)) 133 134 struct intel_vgpu_display { 135 struct intel_vgpu_i2c_edid i2c_edid; 136 struct intel_vgpu_port ports[I915_MAX_PORTS]; 137 struct intel_vgpu_sbi sbi; 138 }; 139 140 struct vgpu_sched_ctl { 141 int weight; 142 }; 143 144 enum { 145 INTEL_VGPU_EXECLIST_SUBMISSION = 1, 146 INTEL_VGPU_GUC_SUBMISSION, 147 }; 148 149 struct intel_vgpu_submission_ops { 150 const char *name; 151 int (*init)(struct intel_vgpu *vgpu, unsigned long engine_mask); 152 void (*clean)(struct intel_vgpu *vgpu, unsigned long engine_mask); 153 void (*reset)(struct intel_vgpu *vgpu, unsigned long engine_mask); 154 }; 155 156 struct intel_vgpu_submission { 157 struct intel_vgpu_execlist execlist[I915_NUM_ENGINES]; 158 struct list_head workload_q_head[I915_NUM_ENGINES]; 159 struct kmem_cache *workloads; 160 atomic_t running_workload_num; 161 struct i915_gem_context *shadow_ctx; 162 DECLARE_BITMAP(shadow_ctx_desc_updated, I915_NUM_ENGINES); 163 DECLARE_BITMAP(tlb_handle_pending, I915_NUM_ENGINES); 164 void *ring_scan_buffer[I915_NUM_ENGINES]; 165 int ring_scan_buffer_size[I915_NUM_ENGINES]; 166 const struct intel_vgpu_submission_ops *ops; 167 int virtual_submission_interface; 168 bool active; 169 }; 170 171 struct intel_vgpu { 172 struct intel_gvt *gvt; 173 struct mutex vgpu_lock; 174 int id; 175 unsigned long handle; /* vGPU handle used by hypervisor MPT modules */ 176 bool active; 177 bool pv_notified; 178 bool failsafe; 179 unsigned int resetting_eng; 180 181 /* Both sched_data and sched_ctl can be seen a part of the global gvt 182 * scheduler structure. So below 2 vgpu data are protected 183 * by sched_lock, not vgpu_lock. 184 */ 185 void *sched_data; 186 struct vgpu_sched_ctl sched_ctl; 187 188 struct intel_vgpu_fence fence; 189 struct intel_vgpu_gm gm; 190 struct intel_vgpu_cfg_space cfg_space; 191 struct intel_vgpu_mmio mmio; 192 struct intel_vgpu_irq irq; 193 struct intel_vgpu_gtt gtt; 194 struct intel_vgpu_opregion opregion; 195 struct intel_vgpu_display display; 196 struct intel_vgpu_submission submission; 197 struct radix_tree_root page_track_tree; 198 u32 hws_pga[I915_NUM_ENGINES]; 199 200 struct dentry *debugfs; 201 202 #if IS_ENABLED(CONFIG_DRM_I915_GVT_KVMGT) 203 struct { 204 struct mdev_device *mdev; 205 struct vfio_region *region; 206 int num_regions; 207 struct eventfd_ctx *intx_trigger; 208 struct eventfd_ctx *msi_trigger; 209 210 /* 211 * Two caches are used to avoid mapping duplicated pages (eg. 212 * scratch pages). This help to reduce dma setup overhead. 213 */ 214 struct rb_root gfn_cache; 215 struct rb_root dma_addr_cache; 216 unsigned long nr_cache_entries; 217 struct mutex cache_lock; 218 219 struct notifier_block iommu_notifier; 220 struct notifier_block group_notifier; 221 struct kvm *kvm; 222 struct work_struct release_work; 223 atomic_t released; 224 struct vfio_device *vfio_device; 225 } vdev; 226 #endif 227 228 struct list_head dmabuf_obj_list_head; 229 struct mutex dmabuf_lock; 230 struct idr object_idr; 231 232 struct completion vblank_done; 233 234 u32 scan_nonprivbb; 235 }; 236 237 /* validating GM healthy status*/ 238 #define vgpu_is_vm_unhealthy(ret_val) \ 239 (((ret_val) == -EBADRQC) || ((ret_val) == -EFAULT)) 240 241 struct intel_gvt_gm { 242 unsigned long vgpu_allocated_low_gm_size; 243 unsigned long vgpu_allocated_high_gm_size; 244 }; 245 246 struct intel_gvt_fence { 247 unsigned long vgpu_allocated_fence_num; 248 }; 249 250 /* Special MMIO blocks. */ 251 struct gvt_mmio_block { 252 unsigned int device; 253 i915_reg_t offset; 254 unsigned int size; 255 gvt_mmio_func read; 256 gvt_mmio_func write; 257 }; 258 259 #define INTEL_GVT_MMIO_HASH_BITS 11 260 261 struct intel_gvt_mmio { 262 u8 *mmio_attribute; 263 /* Register contains RO bits */ 264 #define F_RO (1 << 0) 265 /* Register contains graphics address */ 266 #define F_GMADR (1 << 1) 267 /* Mode mask registers with high 16 bits as the mask bits */ 268 #define F_MODE_MASK (1 << 2) 269 /* This reg can be accessed by GPU commands */ 270 #define F_CMD_ACCESS (1 << 3) 271 /* This reg has been accessed by a VM */ 272 #define F_ACCESSED (1 << 4) 273 /* This reg has been accessed through GPU commands */ 274 #define F_CMD_ACCESSED (1 << 5) 275 /* This reg could be accessed by unaligned address */ 276 #define F_UNALIGN (1 << 6) 277 278 struct gvt_mmio_block *mmio_block; 279 unsigned int num_mmio_block; 280 281 DECLARE_HASHTABLE(mmio_info_table, INTEL_GVT_MMIO_HASH_BITS); 282 unsigned long num_tracked_mmio; 283 }; 284 285 struct intel_gvt_firmware { 286 void *cfg_space; 287 void *mmio; 288 bool firmware_loaded; 289 }; 290 291 #define NR_MAX_INTEL_VGPU_TYPES 20 292 struct intel_vgpu_type { 293 char name[16]; 294 unsigned int avail_instance; 295 unsigned int low_gm_size; 296 unsigned int high_gm_size; 297 unsigned int fence; 298 unsigned int weight; 299 enum intel_vgpu_edid resolution; 300 }; 301 302 struct intel_gvt { 303 /* GVT scope lock, protect GVT itself, and all resource currently 304 * not yet protected by special locks(vgpu and scheduler lock). 305 */ 306 struct mutex lock; 307 /* scheduler scope lock, protect gvt and vgpu schedule related data */ 308 struct mutex sched_lock; 309 310 struct drm_i915_private *dev_priv; 311 struct idr vgpu_idr; /* vGPU IDR pool */ 312 313 struct intel_gvt_device_info device_info; 314 struct intel_gvt_gm gm; 315 struct intel_gvt_fence fence; 316 struct intel_gvt_mmio mmio; 317 struct intel_gvt_firmware firmware; 318 struct intel_gvt_irq irq; 319 struct intel_gvt_gtt gtt; 320 struct intel_gvt_workload_scheduler scheduler; 321 struct notifier_block shadow_ctx_notifier_block[I915_NUM_ENGINES]; 322 DECLARE_HASHTABLE(cmd_table, GVT_CMD_HASH_BITS); 323 struct intel_vgpu_type *types; 324 unsigned int num_types; 325 struct intel_vgpu *idle_vgpu; 326 327 struct task_struct *service_thread; 328 wait_queue_head_t service_thread_wq; 329 330 /* service_request is always used in bit operation, we should always 331 * use it with atomic bit ops so that no need to use gvt big lock. 332 */ 333 unsigned long service_request; 334 335 struct { 336 struct engine_mmio *mmio; 337 int ctx_mmio_count[I915_NUM_ENGINES]; 338 } engine_mmio_list; 339 340 struct dentry *debugfs_root; 341 }; 342 343 static inline struct intel_gvt *to_gvt(struct drm_i915_private *i915) 344 { 345 return i915->gvt; 346 } 347 348 enum { 349 INTEL_GVT_REQUEST_EMULATE_VBLANK = 0, 350 351 /* Scheduling trigger by timer */ 352 INTEL_GVT_REQUEST_SCHED = 1, 353 354 /* Scheduling trigger by event */ 355 INTEL_GVT_REQUEST_EVENT_SCHED = 2, 356 }; 357 358 static inline void intel_gvt_request_service(struct intel_gvt *gvt, 359 int service) 360 { 361 set_bit(service, (void *)&gvt->service_request); 362 wake_up(&gvt->service_thread_wq); 363 } 364 365 void intel_gvt_free_firmware(struct intel_gvt *gvt); 366 int intel_gvt_load_firmware(struct intel_gvt *gvt); 367 368 /* Aperture/GM space definitions for GVT device */ 369 #define MB_TO_BYTES(mb) ((mb) << 20ULL) 370 #define BYTES_TO_MB(b) ((b) >> 20ULL) 371 372 #define HOST_LOW_GM_SIZE MB_TO_BYTES(128) 373 #define HOST_HIGH_GM_SIZE MB_TO_BYTES(384) 374 #define HOST_FENCE 4 375 376 /* Aperture/GM space definitions for GVT device */ 377 #define gvt_aperture_sz(gvt) (gvt->dev_priv->ggtt.mappable_end) 378 #define gvt_aperture_pa_base(gvt) (gvt->dev_priv->ggtt.gmadr.start) 379 380 #define gvt_ggtt_gm_sz(gvt) (gvt->dev_priv->ggtt.vm.total) 381 #define gvt_ggtt_sz(gvt) \ 382 ((gvt->dev_priv->ggtt.vm.total >> PAGE_SHIFT) << 3) 383 #define gvt_hidden_sz(gvt) (gvt_ggtt_gm_sz(gvt) - gvt_aperture_sz(gvt)) 384 385 #define gvt_aperture_gmadr_base(gvt) (0) 386 #define gvt_aperture_gmadr_end(gvt) (gvt_aperture_gmadr_base(gvt) \ 387 + gvt_aperture_sz(gvt) - 1) 388 389 #define gvt_hidden_gmadr_base(gvt) (gvt_aperture_gmadr_base(gvt) \ 390 + gvt_aperture_sz(gvt)) 391 #define gvt_hidden_gmadr_end(gvt) (gvt_hidden_gmadr_base(gvt) \ 392 + gvt_hidden_sz(gvt) - 1) 393 394 #define gvt_fence_sz(gvt) (gvt->dev_priv->num_fence_regs) 395 396 /* Aperture/GM space definitions for vGPU */ 397 #define vgpu_aperture_offset(vgpu) ((vgpu)->gm.low_gm_node.start) 398 #define vgpu_hidden_offset(vgpu) ((vgpu)->gm.high_gm_node.start) 399 #define vgpu_aperture_sz(vgpu) ((vgpu)->gm.aperture_sz) 400 #define vgpu_hidden_sz(vgpu) ((vgpu)->gm.hidden_sz) 401 402 #define vgpu_aperture_pa_base(vgpu) \ 403 (gvt_aperture_pa_base(vgpu->gvt) + vgpu_aperture_offset(vgpu)) 404 405 #define vgpu_ggtt_gm_sz(vgpu) ((vgpu)->gm.aperture_sz + (vgpu)->gm.hidden_sz) 406 407 #define vgpu_aperture_pa_end(vgpu) \ 408 (vgpu_aperture_pa_base(vgpu) + vgpu_aperture_sz(vgpu) - 1) 409 410 #define vgpu_aperture_gmadr_base(vgpu) (vgpu_aperture_offset(vgpu)) 411 #define vgpu_aperture_gmadr_end(vgpu) \ 412 (vgpu_aperture_gmadr_base(vgpu) + vgpu_aperture_sz(vgpu) - 1) 413 414 #define vgpu_hidden_gmadr_base(vgpu) (vgpu_hidden_offset(vgpu)) 415 #define vgpu_hidden_gmadr_end(vgpu) \ 416 (vgpu_hidden_gmadr_base(vgpu) + vgpu_hidden_sz(vgpu) - 1) 417 418 #define vgpu_fence_base(vgpu) (vgpu->fence.base) 419 #define vgpu_fence_sz(vgpu) (vgpu->fence.size) 420 421 struct intel_vgpu_creation_params { 422 __u64 handle; 423 __u64 low_gm_sz; /* in MB */ 424 __u64 high_gm_sz; /* in MB */ 425 __u64 fence_sz; 426 __u64 resolution; 427 __s32 primary; 428 __u64 vgpu_id; 429 430 __u32 weight; 431 }; 432 433 int intel_vgpu_alloc_resource(struct intel_vgpu *vgpu, 434 struct intel_vgpu_creation_params *param); 435 void intel_vgpu_reset_resource(struct intel_vgpu *vgpu); 436 void intel_vgpu_free_resource(struct intel_vgpu *vgpu); 437 void intel_vgpu_write_fence(struct intel_vgpu *vgpu, 438 u32 fence, u64 value); 439 440 /* Macros for easily accessing vGPU virtual/shadow register. 441 Explicitly seperate use for typed MMIO reg or real offset.*/ 442 #define vgpu_vreg_t(vgpu, reg) \ 443 (*(u32 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg))) 444 #define vgpu_vreg(vgpu, offset) \ 445 (*(u32 *)(vgpu->mmio.vreg + (offset))) 446 #define vgpu_vreg64_t(vgpu, reg) \ 447 (*(u64 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg))) 448 #define vgpu_vreg64(vgpu, offset) \ 449 (*(u64 *)(vgpu->mmio.vreg + (offset))) 450 #define vgpu_sreg_t(vgpu, reg) \ 451 (*(u32 *)(vgpu->mmio.sreg + i915_mmio_reg_offset(reg))) 452 #define vgpu_sreg(vgpu, offset) \ 453 (*(u32 *)(vgpu->mmio.sreg + (offset))) 454 455 #define for_each_active_vgpu(gvt, vgpu, id) \ 456 idr_for_each_entry((&(gvt)->vgpu_idr), (vgpu), (id)) \ 457 for_each_if(vgpu->active) 458 459 static inline void intel_vgpu_write_pci_bar(struct intel_vgpu *vgpu, 460 u32 offset, u32 val, bool low) 461 { 462 u32 *pval; 463 464 /* BAR offset should be 32 bits algiend */ 465 offset = rounddown(offset, 4); 466 pval = (u32 *)(vgpu_cfg_space(vgpu) + offset); 467 468 if (low) { 469 /* 470 * only update bit 31 - bit 4, 471 * leave the bit 3 - bit 0 unchanged. 472 */ 473 *pval = (val & GENMASK(31, 4)) | (*pval & GENMASK(3, 0)); 474 } else { 475 *pval = val; 476 } 477 } 478 479 int intel_gvt_init_vgpu_types(struct intel_gvt *gvt); 480 void intel_gvt_clean_vgpu_types(struct intel_gvt *gvt); 481 482 struct intel_vgpu *intel_gvt_create_idle_vgpu(struct intel_gvt *gvt); 483 void intel_gvt_destroy_idle_vgpu(struct intel_vgpu *vgpu); 484 struct intel_vgpu *intel_gvt_create_vgpu(struct intel_gvt *gvt, 485 struct intel_vgpu_type *type); 486 void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu); 487 void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr, 488 unsigned int engine_mask); 489 void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu); 490 void intel_gvt_activate_vgpu(struct intel_vgpu *vgpu); 491 void intel_gvt_deactivate_vgpu(struct intel_vgpu *vgpu); 492 493 /* validating GM functions */ 494 #define vgpu_gmadr_is_aperture(vgpu, gmadr) \ 495 ((gmadr >= vgpu_aperture_gmadr_base(vgpu)) && \ 496 (gmadr <= vgpu_aperture_gmadr_end(vgpu))) 497 498 #define vgpu_gmadr_is_hidden(vgpu, gmadr) \ 499 ((gmadr >= vgpu_hidden_gmadr_base(vgpu)) && \ 500 (gmadr <= vgpu_hidden_gmadr_end(vgpu))) 501 502 #define vgpu_gmadr_is_valid(vgpu, gmadr) \ 503 ((vgpu_gmadr_is_aperture(vgpu, gmadr) || \ 504 (vgpu_gmadr_is_hidden(vgpu, gmadr)))) 505 506 #define gvt_gmadr_is_aperture(gvt, gmadr) \ 507 ((gmadr >= gvt_aperture_gmadr_base(gvt)) && \ 508 (gmadr <= gvt_aperture_gmadr_end(gvt))) 509 510 #define gvt_gmadr_is_hidden(gvt, gmadr) \ 511 ((gmadr >= gvt_hidden_gmadr_base(gvt)) && \ 512 (gmadr <= gvt_hidden_gmadr_end(gvt))) 513 514 #define gvt_gmadr_is_valid(gvt, gmadr) \ 515 (gvt_gmadr_is_aperture(gvt, gmadr) || \ 516 gvt_gmadr_is_hidden(gvt, gmadr)) 517 518 bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size); 519 int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr); 520 int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u64 h_addr, u64 *g_addr); 521 int intel_gvt_ggtt_index_g2h(struct intel_vgpu *vgpu, unsigned long g_index, 522 unsigned long *h_index); 523 int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_index, 524 unsigned long *g_index); 525 526 void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu, 527 bool primary); 528 void intel_vgpu_reset_cfg_space(struct intel_vgpu *vgpu); 529 530 int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset, 531 void *p_data, unsigned int bytes); 532 533 int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset, 534 void *p_data, unsigned int bytes); 535 536 static inline u64 intel_vgpu_get_bar_gpa(struct intel_vgpu *vgpu, int bar) 537 { 538 /* We are 64bit bar. */ 539 return (*(u64 *)(vgpu->cfg_space.virtual_cfg_space + bar)) & 540 PCI_BASE_ADDRESS_MEM_MASK; 541 } 542 543 void intel_vgpu_clean_opregion(struct intel_vgpu *vgpu); 544 int intel_vgpu_init_opregion(struct intel_vgpu *vgpu); 545 int intel_vgpu_opregion_base_write_handler(struct intel_vgpu *vgpu, u32 gpa); 546 547 int intel_vgpu_emulate_opregion_request(struct intel_vgpu *vgpu, u32 swsci); 548 void populate_pvinfo_page(struct intel_vgpu *vgpu); 549 550 int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload); 551 void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason); 552 553 struct intel_gvt_ops { 554 int (*emulate_cfg_read)(struct intel_vgpu *, unsigned int, void *, 555 unsigned int); 556 int (*emulate_cfg_write)(struct intel_vgpu *, unsigned int, void *, 557 unsigned int); 558 int (*emulate_mmio_read)(struct intel_vgpu *, u64, void *, 559 unsigned int); 560 int (*emulate_mmio_write)(struct intel_vgpu *, u64, void *, 561 unsigned int); 562 struct intel_vgpu *(*vgpu_create)(struct intel_gvt *, 563 struct intel_vgpu_type *); 564 void (*vgpu_destroy)(struct intel_vgpu *); 565 void (*vgpu_reset)(struct intel_vgpu *); 566 void (*vgpu_activate)(struct intel_vgpu *); 567 void (*vgpu_deactivate)(struct intel_vgpu *); 568 struct intel_vgpu_type *(*gvt_find_vgpu_type)(struct intel_gvt *gvt, 569 const char *name); 570 bool (*get_gvt_attrs)(struct attribute ***type_attrs, 571 struct attribute_group ***intel_vgpu_type_groups); 572 int (*vgpu_query_plane)(struct intel_vgpu *vgpu, void *); 573 int (*vgpu_get_dmabuf)(struct intel_vgpu *vgpu, unsigned int); 574 int (*write_protect_handler)(struct intel_vgpu *, u64, void *, 575 unsigned int); 576 }; 577 578 579 enum { 580 GVT_FAILSAFE_UNSUPPORTED_GUEST, 581 GVT_FAILSAFE_INSUFFICIENT_RESOURCE, 582 GVT_FAILSAFE_GUEST_ERR, 583 }; 584 585 static inline void mmio_hw_access_pre(struct drm_i915_private *dev_priv) 586 { 587 intel_runtime_pm_get(dev_priv); 588 } 589 590 static inline void mmio_hw_access_post(struct drm_i915_private *dev_priv) 591 { 592 intel_runtime_pm_put(dev_priv); 593 } 594 595 /** 596 * intel_gvt_mmio_set_accessed - mark a MMIO has been accessed 597 * @gvt: a GVT device 598 * @offset: register offset 599 * 600 */ 601 static inline void intel_gvt_mmio_set_accessed( 602 struct intel_gvt *gvt, unsigned int offset) 603 { 604 gvt->mmio.mmio_attribute[offset >> 2] |= F_ACCESSED; 605 } 606 607 /** 608 * intel_gvt_mmio_is_cmd_accessed - mark a MMIO could be accessed by command 609 * @gvt: a GVT device 610 * @offset: register offset 611 * 612 */ 613 static inline bool intel_gvt_mmio_is_cmd_access( 614 struct intel_gvt *gvt, unsigned int offset) 615 { 616 return gvt->mmio.mmio_attribute[offset >> 2] & F_CMD_ACCESS; 617 } 618 619 /** 620 * intel_gvt_mmio_is_unalign - mark a MMIO could be accessed unaligned 621 * @gvt: a GVT device 622 * @offset: register offset 623 * 624 */ 625 static inline bool intel_gvt_mmio_is_unalign( 626 struct intel_gvt *gvt, unsigned int offset) 627 { 628 return gvt->mmio.mmio_attribute[offset >> 2] & F_UNALIGN; 629 } 630 631 /** 632 * intel_gvt_mmio_set_cmd_accessed - mark a MMIO has been accessed by command 633 * @gvt: a GVT device 634 * @offset: register offset 635 * 636 */ 637 static inline void intel_gvt_mmio_set_cmd_accessed( 638 struct intel_gvt *gvt, unsigned int offset) 639 { 640 gvt->mmio.mmio_attribute[offset >> 2] |= F_CMD_ACCESSED; 641 } 642 643 /** 644 * intel_gvt_mmio_has_mode_mask - if a MMIO has a mode mask 645 * @gvt: a GVT device 646 * @offset: register offset 647 * 648 * Returns: 649 * True if a MMIO has a mode mask in its higher 16 bits, false if it isn't. 650 * 651 */ 652 static inline bool intel_gvt_mmio_has_mode_mask( 653 struct intel_gvt *gvt, unsigned int offset) 654 { 655 return gvt->mmio.mmio_attribute[offset >> 2] & F_MODE_MASK; 656 } 657 658 int intel_gvt_debugfs_add_vgpu(struct intel_vgpu *vgpu); 659 void intel_gvt_debugfs_remove_vgpu(struct intel_vgpu *vgpu); 660 int intel_gvt_debugfs_init(struct intel_gvt *gvt); 661 void intel_gvt_debugfs_clean(struct intel_gvt *gvt); 662 663 664 #include "trace.h" 665 #include "mpt.h" 666 667 #endif 668