1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Kevin Tian <kevin.tian@intel.com> 25 * Eddie Dong <eddie.dong@intel.com> 26 * 27 * Contributors: 28 * Niu Bing <bing.niu@intel.com> 29 * Zhi Wang <zhi.a.wang@intel.com> 30 * 31 */ 32 33 #ifndef _GVT_H_ 34 #define _GVT_H_ 35 36 #include "debug.h" 37 #include "hypercall.h" 38 #include "mmio.h" 39 #include "reg.h" 40 #include "interrupt.h" 41 #include "gtt.h" 42 #include "display.h" 43 #include "edid.h" 44 #include "execlist.h" 45 #include "scheduler.h" 46 #include "sched_policy.h" 47 #include "render.h" 48 #include "cmd_parser.h" 49 50 #define GVT_MAX_VGPU 8 51 52 enum { 53 INTEL_GVT_HYPERVISOR_XEN = 0, 54 INTEL_GVT_HYPERVISOR_KVM, 55 }; 56 57 struct intel_gvt_host { 58 bool initialized; 59 int hypervisor_type; 60 struct intel_gvt_mpt *mpt; 61 }; 62 63 extern struct intel_gvt_host intel_gvt_host; 64 65 /* Describe per-platform limitations. */ 66 struct intel_gvt_device_info { 67 u32 max_support_vgpus; 68 u32 cfg_space_size; 69 u32 mmio_size; 70 u32 mmio_bar; 71 unsigned long msi_cap_offset; 72 u32 gtt_start_offset; 73 u32 gtt_entry_size; 74 u32 gtt_entry_size_shift; 75 int gmadr_bytes_in_cmd; 76 u32 max_surface_size; 77 }; 78 79 /* GM resources owned by a vGPU */ 80 struct intel_vgpu_gm { 81 u64 aperture_sz; 82 u64 hidden_sz; 83 void *aperture_va; 84 struct drm_mm_node low_gm_node; 85 struct drm_mm_node high_gm_node; 86 }; 87 88 #define INTEL_GVT_MAX_NUM_FENCES 32 89 90 /* Fences owned by a vGPU */ 91 struct intel_vgpu_fence { 92 struct drm_i915_fence_reg *regs[INTEL_GVT_MAX_NUM_FENCES]; 93 u32 base; 94 u32 size; 95 }; 96 97 struct intel_vgpu_mmio { 98 void *vreg; 99 void *sreg; 100 bool disable_warn_untrack; 101 }; 102 103 #define INTEL_GVT_MAX_BAR_NUM 4 104 105 struct intel_vgpu_pci_bar { 106 u64 size; 107 bool tracked; 108 }; 109 110 struct intel_vgpu_cfg_space { 111 unsigned char virtual_cfg_space[PCI_CFG_SPACE_EXP_SIZE]; 112 struct intel_vgpu_pci_bar bar[INTEL_GVT_MAX_BAR_NUM]; 113 }; 114 115 #define vgpu_cfg_space(vgpu) ((vgpu)->cfg_space.virtual_cfg_space) 116 117 #define INTEL_GVT_MAX_PIPE 4 118 119 struct intel_vgpu_irq { 120 bool irq_warn_once[INTEL_GVT_EVENT_MAX]; 121 DECLARE_BITMAP(flip_done_event[INTEL_GVT_MAX_PIPE], 122 INTEL_GVT_EVENT_MAX); 123 }; 124 125 struct intel_vgpu_opregion { 126 void *va; 127 u32 gfn[INTEL_GVT_OPREGION_PAGES]; 128 }; 129 130 #define vgpu_opregion(vgpu) (&(vgpu->opregion)) 131 132 #define INTEL_GVT_MAX_PORT 5 133 134 struct intel_vgpu_display { 135 struct intel_vgpu_i2c_edid i2c_edid; 136 struct intel_vgpu_port ports[INTEL_GVT_MAX_PORT]; 137 struct intel_vgpu_sbi sbi; 138 }; 139 140 struct vgpu_sched_ctl { 141 int weight; 142 }; 143 144 enum { 145 INTEL_VGPU_EXECLIST_SUBMISSION = 1, 146 INTEL_VGPU_GUC_SUBMISSION, 147 }; 148 149 struct intel_vgpu_submission_ops { 150 const char *name; 151 int (*init)(struct intel_vgpu *vgpu); 152 void (*clean)(struct intel_vgpu *vgpu); 153 void (*reset)(struct intel_vgpu *vgpu, unsigned long engine_mask); 154 }; 155 156 struct intel_vgpu_submission { 157 struct intel_vgpu_execlist execlist[I915_NUM_ENGINES]; 158 struct list_head workload_q_head[I915_NUM_ENGINES]; 159 struct kmem_cache *workloads; 160 atomic_t running_workload_num; 161 struct i915_gem_context *shadow_ctx; 162 DECLARE_BITMAP(shadow_ctx_desc_updated, I915_NUM_ENGINES); 163 DECLARE_BITMAP(tlb_handle_pending, I915_NUM_ENGINES); 164 void *ring_scan_buffer[I915_NUM_ENGINES]; 165 int ring_scan_buffer_size[I915_NUM_ENGINES]; 166 const struct intel_vgpu_submission_ops *ops; 167 int virtual_submission_interface; 168 bool active; 169 }; 170 171 struct intel_vgpu { 172 struct intel_gvt *gvt; 173 int id; 174 unsigned long handle; /* vGPU handle used by hypervisor MPT modules */ 175 bool active; 176 bool pv_notified; 177 bool failsafe; 178 unsigned int resetting_eng; 179 void *sched_data; 180 struct vgpu_sched_ctl sched_ctl; 181 182 struct intel_vgpu_fence fence; 183 struct intel_vgpu_gm gm; 184 struct intel_vgpu_cfg_space cfg_space; 185 struct intel_vgpu_mmio mmio; 186 struct intel_vgpu_irq irq; 187 struct intel_vgpu_gtt gtt; 188 struct intel_vgpu_opregion opregion; 189 struct intel_vgpu_display display; 190 struct intel_vgpu_submission submission; 191 u32 hws_pga[I915_NUM_ENGINES]; 192 193 struct dentry *debugfs; 194 195 #if IS_ENABLED(CONFIG_DRM_I915_GVT_KVMGT) 196 struct { 197 struct mdev_device *mdev; 198 struct vfio_region *region; 199 int num_regions; 200 struct eventfd_ctx *intx_trigger; 201 struct eventfd_ctx *msi_trigger; 202 struct rb_root cache; 203 struct mutex cache_lock; 204 struct notifier_block iommu_notifier; 205 struct notifier_block group_notifier; 206 struct kvm *kvm; 207 struct work_struct release_work; 208 atomic_t released; 209 } vdev; 210 #endif 211 }; 212 213 /* validating GM healthy status*/ 214 #define vgpu_is_vm_unhealthy(ret_val) \ 215 (((ret_val) == -EBADRQC) || ((ret_val) == -EFAULT)) 216 217 struct intel_gvt_gm { 218 unsigned long vgpu_allocated_low_gm_size; 219 unsigned long vgpu_allocated_high_gm_size; 220 }; 221 222 struct intel_gvt_fence { 223 unsigned long vgpu_allocated_fence_num; 224 }; 225 226 /* Special MMIO blocks. */ 227 struct gvt_mmio_block { 228 unsigned int device; 229 i915_reg_t offset; 230 unsigned int size; 231 gvt_mmio_func read; 232 gvt_mmio_func write; 233 }; 234 235 #define INTEL_GVT_MMIO_HASH_BITS 11 236 237 struct intel_gvt_mmio { 238 u8 *mmio_attribute; 239 /* Register contains RO bits */ 240 #define F_RO (1 << 0) 241 /* Register contains graphics address */ 242 #define F_GMADR (1 << 1) 243 /* Mode mask registers with high 16 bits as the mask bits */ 244 #define F_MODE_MASK (1 << 2) 245 /* This reg can be accessed by GPU commands */ 246 #define F_CMD_ACCESS (1 << 3) 247 /* This reg has been accessed by a VM */ 248 #define F_ACCESSED (1 << 4) 249 /* This reg has been accessed through GPU commands */ 250 #define F_CMD_ACCESSED (1 << 5) 251 /* This reg could be accessed by unaligned address */ 252 #define F_UNALIGN (1 << 6) 253 254 struct gvt_mmio_block *mmio_block; 255 unsigned int num_mmio_block; 256 257 DECLARE_HASHTABLE(mmio_info_table, INTEL_GVT_MMIO_HASH_BITS); 258 unsigned long num_tracked_mmio; 259 }; 260 261 struct intel_gvt_firmware { 262 void *cfg_space; 263 void *mmio; 264 bool firmware_loaded; 265 }; 266 267 #define NR_MAX_INTEL_VGPU_TYPES 20 268 struct intel_vgpu_type { 269 char name[16]; 270 unsigned int avail_instance; 271 unsigned int low_gm_size; 272 unsigned int high_gm_size; 273 unsigned int fence; 274 unsigned int weight; 275 enum intel_vgpu_edid resolution; 276 }; 277 278 struct intel_gvt { 279 struct mutex lock; 280 struct drm_i915_private *dev_priv; 281 struct idr vgpu_idr; /* vGPU IDR pool */ 282 283 struct intel_gvt_device_info device_info; 284 struct intel_gvt_gm gm; 285 struct intel_gvt_fence fence; 286 struct intel_gvt_mmio mmio; 287 struct intel_gvt_firmware firmware; 288 struct intel_gvt_irq irq; 289 struct intel_gvt_gtt gtt; 290 struct intel_gvt_workload_scheduler scheduler; 291 struct notifier_block shadow_ctx_notifier_block[I915_NUM_ENGINES]; 292 DECLARE_HASHTABLE(cmd_table, GVT_CMD_HASH_BITS); 293 struct intel_vgpu_type *types; 294 unsigned int num_types; 295 struct intel_vgpu *idle_vgpu; 296 297 struct task_struct *service_thread; 298 wait_queue_head_t service_thread_wq; 299 unsigned long service_request; 300 301 struct dentry *debugfs_root; 302 }; 303 304 static inline struct intel_gvt *to_gvt(struct drm_i915_private *i915) 305 { 306 return i915->gvt; 307 } 308 309 enum { 310 INTEL_GVT_REQUEST_EMULATE_VBLANK = 0, 311 312 /* Scheduling trigger by timer */ 313 INTEL_GVT_REQUEST_SCHED = 1, 314 315 /* Scheduling trigger by event */ 316 INTEL_GVT_REQUEST_EVENT_SCHED = 2, 317 }; 318 319 static inline void intel_gvt_request_service(struct intel_gvt *gvt, 320 int service) 321 { 322 set_bit(service, (void *)&gvt->service_request); 323 wake_up(&gvt->service_thread_wq); 324 } 325 326 void intel_gvt_free_firmware(struct intel_gvt *gvt); 327 int intel_gvt_load_firmware(struct intel_gvt *gvt); 328 329 /* Aperture/GM space definitions for GVT device */ 330 #define MB_TO_BYTES(mb) ((mb) << 20ULL) 331 #define BYTES_TO_MB(b) ((b) >> 20ULL) 332 333 #define HOST_LOW_GM_SIZE MB_TO_BYTES(128) 334 #define HOST_HIGH_GM_SIZE MB_TO_BYTES(384) 335 #define HOST_FENCE 4 336 337 /* Aperture/GM space definitions for GVT device */ 338 #define gvt_aperture_sz(gvt) (gvt->dev_priv->ggtt.mappable_end) 339 #define gvt_aperture_pa_base(gvt) (gvt->dev_priv->ggtt.mappable_base) 340 341 #define gvt_ggtt_gm_sz(gvt) (gvt->dev_priv->ggtt.base.total) 342 #define gvt_ggtt_sz(gvt) \ 343 ((gvt->dev_priv->ggtt.base.total >> PAGE_SHIFT) << 3) 344 #define gvt_hidden_sz(gvt) (gvt_ggtt_gm_sz(gvt) - gvt_aperture_sz(gvt)) 345 346 #define gvt_aperture_gmadr_base(gvt) (0) 347 #define gvt_aperture_gmadr_end(gvt) (gvt_aperture_gmadr_base(gvt) \ 348 + gvt_aperture_sz(gvt) - 1) 349 350 #define gvt_hidden_gmadr_base(gvt) (gvt_aperture_gmadr_base(gvt) \ 351 + gvt_aperture_sz(gvt)) 352 #define gvt_hidden_gmadr_end(gvt) (gvt_hidden_gmadr_base(gvt) \ 353 + gvt_hidden_sz(gvt) - 1) 354 355 #define gvt_fence_sz(gvt) (gvt->dev_priv->num_fence_regs) 356 357 /* Aperture/GM space definitions for vGPU */ 358 #define vgpu_aperture_offset(vgpu) ((vgpu)->gm.low_gm_node.start) 359 #define vgpu_hidden_offset(vgpu) ((vgpu)->gm.high_gm_node.start) 360 #define vgpu_aperture_sz(vgpu) ((vgpu)->gm.aperture_sz) 361 #define vgpu_hidden_sz(vgpu) ((vgpu)->gm.hidden_sz) 362 363 #define vgpu_aperture_pa_base(vgpu) \ 364 (gvt_aperture_pa_base(vgpu->gvt) + vgpu_aperture_offset(vgpu)) 365 366 #define vgpu_ggtt_gm_sz(vgpu) ((vgpu)->gm.aperture_sz + (vgpu)->gm.hidden_sz) 367 368 #define vgpu_aperture_pa_end(vgpu) \ 369 (vgpu_aperture_pa_base(vgpu) + vgpu_aperture_sz(vgpu) - 1) 370 371 #define vgpu_aperture_gmadr_base(vgpu) (vgpu_aperture_offset(vgpu)) 372 #define vgpu_aperture_gmadr_end(vgpu) \ 373 (vgpu_aperture_gmadr_base(vgpu) + vgpu_aperture_sz(vgpu) - 1) 374 375 #define vgpu_hidden_gmadr_base(vgpu) (vgpu_hidden_offset(vgpu)) 376 #define vgpu_hidden_gmadr_end(vgpu) \ 377 (vgpu_hidden_gmadr_base(vgpu) + vgpu_hidden_sz(vgpu) - 1) 378 379 #define vgpu_fence_base(vgpu) (vgpu->fence.base) 380 #define vgpu_fence_sz(vgpu) (vgpu->fence.size) 381 382 struct intel_vgpu_creation_params { 383 __u64 handle; 384 __u64 low_gm_sz; /* in MB */ 385 __u64 high_gm_sz; /* in MB */ 386 __u64 fence_sz; 387 __u64 resolution; 388 __s32 primary; 389 __u64 vgpu_id; 390 391 __u32 weight; 392 }; 393 394 int intel_vgpu_alloc_resource(struct intel_vgpu *vgpu, 395 struct intel_vgpu_creation_params *param); 396 void intel_vgpu_reset_resource(struct intel_vgpu *vgpu); 397 void intel_vgpu_free_resource(struct intel_vgpu *vgpu); 398 void intel_vgpu_write_fence(struct intel_vgpu *vgpu, 399 u32 fence, u64 value); 400 401 /* Macros for easily accessing vGPU virtual/shadow register */ 402 #define vgpu_vreg(vgpu, reg) \ 403 (*(u32 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg))) 404 #define vgpu_vreg8(vgpu, reg) \ 405 (*(u8 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg))) 406 #define vgpu_vreg16(vgpu, reg) \ 407 (*(u16 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg))) 408 #define vgpu_vreg64(vgpu, reg) \ 409 (*(u64 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg))) 410 #define vgpu_sreg(vgpu, reg) \ 411 (*(u32 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg))) 412 #define vgpu_sreg8(vgpu, reg) \ 413 (*(u8 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg))) 414 #define vgpu_sreg16(vgpu, reg) \ 415 (*(u16 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg))) 416 #define vgpu_sreg64(vgpu, reg) \ 417 (*(u64 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg))) 418 419 #define for_each_active_vgpu(gvt, vgpu, id) \ 420 idr_for_each_entry((&(gvt)->vgpu_idr), (vgpu), (id)) \ 421 for_each_if(vgpu->active) 422 423 static inline void intel_vgpu_write_pci_bar(struct intel_vgpu *vgpu, 424 u32 offset, u32 val, bool low) 425 { 426 u32 *pval; 427 428 /* BAR offset should be 32 bits algiend */ 429 offset = rounddown(offset, 4); 430 pval = (u32 *)(vgpu_cfg_space(vgpu) + offset); 431 432 if (low) { 433 /* 434 * only update bit 31 - bit 4, 435 * leave the bit 3 - bit 0 unchanged. 436 */ 437 *pval = (val & GENMASK(31, 4)) | (*pval & GENMASK(3, 0)); 438 } else { 439 *pval = val; 440 } 441 } 442 443 int intel_gvt_init_vgpu_types(struct intel_gvt *gvt); 444 void intel_gvt_clean_vgpu_types(struct intel_gvt *gvt); 445 446 struct intel_vgpu *intel_gvt_create_idle_vgpu(struct intel_gvt *gvt); 447 void intel_gvt_destroy_idle_vgpu(struct intel_vgpu *vgpu); 448 struct intel_vgpu *intel_gvt_create_vgpu(struct intel_gvt *gvt, 449 struct intel_vgpu_type *type); 450 void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu); 451 void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr, 452 unsigned int engine_mask); 453 void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu); 454 void intel_gvt_activate_vgpu(struct intel_vgpu *vgpu); 455 void intel_gvt_deactivate_vgpu(struct intel_vgpu *vgpu); 456 457 /* validating GM functions */ 458 #define vgpu_gmadr_is_aperture(vgpu, gmadr) \ 459 ((gmadr >= vgpu_aperture_gmadr_base(vgpu)) && \ 460 (gmadr <= vgpu_aperture_gmadr_end(vgpu))) 461 462 #define vgpu_gmadr_is_hidden(vgpu, gmadr) \ 463 ((gmadr >= vgpu_hidden_gmadr_base(vgpu)) && \ 464 (gmadr <= vgpu_hidden_gmadr_end(vgpu))) 465 466 #define vgpu_gmadr_is_valid(vgpu, gmadr) \ 467 ((vgpu_gmadr_is_aperture(vgpu, gmadr) || \ 468 (vgpu_gmadr_is_hidden(vgpu, gmadr)))) 469 470 #define gvt_gmadr_is_aperture(gvt, gmadr) \ 471 ((gmadr >= gvt_aperture_gmadr_base(gvt)) && \ 472 (gmadr <= gvt_aperture_gmadr_end(gvt))) 473 474 #define gvt_gmadr_is_hidden(gvt, gmadr) \ 475 ((gmadr >= gvt_hidden_gmadr_base(gvt)) && \ 476 (gmadr <= gvt_hidden_gmadr_end(gvt))) 477 478 #define gvt_gmadr_is_valid(gvt, gmadr) \ 479 (gvt_gmadr_is_aperture(gvt, gmadr) || \ 480 gvt_gmadr_is_hidden(gvt, gmadr)) 481 482 bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size); 483 int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr); 484 int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u64 h_addr, u64 *g_addr); 485 int intel_gvt_ggtt_index_g2h(struct intel_vgpu *vgpu, unsigned long g_index, 486 unsigned long *h_index); 487 int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_index, 488 unsigned long *g_index); 489 490 void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu, 491 bool primary); 492 void intel_vgpu_reset_cfg_space(struct intel_vgpu *vgpu); 493 494 int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset, 495 void *p_data, unsigned int bytes); 496 497 int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset, 498 void *p_data, unsigned int bytes); 499 500 static inline u64 intel_vgpu_get_bar_gpa(struct intel_vgpu *vgpu, int bar) 501 { 502 /* We are 64bit bar. */ 503 return (*(u64 *)(vgpu->cfg_space.virtual_cfg_space + bar)) & 504 PCI_BASE_ADDRESS_MEM_MASK; 505 } 506 507 void intel_vgpu_clean_opregion(struct intel_vgpu *vgpu); 508 int intel_vgpu_init_opregion(struct intel_vgpu *vgpu, u32 gpa); 509 510 int intel_vgpu_emulate_opregion_request(struct intel_vgpu *vgpu, u32 swsci); 511 void populate_pvinfo_page(struct intel_vgpu *vgpu); 512 513 int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload); 514 void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason); 515 516 struct intel_gvt_ops { 517 int (*emulate_cfg_read)(struct intel_vgpu *, unsigned int, void *, 518 unsigned int); 519 int (*emulate_cfg_write)(struct intel_vgpu *, unsigned int, void *, 520 unsigned int); 521 int (*emulate_mmio_read)(struct intel_vgpu *, u64, void *, 522 unsigned int); 523 int (*emulate_mmio_write)(struct intel_vgpu *, u64, void *, 524 unsigned int); 525 struct intel_vgpu *(*vgpu_create)(struct intel_gvt *, 526 struct intel_vgpu_type *); 527 void (*vgpu_destroy)(struct intel_vgpu *); 528 void (*vgpu_reset)(struct intel_vgpu *); 529 void (*vgpu_activate)(struct intel_vgpu *); 530 void (*vgpu_deactivate)(struct intel_vgpu *); 531 struct intel_vgpu_type *(*gvt_find_vgpu_type)(struct intel_gvt *gvt, 532 const char *name); 533 bool (*get_gvt_attrs)(struct attribute ***type_attrs, 534 struct attribute_group ***intel_vgpu_type_groups); 535 }; 536 537 538 enum { 539 GVT_FAILSAFE_UNSUPPORTED_GUEST, 540 GVT_FAILSAFE_INSUFFICIENT_RESOURCE, 541 GVT_FAILSAFE_GUEST_ERR, 542 }; 543 544 static inline void mmio_hw_access_pre(struct drm_i915_private *dev_priv) 545 { 546 intel_runtime_pm_get(dev_priv); 547 } 548 549 static inline void mmio_hw_access_post(struct drm_i915_private *dev_priv) 550 { 551 intel_runtime_pm_put(dev_priv); 552 } 553 554 /** 555 * intel_gvt_mmio_set_accessed - mark a MMIO has been accessed 556 * @gvt: a GVT device 557 * @offset: register offset 558 * 559 */ 560 static inline void intel_gvt_mmio_set_accessed( 561 struct intel_gvt *gvt, unsigned int offset) 562 { 563 gvt->mmio.mmio_attribute[offset >> 2] |= F_ACCESSED; 564 } 565 566 /** 567 * intel_gvt_mmio_is_cmd_accessed - mark a MMIO could be accessed by command 568 * @gvt: a GVT device 569 * @offset: register offset 570 * 571 */ 572 static inline bool intel_gvt_mmio_is_cmd_access( 573 struct intel_gvt *gvt, unsigned int offset) 574 { 575 return gvt->mmio.mmio_attribute[offset >> 2] & F_CMD_ACCESS; 576 } 577 578 /** 579 * intel_gvt_mmio_is_unalign - mark a MMIO could be accessed unaligned 580 * @gvt: a GVT device 581 * @offset: register offset 582 * 583 */ 584 static inline bool intel_gvt_mmio_is_unalign( 585 struct intel_gvt *gvt, unsigned int offset) 586 { 587 return gvt->mmio.mmio_attribute[offset >> 2] & F_UNALIGN; 588 } 589 590 /** 591 * intel_gvt_mmio_set_cmd_accessed - mark a MMIO has been accessed by command 592 * @gvt: a GVT device 593 * @offset: register offset 594 * 595 */ 596 static inline void intel_gvt_mmio_set_cmd_accessed( 597 struct intel_gvt *gvt, unsigned int offset) 598 { 599 gvt->mmio.mmio_attribute[offset >> 2] |= F_CMD_ACCESSED; 600 } 601 602 /** 603 * intel_gvt_mmio_has_mode_mask - if a MMIO has a mode mask 604 * @gvt: a GVT device 605 * @offset: register offset 606 * 607 * Returns: 608 * True if a MMIO has a mode mask in its higher 16 bits, false if it isn't. 609 * 610 */ 611 static inline bool intel_gvt_mmio_has_mode_mask( 612 struct intel_gvt *gvt, unsigned int offset) 613 { 614 return gvt->mmio.mmio_attribute[offset >> 2] & F_MODE_MASK; 615 } 616 617 int intel_gvt_debugfs_add_vgpu(struct intel_vgpu *vgpu); 618 void intel_gvt_debugfs_remove_vgpu(struct intel_vgpu *vgpu); 619 int intel_gvt_debugfs_init(struct intel_gvt *gvt); 620 void intel_gvt_debugfs_clean(struct intel_gvt *gvt); 621 622 623 #include "trace.h" 624 #include "mpt.h" 625 626 #endif 627