1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Kevin Tian <kevin.tian@intel.com> 25 * Eddie Dong <eddie.dong@intel.com> 26 * 27 * Contributors: 28 * Niu Bing <bing.niu@intel.com> 29 * Zhi Wang <zhi.a.wang@intel.com> 30 * 31 */ 32 33 #ifndef _GVT_H_ 34 #define _GVT_H_ 35 36 #include <uapi/linux/pci_regs.h> 37 38 #include "i915_drv.h" 39 40 #include "debug.h" 41 #include "hypercall.h" 42 #include "mmio.h" 43 #include "reg.h" 44 #include "interrupt.h" 45 #include "gtt.h" 46 #include "display.h" 47 #include "edid.h" 48 #include "execlist.h" 49 #include "scheduler.h" 50 #include "sched_policy.h" 51 #include "mmio_context.h" 52 #include "cmd_parser.h" 53 #include "fb_decoder.h" 54 #include "dmabuf.h" 55 #include "page_track.h" 56 57 #define GVT_MAX_VGPU 8 58 59 struct intel_gvt_host { 60 struct device *dev; 61 bool initialized; 62 int hypervisor_type; 63 const struct intel_gvt_mpt *mpt; 64 }; 65 66 extern struct intel_gvt_host intel_gvt_host; 67 68 /* Describe per-platform limitations. */ 69 struct intel_gvt_device_info { 70 u32 max_support_vgpus; 71 u32 cfg_space_size; 72 u32 mmio_size; 73 u32 mmio_bar; 74 unsigned long msi_cap_offset; 75 u32 gtt_start_offset; 76 u32 gtt_entry_size; 77 u32 gtt_entry_size_shift; 78 int gmadr_bytes_in_cmd; 79 u32 max_surface_size; 80 }; 81 82 /* GM resources owned by a vGPU */ 83 struct intel_vgpu_gm { 84 u64 aperture_sz; 85 u64 hidden_sz; 86 struct drm_mm_node low_gm_node; 87 struct drm_mm_node high_gm_node; 88 }; 89 90 #define INTEL_GVT_MAX_NUM_FENCES 32 91 92 /* Fences owned by a vGPU */ 93 struct intel_vgpu_fence { 94 struct i915_fence_reg *regs[INTEL_GVT_MAX_NUM_FENCES]; 95 u32 base; 96 u32 size; 97 }; 98 99 struct intel_vgpu_mmio { 100 void *vreg; 101 }; 102 103 #define INTEL_GVT_MAX_BAR_NUM 4 104 105 struct intel_vgpu_pci_bar { 106 u64 size; 107 bool tracked; 108 }; 109 110 struct intel_vgpu_cfg_space { 111 unsigned char virtual_cfg_space[PCI_CFG_SPACE_EXP_SIZE]; 112 struct intel_vgpu_pci_bar bar[INTEL_GVT_MAX_BAR_NUM]; 113 u32 pmcsr_off; 114 }; 115 116 #define vgpu_cfg_space(vgpu) ((vgpu)->cfg_space.virtual_cfg_space) 117 118 struct intel_vgpu_irq { 119 bool irq_warn_once[INTEL_GVT_EVENT_MAX]; 120 DECLARE_BITMAP(flip_done_event[I915_MAX_PIPES], 121 INTEL_GVT_EVENT_MAX); 122 }; 123 124 struct intel_vgpu_opregion { 125 bool mapped; 126 void *va; 127 u32 gfn[INTEL_GVT_OPREGION_PAGES]; 128 }; 129 130 #define vgpu_opregion(vgpu) (&(vgpu->opregion)) 131 132 struct intel_vgpu_display { 133 struct intel_vgpu_i2c_edid i2c_edid; 134 struct intel_vgpu_port ports[I915_MAX_PORTS]; 135 struct intel_vgpu_sbi sbi; 136 }; 137 138 struct vgpu_sched_ctl { 139 int weight; 140 }; 141 142 enum { 143 INTEL_VGPU_EXECLIST_SUBMISSION = 1, 144 INTEL_VGPU_GUC_SUBMISSION, 145 }; 146 147 struct intel_vgpu_submission_ops { 148 const char *name; 149 int (*init)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask); 150 void (*clean)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask); 151 void (*reset)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask); 152 }; 153 154 struct intel_vgpu_submission { 155 struct intel_vgpu_execlist execlist[I915_NUM_ENGINES]; 156 struct list_head workload_q_head[I915_NUM_ENGINES]; 157 struct intel_context *shadow[I915_NUM_ENGINES]; 158 struct kmem_cache *workloads; 159 atomic_t running_workload_num; 160 union { 161 u64 i915_context_pml4; 162 u64 i915_context_pdps[GEN8_3LVL_PDPES]; 163 }; 164 DECLARE_BITMAP(shadow_ctx_desc_updated, I915_NUM_ENGINES); 165 DECLARE_BITMAP(tlb_handle_pending, I915_NUM_ENGINES); 166 void *ring_scan_buffer[I915_NUM_ENGINES]; 167 int ring_scan_buffer_size[I915_NUM_ENGINES]; 168 const struct intel_vgpu_submission_ops *ops; 169 int virtual_submission_interface; 170 bool active; 171 struct { 172 u32 lrca; 173 bool valid; 174 u64 ring_context_gpa; 175 } last_ctx[I915_NUM_ENGINES]; 176 }; 177 178 struct intel_vgpu { 179 struct intel_gvt *gvt; 180 struct mutex vgpu_lock; 181 int id; 182 unsigned long handle; /* vGPU handle used by hypervisor MPT modules */ 183 bool active; 184 bool pv_notified; 185 bool failsafe; 186 unsigned int resetting_eng; 187 188 /* Both sched_data and sched_ctl can be seen a part of the global gvt 189 * scheduler structure. So below 2 vgpu data are protected 190 * by sched_lock, not vgpu_lock. 191 */ 192 void *sched_data; 193 struct vgpu_sched_ctl sched_ctl; 194 195 struct intel_vgpu_fence fence; 196 struct intel_vgpu_gm gm; 197 struct intel_vgpu_cfg_space cfg_space; 198 struct intel_vgpu_mmio mmio; 199 struct intel_vgpu_irq irq; 200 struct intel_vgpu_gtt gtt; 201 struct intel_vgpu_opregion opregion; 202 struct intel_vgpu_display display; 203 struct intel_vgpu_submission submission; 204 struct radix_tree_root page_track_tree; 205 u32 hws_pga[I915_NUM_ENGINES]; 206 /* Set on PCI_D3, reset on DMLR, not reflecting the actual PM state */ 207 bool d3_entered; 208 209 struct dentry *debugfs; 210 211 /* Hypervisor-specific device state. */ 212 void *vdev; 213 214 struct list_head dmabuf_obj_list_head; 215 struct mutex dmabuf_lock; 216 struct idr object_idr; 217 218 u32 scan_nonprivbb; 219 }; 220 221 static inline void *intel_vgpu_vdev(struct intel_vgpu *vgpu) 222 { 223 return vgpu->vdev; 224 } 225 226 /* validating GM healthy status*/ 227 #define vgpu_is_vm_unhealthy(ret_val) \ 228 (((ret_val) == -EBADRQC) || ((ret_val) == -EFAULT)) 229 230 struct intel_gvt_gm { 231 unsigned long vgpu_allocated_low_gm_size; 232 unsigned long vgpu_allocated_high_gm_size; 233 }; 234 235 struct intel_gvt_fence { 236 unsigned long vgpu_allocated_fence_num; 237 }; 238 239 /* Special MMIO blocks. */ 240 struct gvt_mmio_block { 241 unsigned int device; 242 i915_reg_t offset; 243 unsigned int size; 244 gvt_mmio_func read; 245 gvt_mmio_func write; 246 }; 247 248 #define INTEL_GVT_MMIO_HASH_BITS 11 249 250 struct intel_gvt_mmio { 251 u8 *mmio_attribute; 252 /* Register contains RO bits */ 253 #define F_RO (1 << 0) 254 /* Register contains graphics address */ 255 #define F_GMADR (1 << 1) 256 /* Mode mask registers with high 16 bits as the mask bits */ 257 #define F_MODE_MASK (1 << 2) 258 /* This reg can be accessed by GPU commands */ 259 #define F_CMD_ACCESS (1 << 3) 260 /* This reg has been accessed by a VM */ 261 #define F_ACCESSED (1 << 4) 262 /* This reg requires save & restore during host PM suspend/resume */ 263 #define F_PM_SAVE (1 << 5) 264 /* This reg could be accessed by unaligned address */ 265 #define F_UNALIGN (1 << 6) 266 /* This reg is in GVT's mmio save-restor list and in hardware 267 * logical context image 268 */ 269 #define F_SR_IN_CTX (1 << 7) 270 271 struct gvt_mmio_block *mmio_block; 272 unsigned int num_mmio_block; 273 274 DECLARE_HASHTABLE(mmio_info_table, INTEL_GVT_MMIO_HASH_BITS); 275 unsigned long num_tracked_mmio; 276 }; 277 278 struct intel_gvt_firmware { 279 void *cfg_space; 280 void *mmio; 281 bool firmware_loaded; 282 }; 283 284 #define NR_MAX_INTEL_VGPU_TYPES 20 285 struct intel_vgpu_type { 286 char name[16]; 287 unsigned int avail_instance; 288 unsigned int low_gm_size; 289 unsigned int high_gm_size; 290 unsigned int fence; 291 unsigned int weight; 292 enum intel_vgpu_edid resolution; 293 }; 294 295 struct intel_gvt { 296 /* GVT scope lock, protect GVT itself, and all resource currently 297 * not yet protected by special locks(vgpu and scheduler lock). 298 */ 299 struct mutex lock; 300 /* scheduler scope lock, protect gvt and vgpu schedule related data */ 301 struct mutex sched_lock; 302 303 struct intel_gt *gt; 304 struct idr vgpu_idr; /* vGPU IDR pool */ 305 306 struct intel_gvt_device_info device_info; 307 struct intel_gvt_gm gm; 308 struct intel_gvt_fence fence; 309 struct intel_gvt_mmio mmio; 310 struct intel_gvt_firmware firmware; 311 struct intel_gvt_irq irq; 312 struct intel_gvt_gtt gtt; 313 struct intel_gvt_workload_scheduler scheduler; 314 struct notifier_block shadow_ctx_notifier_block[I915_NUM_ENGINES]; 315 DECLARE_HASHTABLE(cmd_table, GVT_CMD_HASH_BITS); 316 struct intel_vgpu_type *types; 317 unsigned int num_types; 318 struct intel_vgpu *idle_vgpu; 319 320 struct task_struct *service_thread; 321 wait_queue_head_t service_thread_wq; 322 323 /* service_request is always used in bit operation, we should always 324 * use it with atomic bit ops so that no need to use gvt big lock. 325 */ 326 unsigned long service_request; 327 328 struct { 329 struct engine_mmio *mmio; 330 int ctx_mmio_count[I915_NUM_ENGINES]; 331 u32 *tlb_mmio_offset_list; 332 u32 tlb_mmio_offset_list_cnt; 333 u32 *mocs_mmio_offset_list; 334 u32 mocs_mmio_offset_list_cnt; 335 } engine_mmio_list; 336 337 struct dentry *debugfs_root; 338 }; 339 340 static inline struct intel_gvt *to_gvt(struct drm_i915_private *i915) 341 { 342 return i915->gvt; 343 } 344 345 enum { 346 INTEL_GVT_REQUEST_EMULATE_VBLANK = 0, 347 348 /* Scheduling trigger by timer */ 349 INTEL_GVT_REQUEST_SCHED = 1, 350 351 /* Scheduling trigger by event */ 352 INTEL_GVT_REQUEST_EVENT_SCHED = 2, 353 }; 354 355 static inline void intel_gvt_request_service(struct intel_gvt *gvt, 356 int service) 357 { 358 set_bit(service, (void *)&gvt->service_request); 359 wake_up(&gvt->service_thread_wq); 360 } 361 362 void intel_gvt_free_firmware(struct intel_gvt *gvt); 363 int intel_gvt_load_firmware(struct intel_gvt *gvt); 364 365 /* Aperture/GM space definitions for GVT device */ 366 #define MB_TO_BYTES(mb) ((mb) << 20ULL) 367 #define BYTES_TO_MB(b) ((b) >> 20ULL) 368 369 #define HOST_LOW_GM_SIZE MB_TO_BYTES(128) 370 #define HOST_HIGH_GM_SIZE MB_TO_BYTES(384) 371 #define HOST_FENCE 4 372 373 #define gvt_to_ggtt(gvt) ((gvt)->gt->ggtt) 374 375 /* Aperture/GM space definitions for GVT device */ 376 #define gvt_aperture_sz(gvt) gvt_to_ggtt(gvt)->mappable_end 377 #define gvt_aperture_pa_base(gvt) gvt_to_ggtt(gvt)->gmadr.start 378 379 #define gvt_ggtt_gm_sz(gvt) gvt_to_ggtt(gvt)->vm.total 380 #define gvt_ggtt_sz(gvt) (gvt_to_ggtt(gvt)->vm.total >> PAGE_SHIFT << 3) 381 #define gvt_hidden_sz(gvt) (gvt_ggtt_gm_sz(gvt) - gvt_aperture_sz(gvt)) 382 383 #define gvt_aperture_gmadr_base(gvt) (0) 384 #define gvt_aperture_gmadr_end(gvt) (gvt_aperture_gmadr_base(gvt) \ 385 + gvt_aperture_sz(gvt) - 1) 386 387 #define gvt_hidden_gmadr_base(gvt) (gvt_aperture_gmadr_base(gvt) \ 388 + gvt_aperture_sz(gvt)) 389 #define gvt_hidden_gmadr_end(gvt) (gvt_hidden_gmadr_base(gvt) \ 390 + gvt_hidden_sz(gvt) - 1) 391 392 #define gvt_fence_sz(gvt) (gvt_to_ggtt(gvt)->num_fences) 393 394 /* Aperture/GM space definitions for vGPU */ 395 #define vgpu_aperture_offset(vgpu) ((vgpu)->gm.low_gm_node.start) 396 #define vgpu_hidden_offset(vgpu) ((vgpu)->gm.high_gm_node.start) 397 #define vgpu_aperture_sz(vgpu) ((vgpu)->gm.aperture_sz) 398 #define vgpu_hidden_sz(vgpu) ((vgpu)->gm.hidden_sz) 399 400 #define vgpu_aperture_pa_base(vgpu) \ 401 (gvt_aperture_pa_base(vgpu->gvt) + vgpu_aperture_offset(vgpu)) 402 403 #define vgpu_ggtt_gm_sz(vgpu) ((vgpu)->gm.aperture_sz + (vgpu)->gm.hidden_sz) 404 405 #define vgpu_aperture_pa_end(vgpu) \ 406 (vgpu_aperture_pa_base(vgpu) + vgpu_aperture_sz(vgpu) - 1) 407 408 #define vgpu_aperture_gmadr_base(vgpu) (vgpu_aperture_offset(vgpu)) 409 #define vgpu_aperture_gmadr_end(vgpu) \ 410 (vgpu_aperture_gmadr_base(vgpu) + vgpu_aperture_sz(vgpu) - 1) 411 412 #define vgpu_hidden_gmadr_base(vgpu) (vgpu_hidden_offset(vgpu)) 413 #define vgpu_hidden_gmadr_end(vgpu) \ 414 (vgpu_hidden_gmadr_base(vgpu) + vgpu_hidden_sz(vgpu) - 1) 415 416 #define vgpu_fence_base(vgpu) (vgpu->fence.base) 417 #define vgpu_fence_sz(vgpu) (vgpu->fence.size) 418 419 struct intel_vgpu_creation_params { 420 __u64 handle; 421 __u64 low_gm_sz; /* in MB */ 422 __u64 high_gm_sz; /* in MB */ 423 __u64 fence_sz; 424 __u64 resolution; 425 __s32 primary; 426 __u64 vgpu_id; 427 428 __u32 weight; 429 }; 430 431 int intel_vgpu_alloc_resource(struct intel_vgpu *vgpu, 432 struct intel_vgpu_creation_params *param); 433 void intel_vgpu_reset_resource(struct intel_vgpu *vgpu); 434 void intel_vgpu_free_resource(struct intel_vgpu *vgpu); 435 void intel_vgpu_write_fence(struct intel_vgpu *vgpu, 436 u32 fence, u64 value); 437 438 /* Macros for easily accessing vGPU virtual/shadow register. 439 Explicitly seperate use for typed MMIO reg or real offset.*/ 440 #define vgpu_vreg_t(vgpu, reg) \ 441 (*(u32 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg))) 442 #define vgpu_vreg(vgpu, offset) \ 443 (*(u32 *)(vgpu->mmio.vreg + (offset))) 444 #define vgpu_vreg64_t(vgpu, reg) \ 445 (*(u64 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg))) 446 #define vgpu_vreg64(vgpu, offset) \ 447 (*(u64 *)(vgpu->mmio.vreg + (offset))) 448 449 #define for_each_active_vgpu(gvt, vgpu, id) \ 450 idr_for_each_entry((&(gvt)->vgpu_idr), (vgpu), (id)) \ 451 for_each_if(vgpu->active) 452 453 static inline void intel_vgpu_write_pci_bar(struct intel_vgpu *vgpu, 454 u32 offset, u32 val, bool low) 455 { 456 u32 *pval; 457 458 /* BAR offset should be 32 bits algiend */ 459 offset = rounddown(offset, 4); 460 pval = (u32 *)(vgpu_cfg_space(vgpu) + offset); 461 462 if (low) { 463 /* 464 * only update bit 31 - bit 4, 465 * leave the bit 3 - bit 0 unchanged. 466 */ 467 *pval = (val & GENMASK(31, 4)) | (*pval & GENMASK(3, 0)); 468 } else { 469 *pval = val; 470 } 471 } 472 473 int intel_gvt_init_vgpu_types(struct intel_gvt *gvt); 474 void intel_gvt_clean_vgpu_types(struct intel_gvt *gvt); 475 476 struct intel_vgpu *intel_gvt_create_idle_vgpu(struct intel_gvt *gvt); 477 void intel_gvt_destroy_idle_vgpu(struct intel_vgpu *vgpu); 478 struct intel_vgpu *intel_gvt_create_vgpu(struct intel_gvt *gvt, 479 struct intel_vgpu_type *type); 480 void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu); 481 void intel_gvt_release_vgpu(struct intel_vgpu *vgpu); 482 void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr, 483 intel_engine_mask_t engine_mask); 484 void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu); 485 void intel_gvt_activate_vgpu(struct intel_vgpu *vgpu); 486 void intel_gvt_deactivate_vgpu(struct intel_vgpu *vgpu); 487 488 /* validating GM functions */ 489 #define vgpu_gmadr_is_aperture(vgpu, gmadr) \ 490 ((gmadr >= vgpu_aperture_gmadr_base(vgpu)) && \ 491 (gmadr <= vgpu_aperture_gmadr_end(vgpu))) 492 493 #define vgpu_gmadr_is_hidden(vgpu, gmadr) \ 494 ((gmadr >= vgpu_hidden_gmadr_base(vgpu)) && \ 495 (gmadr <= vgpu_hidden_gmadr_end(vgpu))) 496 497 #define vgpu_gmadr_is_valid(vgpu, gmadr) \ 498 ((vgpu_gmadr_is_aperture(vgpu, gmadr) || \ 499 (vgpu_gmadr_is_hidden(vgpu, gmadr)))) 500 501 #define gvt_gmadr_is_aperture(gvt, gmadr) \ 502 ((gmadr >= gvt_aperture_gmadr_base(gvt)) && \ 503 (gmadr <= gvt_aperture_gmadr_end(gvt))) 504 505 #define gvt_gmadr_is_hidden(gvt, gmadr) \ 506 ((gmadr >= gvt_hidden_gmadr_base(gvt)) && \ 507 (gmadr <= gvt_hidden_gmadr_end(gvt))) 508 509 #define gvt_gmadr_is_valid(gvt, gmadr) \ 510 (gvt_gmadr_is_aperture(gvt, gmadr) || \ 511 gvt_gmadr_is_hidden(gvt, gmadr)) 512 513 bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size); 514 int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr); 515 int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u64 h_addr, u64 *g_addr); 516 int intel_gvt_ggtt_index_g2h(struct intel_vgpu *vgpu, unsigned long g_index, 517 unsigned long *h_index); 518 int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_index, 519 unsigned long *g_index); 520 521 void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu, 522 bool primary); 523 void intel_vgpu_reset_cfg_space(struct intel_vgpu *vgpu); 524 525 int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset, 526 void *p_data, unsigned int bytes); 527 528 int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset, 529 void *p_data, unsigned int bytes); 530 531 void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected); 532 533 static inline u64 intel_vgpu_get_bar_gpa(struct intel_vgpu *vgpu, int bar) 534 { 535 /* We are 64bit bar. */ 536 return (*(u64 *)(vgpu->cfg_space.virtual_cfg_space + bar)) & 537 PCI_BASE_ADDRESS_MEM_MASK; 538 } 539 540 void intel_vgpu_clean_opregion(struct intel_vgpu *vgpu); 541 int intel_vgpu_init_opregion(struct intel_vgpu *vgpu); 542 int intel_vgpu_opregion_base_write_handler(struct intel_vgpu *vgpu, u32 gpa); 543 544 int intel_vgpu_emulate_opregion_request(struct intel_vgpu *vgpu, u32 swsci); 545 void populate_pvinfo_page(struct intel_vgpu *vgpu); 546 547 int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload); 548 void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason); 549 550 struct intel_gvt_ops { 551 int (*emulate_cfg_read)(struct intel_vgpu *, unsigned int, void *, 552 unsigned int); 553 int (*emulate_cfg_write)(struct intel_vgpu *, unsigned int, void *, 554 unsigned int); 555 int (*emulate_mmio_read)(struct intel_vgpu *, u64, void *, 556 unsigned int); 557 int (*emulate_mmio_write)(struct intel_vgpu *, u64, void *, 558 unsigned int); 559 struct intel_vgpu *(*vgpu_create)(struct intel_gvt *, 560 struct intel_vgpu_type *); 561 void (*vgpu_destroy)(struct intel_vgpu *vgpu); 562 void (*vgpu_release)(struct intel_vgpu *vgpu); 563 void (*vgpu_reset)(struct intel_vgpu *); 564 void (*vgpu_activate)(struct intel_vgpu *); 565 void (*vgpu_deactivate)(struct intel_vgpu *); 566 struct intel_vgpu_type *(*gvt_find_vgpu_type)(struct intel_gvt *gvt, 567 const char *name); 568 bool (*get_gvt_attrs)(struct attribute_group ***intel_vgpu_type_groups); 569 int (*vgpu_query_plane)(struct intel_vgpu *vgpu, void *); 570 int (*vgpu_get_dmabuf)(struct intel_vgpu *vgpu, unsigned int); 571 int (*write_protect_handler)(struct intel_vgpu *, u64, void *, 572 unsigned int); 573 void (*emulate_hotplug)(struct intel_vgpu *vgpu, bool connected); 574 }; 575 576 577 enum { 578 GVT_FAILSAFE_UNSUPPORTED_GUEST, 579 GVT_FAILSAFE_INSUFFICIENT_RESOURCE, 580 GVT_FAILSAFE_GUEST_ERR, 581 }; 582 583 static inline void mmio_hw_access_pre(struct intel_gt *gt) 584 { 585 intel_runtime_pm_get(gt->uncore->rpm); 586 } 587 588 static inline void mmio_hw_access_post(struct intel_gt *gt) 589 { 590 intel_runtime_pm_put_unchecked(gt->uncore->rpm); 591 } 592 593 /** 594 * intel_gvt_mmio_set_accessed - mark a MMIO has been accessed 595 * @gvt: a GVT device 596 * @offset: register offset 597 * 598 */ 599 static inline void intel_gvt_mmio_set_accessed( 600 struct intel_gvt *gvt, unsigned int offset) 601 { 602 gvt->mmio.mmio_attribute[offset >> 2] |= F_ACCESSED; 603 } 604 605 /** 606 * intel_gvt_mmio_is_cmd_accessible - if a MMIO could be accessed by command 607 * @gvt: a GVT device 608 * @offset: register offset 609 * 610 * Returns: 611 * True if an MMIO is able to be accessed by GPU commands 612 */ 613 static inline bool intel_gvt_mmio_is_cmd_accessible( 614 struct intel_gvt *gvt, unsigned int offset) 615 { 616 return gvt->mmio.mmio_attribute[offset >> 2] & F_CMD_ACCESS; 617 } 618 619 /** 620 * intel_gvt_mmio_set_cmd_accessible - 621 * mark a MMIO could be accessible by command 622 * @gvt: a GVT device 623 * @offset: register offset 624 * 625 */ 626 static inline void intel_gvt_mmio_set_cmd_accessible( 627 struct intel_gvt *gvt, unsigned int offset) 628 { 629 gvt->mmio.mmio_attribute[offset >> 2] |= F_CMD_ACCESS; 630 } 631 632 /** 633 * intel_gvt_mmio_is_unalign - mark a MMIO could be accessed unaligned 634 * @gvt: a GVT device 635 * @offset: register offset 636 * 637 */ 638 static inline bool intel_gvt_mmio_is_unalign( 639 struct intel_gvt *gvt, unsigned int offset) 640 { 641 return gvt->mmio.mmio_attribute[offset >> 2] & F_UNALIGN; 642 } 643 644 /** 645 * intel_gvt_mmio_has_mode_mask - if a MMIO has a mode mask 646 * @gvt: a GVT device 647 * @offset: register offset 648 * 649 * Returns: 650 * True if a MMIO has a mode mask in its higher 16 bits, false if it isn't. 651 * 652 */ 653 static inline bool intel_gvt_mmio_has_mode_mask( 654 struct intel_gvt *gvt, unsigned int offset) 655 { 656 return gvt->mmio.mmio_attribute[offset >> 2] & F_MODE_MASK; 657 } 658 659 /** 660 * intel_gvt_mmio_is_sr_in_ctx - 661 * check if an MMIO has F_SR_IN_CTX mask 662 * @gvt: a GVT device 663 * @offset: register offset 664 * 665 * Returns: 666 * True if an MMIO has an F_SR_IN_CTX mask, false if it isn't. 667 * 668 */ 669 static inline bool intel_gvt_mmio_is_sr_in_ctx( 670 struct intel_gvt *gvt, unsigned int offset) 671 { 672 return gvt->mmio.mmio_attribute[offset >> 2] & F_SR_IN_CTX; 673 } 674 675 /** 676 * intel_gvt_mmio_set_sr_in_ctx - 677 * mask an MMIO in GVT's mmio save-restore list and also 678 * in hardware logical context image 679 * @gvt: a GVT device 680 * @offset: register offset 681 * 682 */ 683 static inline void intel_gvt_mmio_set_sr_in_ctx( 684 struct intel_gvt *gvt, unsigned int offset) 685 { 686 gvt->mmio.mmio_attribute[offset >> 2] |= F_SR_IN_CTX; 687 } 688 689 void intel_gvt_debugfs_add_vgpu(struct intel_vgpu *vgpu); 690 void intel_gvt_debugfs_remove_vgpu(struct intel_vgpu *vgpu); 691 void intel_gvt_debugfs_init(struct intel_gvt *gvt); 692 void intel_gvt_debugfs_clean(struct intel_gvt *gvt); 693 694 int intel_gvt_pm_resume(struct intel_gvt *gvt); 695 696 #include "trace.h" 697 #include "mpt.h" 698 699 #endif 700