1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Kevin Tian <kevin.tian@intel.com> 25 * Eddie Dong <eddie.dong@intel.com> 26 * 27 * Contributors: 28 * Niu Bing <bing.niu@intel.com> 29 * Zhi Wang <zhi.a.wang@intel.com> 30 * 31 */ 32 33 #ifndef _GVT_H_ 34 #define _GVT_H_ 35 36 #include "debug.h" 37 #include "hypercall.h" 38 #include "mmio.h" 39 #include "reg.h" 40 #include "interrupt.h" 41 #include "gtt.h" 42 #include "display.h" 43 #include "edid.h" 44 #include "execlist.h" 45 #include "scheduler.h" 46 #include "sched_policy.h" 47 #include "render.h" 48 #include "cmd_parser.h" 49 50 #define GVT_MAX_VGPU 8 51 52 enum { 53 INTEL_GVT_HYPERVISOR_XEN = 0, 54 INTEL_GVT_HYPERVISOR_KVM, 55 }; 56 57 struct intel_gvt_host { 58 bool initialized; 59 int hypervisor_type; 60 struct intel_gvt_mpt *mpt; 61 }; 62 63 extern struct intel_gvt_host intel_gvt_host; 64 65 /* Describe per-platform limitations. */ 66 struct intel_gvt_device_info { 67 u32 max_support_vgpus; 68 u32 cfg_space_size; 69 u32 mmio_size; 70 u32 mmio_bar; 71 unsigned long msi_cap_offset; 72 u32 gtt_start_offset; 73 u32 gtt_entry_size; 74 u32 gtt_entry_size_shift; 75 int gmadr_bytes_in_cmd; 76 u32 max_surface_size; 77 }; 78 79 /* GM resources owned by a vGPU */ 80 struct intel_vgpu_gm { 81 u64 aperture_sz; 82 u64 hidden_sz; 83 struct drm_mm_node low_gm_node; 84 struct drm_mm_node high_gm_node; 85 }; 86 87 #define INTEL_GVT_MAX_NUM_FENCES 32 88 89 /* Fences owned by a vGPU */ 90 struct intel_vgpu_fence { 91 struct drm_i915_fence_reg *regs[INTEL_GVT_MAX_NUM_FENCES]; 92 u32 base; 93 u32 size; 94 }; 95 96 struct intel_vgpu_mmio { 97 void *vreg; 98 void *sreg; 99 bool disable_warn_untrack; 100 }; 101 102 #define INTEL_GVT_MAX_CFG_SPACE_SZ 256 103 #define INTEL_GVT_MAX_BAR_NUM 4 104 105 struct intel_vgpu_pci_bar { 106 u64 size; 107 bool tracked; 108 }; 109 110 struct intel_vgpu_cfg_space { 111 unsigned char virtual_cfg_space[INTEL_GVT_MAX_CFG_SPACE_SZ]; 112 struct intel_vgpu_pci_bar bar[INTEL_GVT_MAX_BAR_NUM]; 113 }; 114 115 #define vgpu_cfg_space(vgpu) ((vgpu)->cfg_space.virtual_cfg_space) 116 117 #define INTEL_GVT_MAX_PIPE 4 118 119 struct intel_vgpu_irq { 120 bool irq_warn_once[INTEL_GVT_EVENT_MAX]; 121 DECLARE_BITMAP(flip_done_event[INTEL_GVT_MAX_PIPE], 122 INTEL_GVT_EVENT_MAX); 123 }; 124 125 struct intel_vgpu_opregion { 126 void *va; 127 u32 gfn[INTEL_GVT_OPREGION_PAGES]; 128 struct page *pages[INTEL_GVT_OPREGION_PAGES]; 129 }; 130 131 #define vgpu_opregion(vgpu) (&(vgpu->opregion)) 132 133 #define INTEL_GVT_MAX_PORT 5 134 135 struct intel_vgpu_display { 136 struct intel_vgpu_i2c_edid i2c_edid; 137 struct intel_vgpu_port ports[INTEL_GVT_MAX_PORT]; 138 struct intel_vgpu_sbi sbi; 139 }; 140 141 struct vgpu_sched_ctl { 142 int weight; 143 }; 144 145 struct intel_vgpu { 146 struct intel_gvt *gvt; 147 int id; 148 unsigned long handle; /* vGPU handle used by hypervisor MPT modules */ 149 bool active; 150 bool pv_notified; 151 bool failsafe; 152 unsigned int resetting_eng; 153 void *sched_data; 154 struct vgpu_sched_ctl sched_ctl; 155 156 struct intel_vgpu_fence fence; 157 struct intel_vgpu_gm gm; 158 struct intel_vgpu_cfg_space cfg_space; 159 struct intel_vgpu_mmio mmio; 160 struct intel_vgpu_irq irq; 161 struct intel_vgpu_gtt gtt; 162 struct intel_vgpu_opregion opregion; 163 struct intel_vgpu_display display; 164 struct intel_vgpu_execlist execlist[I915_NUM_ENGINES]; 165 struct list_head workload_q_head[I915_NUM_ENGINES]; 166 struct kmem_cache *workloads; 167 atomic_t running_workload_num; 168 DECLARE_BITMAP(tlb_handle_pending, I915_NUM_ENGINES); 169 struct i915_gem_context *shadow_ctx; 170 DECLARE_BITMAP(shadow_ctx_desc_updated, I915_NUM_ENGINES); 171 172 #if IS_ENABLED(CONFIG_DRM_I915_GVT_KVMGT) 173 struct { 174 struct mdev_device *mdev; 175 struct vfio_region *region; 176 int num_regions; 177 struct eventfd_ctx *intx_trigger; 178 struct eventfd_ctx *msi_trigger; 179 struct rb_root cache; 180 struct mutex cache_lock; 181 struct notifier_block iommu_notifier; 182 struct notifier_block group_notifier; 183 struct kvm *kvm; 184 struct work_struct release_work; 185 atomic_t released; 186 } vdev; 187 #endif 188 }; 189 190 struct intel_gvt_gm { 191 unsigned long vgpu_allocated_low_gm_size; 192 unsigned long vgpu_allocated_high_gm_size; 193 }; 194 195 struct intel_gvt_fence { 196 unsigned long vgpu_allocated_fence_num; 197 }; 198 199 /* Special MMIO blocks. */ 200 struct gvt_mmio_block { 201 unsigned int device; 202 i915_reg_t offset; 203 unsigned int size; 204 gvt_mmio_func read; 205 gvt_mmio_func write; 206 }; 207 208 #define INTEL_GVT_MMIO_HASH_BITS 11 209 210 struct intel_gvt_mmio { 211 u8 *mmio_attribute; 212 /* Register contains RO bits */ 213 #define F_RO (1 << 0) 214 /* Register contains graphics address */ 215 #define F_GMADR (1 << 1) 216 /* Mode mask registers with high 16 bits as the mask bits */ 217 #define F_MODE_MASK (1 << 2) 218 /* This reg can be accessed by GPU commands */ 219 #define F_CMD_ACCESS (1 << 3) 220 /* This reg has been accessed by a VM */ 221 #define F_ACCESSED (1 << 4) 222 /* This reg has been accessed through GPU commands */ 223 #define F_CMD_ACCESSED (1 << 5) 224 /* This reg could be accessed by unaligned address */ 225 #define F_UNALIGN (1 << 6) 226 227 struct gvt_mmio_block *mmio_block; 228 unsigned int num_mmio_block; 229 230 DECLARE_HASHTABLE(mmio_info_table, INTEL_GVT_MMIO_HASH_BITS); 231 unsigned int num_tracked_mmio; 232 }; 233 234 struct intel_gvt_firmware { 235 void *cfg_space; 236 void *mmio; 237 bool firmware_loaded; 238 }; 239 240 struct intel_gvt_opregion { 241 void *opregion_va; 242 u32 opregion_pa; 243 }; 244 245 #define NR_MAX_INTEL_VGPU_TYPES 20 246 struct intel_vgpu_type { 247 char name[16]; 248 unsigned int avail_instance; 249 unsigned int low_gm_size; 250 unsigned int high_gm_size; 251 unsigned int fence; 252 unsigned int weight; 253 enum intel_vgpu_edid resolution; 254 }; 255 256 struct intel_gvt { 257 struct mutex lock; 258 struct drm_i915_private *dev_priv; 259 struct idr vgpu_idr; /* vGPU IDR pool */ 260 261 struct intel_gvt_device_info device_info; 262 struct intel_gvt_gm gm; 263 struct intel_gvt_fence fence; 264 struct intel_gvt_mmio mmio; 265 struct intel_gvt_firmware firmware; 266 struct intel_gvt_irq irq; 267 struct intel_gvt_gtt gtt; 268 struct intel_gvt_opregion opregion; 269 struct intel_gvt_workload_scheduler scheduler; 270 struct notifier_block shadow_ctx_notifier_block[I915_NUM_ENGINES]; 271 DECLARE_HASHTABLE(cmd_table, GVT_CMD_HASH_BITS); 272 struct intel_vgpu_type *types; 273 unsigned int num_types; 274 struct intel_vgpu *idle_vgpu; 275 276 struct task_struct *service_thread; 277 wait_queue_head_t service_thread_wq; 278 unsigned long service_request; 279 }; 280 281 static inline struct intel_gvt *to_gvt(struct drm_i915_private *i915) 282 { 283 return i915->gvt; 284 } 285 286 enum { 287 INTEL_GVT_REQUEST_EMULATE_VBLANK = 0, 288 289 /* Scheduling trigger by timer */ 290 INTEL_GVT_REQUEST_SCHED = 1, 291 292 /* Scheduling trigger by event */ 293 INTEL_GVT_REQUEST_EVENT_SCHED = 2, 294 }; 295 296 static inline void intel_gvt_request_service(struct intel_gvt *gvt, 297 int service) 298 { 299 set_bit(service, (void *)&gvt->service_request); 300 wake_up(&gvt->service_thread_wq); 301 } 302 303 void intel_gvt_free_firmware(struct intel_gvt *gvt); 304 int intel_gvt_load_firmware(struct intel_gvt *gvt); 305 306 /* Aperture/GM space definitions for GVT device */ 307 #define MB_TO_BYTES(mb) ((mb) << 20ULL) 308 #define BYTES_TO_MB(b) ((b) >> 20ULL) 309 310 #define HOST_LOW_GM_SIZE MB_TO_BYTES(128) 311 #define HOST_HIGH_GM_SIZE MB_TO_BYTES(384) 312 #define HOST_FENCE 4 313 314 /* Aperture/GM space definitions for GVT device */ 315 #define gvt_aperture_sz(gvt) (gvt->dev_priv->ggtt.mappable_end) 316 #define gvt_aperture_pa_base(gvt) (gvt->dev_priv->ggtt.mappable_base) 317 318 #define gvt_ggtt_gm_sz(gvt) (gvt->dev_priv->ggtt.base.total) 319 #define gvt_ggtt_sz(gvt) \ 320 ((gvt->dev_priv->ggtt.base.total >> PAGE_SHIFT) << 3) 321 #define gvt_hidden_sz(gvt) (gvt_ggtt_gm_sz(gvt) - gvt_aperture_sz(gvt)) 322 323 #define gvt_aperture_gmadr_base(gvt) (0) 324 #define gvt_aperture_gmadr_end(gvt) (gvt_aperture_gmadr_base(gvt) \ 325 + gvt_aperture_sz(gvt) - 1) 326 327 #define gvt_hidden_gmadr_base(gvt) (gvt_aperture_gmadr_base(gvt) \ 328 + gvt_aperture_sz(gvt)) 329 #define gvt_hidden_gmadr_end(gvt) (gvt_hidden_gmadr_base(gvt) \ 330 + gvt_hidden_sz(gvt) - 1) 331 332 #define gvt_fence_sz(gvt) (gvt->dev_priv->num_fence_regs) 333 334 /* Aperture/GM space definitions for vGPU */ 335 #define vgpu_aperture_offset(vgpu) ((vgpu)->gm.low_gm_node.start) 336 #define vgpu_hidden_offset(vgpu) ((vgpu)->gm.high_gm_node.start) 337 #define vgpu_aperture_sz(vgpu) ((vgpu)->gm.aperture_sz) 338 #define vgpu_hidden_sz(vgpu) ((vgpu)->gm.hidden_sz) 339 340 #define vgpu_aperture_pa_base(vgpu) \ 341 (gvt_aperture_pa_base(vgpu->gvt) + vgpu_aperture_offset(vgpu)) 342 343 #define vgpu_ggtt_gm_sz(vgpu) ((vgpu)->gm.aperture_sz + (vgpu)->gm.hidden_sz) 344 345 #define vgpu_aperture_pa_end(vgpu) \ 346 (vgpu_aperture_pa_base(vgpu) + vgpu_aperture_sz(vgpu) - 1) 347 348 #define vgpu_aperture_gmadr_base(vgpu) (vgpu_aperture_offset(vgpu)) 349 #define vgpu_aperture_gmadr_end(vgpu) \ 350 (vgpu_aperture_gmadr_base(vgpu) + vgpu_aperture_sz(vgpu) - 1) 351 352 #define vgpu_hidden_gmadr_base(vgpu) (vgpu_hidden_offset(vgpu)) 353 #define vgpu_hidden_gmadr_end(vgpu) \ 354 (vgpu_hidden_gmadr_base(vgpu) + vgpu_hidden_sz(vgpu) - 1) 355 356 #define vgpu_fence_base(vgpu) (vgpu->fence.base) 357 #define vgpu_fence_sz(vgpu) (vgpu->fence.size) 358 359 struct intel_vgpu_creation_params { 360 __u64 handle; 361 __u64 low_gm_sz; /* in MB */ 362 __u64 high_gm_sz; /* in MB */ 363 __u64 fence_sz; 364 __u64 resolution; 365 __s32 primary; 366 __u64 vgpu_id; 367 368 __u32 weight; 369 }; 370 371 int intel_vgpu_alloc_resource(struct intel_vgpu *vgpu, 372 struct intel_vgpu_creation_params *param); 373 void intel_vgpu_reset_resource(struct intel_vgpu *vgpu); 374 void intel_vgpu_free_resource(struct intel_vgpu *vgpu); 375 void intel_vgpu_write_fence(struct intel_vgpu *vgpu, 376 u32 fence, u64 value); 377 378 /* Macros for easily accessing vGPU virtual/shadow register */ 379 #define vgpu_vreg(vgpu, reg) \ 380 (*(u32 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg))) 381 #define vgpu_vreg8(vgpu, reg) \ 382 (*(u8 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg))) 383 #define vgpu_vreg16(vgpu, reg) \ 384 (*(u16 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg))) 385 #define vgpu_vreg64(vgpu, reg) \ 386 (*(u64 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg))) 387 #define vgpu_sreg(vgpu, reg) \ 388 (*(u32 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg))) 389 #define vgpu_sreg8(vgpu, reg) \ 390 (*(u8 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg))) 391 #define vgpu_sreg16(vgpu, reg) \ 392 (*(u16 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg))) 393 #define vgpu_sreg64(vgpu, reg) \ 394 (*(u64 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg))) 395 396 #define for_each_active_vgpu(gvt, vgpu, id) \ 397 idr_for_each_entry((&(gvt)->vgpu_idr), (vgpu), (id)) \ 398 for_each_if(vgpu->active) 399 400 static inline void intel_vgpu_write_pci_bar(struct intel_vgpu *vgpu, 401 u32 offset, u32 val, bool low) 402 { 403 u32 *pval; 404 405 /* BAR offset should be 32 bits algiend */ 406 offset = rounddown(offset, 4); 407 pval = (u32 *)(vgpu_cfg_space(vgpu) + offset); 408 409 if (low) { 410 /* 411 * only update bit 31 - bit 4, 412 * leave the bit 3 - bit 0 unchanged. 413 */ 414 *pval = (val & GENMASK(31, 4)) | (*pval & GENMASK(3, 0)); 415 } else { 416 *pval = val; 417 } 418 } 419 420 int intel_gvt_init_vgpu_types(struct intel_gvt *gvt); 421 void intel_gvt_clean_vgpu_types(struct intel_gvt *gvt); 422 423 struct intel_vgpu *intel_gvt_create_idle_vgpu(struct intel_gvt *gvt); 424 void intel_gvt_destroy_idle_vgpu(struct intel_vgpu *vgpu); 425 struct intel_vgpu *intel_gvt_create_vgpu(struct intel_gvt *gvt, 426 struct intel_vgpu_type *type); 427 void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu); 428 void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr, 429 unsigned int engine_mask); 430 void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu); 431 void intel_gvt_activate_vgpu(struct intel_vgpu *vgpu); 432 void intel_gvt_deactivate_vgpu(struct intel_vgpu *vgpu); 433 434 /* validating GM functions */ 435 #define vgpu_gmadr_is_aperture(vgpu, gmadr) \ 436 ((gmadr >= vgpu_aperture_gmadr_base(vgpu)) && \ 437 (gmadr <= vgpu_aperture_gmadr_end(vgpu))) 438 439 #define vgpu_gmadr_is_hidden(vgpu, gmadr) \ 440 ((gmadr >= vgpu_hidden_gmadr_base(vgpu)) && \ 441 (gmadr <= vgpu_hidden_gmadr_end(vgpu))) 442 443 #define vgpu_gmadr_is_valid(vgpu, gmadr) \ 444 ((vgpu_gmadr_is_aperture(vgpu, gmadr) || \ 445 (vgpu_gmadr_is_hidden(vgpu, gmadr)))) 446 447 #define gvt_gmadr_is_aperture(gvt, gmadr) \ 448 ((gmadr >= gvt_aperture_gmadr_base(gvt)) && \ 449 (gmadr <= gvt_aperture_gmadr_end(gvt))) 450 451 #define gvt_gmadr_is_hidden(gvt, gmadr) \ 452 ((gmadr >= gvt_hidden_gmadr_base(gvt)) && \ 453 (gmadr <= gvt_hidden_gmadr_end(gvt))) 454 455 #define gvt_gmadr_is_valid(gvt, gmadr) \ 456 (gvt_gmadr_is_aperture(gvt, gmadr) || \ 457 gvt_gmadr_is_hidden(gvt, gmadr)) 458 459 bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size); 460 int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr); 461 int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u64 h_addr, u64 *g_addr); 462 int intel_gvt_ggtt_index_g2h(struct intel_vgpu *vgpu, unsigned long g_index, 463 unsigned long *h_index); 464 int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_index, 465 unsigned long *g_index); 466 467 void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu, 468 bool primary); 469 void intel_vgpu_reset_cfg_space(struct intel_vgpu *vgpu); 470 471 int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset, 472 void *p_data, unsigned int bytes); 473 474 int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset, 475 void *p_data, unsigned int bytes); 476 477 void intel_gvt_clean_opregion(struct intel_gvt *gvt); 478 int intel_gvt_init_opregion(struct intel_gvt *gvt); 479 480 void intel_vgpu_clean_opregion(struct intel_vgpu *vgpu); 481 int intel_vgpu_init_opregion(struct intel_vgpu *vgpu, u32 gpa); 482 483 int intel_vgpu_emulate_opregion_request(struct intel_vgpu *vgpu, u32 swsci); 484 void populate_pvinfo_page(struct intel_vgpu *vgpu); 485 486 int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload); 487 488 struct intel_gvt_ops { 489 int (*emulate_cfg_read)(struct intel_vgpu *, unsigned int, void *, 490 unsigned int); 491 int (*emulate_cfg_write)(struct intel_vgpu *, unsigned int, void *, 492 unsigned int); 493 int (*emulate_mmio_read)(struct intel_vgpu *, u64, void *, 494 unsigned int); 495 int (*emulate_mmio_write)(struct intel_vgpu *, u64, void *, 496 unsigned int); 497 struct intel_vgpu *(*vgpu_create)(struct intel_gvt *, 498 struct intel_vgpu_type *); 499 void (*vgpu_destroy)(struct intel_vgpu *); 500 void (*vgpu_reset)(struct intel_vgpu *); 501 void (*vgpu_activate)(struct intel_vgpu *); 502 void (*vgpu_deactivate)(struct intel_vgpu *); 503 }; 504 505 506 enum { 507 GVT_FAILSAFE_UNSUPPORTED_GUEST, 508 GVT_FAILSAFE_INSUFFICIENT_RESOURCE, 509 }; 510 511 static inline void mmio_hw_access_pre(struct drm_i915_private *dev_priv) 512 { 513 intel_runtime_pm_get(dev_priv); 514 } 515 516 static inline void mmio_hw_access_post(struct drm_i915_private *dev_priv) 517 { 518 intel_runtime_pm_put(dev_priv); 519 } 520 521 /** 522 * intel_gvt_mmio_set_accessed - mark a MMIO has been accessed 523 * @gvt: a GVT device 524 * @offset: register offset 525 * 526 */ 527 static inline void intel_gvt_mmio_set_accessed( 528 struct intel_gvt *gvt, unsigned int offset) 529 { 530 gvt->mmio.mmio_attribute[offset >> 2] |= F_ACCESSED; 531 } 532 533 /** 534 * intel_gvt_mmio_is_cmd_accessed - mark a MMIO could be accessed by command 535 * @gvt: a GVT device 536 * @offset: register offset 537 * 538 */ 539 static inline bool intel_gvt_mmio_is_cmd_access( 540 struct intel_gvt *gvt, unsigned int offset) 541 { 542 return gvt->mmio.mmio_attribute[offset >> 2] & F_CMD_ACCESS; 543 } 544 545 /** 546 * intel_gvt_mmio_is_unalign - mark a MMIO could be accessed unaligned 547 * @gvt: a GVT device 548 * @offset: register offset 549 * 550 */ 551 static inline bool intel_gvt_mmio_is_unalign( 552 struct intel_gvt *gvt, unsigned int offset) 553 { 554 return gvt->mmio.mmio_attribute[offset >> 2] & F_UNALIGN; 555 } 556 557 /** 558 * intel_gvt_mmio_set_cmd_accessed - mark a MMIO has been accessed by command 559 * @gvt: a GVT device 560 * @offset: register offset 561 * 562 */ 563 static inline void intel_gvt_mmio_set_cmd_accessed( 564 struct intel_gvt *gvt, unsigned int offset) 565 { 566 gvt->mmio.mmio_attribute[offset >> 2] |= F_CMD_ACCESSED; 567 } 568 569 /** 570 * intel_gvt_mmio_has_mode_mask - if a MMIO has a mode mask 571 * @gvt: a GVT device 572 * @offset: register offset 573 * 574 * Returns: 575 * True if a MMIO has a mode mask in its higher 16 bits, false if it isn't. 576 * 577 */ 578 static inline bool intel_gvt_mmio_has_mode_mask( 579 struct intel_gvt *gvt, unsigned int offset) 580 { 581 return gvt->mmio.mmio_attribute[offset >> 2] & F_MODE_MASK; 582 } 583 584 #include "trace.h" 585 #include "mpt.h" 586 587 #endif 588