1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Kevin Tian <kevin.tian@intel.com> 25 * Eddie Dong <eddie.dong@intel.com> 26 * 27 * Contributors: 28 * Niu Bing <bing.niu@intel.com> 29 * Zhi Wang <zhi.a.wang@intel.com> 30 * 31 */ 32 33 #ifndef _GVT_H_ 34 #define _GVT_H_ 35 36 #include <uapi/linux/pci_regs.h> 37 #include <linux/kvm_host.h> 38 #include <linux/vfio.h> 39 #include <linux/mdev.h> 40 41 #include "i915_drv.h" 42 #include "intel_gvt.h" 43 44 #include "debug.h" 45 #include "mmio.h" 46 #include "reg.h" 47 #include "interrupt.h" 48 #include "gtt.h" 49 #include "display.h" 50 #include "edid.h" 51 #include "execlist.h" 52 #include "scheduler.h" 53 #include "sched_policy.h" 54 #include "mmio_context.h" 55 #include "cmd_parser.h" 56 #include "fb_decoder.h" 57 #include "dmabuf.h" 58 #include "page_track.h" 59 60 #define GVT_MAX_VGPU 8 61 62 /* Describe per-platform limitations. */ 63 struct intel_gvt_device_info { 64 u32 max_support_vgpus; 65 u32 cfg_space_size; 66 u32 mmio_size; 67 u32 mmio_bar; 68 unsigned long msi_cap_offset; 69 u32 gtt_start_offset; 70 u32 gtt_entry_size; 71 u32 gtt_entry_size_shift; 72 int gmadr_bytes_in_cmd; 73 u32 max_surface_size; 74 }; 75 76 /* GM resources owned by a vGPU */ 77 struct intel_vgpu_gm { 78 u64 aperture_sz; 79 u64 hidden_sz; 80 struct drm_mm_node low_gm_node; 81 struct drm_mm_node high_gm_node; 82 }; 83 84 #define INTEL_GVT_MAX_NUM_FENCES 32 85 86 /* Fences owned by a vGPU */ 87 struct intel_vgpu_fence { 88 struct i915_fence_reg *regs[INTEL_GVT_MAX_NUM_FENCES]; 89 u32 base; 90 u32 size; 91 }; 92 93 struct intel_vgpu_mmio { 94 void *vreg; 95 }; 96 97 #define INTEL_GVT_MAX_BAR_NUM 4 98 99 struct intel_vgpu_pci_bar { 100 u64 size; 101 bool tracked; 102 }; 103 104 struct intel_vgpu_cfg_space { 105 unsigned char virtual_cfg_space[PCI_CFG_SPACE_EXP_SIZE]; 106 struct intel_vgpu_pci_bar bar[INTEL_GVT_MAX_BAR_NUM]; 107 u32 pmcsr_off; 108 }; 109 110 #define vgpu_cfg_space(vgpu) ((vgpu)->cfg_space.virtual_cfg_space) 111 112 struct intel_vgpu_irq { 113 bool irq_warn_once[INTEL_GVT_EVENT_MAX]; 114 DECLARE_BITMAP(flip_done_event[I915_MAX_PIPES], 115 INTEL_GVT_EVENT_MAX); 116 }; 117 118 struct intel_vgpu_opregion { 119 bool mapped; 120 void *va; 121 u32 gfn[INTEL_GVT_OPREGION_PAGES]; 122 }; 123 124 #define vgpu_opregion(vgpu) (&(vgpu->opregion)) 125 126 struct intel_vgpu_display { 127 struct intel_vgpu_i2c_edid i2c_edid; 128 struct intel_vgpu_port ports[I915_MAX_PORTS]; 129 struct intel_vgpu_sbi sbi; 130 enum port port_num; 131 }; 132 133 struct vgpu_sched_ctl { 134 int weight; 135 }; 136 137 enum { 138 INTEL_VGPU_EXECLIST_SUBMISSION = 1, 139 INTEL_VGPU_GUC_SUBMISSION, 140 }; 141 142 struct intel_vgpu_submission_ops { 143 const char *name; 144 int (*init)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask); 145 void (*clean)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask); 146 void (*reset)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask); 147 }; 148 149 struct intel_vgpu_submission { 150 struct intel_vgpu_execlist execlist[I915_NUM_ENGINES]; 151 struct list_head workload_q_head[I915_NUM_ENGINES]; 152 struct intel_context *shadow[I915_NUM_ENGINES]; 153 struct kmem_cache *workloads; 154 atomic_t running_workload_num; 155 union { 156 u64 i915_context_pml4; 157 u64 i915_context_pdps[GEN8_3LVL_PDPES]; 158 }; 159 DECLARE_BITMAP(shadow_ctx_desc_updated, I915_NUM_ENGINES); 160 DECLARE_BITMAP(tlb_handle_pending, I915_NUM_ENGINES); 161 void *ring_scan_buffer[I915_NUM_ENGINES]; 162 int ring_scan_buffer_size[I915_NUM_ENGINES]; 163 const struct intel_vgpu_submission_ops *ops; 164 int virtual_submission_interface; 165 bool active; 166 struct { 167 u32 lrca; 168 bool valid; 169 u64 ring_context_gpa; 170 } last_ctx[I915_NUM_ENGINES]; 171 }; 172 173 #define KVMGT_DEBUGFS_FILENAME "kvmgt_nr_cache_entries" 174 175 struct intel_vgpu { 176 struct vfio_device vfio_device; 177 struct intel_gvt *gvt; 178 struct mutex vgpu_lock; 179 int id; 180 bool active; 181 bool attached; 182 bool pv_notified; 183 bool failsafe; 184 unsigned int resetting_eng; 185 186 /* Both sched_data and sched_ctl can be seen a part of the global gvt 187 * scheduler structure. So below 2 vgpu data are protected 188 * by sched_lock, not vgpu_lock. 189 */ 190 void *sched_data; 191 struct vgpu_sched_ctl sched_ctl; 192 193 struct intel_vgpu_fence fence; 194 struct intel_vgpu_gm gm; 195 struct intel_vgpu_cfg_space cfg_space; 196 struct intel_vgpu_mmio mmio; 197 struct intel_vgpu_irq irq; 198 struct intel_vgpu_gtt gtt; 199 struct intel_vgpu_opregion opregion; 200 struct intel_vgpu_display display; 201 struct intel_vgpu_submission submission; 202 struct radix_tree_root page_track_tree; 203 u32 hws_pga[I915_NUM_ENGINES]; 204 /* Set on PCI_D3, reset on DMLR, not reflecting the actual PM state */ 205 bool d3_entered; 206 207 struct dentry *debugfs; 208 209 struct list_head dmabuf_obj_list_head; 210 struct mutex dmabuf_lock; 211 struct idr object_idr; 212 struct intel_vgpu_vblank_timer vblank_timer; 213 214 u32 scan_nonprivbb; 215 216 struct vfio_region *region; 217 int num_regions; 218 struct eventfd_ctx *intx_trigger; 219 struct eventfd_ctx *msi_trigger; 220 221 /* 222 * Two caches are used to avoid mapping duplicated pages (eg. 223 * scratch pages). This help to reduce dma setup overhead. 224 */ 225 struct rb_root gfn_cache; 226 struct rb_root dma_addr_cache; 227 unsigned long nr_cache_entries; 228 struct mutex cache_lock; 229 230 struct kvm_page_track_notifier_node track_node; 231 #define NR_BKT (1 << 18) 232 struct hlist_head ptable[NR_BKT]; 233 #undef NR_BKT 234 }; 235 236 /* validating GM healthy status*/ 237 #define vgpu_is_vm_unhealthy(ret_val) \ 238 (((ret_val) == -EBADRQC) || ((ret_val) == -EFAULT)) 239 240 struct intel_gvt_gm { 241 unsigned long vgpu_allocated_low_gm_size; 242 unsigned long vgpu_allocated_high_gm_size; 243 }; 244 245 struct intel_gvt_fence { 246 unsigned long vgpu_allocated_fence_num; 247 }; 248 249 /* Special MMIO blocks. */ 250 struct gvt_mmio_block { 251 unsigned int device; 252 i915_reg_t offset; 253 unsigned int size; 254 gvt_mmio_func read; 255 gvt_mmio_func write; 256 }; 257 258 #define INTEL_GVT_MMIO_HASH_BITS 11 259 260 struct intel_gvt_mmio { 261 u16 *mmio_attribute; 262 /* Register contains RO bits */ 263 #define F_RO (1 << 0) 264 /* Register contains graphics address */ 265 #define F_GMADR (1 << 1) 266 /* Mode mask registers with high 16 bits as the mask bits */ 267 #define F_MODE_MASK (1 << 2) 268 /* This reg can be accessed by GPU commands */ 269 #define F_CMD_ACCESS (1 << 3) 270 /* This reg has been accessed by a VM */ 271 #define F_ACCESSED (1 << 4) 272 /* This reg requires save & restore during host PM suspend/resume */ 273 #define F_PM_SAVE (1 << 5) 274 /* This reg could be accessed by unaligned address */ 275 #define F_UNALIGN (1 << 6) 276 /* This reg is in GVT's mmio save-restor list and in hardware 277 * logical context image 278 */ 279 #define F_SR_IN_CTX (1 << 7) 280 /* Value of command write of this reg needs to be patched */ 281 #define F_CMD_WRITE_PATCH (1 << 8) 282 283 struct gvt_mmio_block *mmio_block; 284 unsigned int num_mmio_block; 285 286 DECLARE_HASHTABLE(mmio_info_table, INTEL_GVT_MMIO_HASH_BITS); 287 unsigned long num_tracked_mmio; 288 }; 289 290 struct intel_gvt_firmware { 291 void *cfg_space; 292 void *mmio; 293 bool firmware_loaded; 294 }; 295 296 struct intel_vgpu_config { 297 unsigned int low_mm; 298 unsigned int high_mm; 299 unsigned int fence; 300 301 /* 302 * A vGPU with a weight of 8 will get twice as much GPU as a vGPU with 303 * a weight of 4 on a contended host, different vGPU type has different 304 * weight set. Legal weights range from 1 to 16. 305 */ 306 unsigned int weight; 307 enum intel_vgpu_edid edid; 308 const char *name; 309 }; 310 311 struct intel_vgpu_type { 312 struct mdev_type type; 313 char name[16]; 314 const struct intel_vgpu_config *conf; 315 }; 316 317 struct intel_gvt { 318 /* GVT scope lock, protect GVT itself, and all resource currently 319 * not yet protected by special locks(vgpu and scheduler lock). 320 */ 321 struct mutex lock; 322 /* scheduler scope lock, protect gvt and vgpu schedule related data */ 323 struct mutex sched_lock; 324 325 struct intel_gt *gt; 326 struct idr vgpu_idr; /* vGPU IDR pool */ 327 328 struct intel_gvt_device_info device_info; 329 struct intel_gvt_gm gm; 330 struct intel_gvt_fence fence; 331 struct intel_gvt_mmio mmio; 332 struct intel_gvt_firmware firmware; 333 struct intel_gvt_irq irq; 334 struct intel_gvt_gtt gtt; 335 struct intel_gvt_workload_scheduler scheduler; 336 struct notifier_block shadow_ctx_notifier_block[I915_NUM_ENGINES]; 337 DECLARE_HASHTABLE(cmd_table, GVT_CMD_HASH_BITS); 338 struct mdev_parent parent; 339 struct mdev_type **mdev_types; 340 struct intel_vgpu_type *types; 341 unsigned int num_types; 342 struct intel_vgpu *idle_vgpu; 343 344 struct task_struct *service_thread; 345 wait_queue_head_t service_thread_wq; 346 347 /* service_request is always used in bit operation, we should always 348 * use it with atomic bit ops so that no need to use gvt big lock. 349 */ 350 unsigned long service_request; 351 352 struct { 353 struct engine_mmio *mmio; 354 int ctx_mmio_count[I915_NUM_ENGINES]; 355 u32 *tlb_mmio_offset_list; 356 u32 tlb_mmio_offset_list_cnt; 357 u32 *mocs_mmio_offset_list; 358 u32 mocs_mmio_offset_list_cnt; 359 } engine_mmio_list; 360 bool is_reg_whitelist_updated; 361 362 struct dentry *debugfs_root; 363 }; 364 365 static inline struct intel_gvt *to_gvt(struct drm_i915_private *i915) 366 { 367 return i915->gvt; 368 } 369 370 enum { 371 /* Scheduling trigger by timer */ 372 INTEL_GVT_REQUEST_SCHED = 0, 373 374 /* Scheduling trigger by event */ 375 INTEL_GVT_REQUEST_EVENT_SCHED = 1, 376 377 /* per-vGPU vblank emulation request */ 378 INTEL_GVT_REQUEST_EMULATE_VBLANK = 2, 379 INTEL_GVT_REQUEST_EMULATE_VBLANK_MAX = INTEL_GVT_REQUEST_EMULATE_VBLANK 380 + GVT_MAX_VGPU, 381 }; 382 383 static inline void intel_gvt_request_service(struct intel_gvt *gvt, 384 int service) 385 { 386 set_bit(service, (void *)&gvt->service_request); 387 wake_up(&gvt->service_thread_wq); 388 } 389 390 void intel_gvt_free_firmware(struct intel_gvt *gvt); 391 int intel_gvt_load_firmware(struct intel_gvt *gvt); 392 393 /* Aperture/GM space definitions for GVT device */ 394 #define MB_TO_BYTES(mb) ((mb) << 20ULL) 395 #define BYTES_TO_MB(b) ((b) >> 20ULL) 396 397 #define HOST_LOW_GM_SIZE MB_TO_BYTES(128) 398 #define HOST_HIGH_GM_SIZE MB_TO_BYTES(384) 399 #define HOST_FENCE 4 400 401 #define gvt_to_ggtt(gvt) ((gvt)->gt->ggtt) 402 403 /* Aperture/GM space definitions for GVT device */ 404 #define gvt_aperture_sz(gvt) gvt_to_ggtt(gvt)->mappable_end 405 #define gvt_aperture_pa_base(gvt) gvt_to_ggtt(gvt)->gmadr.start 406 407 #define gvt_ggtt_gm_sz(gvt) gvt_to_ggtt(gvt)->vm.total 408 #define gvt_ggtt_sz(gvt) (gvt_to_ggtt(gvt)->vm.total >> PAGE_SHIFT << 3) 409 #define gvt_hidden_sz(gvt) (gvt_ggtt_gm_sz(gvt) - gvt_aperture_sz(gvt)) 410 411 #define gvt_aperture_gmadr_base(gvt) (0) 412 #define gvt_aperture_gmadr_end(gvt) (gvt_aperture_gmadr_base(gvt) \ 413 + gvt_aperture_sz(gvt) - 1) 414 415 #define gvt_hidden_gmadr_base(gvt) (gvt_aperture_gmadr_base(gvt) \ 416 + gvt_aperture_sz(gvt)) 417 #define gvt_hidden_gmadr_end(gvt) (gvt_hidden_gmadr_base(gvt) \ 418 + gvt_hidden_sz(gvt) - 1) 419 420 #define gvt_fence_sz(gvt) (gvt_to_ggtt(gvt)->num_fences) 421 422 /* Aperture/GM space definitions for vGPU */ 423 #define vgpu_aperture_offset(vgpu) ((vgpu)->gm.low_gm_node.start) 424 #define vgpu_hidden_offset(vgpu) ((vgpu)->gm.high_gm_node.start) 425 #define vgpu_aperture_sz(vgpu) ((vgpu)->gm.aperture_sz) 426 #define vgpu_hidden_sz(vgpu) ((vgpu)->gm.hidden_sz) 427 428 #define vgpu_aperture_pa_base(vgpu) \ 429 (gvt_aperture_pa_base(vgpu->gvt) + vgpu_aperture_offset(vgpu)) 430 431 #define vgpu_ggtt_gm_sz(vgpu) ((vgpu)->gm.aperture_sz + (vgpu)->gm.hidden_sz) 432 433 #define vgpu_aperture_pa_end(vgpu) \ 434 (vgpu_aperture_pa_base(vgpu) + vgpu_aperture_sz(vgpu) - 1) 435 436 #define vgpu_aperture_gmadr_base(vgpu) (vgpu_aperture_offset(vgpu)) 437 #define vgpu_aperture_gmadr_end(vgpu) \ 438 (vgpu_aperture_gmadr_base(vgpu) + vgpu_aperture_sz(vgpu) - 1) 439 440 #define vgpu_hidden_gmadr_base(vgpu) (vgpu_hidden_offset(vgpu)) 441 #define vgpu_hidden_gmadr_end(vgpu) \ 442 (vgpu_hidden_gmadr_base(vgpu) + vgpu_hidden_sz(vgpu) - 1) 443 444 #define vgpu_fence_base(vgpu) (vgpu->fence.base) 445 #define vgpu_fence_sz(vgpu) (vgpu->fence.size) 446 447 /* ring context size i.e. the first 0x50 dwords*/ 448 #define RING_CTX_SIZE 320 449 450 int intel_vgpu_alloc_resource(struct intel_vgpu *vgpu, 451 const struct intel_vgpu_config *conf); 452 void intel_vgpu_reset_resource(struct intel_vgpu *vgpu); 453 void intel_vgpu_free_resource(struct intel_vgpu *vgpu); 454 void intel_vgpu_write_fence(struct intel_vgpu *vgpu, 455 u32 fence, u64 value); 456 457 /* Macros for easily accessing vGPU virtual/shadow register. 458 Explicitly seperate use for typed MMIO reg or real offset.*/ 459 #define vgpu_vreg_t(vgpu, reg) \ 460 (*(u32 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg))) 461 #define vgpu_vreg(vgpu, offset) \ 462 (*(u32 *)(vgpu->mmio.vreg + (offset))) 463 #define vgpu_vreg64_t(vgpu, reg) \ 464 (*(u64 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg))) 465 #define vgpu_vreg64(vgpu, offset) \ 466 (*(u64 *)(vgpu->mmio.vreg + (offset))) 467 468 #define for_each_active_vgpu(gvt, vgpu, id) \ 469 idr_for_each_entry((&(gvt)->vgpu_idr), (vgpu), (id)) \ 470 for_each_if(vgpu->active) 471 472 static inline void intel_vgpu_write_pci_bar(struct intel_vgpu *vgpu, 473 u32 offset, u32 val, bool low) 474 { 475 u32 *pval; 476 477 /* BAR offset should be 32 bits algiend */ 478 offset = rounddown(offset, 4); 479 pval = (u32 *)(vgpu_cfg_space(vgpu) + offset); 480 481 if (low) { 482 /* 483 * only update bit 31 - bit 4, 484 * leave the bit 3 - bit 0 unchanged. 485 */ 486 *pval = (val & GENMASK(31, 4)) | (*pval & GENMASK(3, 0)); 487 } else { 488 *pval = val; 489 } 490 } 491 492 int intel_gvt_init_vgpu_types(struct intel_gvt *gvt); 493 void intel_gvt_clean_vgpu_types(struct intel_gvt *gvt); 494 495 struct intel_vgpu *intel_gvt_create_idle_vgpu(struct intel_gvt *gvt); 496 void intel_gvt_destroy_idle_vgpu(struct intel_vgpu *vgpu); 497 int intel_gvt_create_vgpu(struct intel_vgpu *vgpu, 498 const struct intel_vgpu_config *conf); 499 void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu); 500 void intel_gvt_release_vgpu(struct intel_vgpu *vgpu); 501 void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr, 502 intel_engine_mask_t engine_mask); 503 void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu); 504 void intel_gvt_activate_vgpu(struct intel_vgpu *vgpu); 505 void intel_gvt_deactivate_vgpu(struct intel_vgpu *vgpu); 506 507 int intel_gvt_set_opregion(struct intel_vgpu *vgpu); 508 int intel_gvt_set_edid(struct intel_vgpu *vgpu, int port_num); 509 510 /* validating GM functions */ 511 #define vgpu_gmadr_is_aperture(vgpu, gmadr) \ 512 ((gmadr >= vgpu_aperture_gmadr_base(vgpu)) && \ 513 (gmadr <= vgpu_aperture_gmadr_end(vgpu))) 514 515 #define vgpu_gmadr_is_hidden(vgpu, gmadr) \ 516 ((gmadr >= vgpu_hidden_gmadr_base(vgpu)) && \ 517 (gmadr <= vgpu_hidden_gmadr_end(vgpu))) 518 519 #define vgpu_gmadr_is_valid(vgpu, gmadr) \ 520 ((vgpu_gmadr_is_aperture(vgpu, gmadr) || \ 521 (vgpu_gmadr_is_hidden(vgpu, gmadr)))) 522 523 #define gvt_gmadr_is_aperture(gvt, gmadr) \ 524 ((gmadr >= gvt_aperture_gmadr_base(gvt)) && \ 525 (gmadr <= gvt_aperture_gmadr_end(gvt))) 526 527 #define gvt_gmadr_is_hidden(gvt, gmadr) \ 528 ((gmadr >= gvt_hidden_gmadr_base(gvt)) && \ 529 (gmadr <= gvt_hidden_gmadr_end(gvt))) 530 531 #define gvt_gmadr_is_valid(gvt, gmadr) \ 532 (gvt_gmadr_is_aperture(gvt, gmadr) || \ 533 gvt_gmadr_is_hidden(gvt, gmadr)) 534 535 bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size); 536 int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr); 537 int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u64 h_addr, u64 *g_addr); 538 int intel_gvt_ggtt_index_g2h(struct intel_vgpu *vgpu, unsigned long g_index, 539 unsigned long *h_index); 540 int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_index, 541 unsigned long *g_index); 542 543 void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu, 544 bool primary); 545 void intel_vgpu_reset_cfg_space(struct intel_vgpu *vgpu); 546 547 int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset, 548 void *p_data, unsigned int bytes); 549 550 int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset, 551 void *p_data, unsigned int bytes); 552 553 void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected); 554 555 static inline u64 intel_vgpu_get_bar_gpa(struct intel_vgpu *vgpu, int bar) 556 { 557 /* We are 64bit bar. */ 558 return (*(u64 *)(vgpu->cfg_space.virtual_cfg_space + bar)) & 559 PCI_BASE_ADDRESS_MEM_MASK; 560 } 561 562 void intel_vgpu_clean_opregion(struct intel_vgpu *vgpu); 563 int intel_vgpu_init_opregion(struct intel_vgpu *vgpu); 564 int intel_vgpu_opregion_base_write_handler(struct intel_vgpu *vgpu, u32 gpa); 565 566 int intel_vgpu_emulate_opregion_request(struct intel_vgpu *vgpu, u32 swsci); 567 void populate_pvinfo_page(struct intel_vgpu *vgpu); 568 569 int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload); 570 void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason); 571 void intel_vgpu_detach_regions(struct intel_vgpu *vgpu); 572 573 enum { 574 GVT_FAILSAFE_UNSUPPORTED_GUEST, 575 GVT_FAILSAFE_INSUFFICIENT_RESOURCE, 576 GVT_FAILSAFE_GUEST_ERR, 577 }; 578 579 static inline void mmio_hw_access_pre(struct intel_gt *gt) 580 { 581 intel_runtime_pm_get(gt->uncore->rpm); 582 } 583 584 static inline void mmio_hw_access_post(struct intel_gt *gt) 585 { 586 intel_runtime_pm_put_unchecked(gt->uncore->rpm); 587 } 588 589 /** 590 * intel_gvt_mmio_set_accessed - mark a MMIO has been accessed 591 * @gvt: a GVT device 592 * @offset: register offset 593 * 594 */ 595 static inline void intel_gvt_mmio_set_accessed( 596 struct intel_gvt *gvt, unsigned int offset) 597 { 598 gvt->mmio.mmio_attribute[offset >> 2] |= F_ACCESSED; 599 } 600 601 /** 602 * intel_gvt_mmio_is_cmd_accessible - if a MMIO could be accessed by command 603 * @gvt: a GVT device 604 * @offset: register offset 605 * 606 * Returns: 607 * True if an MMIO is able to be accessed by GPU commands 608 */ 609 static inline bool intel_gvt_mmio_is_cmd_accessible( 610 struct intel_gvt *gvt, unsigned int offset) 611 { 612 return gvt->mmio.mmio_attribute[offset >> 2] & F_CMD_ACCESS; 613 } 614 615 /** 616 * intel_gvt_mmio_set_cmd_accessible - 617 * mark a MMIO could be accessible by command 618 * @gvt: a GVT device 619 * @offset: register offset 620 * 621 */ 622 static inline void intel_gvt_mmio_set_cmd_accessible( 623 struct intel_gvt *gvt, unsigned int offset) 624 { 625 gvt->mmio.mmio_attribute[offset >> 2] |= F_CMD_ACCESS; 626 } 627 628 /** 629 * intel_gvt_mmio_is_unalign - mark a MMIO could be accessed unaligned 630 * @gvt: a GVT device 631 * @offset: register offset 632 * 633 */ 634 static inline bool intel_gvt_mmio_is_unalign( 635 struct intel_gvt *gvt, unsigned int offset) 636 { 637 return gvt->mmio.mmio_attribute[offset >> 2] & F_UNALIGN; 638 } 639 640 /** 641 * intel_gvt_mmio_has_mode_mask - if a MMIO has a mode mask 642 * @gvt: a GVT device 643 * @offset: register offset 644 * 645 * Returns: 646 * True if a MMIO has a mode mask in its higher 16 bits, false if it isn't. 647 * 648 */ 649 static inline bool intel_gvt_mmio_has_mode_mask( 650 struct intel_gvt *gvt, unsigned int offset) 651 { 652 return gvt->mmio.mmio_attribute[offset >> 2] & F_MODE_MASK; 653 } 654 655 /** 656 * intel_gvt_mmio_is_sr_in_ctx - 657 * check if an MMIO has F_SR_IN_CTX mask 658 * @gvt: a GVT device 659 * @offset: register offset 660 * 661 * Returns: 662 * True if an MMIO has an F_SR_IN_CTX mask, false if it isn't. 663 * 664 */ 665 static inline bool intel_gvt_mmio_is_sr_in_ctx( 666 struct intel_gvt *gvt, unsigned int offset) 667 { 668 return gvt->mmio.mmio_attribute[offset >> 2] & F_SR_IN_CTX; 669 } 670 671 /** 672 * intel_gvt_mmio_set_sr_in_ctx - 673 * mask an MMIO in GVT's mmio save-restore list and also 674 * in hardware logical context image 675 * @gvt: a GVT device 676 * @offset: register offset 677 * 678 */ 679 static inline void intel_gvt_mmio_set_sr_in_ctx( 680 struct intel_gvt *gvt, unsigned int offset) 681 { 682 gvt->mmio.mmio_attribute[offset >> 2] |= F_SR_IN_CTX; 683 } 684 685 void intel_gvt_debugfs_add_vgpu(struct intel_vgpu *vgpu); 686 /** 687 * intel_gvt_mmio_set_cmd_write_patch - 688 * mark an MMIO if its cmd write needs to be 689 * patched 690 * @gvt: a GVT device 691 * @offset: register offset 692 * 693 */ 694 static inline void intel_gvt_mmio_set_cmd_write_patch( 695 struct intel_gvt *gvt, unsigned int offset) 696 { 697 gvt->mmio.mmio_attribute[offset >> 2] |= F_CMD_WRITE_PATCH; 698 } 699 700 /** 701 * intel_gvt_mmio_is_cmd_write_patch - check if an mmio's cmd access needs to 702 * be patched 703 * @gvt: a GVT device 704 * @offset: register offset 705 * 706 * Returns: 707 * True if GPU commmand write to an MMIO should be patched 708 */ 709 static inline bool intel_gvt_mmio_is_cmd_write_patch( 710 struct intel_gvt *gvt, unsigned int offset) 711 { 712 return gvt->mmio.mmio_attribute[offset >> 2] & F_CMD_WRITE_PATCH; 713 } 714 715 /** 716 * intel_gvt_read_gpa - copy data from GPA to host data buffer 717 * @vgpu: a vGPU 718 * @gpa: guest physical address 719 * @buf: host data buffer 720 * @len: data length 721 * 722 * Returns: 723 * Zero on success, negative error code if failed. 724 */ 725 static inline int intel_gvt_read_gpa(struct intel_vgpu *vgpu, unsigned long gpa, 726 void *buf, unsigned long len) 727 { 728 if (!vgpu->attached) 729 return -ESRCH; 730 return vfio_dma_rw(&vgpu->vfio_device, gpa, buf, len, false); 731 } 732 733 /** 734 * intel_gvt_write_gpa - copy data from host data buffer to GPA 735 * @vgpu: a vGPU 736 * @gpa: guest physical address 737 * @buf: host data buffer 738 * @len: data length 739 * 740 * Returns: 741 * Zero on success, negative error code if failed. 742 */ 743 static inline int intel_gvt_write_gpa(struct intel_vgpu *vgpu, 744 unsigned long gpa, void *buf, unsigned long len) 745 { 746 if (!vgpu->attached) 747 return -ESRCH; 748 return vfio_dma_rw(&vgpu->vfio_device, gpa, buf, len, true); 749 } 750 751 void intel_gvt_debugfs_remove_vgpu(struct intel_vgpu *vgpu); 752 void intel_gvt_debugfs_init(struct intel_gvt *gvt); 753 void intel_gvt_debugfs_clean(struct intel_gvt *gvt); 754 755 int intel_gvt_page_track_add(struct intel_vgpu *info, u64 gfn); 756 int intel_gvt_page_track_remove(struct intel_vgpu *info, u64 gfn); 757 int intel_gvt_dma_pin_guest_page(struct intel_vgpu *vgpu, dma_addr_t dma_addr); 758 int intel_gvt_dma_map_guest_page(struct intel_vgpu *vgpu, unsigned long gfn, 759 unsigned long size, dma_addr_t *dma_addr); 760 void intel_gvt_dma_unmap_guest_page(struct intel_vgpu *vgpu, 761 dma_addr_t dma_addr); 762 763 #include "trace.h" 764 765 #endif 766