1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Zhi Wang <zhi.a.wang@intel.com> 25 * Zhenyu Wang <zhenyuw@linux.intel.com> 26 * Xiao Zheng <xiao.zheng@intel.com> 27 * 28 * Contributors: 29 * Min He <min.he@intel.com> 30 * Bing Niu <bing.niu@intel.com> 31 * 32 */ 33 34 #ifndef _GVT_GTT_H_ 35 #define _GVT_GTT_H_ 36 37 #define I915_GTT_PAGE_SHIFT 12 38 #define I915_GTT_PAGE_MASK (~(I915_GTT_PAGE_SIZE - 1)) 39 40 struct intel_vgpu_mm; 41 42 #define INTEL_GVT_INVALID_ADDR (~0UL) 43 44 struct intel_gvt_gtt_entry { 45 u64 val64; 46 int type; 47 }; 48 49 struct intel_gvt_gtt_pte_ops { 50 int (*get_entry)(void *pt, 51 struct intel_gvt_gtt_entry *e, 52 unsigned long index, 53 bool hypervisor_access, 54 unsigned long gpa, 55 struct intel_vgpu *vgpu); 56 int (*set_entry)(void *pt, 57 struct intel_gvt_gtt_entry *e, 58 unsigned long index, 59 bool hypervisor_access, 60 unsigned long gpa, 61 struct intel_vgpu *vgpu); 62 bool (*test_present)(struct intel_gvt_gtt_entry *e); 63 void (*clear_present)(struct intel_gvt_gtt_entry *e); 64 void (*set_present)(struct intel_gvt_gtt_entry *e); 65 bool (*test_pse)(struct intel_gvt_gtt_entry *e); 66 bool (*test_ips)(struct intel_gvt_gtt_entry *e); 67 void (*clear_ips)(struct intel_gvt_gtt_entry *e); 68 void (*set_pfn)(struct intel_gvt_gtt_entry *e, unsigned long pfn); 69 unsigned long (*get_pfn)(struct intel_gvt_gtt_entry *e); 70 }; 71 72 struct intel_gvt_gtt_gma_ops { 73 unsigned long (*gma_to_ggtt_pte_index)(unsigned long gma); 74 unsigned long (*gma_to_pte_index)(unsigned long gma); 75 unsigned long (*gma_to_pde_index)(unsigned long gma); 76 unsigned long (*gma_to_l3_pdp_index)(unsigned long gma); 77 unsigned long (*gma_to_l4_pdp_index)(unsigned long gma); 78 unsigned long (*gma_to_pml4_index)(unsigned long gma); 79 }; 80 81 struct intel_gvt_gtt { 82 struct intel_gvt_gtt_pte_ops *pte_ops; 83 struct intel_gvt_gtt_gma_ops *gma_ops; 84 int (*mm_alloc_page_table)(struct intel_vgpu_mm *mm); 85 void (*mm_free_page_table)(struct intel_vgpu_mm *mm); 86 struct list_head oos_page_use_list_head; 87 struct list_head oos_page_free_list_head; 88 struct list_head ppgtt_mm_lru_list_head; 89 90 struct page *scratch_page; 91 unsigned long scratch_mfn; 92 }; 93 94 typedef enum { 95 GTT_TYPE_INVALID = -1, 96 97 GTT_TYPE_GGTT_PTE, 98 99 GTT_TYPE_PPGTT_PTE_4K_ENTRY, 100 GTT_TYPE_PPGTT_PTE_64K_ENTRY, 101 GTT_TYPE_PPGTT_PTE_2M_ENTRY, 102 GTT_TYPE_PPGTT_PTE_1G_ENTRY, 103 104 GTT_TYPE_PPGTT_PTE_ENTRY, 105 106 GTT_TYPE_PPGTT_PDE_ENTRY, 107 GTT_TYPE_PPGTT_PDP_ENTRY, 108 GTT_TYPE_PPGTT_PML4_ENTRY, 109 110 GTT_TYPE_PPGTT_ROOT_ENTRY, 111 112 GTT_TYPE_PPGTT_ROOT_L3_ENTRY, 113 GTT_TYPE_PPGTT_ROOT_L4_ENTRY, 114 115 GTT_TYPE_PPGTT_ENTRY, 116 117 GTT_TYPE_PPGTT_PTE_PT, 118 GTT_TYPE_PPGTT_PDE_PT, 119 GTT_TYPE_PPGTT_PDP_PT, 120 GTT_TYPE_PPGTT_PML4_PT, 121 122 GTT_TYPE_MAX, 123 } intel_gvt_gtt_type_t; 124 125 enum intel_gvt_mm_type { 126 INTEL_GVT_MM_GGTT, 127 INTEL_GVT_MM_PPGTT, 128 }; 129 130 #define GVT_RING_CTX_NR_PDPS GEN8_3LVL_PDPES 131 132 struct intel_vgpu_mm { 133 enum intel_gvt_mm_type type; 134 struct intel_vgpu *vgpu; 135 136 struct kref ref; 137 atomic_t pincount; 138 139 union { 140 struct { 141 intel_gvt_gtt_type_t root_entry_type; 142 /* 143 * The 4 PDPs in ring context. For 48bit addressing, 144 * only PDP0 is valid and point to PML4. For 32it 145 * addressing, all 4 are used as true PDPs. 146 */ 147 u64 guest_pdps[GVT_RING_CTX_NR_PDPS]; 148 u64 shadow_pdps[GVT_RING_CTX_NR_PDPS]; 149 bool shadowed; 150 151 struct list_head list; 152 struct list_head lru_list; 153 } ppgtt_mm; 154 struct { 155 void *virtual_ggtt; 156 } ggtt_mm; 157 }; 158 }; 159 160 struct intel_vgpu_mm *intel_vgpu_create_ppgtt_mm(struct intel_vgpu *vgpu, 161 intel_gvt_gtt_type_t root_entry_type, u64 pdps[]); 162 163 static inline void intel_vgpu_mm_get(struct intel_vgpu_mm *mm) 164 { 165 kref_get(&mm->ref); 166 } 167 168 void _intel_vgpu_mm_release(struct kref *mm_ref); 169 170 static inline void intel_vgpu_mm_put(struct intel_vgpu_mm *mm) 171 { 172 kref_put(&mm->ref, _intel_vgpu_mm_release); 173 } 174 175 static inline void intel_vgpu_destroy_mm(struct intel_vgpu_mm *mm) 176 { 177 intel_vgpu_mm_put(mm); 178 } 179 180 struct intel_vgpu_guest_page; 181 182 struct intel_vgpu_scratch_pt { 183 struct page *page; 184 unsigned long page_mfn; 185 }; 186 187 struct intel_vgpu_gtt { 188 struct intel_vgpu_mm *ggtt_mm; 189 unsigned long active_ppgtt_mm_bitmap; 190 struct list_head ppgtt_mm_list_head; 191 struct radix_tree_root spt_tree; 192 struct list_head oos_page_list_head; 193 struct list_head post_shadow_list_head; 194 struct intel_vgpu_scratch_pt scratch_pt[GTT_TYPE_MAX]; 195 }; 196 197 extern int intel_vgpu_init_gtt(struct intel_vgpu *vgpu); 198 extern void intel_vgpu_clean_gtt(struct intel_vgpu *vgpu); 199 void intel_vgpu_reset_ggtt(struct intel_vgpu *vgpu, bool invalidate_old); 200 void intel_vgpu_invalidate_ppgtt(struct intel_vgpu *vgpu); 201 202 extern int intel_gvt_init_gtt(struct intel_gvt *gvt); 203 void intel_vgpu_reset_gtt(struct intel_vgpu *vgpu); 204 extern void intel_gvt_clean_gtt(struct intel_gvt *gvt); 205 206 extern struct intel_vgpu_mm *intel_gvt_find_ppgtt_mm(struct intel_vgpu *vgpu, 207 int page_table_level, void *root_entry); 208 209 struct intel_vgpu_oos_page { 210 struct intel_vgpu_ppgtt_spt *spt; 211 struct list_head list; 212 struct list_head vm_list; 213 int id; 214 unsigned char mem[I915_GTT_PAGE_SIZE]; 215 }; 216 217 #define GTT_ENTRY_NUM_IN_ONE_PAGE 512 218 219 /* Represent a vgpu shadow page table. */ 220 struct intel_vgpu_ppgtt_spt { 221 atomic_t refcount; 222 struct intel_vgpu *vgpu; 223 224 struct { 225 intel_gvt_gtt_type_t type; 226 void *vaddr; 227 struct page *page; 228 unsigned long mfn; 229 } shadow_page; 230 231 struct { 232 intel_gvt_gtt_type_t type; 233 unsigned long gfn; 234 unsigned long write_cnt; 235 struct intel_vgpu_oos_page *oos_page; 236 } guest_page; 237 238 DECLARE_BITMAP(post_shadow_bitmap, GTT_ENTRY_NUM_IN_ONE_PAGE); 239 struct list_head post_shadow_list; 240 }; 241 242 int intel_vgpu_sync_oos_pages(struct intel_vgpu *vgpu); 243 244 int intel_vgpu_flush_post_shadow(struct intel_vgpu *vgpu); 245 246 int intel_vgpu_pin_mm(struct intel_vgpu_mm *mm); 247 248 void intel_vgpu_unpin_mm(struct intel_vgpu_mm *mm); 249 250 unsigned long intel_vgpu_gma_to_gpa(struct intel_vgpu_mm *mm, 251 unsigned long gma); 252 253 struct intel_vgpu_mm *intel_vgpu_find_ppgtt_mm(struct intel_vgpu *vgpu, 254 u64 pdps[]); 255 256 struct intel_vgpu_mm *intel_vgpu_get_ppgtt_mm(struct intel_vgpu *vgpu, 257 intel_gvt_gtt_type_t root_entry_type, u64 pdps[]); 258 259 int intel_vgpu_put_ppgtt_mm(struct intel_vgpu *vgpu, u64 pdps[]); 260 261 int intel_vgpu_emulate_ggtt_mmio_read(struct intel_vgpu *vgpu, 262 unsigned int off, void *p_data, unsigned int bytes); 263 264 int intel_vgpu_emulate_ggtt_mmio_write(struct intel_vgpu *vgpu, 265 unsigned int off, void *p_data, unsigned int bytes); 266 267 #endif /* _GVT_GTT_H_ */ 268