1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Zhi Wang <zhi.a.wang@intel.com> 25 * Zhenyu Wang <zhenyuw@linux.intel.com> 26 * Xiao Zheng <xiao.zheng@intel.com> 27 * 28 * Contributors: 29 * Min He <min.he@intel.com> 30 * Bing Niu <bing.niu@intel.com> 31 * 32 */ 33 34 #ifndef _GVT_GTT_H_ 35 #define _GVT_GTT_H_ 36 37 #define I915_GTT_PAGE_SHIFT 12 38 39 struct intel_vgpu_mm; 40 41 #define INTEL_GVT_INVALID_ADDR (~0UL) 42 43 struct intel_gvt_gtt_entry { 44 u64 val64; 45 int type; 46 }; 47 48 struct intel_gvt_gtt_pte_ops { 49 int (*get_entry)(void *pt, 50 struct intel_gvt_gtt_entry *e, 51 unsigned long index, 52 bool hypervisor_access, 53 unsigned long gpa, 54 struct intel_vgpu *vgpu); 55 int (*set_entry)(void *pt, 56 struct intel_gvt_gtt_entry *e, 57 unsigned long index, 58 bool hypervisor_access, 59 unsigned long gpa, 60 struct intel_vgpu *vgpu); 61 bool (*test_present)(struct intel_gvt_gtt_entry *e); 62 void (*clear_present)(struct intel_gvt_gtt_entry *e); 63 void (*set_present)(struct intel_gvt_gtt_entry *e); 64 bool (*test_pse)(struct intel_gvt_gtt_entry *e); 65 void (*clear_pse)(struct intel_gvt_gtt_entry *e); 66 bool (*test_ips)(struct intel_gvt_gtt_entry *e); 67 void (*clear_ips)(struct intel_gvt_gtt_entry *e); 68 bool (*test_64k_splited)(struct intel_gvt_gtt_entry *e); 69 void (*clear_64k_splited)(struct intel_gvt_gtt_entry *e); 70 void (*set_64k_splited)(struct intel_gvt_gtt_entry *e); 71 void (*set_pfn)(struct intel_gvt_gtt_entry *e, unsigned long pfn); 72 unsigned long (*get_pfn)(struct intel_gvt_gtt_entry *e); 73 }; 74 75 struct intel_gvt_gtt_gma_ops { 76 unsigned long (*gma_to_ggtt_pte_index)(unsigned long gma); 77 unsigned long (*gma_to_pte_index)(unsigned long gma); 78 unsigned long (*gma_to_pde_index)(unsigned long gma); 79 unsigned long (*gma_to_l3_pdp_index)(unsigned long gma); 80 unsigned long (*gma_to_l4_pdp_index)(unsigned long gma); 81 unsigned long (*gma_to_pml4_index)(unsigned long gma); 82 }; 83 84 struct intel_gvt_gtt { 85 struct intel_gvt_gtt_pte_ops *pte_ops; 86 struct intel_gvt_gtt_gma_ops *gma_ops; 87 int (*mm_alloc_page_table)(struct intel_vgpu_mm *mm); 88 void (*mm_free_page_table)(struct intel_vgpu_mm *mm); 89 struct list_head oos_page_use_list_head; 90 struct list_head oos_page_free_list_head; 91 struct list_head ppgtt_mm_lru_list_head; 92 93 struct page *scratch_page; 94 unsigned long scratch_mfn; 95 }; 96 97 typedef enum { 98 GTT_TYPE_INVALID = -1, 99 100 GTT_TYPE_GGTT_PTE, 101 102 GTT_TYPE_PPGTT_PTE_4K_ENTRY, 103 GTT_TYPE_PPGTT_PTE_64K_ENTRY, 104 GTT_TYPE_PPGTT_PTE_2M_ENTRY, 105 GTT_TYPE_PPGTT_PTE_1G_ENTRY, 106 107 GTT_TYPE_PPGTT_PTE_ENTRY, 108 109 GTT_TYPE_PPGTT_PDE_ENTRY, 110 GTT_TYPE_PPGTT_PDP_ENTRY, 111 GTT_TYPE_PPGTT_PML4_ENTRY, 112 113 GTT_TYPE_PPGTT_ROOT_ENTRY, 114 115 GTT_TYPE_PPGTT_ROOT_L3_ENTRY, 116 GTT_TYPE_PPGTT_ROOT_L4_ENTRY, 117 118 GTT_TYPE_PPGTT_ENTRY, 119 120 GTT_TYPE_PPGTT_PTE_PT, 121 GTT_TYPE_PPGTT_PDE_PT, 122 GTT_TYPE_PPGTT_PDP_PT, 123 GTT_TYPE_PPGTT_PML4_PT, 124 125 GTT_TYPE_MAX, 126 } intel_gvt_gtt_type_t; 127 128 enum intel_gvt_mm_type { 129 INTEL_GVT_MM_GGTT, 130 INTEL_GVT_MM_PPGTT, 131 }; 132 133 #define GVT_RING_CTX_NR_PDPS GEN8_3LVL_PDPES 134 135 struct intel_gvt_partial_pte { 136 unsigned long offset; 137 u64 data; 138 struct list_head list; 139 }; 140 141 struct intel_vgpu_mm { 142 enum intel_gvt_mm_type type; 143 struct intel_vgpu *vgpu; 144 145 struct kref ref; 146 atomic_t pincount; 147 148 union { 149 struct { 150 intel_gvt_gtt_type_t root_entry_type; 151 /* 152 * The 4 PDPs in ring context. For 48bit addressing, 153 * only PDP0 is valid and point to PML4. For 32it 154 * addressing, all 4 are used as true PDPs. 155 */ 156 u64 guest_pdps[GVT_RING_CTX_NR_PDPS]; 157 u64 shadow_pdps[GVT_RING_CTX_NR_PDPS]; 158 bool shadowed; 159 160 struct list_head list; 161 struct list_head lru_list; 162 } ppgtt_mm; 163 struct { 164 void *virtual_ggtt; 165 struct list_head partial_pte_list; 166 } ggtt_mm; 167 }; 168 }; 169 170 struct intel_vgpu_mm *intel_vgpu_create_ppgtt_mm(struct intel_vgpu *vgpu, 171 intel_gvt_gtt_type_t root_entry_type, u64 pdps[]); 172 173 static inline void intel_vgpu_mm_get(struct intel_vgpu_mm *mm) 174 { 175 kref_get(&mm->ref); 176 } 177 178 void _intel_vgpu_mm_release(struct kref *mm_ref); 179 180 static inline void intel_vgpu_mm_put(struct intel_vgpu_mm *mm) 181 { 182 kref_put(&mm->ref, _intel_vgpu_mm_release); 183 } 184 185 static inline void intel_vgpu_destroy_mm(struct intel_vgpu_mm *mm) 186 { 187 intel_vgpu_mm_put(mm); 188 } 189 190 struct intel_vgpu_guest_page; 191 192 struct intel_vgpu_scratch_pt { 193 struct page *page; 194 unsigned long page_mfn; 195 }; 196 197 struct intel_vgpu_gtt { 198 struct intel_vgpu_mm *ggtt_mm; 199 unsigned long active_ppgtt_mm_bitmap; 200 struct list_head ppgtt_mm_list_head; 201 struct radix_tree_root spt_tree; 202 struct list_head oos_page_list_head; 203 struct list_head post_shadow_list_head; 204 struct intel_vgpu_scratch_pt scratch_pt[GTT_TYPE_MAX]; 205 }; 206 207 extern int intel_vgpu_init_gtt(struct intel_vgpu *vgpu); 208 extern void intel_vgpu_clean_gtt(struct intel_vgpu *vgpu); 209 void intel_vgpu_reset_ggtt(struct intel_vgpu *vgpu, bool invalidate_old); 210 void intel_vgpu_invalidate_ppgtt(struct intel_vgpu *vgpu); 211 212 extern int intel_gvt_init_gtt(struct intel_gvt *gvt); 213 void intel_vgpu_reset_gtt(struct intel_vgpu *vgpu); 214 extern void intel_gvt_clean_gtt(struct intel_gvt *gvt); 215 216 extern struct intel_vgpu_mm *intel_gvt_find_ppgtt_mm(struct intel_vgpu *vgpu, 217 int page_table_level, void *root_entry); 218 219 struct intel_vgpu_oos_page { 220 struct intel_vgpu_ppgtt_spt *spt; 221 struct list_head list; 222 struct list_head vm_list; 223 int id; 224 unsigned char mem[I915_GTT_PAGE_SIZE]; 225 }; 226 227 #define GTT_ENTRY_NUM_IN_ONE_PAGE 512 228 229 /* Represent a vgpu shadow page table. */ 230 struct intel_vgpu_ppgtt_spt { 231 atomic_t refcount; 232 struct intel_vgpu *vgpu; 233 234 struct { 235 intel_gvt_gtt_type_t type; 236 bool pde_ips; /* for 64KB PTEs */ 237 void *vaddr; 238 struct page *page; 239 unsigned long mfn; 240 } shadow_page; 241 242 struct { 243 intel_gvt_gtt_type_t type; 244 bool pde_ips; /* for 64KB PTEs */ 245 unsigned long gfn; 246 unsigned long write_cnt; 247 struct intel_vgpu_oos_page *oos_page; 248 } guest_page; 249 250 DECLARE_BITMAP(post_shadow_bitmap, GTT_ENTRY_NUM_IN_ONE_PAGE); 251 struct list_head post_shadow_list; 252 }; 253 254 int intel_vgpu_sync_oos_pages(struct intel_vgpu *vgpu); 255 256 int intel_vgpu_flush_post_shadow(struct intel_vgpu *vgpu); 257 258 int intel_vgpu_pin_mm(struct intel_vgpu_mm *mm); 259 260 void intel_vgpu_unpin_mm(struct intel_vgpu_mm *mm); 261 262 unsigned long intel_vgpu_gma_to_gpa(struct intel_vgpu_mm *mm, 263 unsigned long gma); 264 265 struct intel_vgpu_mm *intel_vgpu_find_ppgtt_mm(struct intel_vgpu *vgpu, 266 u64 pdps[]); 267 268 struct intel_vgpu_mm *intel_vgpu_get_ppgtt_mm(struct intel_vgpu *vgpu, 269 intel_gvt_gtt_type_t root_entry_type, u64 pdps[]); 270 271 int intel_vgpu_put_ppgtt_mm(struct intel_vgpu *vgpu, u64 pdps[]); 272 273 int intel_vgpu_emulate_ggtt_mmio_read(struct intel_vgpu *vgpu, 274 unsigned int off, void *p_data, unsigned int bytes); 275 276 int intel_vgpu_emulate_ggtt_mmio_write(struct intel_vgpu *vgpu, 277 unsigned int off, void *p_data, unsigned int bytes); 278 279 #endif /* _GVT_GTT_H_ */ 280