1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Kevin Tian <kevin.tian@intel.com> 25 * 26 * Contributors: 27 * Bing Niu <bing.niu@intel.com> 28 * Xu Han <xu.han@intel.com> 29 * Ping Gao <ping.a.gao@intel.com> 30 * Xiaoguang Chen <xiaoguang.chen@intel.com> 31 * Yang Liu <yang2.liu@intel.com> 32 * Tina Zhang <tina.zhang@intel.com> 33 * 34 */ 35 36 #include <uapi/drm/drm_fourcc.h> 37 #include "i915_drv.h" 38 #include "gvt.h" 39 40 #define PRIMARY_FORMAT_NUM 16 41 struct pixel_format { 42 int drm_format; /* Pixel format in DRM definition */ 43 int bpp; /* Bits per pixel, 0 indicates invalid */ 44 char *desc; /* The description */ 45 }; 46 47 static struct pixel_format bdw_pixel_formats[] = { 48 {DRM_FORMAT_C8, 8, "8-bit Indexed"}, 49 {DRM_FORMAT_RGB565, 16, "16-bit BGRX (5:6:5 MSB-R:G:B)"}, 50 {DRM_FORMAT_XRGB8888, 32, "32-bit BGRX (8:8:8:8 MSB-X:R:G:B)"}, 51 {DRM_FORMAT_XBGR2101010, 32, "32-bit RGBX (2:10:10:10 MSB-X:B:G:R)"}, 52 53 {DRM_FORMAT_XRGB2101010, 32, "32-bit BGRX (2:10:10:10 MSB-X:R:G:B)"}, 54 {DRM_FORMAT_XBGR8888, 32, "32-bit RGBX (8:8:8:8 MSB-X:B:G:R)"}, 55 56 /* non-supported format has bpp default to 0 */ 57 {0, 0, NULL}, 58 }; 59 60 static struct pixel_format skl_pixel_formats[] = { 61 {DRM_FORMAT_YUYV, 16, "16-bit packed YUYV (8:8:8:8 MSB-V:Y2:U:Y1)"}, 62 {DRM_FORMAT_UYVY, 16, "16-bit packed UYVY (8:8:8:8 MSB-Y2:V:Y1:U)"}, 63 {DRM_FORMAT_YVYU, 16, "16-bit packed YVYU (8:8:8:8 MSB-U:Y2:V:Y1)"}, 64 {DRM_FORMAT_VYUY, 16, "16-bit packed VYUY (8:8:8:8 MSB-Y2:U:Y1:V)"}, 65 66 {DRM_FORMAT_C8, 8, "8-bit Indexed"}, 67 {DRM_FORMAT_RGB565, 16, "16-bit BGRX (5:6:5 MSB-R:G:B)"}, 68 {DRM_FORMAT_ABGR8888, 32, "32-bit RGBA (8:8:8:8 MSB-A:B:G:R)"}, 69 {DRM_FORMAT_XBGR8888, 32, "32-bit RGBX (8:8:8:8 MSB-X:B:G:R)"}, 70 71 {DRM_FORMAT_ARGB8888, 32, "32-bit BGRA (8:8:8:8 MSB-A:R:G:B)"}, 72 {DRM_FORMAT_XRGB8888, 32, "32-bit BGRX (8:8:8:8 MSB-X:R:G:B)"}, 73 {DRM_FORMAT_XBGR2101010, 32, "32-bit RGBX (2:10:10:10 MSB-X:B:G:R)"}, 74 {DRM_FORMAT_XRGB2101010, 32, "32-bit BGRX (2:10:10:10 MSB-X:R:G:B)"}, 75 76 /* non-supported format has bpp default to 0 */ 77 {0, 0, NULL}, 78 }; 79 80 static int bdw_format_to_drm(int format) 81 { 82 int bdw_pixel_formats_index = 6; 83 84 switch (format) { 85 case DISPPLANE_8BPP: 86 bdw_pixel_formats_index = 0; 87 break; 88 case DISPPLANE_BGRX565: 89 bdw_pixel_formats_index = 1; 90 break; 91 case DISPPLANE_BGRX888: 92 bdw_pixel_formats_index = 2; 93 break; 94 case DISPPLANE_RGBX101010: 95 bdw_pixel_formats_index = 3; 96 break; 97 case DISPPLANE_BGRX101010: 98 bdw_pixel_formats_index = 4; 99 break; 100 case DISPPLANE_RGBX888: 101 bdw_pixel_formats_index = 5; 102 break; 103 104 default: 105 break; 106 } 107 108 return bdw_pixel_formats_index; 109 } 110 111 static int skl_format_to_drm(int format, bool rgb_order, bool alpha, 112 int yuv_order) 113 { 114 int skl_pixel_formats_index = 12; 115 116 switch (format) { 117 case PLANE_CTL_FORMAT_INDEXED: 118 skl_pixel_formats_index = 4; 119 break; 120 case PLANE_CTL_FORMAT_RGB_565: 121 skl_pixel_formats_index = 5; 122 break; 123 case PLANE_CTL_FORMAT_XRGB_8888: 124 if (rgb_order) 125 skl_pixel_formats_index = alpha ? 6 : 7; 126 else 127 skl_pixel_formats_index = alpha ? 8 : 9; 128 break; 129 case PLANE_CTL_FORMAT_XRGB_2101010: 130 skl_pixel_formats_index = rgb_order ? 10 : 11; 131 break; 132 case PLANE_CTL_FORMAT_YUV422: 133 skl_pixel_formats_index = yuv_order >> 16; 134 if (skl_pixel_formats_index > 3) 135 return -EINVAL; 136 break; 137 138 default: 139 break; 140 } 141 142 return skl_pixel_formats_index; 143 } 144 145 static u32 intel_vgpu_get_stride(struct intel_vgpu *vgpu, int pipe, 146 u32 tiled, int stride_mask, int bpp) 147 { 148 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 149 150 u32 stride_reg = vgpu_vreg(vgpu, DSPSTRIDE(pipe)) & stride_mask; 151 u32 stride = stride_reg; 152 153 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { 154 switch (tiled) { 155 case PLANE_CTL_TILED_LINEAR: 156 stride = stride_reg * 64; 157 break; 158 case PLANE_CTL_TILED_X: 159 stride = stride_reg * 512; 160 break; 161 case PLANE_CTL_TILED_Y: 162 stride = stride_reg * 128; 163 break; 164 case PLANE_CTL_TILED_YF: 165 if (bpp == 8) 166 stride = stride_reg * 64; 167 else if (bpp == 16 || bpp == 32 || bpp == 64) 168 stride = stride_reg * 128; 169 else 170 gvt_dbg_core("skl: unsupported bpp:%d\n", bpp); 171 break; 172 default: 173 gvt_dbg_core("skl: unsupported tile format:%x\n", 174 tiled); 175 } 176 } 177 178 return stride; 179 } 180 181 static int get_active_pipe(struct intel_vgpu *vgpu) 182 { 183 int i; 184 185 for (i = 0; i < I915_MAX_PIPES; i++) 186 if (pipe_is_enabled(vgpu, i)) 187 break; 188 189 return i; 190 } 191 192 /** 193 * intel_vgpu_decode_primary_plane - Decode primary plane 194 * @vgpu: input vgpu 195 * @plane: primary plane to save decoded info 196 * This function is called for decoding plane 197 * 198 * Returns: 199 * 0 on success, non-zero if failed. 200 */ 201 int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu, 202 struct intel_vgpu_primary_plane_format *plane) 203 { 204 u32 val, fmt; 205 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 206 int pipe; 207 208 pipe = get_active_pipe(vgpu); 209 if (pipe >= I915_MAX_PIPES) 210 return -ENODEV; 211 212 val = vgpu_vreg(vgpu, DSPCNTR(pipe)); 213 plane->enabled = !!(val & DISPLAY_PLANE_ENABLE); 214 if (!plane->enabled) 215 return -ENODEV; 216 217 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { 218 plane->tiled = (val & PLANE_CTL_TILED_MASK) >> 219 _PLANE_CTL_TILED_SHIFT; 220 fmt = skl_format_to_drm( 221 val & PLANE_CTL_FORMAT_MASK, 222 val & PLANE_CTL_ORDER_RGBX, 223 val & PLANE_CTL_ALPHA_MASK, 224 val & PLANE_CTL_YUV422_ORDER_MASK); 225 226 if (fmt >= ARRAY_SIZE(skl_pixel_formats)) { 227 gvt_vgpu_err("Out-of-bounds pixel format index\n"); 228 return -EINVAL; 229 } 230 231 plane->bpp = skl_pixel_formats[fmt].bpp; 232 plane->drm_format = skl_pixel_formats[fmt].drm_format; 233 } else { 234 plane->tiled = !!(val & DISPPLANE_TILED); 235 fmt = bdw_format_to_drm(val & DISPPLANE_PIXFORMAT_MASK); 236 plane->bpp = bdw_pixel_formats[fmt].bpp; 237 plane->drm_format = bdw_pixel_formats[fmt].drm_format; 238 } 239 240 if (!plane->bpp) { 241 gvt_vgpu_err("Non-supported pixel format (0x%x)\n", fmt); 242 return -EINVAL; 243 } 244 245 plane->hw_format = fmt; 246 247 plane->base = vgpu_vreg(vgpu, DSPSURF(pipe)) & I915_GTT_PAGE_MASK; 248 if (!intel_gvt_ggtt_validate_range(vgpu, plane->base, 0)) { 249 gvt_vgpu_err("invalid gma address: %lx\n", 250 (unsigned long)plane->base); 251 return -EINVAL; 252 } 253 254 plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base); 255 if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) { 256 gvt_vgpu_err("invalid gma address: %lx\n", 257 (unsigned long)plane->base); 258 return -EINVAL; 259 } 260 261 plane->stride = intel_vgpu_get_stride(vgpu, pipe, (plane->tiled << 10), 262 (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) ? 263 (_PRI_PLANE_STRIDE_MASK >> 6) : 264 _PRI_PLANE_STRIDE_MASK, plane->bpp); 265 266 plane->width = (vgpu_vreg(vgpu, PIPESRC(pipe)) & _PIPE_H_SRCSZ_MASK) >> 267 _PIPE_H_SRCSZ_SHIFT; 268 plane->width += 1; 269 plane->height = (vgpu_vreg(vgpu, PIPESRC(pipe)) & 270 _PIPE_V_SRCSZ_MASK) >> _PIPE_V_SRCSZ_SHIFT; 271 plane->height += 1; /* raw height is one minus the real value */ 272 273 val = vgpu_vreg(vgpu, DSPTILEOFF(pipe)); 274 plane->x_offset = (val & _PRI_PLANE_X_OFF_MASK) >> 275 _PRI_PLANE_X_OFF_SHIFT; 276 plane->y_offset = (val & _PRI_PLANE_Y_OFF_MASK) >> 277 _PRI_PLANE_Y_OFF_SHIFT; 278 279 return 0; 280 } 281 282 #define CURSOR_FORMAT_NUM (1 << 6) 283 struct cursor_mode_format { 284 int drm_format; /* Pixel format in DRM definition */ 285 u8 bpp; /* Bits per pixel; 0 indicates invalid */ 286 u32 width; /* In pixel */ 287 u32 height; /* In lines */ 288 char *desc; /* The description */ 289 }; 290 291 static struct cursor_mode_format cursor_pixel_formats[] = { 292 {DRM_FORMAT_ARGB8888, 32, 128, 128, "128x128 32bpp ARGB"}, 293 {DRM_FORMAT_ARGB8888, 32, 256, 256, "256x256 32bpp ARGB"}, 294 {DRM_FORMAT_ARGB8888, 32, 64, 64, "64x64 32bpp ARGB"}, 295 {DRM_FORMAT_ARGB8888, 32, 64, 64, "64x64 32bpp ARGB"}, 296 297 /* non-supported format has bpp default to 0 */ 298 {0, 0, 0, 0, NULL}, 299 }; 300 301 static int cursor_mode_to_drm(int mode) 302 { 303 int cursor_pixel_formats_index = 4; 304 305 switch (mode) { 306 case CURSOR_MODE_128_ARGB_AX: 307 cursor_pixel_formats_index = 0; 308 break; 309 case CURSOR_MODE_256_ARGB_AX: 310 cursor_pixel_formats_index = 1; 311 break; 312 case CURSOR_MODE_64_ARGB_AX: 313 cursor_pixel_formats_index = 2; 314 break; 315 case CURSOR_MODE_64_32B_AX: 316 cursor_pixel_formats_index = 3; 317 break; 318 319 default: 320 break; 321 } 322 323 return cursor_pixel_formats_index; 324 } 325 326 /** 327 * intel_vgpu_decode_cursor_plane - Decode sprite plane 328 * @vgpu: input vgpu 329 * @plane: cursor plane to save decoded info 330 * This function is called for decoding plane 331 * 332 * Returns: 333 * 0 on success, non-zero if failed. 334 */ 335 int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu, 336 struct intel_vgpu_cursor_plane_format *plane) 337 { 338 u32 val, mode, index; 339 u32 alpha_plane, alpha_force; 340 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 341 int pipe; 342 343 pipe = get_active_pipe(vgpu); 344 if (pipe >= I915_MAX_PIPES) 345 return -ENODEV; 346 347 val = vgpu_vreg(vgpu, CURCNTR(pipe)); 348 mode = val & CURSOR_MODE; 349 plane->enabled = (mode != CURSOR_MODE_DISABLE); 350 if (!plane->enabled) 351 return -ENODEV; 352 353 index = cursor_mode_to_drm(mode); 354 355 if (!cursor_pixel_formats[index].bpp) { 356 gvt_vgpu_err("Non-supported cursor mode (0x%x)\n", mode); 357 return -EINVAL; 358 } 359 plane->mode = mode; 360 plane->bpp = cursor_pixel_formats[index].bpp; 361 plane->drm_format = cursor_pixel_formats[index].drm_format; 362 plane->width = cursor_pixel_formats[index].width; 363 plane->height = cursor_pixel_formats[index].height; 364 365 alpha_plane = (val & _CURSOR_ALPHA_PLANE_MASK) >> 366 _CURSOR_ALPHA_PLANE_SHIFT; 367 alpha_force = (val & _CURSOR_ALPHA_FORCE_MASK) >> 368 _CURSOR_ALPHA_FORCE_SHIFT; 369 if (alpha_plane || alpha_force) 370 gvt_dbg_core("alpha_plane=0x%x, alpha_force=0x%x\n", 371 alpha_plane, alpha_force); 372 373 plane->base = vgpu_vreg(vgpu, CURBASE(pipe)) & I915_GTT_PAGE_MASK; 374 if (!intel_gvt_ggtt_validate_range(vgpu, plane->base, 0)) { 375 gvt_vgpu_err("invalid gma address: %lx\n", 376 (unsigned long)plane->base); 377 return -EINVAL; 378 } 379 380 plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base); 381 if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) { 382 gvt_vgpu_err("invalid gma address: %lx\n", 383 (unsigned long)plane->base); 384 return -EINVAL; 385 } 386 387 val = vgpu_vreg(vgpu, CURPOS(pipe)); 388 plane->x_pos = (val & _CURSOR_POS_X_MASK) >> _CURSOR_POS_X_SHIFT; 389 plane->x_sign = (val & _CURSOR_SIGN_X_MASK) >> _CURSOR_SIGN_X_SHIFT; 390 plane->y_pos = (val & _CURSOR_POS_Y_MASK) >> _CURSOR_POS_Y_SHIFT; 391 plane->y_sign = (val & _CURSOR_SIGN_Y_MASK) >> _CURSOR_SIGN_Y_SHIFT; 392 393 return 0; 394 } 395 396 #define SPRITE_FORMAT_NUM (1 << 3) 397 398 static struct pixel_format sprite_pixel_formats[SPRITE_FORMAT_NUM] = { 399 [0x0] = {DRM_FORMAT_YUV422, 16, "YUV 16-bit 4:2:2 packed"}, 400 [0x1] = {DRM_FORMAT_XRGB2101010, 32, "RGB 32-bit 2:10:10:10"}, 401 [0x2] = {DRM_FORMAT_XRGB8888, 32, "RGB 32-bit 8:8:8:8"}, 402 [0x4] = {DRM_FORMAT_AYUV, 32, 403 "YUV 32-bit 4:4:4 packed (8:8:8:8 MSB-X:Y:U:V)"}, 404 }; 405 406 /** 407 * intel_vgpu_decode_sprite_plane - Decode sprite plane 408 * @vgpu: input vgpu 409 * @plane: sprite plane to save decoded info 410 * This function is called for decoding plane 411 * 412 * Returns: 413 * 0 on success, non-zero if failed. 414 */ 415 int intel_vgpu_decode_sprite_plane(struct intel_vgpu *vgpu, 416 struct intel_vgpu_sprite_plane_format *plane) 417 { 418 u32 val, fmt; 419 u32 color_order, yuv_order; 420 int drm_format; 421 int pipe; 422 423 pipe = get_active_pipe(vgpu); 424 if (pipe >= I915_MAX_PIPES) 425 return -ENODEV; 426 427 val = vgpu_vreg(vgpu, SPRCTL(pipe)); 428 plane->enabled = !!(val & SPRITE_ENABLE); 429 if (!plane->enabled) 430 return -ENODEV; 431 432 plane->tiled = !!(val & SPRITE_TILED); 433 color_order = !!(val & SPRITE_RGB_ORDER_RGBX); 434 yuv_order = (val & SPRITE_YUV_BYTE_ORDER_MASK) >> 435 _SPRITE_YUV_ORDER_SHIFT; 436 437 fmt = (val & SPRITE_PIXFORMAT_MASK) >> _SPRITE_FMT_SHIFT; 438 if (!sprite_pixel_formats[fmt].bpp) { 439 gvt_vgpu_err("Non-supported pixel format (0x%x)\n", fmt); 440 return -EINVAL; 441 } 442 plane->hw_format = fmt; 443 plane->bpp = sprite_pixel_formats[fmt].bpp; 444 drm_format = sprite_pixel_formats[fmt].drm_format; 445 446 /* Order of RGB values in an RGBxxx buffer may be ordered RGB or 447 * BGR depending on the state of the color_order field 448 */ 449 if (!color_order) { 450 if (drm_format == DRM_FORMAT_XRGB2101010) 451 drm_format = DRM_FORMAT_XBGR2101010; 452 else if (drm_format == DRM_FORMAT_XRGB8888) 453 drm_format = DRM_FORMAT_XBGR8888; 454 } 455 456 if (drm_format == DRM_FORMAT_YUV422) { 457 switch (yuv_order) { 458 case 0: 459 drm_format = DRM_FORMAT_YUYV; 460 break; 461 case 1: 462 drm_format = DRM_FORMAT_UYVY; 463 break; 464 case 2: 465 drm_format = DRM_FORMAT_YVYU; 466 break; 467 case 3: 468 drm_format = DRM_FORMAT_VYUY; 469 break; 470 default: 471 /* yuv_order has only 2 bits */ 472 break; 473 } 474 } 475 476 plane->drm_format = drm_format; 477 478 plane->base = vgpu_vreg(vgpu, SPRSURF(pipe)) & I915_GTT_PAGE_MASK; 479 if (!intel_gvt_ggtt_validate_range(vgpu, plane->base, 0)) { 480 gvt_vgpu_err("invalid gma address: %lx\n", 481 (unsigned long)plane->base); 482 return -EINVAL; 483 } 484 485 plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base); 486 if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) { 487 gvt_vgpu_err("invalid gma address: %lx\n", 488 (unsigned long)plane->base); 489 return -EINVAL; 490 } 491 492 plane->stride = vgpu_vreg(vgpu, SPRSTRIDE(pipe)) & 493 _SPRITE_STRIDE_MASK; 494 495 val = vgpu_vreg(vgpu, SPRSIZE(pipe)); 496 plane->height = (val & _SPRITE_SIZE_HEIGHT_MASK) >> 497 _SPRITE_SIZE_HEIGHT_SHIFT; 498 plane->width = (val & _SPRITE_SIZE_WIDTH_MASK) >> 499 _SPRITE_SIZE_WIDTH_SHIFT; 500 plane->height += 1; /* raw height is one minus the real value */ 501 plane->width += 1; /* raw width is one minus the real value */ 502 503 val = vgpu_vreg(vgpu, SPRPOS(pipe)); 504 plane->x_pos = (val & _SPRITE_POS_X_MASK) >> _SPRITE_POS_X_SHIFT; 505 plane->y_pos = (val & _SPRITE_POS_Y_MASK) >> _SPRITE_POS_Y_SHIFT; 506 507 val = vgpu_vreg(vgpu, SPROFFSET(pipe)); 508 plane->x_offset = (val & _SPRITE_OFFSET_START_X_MASK) >> 509 _SPRITE_OFFSET_START_X_SHIFT; 510 plane->y_offset = (val & _SPRITE_OFFSET_START_Y_MASK) >> 511 _SPRITE_OFFSET_START_Y_SHIFT; 512 513 return 0; 514 } 515