1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Ke Yu 25 * Zhiyuan Lv <zhiyuan.lv@intel.com> 26 * 27 * Contributors: 28 * Terrence Xu <terrence.xu@intel.com> 29 * Changbin Du <changbin.du@intel.com> 30 * Bing Niu <bing.niu@intel.com> 31 * Zhi Wang <zhi.a.wang@intel.com> 32 * 33 */ 34 35 #include "i915_drv.h" 36 #include "gvt.h" 37 38 #define GMBUS1_TOTAL_BYTES_SHIFT 16 39 #define GMBUS1_TOTAL_BYTES_MASK 0x1ff 40 #define gmbus1_total_byte_count(v) (((v) >> \ 41 GMBUS1_TOTAL_BYTES_SHIFT) & GMBUS1_TOTAL_BYTES_MASK) 42 #define gmbus1_slave_addr(v) (((v) & 0xff) >> 1) 43 #define gmbus1_slave_index(v) (((v) >> 8) & 0xff) 44 #define gmbus1_bus_cycle(v) (((v) >> 25) & 0x7) 45 46 /* GMBUS0 bits definitions */ 47 #define _GMBUS_PIN_SEL_MASK (0x7) 48 49 static unsigned char edid_get_byte(struct intel_vgpu *vgpu) 50 { 51 struct intel_vgpu_i2c_edid *edid = &vgpu->display.i2c_edid; 52 unsigned char chr = 0; 53 54 if (edid->state == I2C_NOT_SPECIFIED || !edid->slave_selected) { 55 gvt_vgpu_err("Driver tries to read EDID without proper sequence!\n"); 56 return 0; 57 } 58 if (edid->current_edid_read >= EDID_SIZE) { 59 gvt_vgpu_err("edid_get_byte() exceeds the size of EDID!\n"); 60 return 0; 61 } 62 63 if (!edid->edid_available) { 64 gvt_vgpu_err("Reading EDID but EDID is not available!\n"); 65 return 0; 66 } 67 68 if (intel_vgpu_has_monitor_on_port(vgpu, edid->port)) { 69 struct intel_vgpu_edid_data *edid_data = 70 intel_vgpu_port(vgpu, edid->port)->edid; 71 72 chr = edid_data->edid_block[edid->current_edid_read]; 73 edid->current_edid_read++; 74 } else { 75 gvt_vgpu_err("No EDID available during the reading?\n"); 76 } 77 return chr; 78 } 79 80 static inline int bxt_get_port_from_gmbus0(u32 gmbus0) 81 { 82 int port_select = gmbus0 & _GMBUS_PIN_SEL_MASK; 83 int port = -EINVAL; 84 85 if (port_select == 1) 86 port = PORT_B; 87 else if (port_select == 2) 88 port = PORT_C; 89 else if (port_select == 3) 90 port = PORT_D; 91 return port; 92 } 93 94 static inline int get_port_from_gmbus0(u32 gmbus0) 95 { 96 int port_select = gmbus0 & _GMBUS_PIN_SEL_MASK; 97 int port = -EINVAL; 98 99 if (port_select == 2) 100 port = PORT_E; 101 else if (port_select == 4) 102 port = PORT_C; 103 else if (port_select == 5) 104 port = PORT_B; 105 else if (port_select == 6) 106 port = PORT_D; 107 return port; 108 } 109 110 static void reset_gmbus_controller(struct intel_vgpu *vgpu) 111 { 112 vgpu_vreg_t(vgpu, PCH_GMBUS2) = GMBUS_HW_RDY; 113 if (!vgpu->display.i2c_edid.edid_available) 114 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER; 115 vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE; 116 } 117 118 /* GMBUS0 */ 119 static int gmbus0_mmio_write(struct intel_vgpu *vgpu, 120 unsigned int offset, void *p_data, unsigned int bytes) 121 { 122 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 123 int port, pin_select; 124 125 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes); 126 127 pin_select = vgpu_vreg(vgpu, offset) & _GMBUS_PIN_SEL_MASK; 128 129 intel_vgpu_init_i2c_edid(vgpu); 130 131 if (pin_select == 0) 132 return 0; 133 134 if (IS_BROXTON(dev_priv)) 135 port = bxt_get_port_from_gmbus0(pin_select); 136 else 137 port = get_port_from_gmbus0(pin_select); 138 if (WARN_ON(port < 0)) 139 return 0; 140 141 vgpu->display.i2c_edid.state = I2C_GMBUS; 142 vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE; 143 144 vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE; 145 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY | GMBUS_HW_WAIT_PHASE; 146 147 if (intel_vgpu_has_monitor_on_port(vgpu, port) && 148 !intel_vgpu_port_is_dp(vgpu, port)) { 149 vgpu->display.i2c_edid.port = port; 150 vgpu->display.i2c_edid.edid_available = true; 151 vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_SATOER; 152 } else 153 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER; 154 return 0; 155 } 156 157 static int gmbus1_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 158 void *p_data, unsigned int bytes) 159 { 160 struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid; 161 u32 slave_addr; 162 u32 wvalue = *(u32 *)p_data; 163 164 if (vgpu_vreg(vgpu, offset) & GMBUS_SW_CLR_INT) { 165 if (!(wvalue & GMBUS_SW_CLR_INT)) { 166 vgpu_vreg(vgpu, offset) &= ~GMBUS_SW_CLR_INT; 167 reset_gmbus_controller(vgpu); 168 } 169 /* 170 * TODO: "This bit is cleared to zero when an event 171 * causes the HW_RDY bit transition to occur " 172 */ 173 } else { 174 /* 175 * per bspec setting this bit can cause: 176 * 1) INT status bit cleared 177 * 2) HW_RDY bit asserted 178 */ 179 if (wvalue & GMBUS_SW_CLR_INT) { 180 vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_INT; 181 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY; 182 } 183 184 /* For virtualization, we suppose that HW is always ready, 185 * so GMBUS_SW_RDY should always be cleared 186 */ 187 if (wvalue & GMBUS_SW_RDY) 188 wvalue &= ~GMBUS_SW_RDY; 189 190 i2c_edid->gmbus.total_byte_count = 191 gmbus1_total_byte_count(wvalue); 192 slave_addr = gmbus1_slave_addr(wvalue); 193 194 /* vgpu gmbus only support EDID */ 195 if (slave_addr == EDID_ADDR) { 196 i2c_edid->slave_selected = true; 197 } else if (slave_addr != 0) { 198 gvt_dbg_dpy( 199 "vgpu%d: unsupported gmbus slave addr(0x%x)\n" 200 " gmbus operations will be ignored.\n", 201 vgpu->id, slave_addr); 202 } 203 204 if (wvalue & GMBUS_CYCLE_INDEX) 205 i2c_edid->current_edid_read = 206 gmbus1_slave_index(wvalue); 207 208 i2c_edid->gmbus.cycle_type = gmbus1_bus_cycle(wvalue); 209 switch (gmbus1_bus_cycle(wvalue)) { 210 case GMBUS_NOCYCLE: 211 break; 212 case GMBUS_STOP: 213 /* From spec: 214 * This can only cause a STOP to be generated 215 * if a GMBUS cycle is generated, the GMBUS is 216 * currently in a data/wait/idle phase, or it is in a 217 * WAIT phase 218 */ 219 if (gmbus1_bus_cycle(vgpu_vreg(vgpu, offset)) 220 != GMBUS_NOCYCLE) { 221 intel_vgpu_init_i2c_edid(vgpu); 222 /* After the 'stop' cycle, hw state would become 223 * 'stop phase' and then 'idle phase' after a 224 * few milliseconds. In emulation, we just set 225 * it as 'idle phase' ('stop phase' is not 226 * visible in gmbus interface) 227 */ 228 i2c_edid->gmbus.phase = GMBUS_IDLE_PHASE; 229 vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE; 230 } 231 break; 232 case NIDX_NS_W: 233 case IDX_NS_W: 234 case NIDX_STOP: 235 case IDX_STOP: 236 /* From hw spec the GMBUS phase 237 * transition like this: 238 * START (-->INDEX) -->DATA 239 */ 240 i2c_edid->gmbus.phase = GMBUS_DATA_PHASE; 241 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_ACTIVE; 242 break; 243 default: 244 gvt_vgpu_err("Unknown/reserved GMBUS cycle detected!\n"); 245 break; 246 } 247 /* 248 * From hw spec the WAIT state will be 249 * cleared: 250 * (1) in a new GMBUS cycle 251 * (2) by generating a stop 252 */ 253 vgpu_vreg(vgpu, offset) = wvalue; 254 } 255 return 0; 256 } 257 258 static int gmbus3_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 259 void *p_data, unsigned int bytes) 260 { 261 WARN_ON(1); 262 return 0; 263 } 264 265 static int gmbus3_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 266 void *p_data, unsigned int bytes) 267 { 268 int i; 269 unsigned char byte_data; 270 struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid; 271 int byte_left = i2c_edid->gmbus.total_byte_count - 272 i2c_edid->current_edid_read; 273 int byte_count = byte_left; 274 u32 reg_data = 0; 275 276 /* Data can only be recevied if previous settings correct */ 277 if (vgpu_vreg_t(vgpu, PCH_GMBUS1) & GMBUS_SLAVE_READ) { 278 if (byte_left <= 0) { 279 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); 280 return 0; 281 } 282 283 if (byte_count > 4) 284 byte_count = 4; 285 for (i = 0; i < byte_count; i++) { 286 byte_data = edid_get_byte(vgpu); 287 reg_data |= (byte_data << (i << 3)); 288 } 289 290 memcpy(&vgpu_vreg(vgpu, offset), ®_data, byte_count); 291 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); 292 293 if (byte_left <= 4) { 294 switch (i2c_edid->gmbus.cycle_type) { 295 case NIDX_STOP: 296 case IDX_STOP: 297 i2c_edid->gmbus.phase = GMBUS_IDLE_PHASE; 298 break; 299 case NIDX_NS_W: 300 case IDX_NS_W: 301 default: 302 i2c_edid->gmbus.phase = GMBUS_WAIT_PHASE; 303 break; 304 } 305 intel_vgpu_init_i2c_edid(vgpu); 306 } 307 /* 308 * Read GMBUS3 during send operation, 309 * return the latest written value 310 */ 311 } else { 312 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); 313 gvt_vgpu_err("warning: gmbus3 read with nothing returned\n"); 314 } 315 return 0; 316 } 317 318 static int gmbus2_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 319 void *p_data, unsigned int bytes) 320 { 321 u32 value = vgpu_vreg(vgpu, offset); 322 323 if (!(vgpu_vreg(vgpu, offset) & GMBUS_INUSE)) 324 vgpu_vreg(vgpu, offset) |= GMBUS_INUSE; 325 memcpy(p_data, (void *)&value, bytes); 326 return 0; 327 } 328 329 static int gmbus2_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 330 void *p_data, unsigned int bytes) 331 { 332 u32 wvalue = *(u32 *)p_data; 333 334 if (wvalue & GMBUS_INUSE) 335 vgpu_vreg(vgpu, offset) &= ~GMBUS_INUSE; 336 /* All other bits are read-only */ 337 return 0; 338 } 339 340 /** 341 * intel_gvt_i2c_handle_gmbus_read - emulate gmbus register mmio read 342 * @vgpu: a vGPU 343 * @offset: reg offset 344 * @p_data: data return buffer 345 * @bytes: access data length 346 * 347 * This function is used to emulate gmbus register mmio read 348 * 349 * Returns: 350 * Zero on success, negative error code if failed. 351 * 352 */ 353 int intel_gvt_i2c_handle_gmbus_read(struct intel_vgpu *vgpu, 354 unsigned int offset, void *p_data, unsigned int bytes) 355 { 356 if (WARN_ON(bytes > 8 && (offset & (bytes - 1)))) 357 return -EINVAL; 358 359 if (offset == i915_mmio_reg_offset(PCH_GMBUS2)) 360 return gmbus2_mmio_read(vgpu, offset, p_data, bytes); 361 else if (offset == i915_mmio_reg_offset(PCH_GMBUS3)) 362 return gmbus3_mmio_read(vgpu, offset, p_data, bytes); 363 364 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); 365 return 0; 366 } 367 368 /** 369 * intel_gvt_i2c_handle_gmbus_write - emulate gmbus register mmio write 370 * @vgpu: a vGPU 371 * @offset: reg offset 372 * @p_data: data return buffer 373 * @bytes: access data length 374 * 375 * This function is used to emulate gmbus register mmio write 376 * 377 * Returns: 378 * Zero on success, negative error code if failed. 379 * 380 */ 381 int intel_gvt_i2c_handle_gmbus_write(struct intel_vgpu *vgpu, 382 unsigned int offset, void *p_data, unsigned int bytes) 383 { 384 if (WARN_ON(bytes > 8 && (offset & (bytes - 1)))) 385 return -EINVAL; 386 387 if (offset == i915_mmio_reg_offset(PCH_GMBUS0)) 388 return gmbus0_mmio_write(vgpu, offset, p_data, bytes); 389 else if (offset == i915_mmio_reg_offset(PCH_GMBUS1)) 390 return gmbus1_mmio_write(vgpu, offset, p_data, bytes); 391 else if (offset == i915_mmio_reg_offset(PCH_GMBUS2)) 392 return gmbus2_mmio_write(vgpu, offset, p_data, bytes); 393 else if (offset == i915_mmio_reg_offset(PCH_GMBUS3)) 394 return gmbus3_mmio_write(vgpu, offset, p_data, bytes); 395 396 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes); 397 return 0; 398 } 399 400 enum { 401 AUX_CH_CTL = 0, 402 AUX_CH_DATA1, 403 AUX_CH_DATA2, 404 AUX_CH_DATA3, 405 AUX_CH_DATA4, 406 AUX_CH_DATA5 407 }; 408 409 static inline int get_aux_ch_reg(unsigned int offset) 410 { 411 int reg; 412 413 switch (offset & 0xff) { 414 case 0x10: 415 reg = AUX_CH_CTL; 416 break; 417 case 0x14: 418 reg = AUX_CH_DATA1; 419 break; 420 case 0x18: 421 reg = AUX_CH_DATA2; 422 break; 423 case 0x1c: 424 reg = AUX_CH_DATA3; 425 break; 426 case 0x20: 427 reg = AUX_CH_DATA4; 428 break; 429 case 0x24: 430 reg = AUX_CH_DATA5; 431 break; 432 default: 433 reg = -1; 434 break; 435 } 436 return reg; 437 } 438 439 #define AUX_CTL_MSG_LENGTH(reg) \ 440 ((reg & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> \ 441 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) 442 443 /** 444 * intel_gvt_i2c_handle_aux_ch_write - emulate AUX channel register write 445 * @vgpu: a vGPU 446 * @port_idx: port index 447 * @offset: reg offset 448 * @p_data: write ptr 449 * 450 * This function is used to emulate AUX channel register write 451 * 452 */ 453 void intel_gvt_i2c_handle_aux_ch_write(struct intel_vgpu *vgpu, 454 int port_idx, 455 unsigned int offset, 456 void *p_data) 457 { 458 struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid; 459 int msg_length, ret_msg_size; 460 int msg, addr, ctrl, op; 461 u32 value = *(u32 *)p_data; 462 int aux_data_for_write = 0; 463 int reg = get_aux_ch_reg(offset); 464 465 if (reg != AUX_CH_CTL) { 466 vgpu_vreg(vgpu, offset) = value; 467 return; 468 } 469 470 msg_length = AUX_CTL_MSG_LENGTH(value); 471 // check the msg in DATA register. 472 msg = vgpu_vreg(vgpu, offset + 4); 473 addr = (msg >> 8) & 0xffff; 474 ctrl = (msg >> 24) & 0xff; 475 op = ctrl >> 4; 476 if (!(value & DP_AUX_CH_CTL_SEND_BUSY)) { 477 /* The ctl write to clear some states */ 478 return; 479 } 480 481 /* Always set the wanted value for vms. */ 482 ret_msg_size = (((op & 0x1) == GVT_AUX_I2C_READ) ? 2 : 1); 483 vgpu_vreg(vgpu, offset) = 484 DP_AUX_CH_CTL_DONE | 485 ((ret_msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) & 486 DP_AUX_CH_CTL_MESSAGE_SIZE_MASK); 487 488 if (msg_length == 3) { 489 if (!(op & GVT_AUX_I2C_MOT)) { 490 /* stop */ 491 intel_vgpu_init_i2c_edid(vgpu); 492 } else { 493 /* start or restart */ 494 i2c_edid->aux_ch.i2c_over_aux_ch = true; 495 i2c_edid->aux_ch.aux_ch_mot = true; 496 if (addr == 0) { 497 /* reset the address */ 498 intel_vgpu_init_i2c_edid(vgpu); 499 } else if (addr == EDID_ADDR) { 500 i2c_edid->state = I2C_AUX_CH; 501 i2c_edid->port = port_idx; 502 i2c_edid->slave_selected = true; 503 if (intel_vgpu_has_monitor_on_port(vgpu, 504 port_idx) && 505 intel_vgpu_port_is_dp(vgpu, port_idx)) 506 i2c_edid->edid_available = true; 507 } 508 } 509 } else if ((op & 0x1) == GVT_AUX_I2C_WRITE) { 510 /* TODO 511 * We only support EDID reading from I2C_over_AUX. And 512 * we do not expect the index mode to be used. Right now 513 * the WRITE operation is ignored. It is good enough to 514 * support the gfx driver to do EDID access. 515 */ 516 } else { 517 if (WARN_ON((op & 0x1) != GVT_AUX_I2C_READ)) 518 return; 519 if (WARN_ON(msg_length != 4)) 520 return; 521 if (i2c_edid->edid_available && i2c_edid->slave_selected) { 522 unsigned char val = edid_get_byte(vgpu); 523 524 aux_data_for_write = (val << 16); 525 } else 526 aux_data_for_write = (0xff << 16); 527 } 528 /* write the return value in AUX_CH_DATA reg which includes: 529 * ACK of I2C_WRITE 530 * returned byte if it is READ 531 */ 532 aux_data_for_write |= GVT_AUX_I2C_REPLY_ACK << 24; 533 vgpu_vreg(vgpu, offset + 4) = aux_data_for_write; 534 } 535 536 /** 537 * intel_vgpu_init_i2c_edid - initialize vGPU i2c edid emulation 538 * @vgpu: a vGPU 539 * 540 * This function is used to initialize vGPU i2c edid emulation stuffs 541 * 542 */ 543 void intel_vgpu_init_i2c_edid(struct intel_vgpu *vgpu) 544 { 545 struct intel_vgpu_i2c_edid *edid = &vgpu->display.i2c_edid; 546 547 edid->state = I2C_NOT_SPECIFIED; 548 549 edid->port = -1; 550 edid->slave_selected = false; 551 edid->edid_available = false; 552 edid->current_edid_read = 0; 553 554 memset(&edid->gmbus, 0, sizeof(struct intel_vgpu_i2c_gmbus)); 555 556 edid->aux_ch.i2c_over_aux_ch = false; 557 edid->aux_ch.aux_ch_mot = false; 558 } 559