1 /* 2 * Copyright 2017 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Zhiyuan Lv <zhiyuan.lv@intel.com> 25 * 26 * Contributors: 27 * Xiaoguang Chen 28 * Tina Zhang <tina.zhang@intel.com> 29 */ 30 31 #include <linux/dma-buf.h> 32 #include <drm/drmP.h> 33 #include <linux/vfio.h> 34 35 #include "i915_drv.h" 36 #include "gvt.h" 37 38 #define GEN8_DECODE_PTE(pte) (pte & GENMASK_ULL(63, 12)) 39 40 static int vgpu_gem_get_pages( 41 struct drm_i915_gem_object *obj) 42 { 43 struct drm_i915_private *dev_priv = to_i915(obj->base.dev); 44 struct sg_table *st; 45 struct scatterlist *sg; 46 int i, ret; 47 gen8_pte_t __iomem *gtt_entries; 48 struct intel_vgpu_fb_info *fb_info; 49 50 fb_info = (struct intel_vgpu_fb_info *)obj->gvt_info; 51 if (WARN_ON(!fb_info)) 52 return -ENODEV; 53 54 st = kmalloc(sizeof(*st), GFP_KERNEL); 55 if (unlikely(!st)) 56 return -ENOMEM; 57 58 ret = sg_alloc_table(st, fb_info->size, GFP_KERNEL); 59 if (ret) { 60 kfree(st); 61 return ret; 62 } 63 gtt_entries = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + 64 (fb_info->start >> PAGE_SHIFT); 65 for_each_sg(st->sgl, sg, fb_info->size, i) { 66 sg->offset = 0; 67 sg->length = PAGE_SIZE; 68 sg_dma_address(sg) = 69 GEN8_DECODE_PTE(readq(>t_entries[i])); 70 sg_dma_len(sg) = PAGE_SIZE; 71 } 72 73 __i915_gem_object_set_pages(obj, st, PAGE_SIZE); 74 75 return 0; 76 } 77 78 static void vgpu_gem_put_pages(struct drm_i915_gem_object *obj, 79 struct sg_table *pages) 80 { 81 sg_free_table(pages); 82 kfree(pages); 83 } 84 85 static void dmabuf_gem_object_free(struct kref *kref) 86 { 87 struct intel_vgpu_dmabuf_obj *obj = 88 container_of(kref, struct intel_vgpu_dmabuf_obj, kref); 89 struct intel_vgpu *vgpu = obj->vgpu; 90 struct list_head *pos; 91 struct intel_vgpu_dmabuf_obj *dmabuf_obj; 92 93 if (vgpu && vgpu->active && !list_empty(&vgpu->dmabuf_obj_list_head)) { 94 list_for_each(pos, &vgpu->dmabuf_obj_list_head) { 95 dmabuf_obj = container_of(pos, 96 struct intel_vgpu_dmabuf_obj, list); 97 if (dmabuf_obj == obj) { 98 intel_gvt_hypervisor_put_vfio_device(vgpu); 99 idr_remove(&vgpu->object_idr, 100 dmabuf_obj->dmabuf_id); 101 kfree(dmabuf_obj->info); 102 kfree(dmabuf_obj); 103 list_del(pos); 104 break; 105 } 106 } 107 } else { 108 /* Free the orphan dmabuf_objs here */ 109 kfree(obj->info); 110 kfree(obj); 111 } 112 } 113 114 115 static inline void dmabuf_obj_get(struct intel_vgpu_dmabuf_obj *obj) 116 { 117 kref_get(&obj->kref); 118 } 119 120 static inline void dmabuf_obj_put(struct intel_vgpu_dmabuf_obj *obj) 121 { 122 kref_put(&obj->kref, dmabuf_gem_object_free); 123 } 124 125 static void vgpu_gem_release(struct drm_i915_gem_object *gem_obj) 126 { 127 128 struct intel_vgpu_fb_info *fb_info = gem_obj->gvt_info; 129 struct intel_vgpu_dmabuf_obj *obj = fb_info->obj; 130 struct intel_vgpu *vgpu = obj->vgpu; 131 132 if (vgpu) { 133 mutex_lock(&vgpu->dmabuf_lock); 134 gem_obj->base.dma_buf = NULL; 135 dmabuf_obj_put(obj); 136 mutex_unlock(&vgpu->dmabuf_lock); 137 } else { 138 /* vgpu is NULL, as it has been removed already */ 139 gem_obj->base.dma_buf = NULL; 140 dmabuf_obj_put(obj); 141 } 142 } 143 144 static const struct drm_i915_gem_object_ops intel_vgpu_gem_ops = { 145 .flags = I915_GEM_OBJECT_IS_PROXY, 146 .get_pages = vgpu_gem_get_pages, 147 .put_pages = vgpu_gem_put_pages, 148 .release = vgpu_gem_release, 149 }; 150 151 static struct drm_i915_gem_object *vgpu_create_gem(struct drm_device *dev, 152 struct intel_vgpu_fb_info *info) 153 { 154 struct drm_i915_private *dev_priv = to_i915(dev); 155 struct drm_i915_gem_object *obj; 156 157 obj = i915_gem_object_alloc(dev_priv); 158 if (obj == NULL) 159 return NULL; 160 161 drm_gem_private_object_init(dev, &obj->base, 162 info->size << PAGE_SHIFT); 163 i915_gem_object_init(obj, &intel_vgpu_gem_ops); 164 165 obj->read_domains = I915_GEM_DOMAIN_GTT; 166 obj->write_domain = 0; 167 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { 168 unsigned int tiling_mode = 0; 169 unsigned int stride = 0; 170 171 switch (info->drm_format_mod << 10) { 172 case PLANE_CTL_TILED_LINEAR: 173 tiling_mode = I915_TILING_NONE; 174 break; 175 case PLANE_CTL_TILED_X: 176 tiling_mode = I915_TILING_X; 177 stride = info->stride; 178 break; 179 case PLANE_CTL_TILED_Y: 180 tiling_mode = I915_TILING_Y; 181 stride = info->stride; 182 break; 183 default: 184 gvt_dbg_core("not supported tiling mode\n"); 185 } 186 obj->tiling_and_stride = tiling_mode | stride; 187 } else { 188 obj->tiling_and_stride = info->drm_format_mod ? 189 I915_TILING_X : 0; 190 } 191 192 return obj; 193 } 194 195 static int vgpu_get_plane_info(struct drm_device *dev, 196 struct intel_vgpu *vgpu, 197 struct intel_vgpu_fb_info *info, 198 int plane_id) 199 { 200 struct drm_i915_private *dev_priv = to_i915(dev); 201 struct intel_vgpu_primary_plane_format p; 202 struct intel_vgpu_cursor_plane_format c; 203 int ret; 204 205 if (plane_id == DRM_PLANE_TYPE_PRIMARY) { 206 ret = intel_vgpu_decode_primary_plane(vgpu, &p); 207 if (ret) 208 return ret; 209 info->start = p.base; 210 info->start_gpa = p.base_gpa; 211 info->width = p.width; 212 info->height = p.height; 213 info->stride = p.stride; 214 info->drm_format = p.drm_format; 215 info->drm_format_mod = p.tiled; 216 info->size = (((p.stride * p.height * p.bpp) / 8) + 217 (PAGE_SIZE - 1)) >> PAGE_SHIFT; 218 } else if (plane_id == DRM_PLANE_TYPE_CURSOR) { 219 ret = intel_vgpu_decode_cursor_plane(vgpu, &c); 220 if (ret) 221 return ret; 222 info->start = c.base; 223 info->start_gpa = c.base_gpa; 224 info->width = c.width; 225 info->height = c.height; 226 info->stride = c.width * (c.bpp / 8); 227 info->drm_format = c.drm_format; 228 info->drm_format_mod = 0; 229 info->x_pos = c.x_pos; 230 info->y_pos = c.y_pos; 231 232 /* The invalid cursor hotspot value is delivered to host 233 * until we find a way to get the cursor hotspot info of 234 * guest OS. 235 */ 236 info->x_hot = UINT_MAX; 237 info->y_hot = UINT_MAX; 238 info->size = (((info->stride * c.height * c.bpp) / 8) 239 + (PAGE_SIZE - 1)) >> PAGE_SHIFT; 240 } else { 241 gvt_vgpu_err("invalid plane id:%d\n", plane_id); 242 return -EINVAL; 243 } 244 245 if (info->size == 0) { 246 gvt_vgpu_err("fb size is zero\n"); 247 return -EINVAL; 248 } 249 250 if (info->start & (PAGE_SIZE - 1)) { 251 gvt_vgpu_err("Not aligned fb address:0x%llx\n", info->start); 252 return -EFAULT; 253 } 254 if (((info->start >> PAGE_SHIFT) + info->size) > 255 ggtt_total_entries(&dev_priv->ggtt)) { 256 gvt_vgpu_err("Invalid GTT offset or size\n"); 257 return -EFAULT; 258 } 259 260 if (!intel_gvt_ggtt_validate_range(vgpu, info->start, info->size)) { 261 gvt_vgpu_err("invalid gma addr\n"); 262 return -EFAULT; 263 } 264 265 return 0; 266 } 267 268 static struct intel_vgpu_dmabuf_obj * 269 pick_dmabuf_by_info(struct intel_vgpu *vgpu, 270 struct intel_vgpu_fb_info *latest_info) 271 { 272 struct list_head *pos; 273 struct intel_vgpu_fb_info *fb_info; 274 struct intel_vgpu_dmabuf_obj *dmabuf_obj = NULL; 275 struct intel_vgpu_dmabuf_obj *ret = NULL; 276 277 list_for_each(pos, &vgpu->dmabuf_obj_list_head) { 278 dmabuf_obj = container_of(pos, struct intel_vgpu_dmabuf_obj, 279 list); 280 if ((dmabuf_obj == NULL) || 281 (dmabuf_obj->info == NULL)) 282 continue; 283 284 fb_info = (struct intel_vgpu_fb_info *)dmabuf_obj->info; 285 if ((fb_info->start == latest_info->start) && 286 (fb_info->start_gpa == latest_info->start_gpa) && 287 (fb_info->size == latest_info->size) && 288 (fb_info->drm_format_mod == latest_info->drm_format_mod) && 289 (fb_info->drm_format == latest_info->drm_format) && 290 (fb_info->width == latest_info->width) && 291 (fb_info->height == latest_info->height)) { 292 ret = dmabuf_obj; 293 break; 294 } 295 } 296 297 return ret; 298 } 299 300 static struct intel_vgpu_dmabuf_obj * 301 pick_dmabuf_by_num(struct intel_vgpu *vgpu, u32 id) 302 { 303 struct list_head *pos; 304 struct intel_vgpu_dmabuf_obj *dmabuf_obj = NULL; 305 struct intel_vgpu_dmabuf_obj *ret = NULL; 306 307 list_for_each(pos, &vgpu->dmabuf_obj_list_head) { 308 dmabuf_obj = container_of(pos, struct intel_vgpu_dmabuf_obj, 309 list); 310 if (!dmabuf_obj) 311 continue; 312 313 if (dmabuf_obj->dmabuf_id == id) { 314 ret = dmabuf_obj; 315 break; 316 } 317 } 318 319 return ret; 320 } 321 322 static void update_fb_info(struct vfio_device_gfx_plane_info *gvt_dmabuf, 323 struct intel_vgpu_fb_info *fb_info) 324 { 325 gvt_dmabuf->drm_format = fb_info->drm_format; 326 gvt_dmabuf->drm_format_mod = fb_info->drm_format_mod; 327 gvt_dmabuf->width = fb_info->width; 328 gvt_dmabuf->height = fb_info->height; 329 gvt_dmabuf->stride = fb_info->stride; 330 gvt_dmabuf->size = fb_info->size; 331 gvt_dmabuf->x_pos = fb_info->x_pos; 332 gvt_dmabuf->y_pos = fb_info->y_pos; 333 gvt_dmabuf->x_hot = fb_info->x_hot; 334 gvt_dmabuf->y_hot = fb_info->y_hot; 335 } 336 337 int intel_vgpu_query_plane(struct intel_vgpu *vgpu, void *args) 338 { 339 struct drm_device *dev = &vgpu->gvt->dev_priv->drm; 340 struct vfio_device_gfx_plane_info *gfx_plane_info = args; 341 struct intel_vgpu_dmabuf_obj *dmabuf_obj; 342 struct intel_vgpu_fb_info fb_info; 343 int ret = 0; 344 345 if (gfx_plane_info->flags == (VFIO_GFX_PLANE_TYPE_DMABUF | 346 VFIO_GFX_PLANE_TYPE_PROBE)) 347 return ret; 348 else if ((gfx_plane_info->flags & ~VFIO_GFX_PLANE_TYPE_DMABUF) || 349 (!gfx_plane_info->flags)) 350 return -EINVAL; 351 352 ret = vgpu_get_plane_info(dev, vgpu, &fb_info, 353 gfx_plane_info->drm_plane_type); 354 if (ret != 0) 355 goto out; 356 357 mutex_lock(&vgpu->dmabuf_lock); 358 /* If exists, pick up the exposed dmabuf_obj */ 359 dmabuf_obj = pick_dmabuf_by_info(vgpu, &fb_info); 360 if (dmabuf_obj) { 361 update_fb_info(gfx_plane_info, &fb_info); 362 gfx_plane_info->dmabuf_id = dmabuf_obj->dmabuf_id; 363 364 /* This buffer may be released between query_plane ioctl and 365 * get_dmabuf ioctl. Add the refcount to make sure it won't 366 * be released between the two ioctls. 367 */ 368 if (!dmabuf_obj->initref) { 369 dmabuf_obj->initref = true; 370 dmabuf_obj_get(dmabuf_obj); 371 } 372 ret = 0; 373 gvt_dbg_dpy("vgpu%d: re-use dmabuf_obj ref %d, id %d\n", 374 vgpu->id, kref_read(&dmabuf_obj->kref), 375 gfx_plane_info->dmabuf_id); 376 mutex_unlock(&vgpu->dmabuf_lock); 377 goto out; 378 } 379 380 mutex_unlock(&vgpu->dmabuf_lock); 381 382 /* Need to allocate a new one*/ 383 dmabuf_obj = kmalloc(sizeof(struct intel_vgpu_dmabuf_obj), GFP_KERNEL); 384 if (unlikely(!dmabuf_obj)) { 385 gvt_vgpu_err("alloc dmabuf_obj failed\n"); 386 ret = -ENOMEM; 387 goto out; 388 } 389 390 dmabuf_obj->info = kmalloc(sizeof(struct intel_vgpu_fb_info), 391 GFP_KERNEL); 392 if (unlikely(!dmabuf_obj->info)) { 393 gvt_vgpu_err("allocate intel vgpu fb info failed\n"); 394 ret = -ENOMEM; 395 goto out_free_dmabuf; 396 } 397 memcpy(dmabuf_obj->info, &fb_info, sizeof(struct intel_vgpu_fb_info)); 398 399 ((struct intel_vgpu_fb_info *)dmabuf_obj->info)->obj = dmabuf_obj; 400 401 dmabuf_obj->vgpu = vgpu; 402 403 ret = idr_alloc(&vgpu->object_idr, dmabuf_obj, 1, 0, GFP_NOWAIT); 404 if (ret < 0) 405 goto out_free_info; 406 gfx_plane_info->dmabuf_id = ret; 407 dmabuf_obj->dmabuf_id = ret; 408 409 dmabuf_obj->initref = true; 410 411 kref_init(&dmabuf_obj->kref); 412 413 mutex_lock(&vgpu->dmabuf_lock); 414 if (intel_gvt_hypervisor_get_vfio_device(vgpu)) { 415 gvt_vgpu_err("get vfio device failed\n"); 416 mutex_unlock(&vgpu->dmabuf_lock); 417 goto out_free_info; 418 } 419 mutex_unlock(&vgpu->dmabuf_lock); 420 421 update_fb_info(gfx_plane_info, &fb_info); 422 423 INIT_LIST_HEAD(&dmabuf_obj->list); 424 mutex_lock(&vgpu->dmabuf_lock); 425 list_add_tail(&dmabuf_obj->list, &vgpu->dmabuf_obj_list_head); 426 mutex_unlock(&vgpu->dmabuf_lock); 427 428 gvt_dbg_dpy("vgpu%d: %s new dmabuf_obj ref %d, id %d\n", vgpu->id, 429 __func__, kref_read(&dmabuf_obj->kref), ret); 430 431 return 0; 432 433 out_free_info: 434 kfree(dmabuf_obj->info); 435 out_free_dmabuf: 436 kfree(dmabuf_obj); 437 out: 438 /* ENODEV means plane isn't ready, which might be a normal case. */ 439 return (ret == -ENODEV) ? 0 : ret; 440 } 441 442 /* To associate an exposed dmabuf with the dmabuf_obj */ 443 int intel_vgpu_get_dmabuf(struct intel_vgpu *vgpu, unsigned int dmabuf_id) 444 { 445 struct drm_device *dev = &vgpu->gvt->dev_priv->drm; 446 struct intel_vgpu_dmabuf_obj *dmabuf_obj; 447 struct drm_i915_gem_object *obj; 448 struct dma_buf *dmabuf; 449 int dmabuf_fd; 450 int ret = 0; 451 452 mutex_lock(&vgpu->dmabuf_lock); 453 454 dmabuf_obj = pick_dmabuf_by_num(vgpu, dmabuf_id); 455 if (dmabuf_obj == NULL) { 456 gvt_vgpu_err("invalid dmabuf id:%d\n", dmabuf_id); 457 ret = -EINVAL; 458 goto out; 459 } 460 461 obj = vgpu_create_gem(dev, dmabuf_obj->info); 462 if (obj == NULL) { 463 gvt_vgpu_err("create gvt gem obj failed\n"); 464 ret = -ENOMEM; 465 goto out; 466 } 467 468 obj->gvt_info = dmabuf_obj->info; 469 470 dmabuf = i915_gem_prime_export(dev, &obj->base, DRM_CLOEXEC | DRM_RDWR); 471 if (IS_ERR(dmabuf)) { 472 gvt_vgpu_err("export dma-buf failed\n"); 473 ret = PTR_ERR(dmabuf); 474 goto out_free_gem; 475 } 476 477 i915_gem_object_put(obj); 478 479 ret = dma_buf_fd(dmabuf, DRM_CLOEXEC | DRM_RDWR); 480 if (ret < 0) { 481 gvt_vgpu_err("create dma-buf fd failed ret:%d\n", ret); 482 goto out_free_dmabuf; 483 } 484 dmabuf_fd = ret; 485 486 dmabuf_obj_get(dmabuf_obj); 487 488 if (dmabuf_obj->initref) { 489 dmabuf_obj->initref = false; 490 dmabuf_obj_put(dmabuf_obj); 491 } 492 493 mutex_unlock(&vgpu->dmabuf_lock); 494 495 gvt_dbg_dpy("vgpu%d: dmabuf:%d, dmabuf ref %d, fd:%d\n" 496 " file count: %ld, GEM ref: %d\n", 497 vgpu->id, dmabuf_obj->dmabuf_id, 498 kref_read(&dmabuf_obj->kref), 499 dmabuf_fd, 500 file_count(dmabuf->file), 501 kref_read(&obj->base.refcount)); 502 503 return dmabuf_fd; 504 505 out_free_dmabuf: 506 dma_buf_put(dmabuf); 507 out_free_gem: 508 i915_gem_object_put(obj); 509 out: 510 mutex_unlock(&vgpu->dmabuf_lock); 511 return ret; 512 } 513 514 void intel_vgpu_dmabuf_cleanup(struct intel_vgpu *vgpu) 515 { 516 struct list_head *pos, *n; 517 struct intel_vgpu_dmabuf_obj *dmabuf_obj; 518 519 mutex_lock(&vgpu->dmabuf_lock); 520 list_for_each_safe(pos, n, &vgpu->dmabuf_obj_list_head) { 521 dmabuf_obj = container_of(pos, struct intel_vgpu_dmabuf_obj, 522 list); 523 dmabuf_obj->vgpu = NULL; 524 525 idr_remove(&vgpu->object_idr, dmabuf_obj->dmabuf_id); 526 intel_gvt_hypervisor_put_vfio_device(vgpu); 527 list_del(pos); 528 529 /* dmabuf_obj might be freed in dmabuf_obj_put */ 530 if (dmabuf_obj->initref) { 531 dmabuf_obj->initref = false; 532 dmabuf_obj_put(dmabuf_obj); 533 } 534 535 } 536 mutex_unlock(&vgpu->dmabuf_lock); 537 } 538