1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Ke Yu 25 * Zhiyuan Lv <zhiyuan.lv@intel.com> 26 * 27 * Contributors: 28 * Terrence Xu <terrence.xu@intel.com> 29 * Changbin Du <changbin.du@intel.com> 30 * Bing Niu <bing.niu@intel.com> 31 * Zhi Wang <zhi.a.wang@intel.com> 32 * 33 */ 34 35 #include "i915_drv.h" 36 #include "gvt.h" 37 38 static int get_edp_pipe(struct intel_vgpu *vgpu) 39 { 40 u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP); 41 int pipe = -1; 42 43 switch (data & TRANS_DDI_EDP_INPUT_MASK) { 44 case TRANS_DDI_EDP_INPUT_A_ON: 45 case TRANS_DDI_EDP_INPUT_A_ONOFF: 46 pipe = PIPE_A; 47 break; 48 case TRANS_DDI_EDP_INPUT_B_ONOFF: 49 pipe = PIPE_B; 50 break; 51 case TRANS_DDI_EDP_INPUT_C_ONOFF: 52 pipe = PIPE_C; 53 break; 54 } 55 return pipe; 56 } 57 58 static int edp_pipe_is_enabled(struct intel_vgpu *vgpu) 59 { 60 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 61 62 if (!(vgpu_vreg_t(vgpu, PIPECONF(_PIPE_EDP)) & PIPECONF_ENABLE)) 63 return 0; 64 65 if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE)) 66 return 0; 67 return 1; 68 } 69 70 int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe) 71 { 72 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 73 74 if (drm_WARN_ON(&dev_priv->drm, 75 pipe < PIPE_A || pipe >= I915_MAX_PIPES)) 76 return -EINVAL; 77 78 if (vgpu_vreg_t(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE) 79 return 1; 80 81 if (edp_pipe_is_enabled(vgpu) && 82 get_edp_pipe(vgpu) == pipe) 83 return 1; 84 return 0; 85 } 86 87 static unsigned char virtual_dp_monitor_edid[GVT_EDID_NUM][EDID_SIZE] = { 88 { 89 /* EDID with 1024x768 as its resolution */ 90 /*Header*/ 91 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 92 /* Vendor & Product Identification */ 93 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17, 94 /* Version & Revision */ 95 0x01, 0x04, 96 /* Basic Display Parameters & Features */ 97 0xa5, 0x34, 0x20, 0x78, 0x23, 98 /* Color Characteristics */ 99 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54, 100 /* Established Timings: maximum resolution is 1024x768 */ 101 0x21, 0x08, 0x00, 102 /* Standard Timings. All invalid */ 103 0x00, 0xc0, 0x00, 0xc0, 0x00, 0x40, 0x00, 0x80, 0x00, 0x00, 104 0x00, 0x40, 0x00, 0x00, 0x00, 0x01, 105 /* 18 Byte Data Blocks 1: invalid */ 106 0x00, 0x00, 0x80, 0xa0, 0x70, 0xb0, 107 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a, 108 /* 18 Byte Data Blocks 2: invalid */ 109 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a, 110 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 111 /* 18 Byte Data Blocks 3: invalid */ 112 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48, 113 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20, 114 /* 18 Byte Data Blocks 4: invalid */ 115 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30, 116 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20, 117 /* Extension Block Count */ 118 0x00, 119 /* Checksum */ 120 0xef, 121 }, 122 { 123 /* EDID with 1920x1200 as its resolution */ 124 /*Header*/ 125 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 126 /* Vendor & Product Identification */ 127 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17, 128 /* Version & Revision */ 129 0x01, 0x04, 130 /* Basic Display Parameters & Features */ 131 0xa5, 0x34, 0x20, 0x78, 0x23, 132 /* Color Characteristics */ 133 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54, 134 /* Established Timings: maximum resolution is 1024x768 */ 135 0x21, 0x08, 0x00, 136 /* 137 * Standard Timings. 138 * below new resolutions can be supported: 139 * 1920x1080, 1280x720, 1280x960, 1280x1024, 140 * 1440x900, 1600x1200, 1680x1050 141 */ 142 0xd1, 0xc0, 0x81, 0xc0, 0x81, 0x40, 0x81, 0x80, 0x95, 0x00, 143 0xa9, 0x40, 0xb3, 0x00, 0x01, 0x01, 144 /* 18 Byte Data Blocks 1: max resolution is 1920x1200 */ 145 0x28, 0x3c, 0x80, 0xa0, 0x70, 0xb0, 146 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a, 147 /* 18 Byte Data Blocks 2: invalid */ 148 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a, 149 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 150 /* 18 Byte Data Blocks 3: invalid */ 151 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48, 152 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20, 153 /* 18 Byte Data Blocks 4: invalid */ 154 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30, 155 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20, 156 /* Extension Block Count */ 157 0x00, 158 /* Checksum */ 159 0x45, 160 }, 161 }; 162 163 #define DPCD_HEADER_SIZE 0xb 164 165 /* let the virtual display supports DP1.2 */ 166 static u8 dpcd_fix_data[DPCD_HEADER_SIZE] = { 167 0x12, 0x014, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 168 }; 169 170 static void emulate_monitor_status_change(struct intel_vgpu *vgpu) 171 { 172 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 173 int pipe; 174 175 if (IS_BROXTON(dev_priv)) { 176 enum transcoder trans; 177 enum port port; 178 179 /* Clear PIPE, DDI, PHY, HPD before setting new */ 180 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= 181 ~(GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | 182 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | 183 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C)); 184 185 for_each_pipe(dev_priv, pipe) { 186 vgpu_vreg_t(vgpu, PIPECONF(pipe)) &= 187 ~(PIPECONF_ENABLE | I965_PIPECONF_ACTIVE); 188 vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE; 189 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE; 190 vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE; 191 vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE; 192 } 193 194 for (trans = TRANSCODER_A; trans <= TRANSCODER_EDP; trans++) { 195 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(trans)) &= 196 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 197 TRANS_DDI_PORT_MASK | TRANS_DDI_FUNC_ENABLE); 198 } 199 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &= 200 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 201 TRANS_DDI_PORT_MASK); 202 203 for (port = PORT_A; port <= PORT_C; port++) { 204 vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) &= 205 ~BXT_PHY_LANE_ENABLED; 206 vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) |= 207 (BXT_PHY_CMNLANE_POWERDOWN_ACK | 208 BXT_PHY_LANE_POWERDOWN_ACK); 209 210 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(port)) &= 211 ~(PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE | 212 PORT_PLL_REF_SEL | PORT_PLL_LOCK | 213 PORT_PLL_ENABLE); 214 215 vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) &= 216 ~(DDI_INIT_DISPLAY_DETECTED | 217 DDI_BUF_CTL_ENABLE); 218 vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) |= DDI_BUF_IS_IDLE; 219 } 220 221 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &= ~(BIT(0) | BIT(1)); 222 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &= 223 ~PHY_POWER_GOOD; 224 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &= 225 ~PHY_POWER_GOOD; 226 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &= ~BIT(30); 227 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &= ~BIT(30); 228 229 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIB_DETECTED; 230 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIC_DETECTED; 231 232 /* 233 * Only 1 PIPE enabled in current vGPU display and PIPE_A is 234 * tied to TRANSCODER_A in HW, so it's safe to assume PIPE_A, 235 * TRANSCODER_A can be enabled. PORT_x depends on the input of 236 * setup_virtual_dp_monitor. 237 */ 238 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE; 239 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= I965_PIPECONF_ACTIVE; 240 241 /* 242 * Golden M/N are calculated based on: 243 * 24 bpp, 4 lanes, 154000 pixel clk (from virtual EDID), 244 * DP link clk 1620 MHz and non-constant_n. 245 * TODO: calculate DP link symbol clk and stream clk m/n. 246 */ 247 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = 63 << TU_SIZE_SHIFT; 248 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e; 249 vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000; 250 vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e; 251 vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000; 252 253 /* Enable per-DDI/PORT vreg */ 254 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { 255 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(1); 256 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |= 257 PHY_POWER_GOOD; 258 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) |= 259 BIT(30); 260 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |= 261 BXT_PHY_LANE_ENABLED; 262 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &= 263 ~(BXT_PHY_CMNLANE_POWERDOWN_ACK | 264 BXT_PHY_LANE_POWERDOWN_ACK); 265 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_A)) |= 266 (PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE | 267 PORT_PLL_REF_SEL | PORT_PLL_LOCK | 268 PORT_PLL_ENABLE); 269 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= 270 (DDI_BUF_CTL_ENABLE | DDI_INIT_DISPLAY_DETECTED); 271 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) &= 272 ~DDI_BUF_IS_IDLE; 273 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)) |= 274 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 275 TRANS_DDI_FUNC_ENABLE); 276 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 277 GEN8_DE_PORT_HOTPLUG(HPD_PORT_A); 278 } 279 280 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) { 281 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED; 282 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0); 283 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |= 284 PHY_POWER_GOOD; 285 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |= 286 BIT(30); 287 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |= 288 BXT_PHY_LANE_ENABLED; 289 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &= 290 ~(BXT_PHY_CMNLANE_POWERDOWN_ACK | 291 BXT_PHY_LANE_POWERDOWN_ACK); 292 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_B)) |= 293 (PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE | 294 PORT_PLL_REF_SEL | PORT_PLL_LOCK | 295 PORT_PLL_ENABLE); 296 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= 297 DDI_BUF_CTL_ENABLE; 298 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= 299 ~DDI_BUF_IS_IDLE; 300 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= 301 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 302 (PORT_B << TRANS_DDI_PORT_SHIFT) | 303 TRANS_DDI_FUNC_ENABLE); 304 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 305 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B); 306 } 307 308 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) { 309 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED; 310 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0); 311 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |= 312 PHY_POWER_GOOD; 313 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |= 314 BIT(30); 315 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |= 316 BXT_PHY_LANE_ENABLED; 317 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) &= 318 ~(BXT_PHY_CMNLANE_POWERDOWN_ACK | 319 BXT_PHY_LANE_POWERDOWN_ACK); 320 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_C)) |= 321 (PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE | 322 PORT_PLL_REF_SEL | PORT_PLL_LOCK | 323 PORT_PLL_ENABLE); 324 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= 325 DDI_BUF_CTL_ENABLE; 326 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= 327 ~DDI_BUF_IS_IDLE; 328 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= 329 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 330 (PORT_B << TRANS_DDI_PORT_SHIFT) | 331 TRANS_DDI_FUNC_ENABLE); 332 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 333 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C); 334 } 335 336 return; 337 } 338 339 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT | 340 SDE_PORTC_HOTPLUG_CPT | 341 SDE_PORTD_HOTPLUG_CPT); 342 343 if (IS_SKYLAKE(dev_priv) || 344 IS_KABYLAKE(dev_priv) || 345 IS_COFFEELAKE(dev_priv) || 346 IS_COMETLAKE(dev_priv)) { 347 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT | 348 SDE_PORTE_HOTPLUG_SPT); 349 vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |= 350 SKL_FUSE_DOWNLOAD_STATUS | 351 SKL_FUSE_PG_DIST_STATUS(SKL_PG0) | 352 SKL_FUSE_PG_DIST_STATUS(SKL_PG1) | 353 SKL_FUSE_PG_DIST_STATUS(SKL_PG2); 354 /* 355 * Only 1 PIPE enabled in current vGPU display and PIPE_A is 356 * tied to TRANSCODER_A in HW, so it's safe to assume PIPE_A, 357 * TRANSCODER_A can be enabled. PORT_x depends on the input of 358 * setup_virtual_dp_monitor, we can bind DPLL0 to any PORT_x 359 * so we fixed to DPLL0 here. 360 * Setup DPLL0: DP link clk 1620 MHz, non SSC, DP Mode 361 */ 362 vgpu_vreg_t(vgpu, DPLL_CTRL1) = 363 DPLL_CTRL1_OVERRIDE(DPLL_ID_SKL_DPLL0); 364 vgpu_vreg_t(vgpu, DPLL_CTRL1) |= 365 DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, DPLL_ID_SKL_DPLL0); 366 vgpu_vreg_t(vgpu, LCPLL1_CTL) = 367 LCPLL_PLL_ENABLE | LCPLL_PLL_LOCK; 368 vgpu_vreg_t(vgpu, DPLL_STATUS) = DPLL_LOCK(DPLL_ID_SKL_DPLL0); 369 /* 370 * Golden M/N are calculated based on: 371 * 24 bpp, 4 lanes, 154000 pixel clk (from virtual EDID), 372 * DP link clk 1620 MHz and non-constant_n. 373 * TODO: calculate DP link symbol clk and stream clk m/n. 374 */ 375 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = 63 << TU_SIZE_SHIFT; 376 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e; 377 vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000; 378 vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e; 379 vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000; 380 } 381 382 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) { 383 vgpu_vreg_t(vgpu, DPLL_CTRL2) &= 384 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_B); 385 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 386 DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_B); 387 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 388 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_B); 389 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED; 390 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &= 391 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 392 TRANS_DDI_PORT_MASK); 393 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= 394 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 395 (PORT_B << TRANS_DDI_PORT_SHIFT) | 396 TRANS_DDI_FUNC_ENABLE); 397 if (IS_BROADWELL(dev_priv)) { 398 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) &= 399 ~PORT_CLK_SEL_MASK; 400 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) |= 401 PORT_CLK_SEL_LCPLL_810; 402 } 403 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE; 404 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE; 405 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT; 406 } 407 408 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) { 409 vgpu_vreg_t(vgpu, DPLL_CTRL2) &= 410 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_C); 411 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 412 DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_C); 413 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 414 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_C); 415 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT; 416 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &= 417 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 418 TRANS_DDI_PORT_MASK); 419 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= 420 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 421 (PORT_C << TRANS_DDI_PORT_SHIFT) | 422 TRANS_DDI_FUNC_ENABLE); 423 if (IS_BROADWELL(dev_priv)) { 424 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) &= 425 ~PORT_CLK_SEL_MASK; 426 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) |= 427 PORT_CLK_SEL_LCPLL_810; 428 } 429 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE; 430 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE; 431 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED; 432 } 433 434 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D)) { 435 vgpu_vreg_t(vgpu, DPLL_CTRL2) &= 436 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_D); 437 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 438 DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_D); 439 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 440 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_D); 441 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT; 442 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &= 443 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 444 TRANS_DDI_PORT_MASK); 445 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= 446 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 447 (PORT_D << TRANS_DDI_PORT_SHIFT) | 448 TRANS_DDI_FUNC_ENABLE); 449 if (IS_BROADWELL(dev_priv)) { 450 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) &= 451 ~PORT_CLK_SEL_MASK; 452 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) |= 453 PORT_CLK_SEL_LCPLL_810; 454 } 455 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE; 456 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE; 457 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED; 458 } 459 460 if ((IS_SKYLAKE(dev_priv) || 461 IS_KABYLAKE(dev_priv) || 462 IS_COFFEELAKE(dev_priv) || 463 IS_COMETLAKE(dev_priv)) && 464 intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) { 465 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT; 466 } 467 468 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { 469 if (IS_BROADWELL(dev_priv)) 470 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 471 GEN8_DE_PORT_HOTPLUG(HPD_PORT_A); 472 else 473 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT; 474 475 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED; 476 } 477 478 /* Clear host CRT status, so guest couldn't detect this host CRT. */ 479 if (IS_BROADWELL(dev_priv)) 480 vgpu_vreg_t(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK; 481 482 /* Disable Primary/Sprite/Cursor plane */ 483 for_each_pipe(dev_priv, pipe) { 484 vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE; 485 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE; 486 vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE; 487 vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE; 488 } 489 490 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE; 491 } 492 493 static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num) 494 { 495 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num); 496 497 kfree(port->edid); 498 port->edid = NULL; 499 500 kfree(port->dpcd); 501 port->dpcd = NULL; 502 } 503 504 static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num, 505 int type, unsigned int resolution) 506 { 507 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 508 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num); 509 510 if (drm_WARN_ON(&i915->drm, resolution >= GVT_EDID_NUM)) 511 return -EINVAL; 512 513 port->edid = kzalloc(sizeof(*(port->edid)), GFP_KERNEL); 514 if (!port->edid) 515 return -ENOMEM; 516 517 port->dpcd = kzalloc(sizeof(*(port->dpcd)), GFP_KERNEL); 518 if (!port->dpcd) { 519 kfree(port->edid); 520 return -ENOMEM; 521 } 522 523 memcpy(port->edid->edid_block, virtual_dp_monitor_edid[resolution], 524 EDID_SIZE); 525 port->edid->data_valid = true; 526 527 memcpy(port->dpcd->data, dpcd_fix_data, DPCD_HEADER_SIZE); 528 port->dpcd->data_valid = true; 529 port->dpcd->data[DPCD_SINK_COUNT] = 0x1; 530 port->type = type; 531 port->id = resolution; 532 533 emulate_monitor_status_change(vgpu); 534 535 return 0; 536 } 537 538 /** 539 * intel_gvt_check_vblank_emulation - check if vblank emulation timer should 540 * be turned on/off when a virtual pipe is enabled/disabled. 541 * @gvt: a GVT device 542 * 543 * This function is used to turn on/off vblank timer according to currently 544 * enabled/disabled virtual pipes. 545 * 546 */ 547 void intel_gvt_check_vblank_emulation(struct intel_gvt *gvt) 548 { 549 struct intel_gvt_irq *irq = &gvt->irq; 550 struct intel_vgpu *vgpu; 551 int pipe, id; 552 int found = false; 553 554 mutex_lock(&gvt->lock); 555 for_each_active_vgpu(gvt, vgpu, id) { 556 for (pipe = 0; pipe < I915_MAX_PIPES; pipe++) { 557 if (pipe_is_enabled(vgpu, pipe)) { 558 found = true; 559 break; 560 } 561 } 562 if (found) 563 break; 564 } 565 566 /* all the pipes are disabled */ 567 if (!found) 568 hrtimer_cancel(&irq->vblank_timer.timer); 569 else 570 hrtimer_start(&irq->vblank_timer.timer, 571 ktime_add_ns(ktime_get(), irq->vblank_timer.period), 572 HRTIMER_MODE_ABS); 573 mutex_unlock(&gvt->lock); 574 } 575 576 static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe) 577 { 578 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 579 struct intel_vgpu_irq *irq = &vgpu->irq; 580 int vblank_event[] = { 581 [PIPE_A] = PIPE_A_VBLANK, 582 [PIPE_B] = PIPE_B_VBLANK, 583 [PIPE_C] = PIPE_C_VBLANK, 584 }; 585 int event; 586 587 if (pipe < PIPE_A || pipe > PIPE_C) 588 return; 589 590 for_each_set_bit(event, irq->flip_done_event[pipe], 591 INTEL_GVT_EVENT_MAX) { 592 clear_bit(event, irq->flip_done_event[pipe]); 593 if (!pipe_is_enabled(vgpu, pipe)) 594 continue; 595 596 intel_vgpu_trigger_virtual_event(vgpu, event); 597 } 598 599 if (pipe_is_enabled(vgpu, pipe)) { 600 vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(pipe))++; 601 intel_vgpu_trigger_virtual_event(vgpu, vblank_event[pipe]); 602 } 603 } 604 605 static void emulate_vblank(struct intel_vgpu *vgpu) 606 { 607 int pipe; 608 609 mutex_lock(&vgpu->vgpu_lock); 610 for_each_pipe(vgpu->gvt->gt->i915, pipe) 611 emulate_vblank_on_pipe(vgpu, pipe); 612 mutex_unlock(&vgpu->vgpu_lock); 613 } 614 615 /** 616 * intel_gvt_emulate_vblank - trigger vblank events for vGPUs on GVT device 617 * @gvt: a GVT device 618 * 619 * This function is used to trigger vblank interrupts for vGPUs on GVT device 620 * 621 */ 622 void intel_gvt_emulate_vblank(struct intel_gvt *gvt) 623 { 624 struct intel_vgpu *vgpu; 625 int id; 626 627 mutex_lock(&gvt->lock); 628 for_each_active_vgpu(gvt, vgpu, id) 629 emulate_vblank(vgpu); 630 mutex_unlock(&gvt->lock); 631 } 632 633 /** 634 * intel_vgpu_emulate_hotplug - trigger hotplug event for vGPU 635 * @vgpu: a vGPU 636 * @connected: link state 637 * 638 * This function is used to trigger hotplug interrupt for vGPU 639 * 640 */ 641 void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected) 642 { 643 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 644 645 /* TODO: add more platforms support */ 646 if (IS_SKYLAKE(i915) || 647 IS_KABYLAKE(i915) || 648 IS_COFFEELAKE(i915) || 649 IS_COMETLAKE(i915)) { 650 if (connected) { 651 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= 652 SFUSE_STRAP_DDID_DETECTED; 653 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT; 654 } else { 655 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= 656 ~SFUSE_STRAP_DDID_DETECTED; 657 vgpu_vreg_t(vgpu, SDEISR) &= ~SDE_PORTD_HOTPLUG_CPT; 658 } 659 vgpu_vreg_t(vgpu, SDEIIR) |= SDE_PORTD_HOTPLUG_CPT; 660 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= 661 PORTD_HOTPLUG_STATUS_MASK; 662 intel_vgpu_trigger_virtual_event(vgpu, DP_D_HOTPLUG); 663 } else if (IS_BROXTON(i915)) { 664 if (connected) { 665 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { 666 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 667 GEN8_DE_PORT_HOTPLUG(HPD_PORT_A); 668 } 669 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) { 670 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= 671 SFUSE_STRAP_DDIB_DETECTED; 672 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 673 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B); 674 } 675 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) { 676 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= 677 SFUSE_STRAP_DDIC_DETECTED; 678 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 679 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C); 680 } 681 } else { 682 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { 683 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= 684 ~GEN8_DE_PORT_HOTPLUG(HPD_PORT_A); 685 } 686 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) { 687 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= 688 ~SFUSE_STRAP_DDIB_DETECTED; 689 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= 690 ~GEN8_DE_PORT_HOTPLUG(HPD_PORT_B); 691 } 692 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) { 693 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= 694 ~SFUSE_STRAP_DDIC_DETECTED; 695 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= 696 ~GEN8_DE_PORT_HOTPLUG(HPD_PORT_C); 697 } 698 } 699 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= 700 PORTB_HOTPLUG_STATUS_MASK; 701 intel_vgpu_trigger_virtual_event(vgpu, DP_B_HOTPLUG); 702 } 703 } 704 705 /** 706 * intel_vgpu_clean_display - clean vGPU virtual display emulation 707 * @vgpu: a vGPU 708 * 709 * This function is used to clean vGPU virtual display emulation stuffs 710 * 711 */ 712 void intel_vgpu_clean_display(struct intel_vgpu *vgpu) 713 { 714 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 715 716 if (IS_SKYLAKE(dev_priv) || 717 IS_KABYLAKE(dev_priv) || 718 IS_COFFEELAKE(dev_priv) || 719 IS_COMETLAKE(dev_priv)) 720 clean_virtual_dp_monitor(vgpu, PORT_D); 721 else 722 clean_virtual_dp_monitor(vgpu, PORT_B); 723 } 724 725 /** 726 * intel_vgpu_init_display- initialize vGPU virtual display emulation 727 * @vgpu: a vGPU 728 * @resolution: resolution index for intel_vgpu_edid 729 * 730 * This function is used to initialize vGPU virtual display emulation stuffs 731 * 732 * Returns: 733 * Zero on success, negative error code if failed. 734 * 735 */ 736 int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution) 737 { 738 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 739 740 intel_vgpu_init_i2c_edid(vgpu); 741 742 if (IS_SKYLAKE(dev_priv) || 743 IS_KABYLAKE(dev_priv) || 744 IS_COFFEELAKE(dev_priv) || 745 IS_COMETLAKE(dev_priv)) 746 return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D, 747 resolution); 748 else 749 return setup_virtual_dp_monitor(vgpu, PORT_B, GVT_DP_B, 750 resolution); 751 } 752 753 /** 754 * intel_vgpu_reset_display- reset vGPU virtual display emulation 755 * @vgpu: a vGPU 756 * 757 * This function is used to reset vGPU virtual display emulation stuffs 758 * 759 */ 760 void intel_vgpu_reset_display(struct intel_vgpu *vgpu) 761 { 762 emulate_monitor_status_change(vgpu); 763 } 764