1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Ke Yu 25 * Zhiyuan Lv <zhiyuan.lv@intel.com> 26 * 27 * Contributors: 28 * Terrence Xu <terrence.xu@intel.com> 29 * Changbin Du <changbin.du@intel.com> 30 * Bing Niu <bing.niu@intel.com> 31 * Zhi Wang <zhi.a.wang@intel.com> 32 * 33 */ 34 35 #include "i915_drv.h" 36 #include "gvt.h" 37 38 static int get_edp_pipe(struct intel_vgpu *vgpu) 39 { 40 u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP); 41 int pipe = -1; 42 43 switch (data & TRANS_DDI_EDP_INPUT_MASK) { 44 case TRANS_DDI_EDP_INPUT_A_ON: 45 case TRANS_DDI_EDP_INPUT_A_ONOFF: 46 pipe = PIPE_A; 47 break; 48 case TRANS_DDI_EDP_INPUT_B_ONOFF: 49 pipe = PIPE_B; 50 break; 51 case TRANS_DDI_EDP_INPUT_C_ONOFF: 52 pipe = PIPE_C; 53 break; 54 } 55 return pipe; 56 } 57 58 static int edp_pipe_is_enabled(struct intel_vgpu *vgpu) 59 { 60 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 61 62 if (!(vgpu_vreg_t(vgpu, PIPECONF(_PIPE_EDP)) & PIPECONF_ENABLE)) 63 return 0; 64 65 if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE)) 66 return 0; 67 return 1; 68 } 69 70 int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe) 71 { 72 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 73 74 if (WARN_ON(pipe < PIPE_A || pipe >= I915_MAX_PIPES)) 75 return -EINVAL; 76 77 if (vgpu_vreg_t(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE) 78 return 1; 79 80 if (edp_pipe_is_enabled(vgpu) && 81 get_edp_pipe(vgpu) == pipe) 82 return 1; 83 return 0; 84 } 85 86 static unsigned char virtual_dp_monitor_edid[GVT_EDID_NUM][EDID_SIZE] = { 87 { 88 /* EDID with 1024x768 as its resolution */ 89 /*Header*/ 90 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 91 /* Vendor & Product Identification */ 92 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17, 93 /* Version & Revision */ 94 0x01, 0x04, 95 /* Basic Display Parameters & Features */ 96 0xa5, 0x34, 0x20, 0x78, 0x23, 97 /* Color Characteristics */ 98 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54, 99 /* Established Timings: maximum resolution is 1024x768 */ 100 0x21, 0x08, 0x00, 101 /* Standard Timings. All invalid */ 102 0x00, 0xc0, 0x00, 0xc0, 0x00, 0x40, 0x00, 0x80, 0x00, 0x00, 103 0x00, 0x40, 0x00, 0x00, 0x00, 0x01, 104 /* 18 Byte Data Blocks 1: invalid */ 105 0x00, 0x00, 0x80, 0xa0, 0x70, 0xb0, 106 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a, 107 /* 18 Byte Data Blocks 2: invalid */ 108 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a, 109 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 110 /* 18 Byte Data Blocks 3: invalid */ 111 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48, 112 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20, 113 /* 18 Byte Data Blocks 4: invalid */ 114 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30, 115 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20, 116 /* Extension Block Count */ 117 0x00, 118 /* Checksum */ 119 0xef, 120 }, 121 { 122 /* EDID with 1920x1200 as its resolution */ 123 /*Header*/ 124 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 125 /* Vendor & Product Identification */ 126 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17, 127 /* Version & Revision */ 128 0x01, 0x04, 129 /* Basic Display Parameters & Features */ 130 0xa5, 0x34, 0x20, 0x78, 0x23, 131 /* Color Characteristics */ 132 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54, 133 /* Established Timings: maximum resolution is 1024x768 */ 134 0x21, 0x08, 0x00, 135 /* 136 * Standard Timings. 137 * below new resolutions can be supported: 138 * 1920x1080, 1280x720, 1280x960, 1280x1024, 139 * 1440x900, 1600x1200, 1680x1050 140 */ 141 0xd1, 0xc0, 0x81, 0xc0, 0x81, 0x40, 0x81, 0x80, 0x95, 0x00, 142 0xa9, 0x40, 0xb3, 0x00, 0x01, 0x01, 143 /* 18 Byte Data Blocks 1: max resolution is 1920x1200 */ 144 0x28, 0x3c, 0x80, 0xa0, 0x70, 0xb0, 145 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a, 146 /* 18 Byte Data Blocks 2: invalid */ 147 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a, 148 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 149 /* 18 Byte Data Blocks 3: invalid */ 150 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48, 151 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20, 152 /* 18 Byte Data Blocks 4: invalid */ 153 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30, 154 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20, 155 /* Extension Block Count */ 156 0x00, 157 /* Checksum */ 158 0x45, 159 }, 160 }; 161 162 #define DPCD_HEADER_SIZE 0xb 163 164 /* let the virtual display supports DP1.2 */ 165 static u8 dpcd_fix_data[DPCD_HEADER_SIZE] = { 166 0x12, 0x014, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 167 }; 168 169 static void emulate_monitor_status_change(struct intel_vgpu *vgpu) 170 { 171 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 172 int pipe; 173 174 if (IS_BROXTON(dev_priv)) { 175 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~(BXT_DE_PORT_HP_DDIA | 176 BXT_DE_PORT_HP_DDIB | 177 BXT_DE_PORT_HP_DDIC); 178 179 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { 180 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 181 BXT_DE_PORT_HP_DDIA; 182 } 183 184 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) { 185 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 186 BXT_DE_PORT_HP_DDIB; 187 } 188 189 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) { 190 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 191 BXT_DE_PORT_HP_DDIC; 192 } 193 194 return; 195 } 196 197 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT | 198 SDE_PORTC_HOTPLUG_CPT | 199 SDE_PORTD_HOTPLUG_CPT); 200 201 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { 202 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT | 203 SDE_PORTE_HOTPLUG_SPT); 204 vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |= 205 SKL_FUSE_DOWNLOAD_STATUS | 206 SKL_FUSE_PG_DIST_STATUS(SKL_PG0) | 207 SKL_FUSE_PG_DIST_STATUS(SKL_PG1) | 208 SKL_FUSE_PG_DIST_STATUS(SKL_PG2); 209 vgpu_vreg_t(vgpu, LCPLL1_CTL) |= 210 LCPLL_PLL_ENABLE | 211 LCPLL_PLL_LOCK; 212 vgpu_vreg_t(vgpu, LCPLL2_CTL) |= LCPLL_PLL_ENABLE; 213 214 } 215 216 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) { 217 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED; 218 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &= 219 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 220 TRANS_DDI_PORT_MASK); 221 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= 222 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 223 (PORT_B << TRANS_DDI_PORT_SHIFT) | 224 TRANS_DDI_FUNC_ENABLE); 225 if (IS_BROADWELL(dev_priv)) { 226 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) &= 227 ~PORT_CLK_SEL_MASK; 228 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) |= 229 PORT_CLK_SEL_LCPLL_810; 230 } 231 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE; 232 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE; 233 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT; 234 } 235 236 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) { 237 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT; 238 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &= 239 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 240 TRANS_DDI_PORT_MASK); 241 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= 242 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 243 (PORT_C << TRANS_DDI_PORT_SHIFT) | 244 TRANS_DDI_FUNC_ENABLE); 245 if (IS_BROADWELL(dev_priv)) { 246 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) &= 247 ~PORT_CLK_SEL_MASK; 248 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) |= 249 PORT_CLK_SEL_LCPLL_810; 250 } 251 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE; 252 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE; 253 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED; 254 } 255 256 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D)) { 257 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT; 258 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &= 259 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 260 TRANS_DDI_PORT_MASK); 261 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= 262 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 263 (PORT_D << TRANS_DDI_PORT_SHIFT) | 264 TRANS_DDI_FUNC_ENABLE); 265 if (IS_BROADWELL(dev_priv)) { 266 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) &= 267 ~PORT_CLK_SEL_MASK; 268 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) |= 269 PORT_CLK_SEL_LCPLL_810; 270 } 271 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE; 272 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE; 273 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED; 274 } 275 276 if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) && 277 intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) { 278 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT; 279 } 280 281 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { 282 if (IS_BROADWELL(dev_priv)) 283 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 284 GEN8_PORT_DP_A_HOTPLUG; 285 else 286 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT; 287 288 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED; 289 } 290 291 /* Clear host CRT status, so guest couldn't detect this host CRT. */ 292 if (IS_BROADWELL(dev_priv)) 293 vgpu_vreg_t(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK; 294 295 /* Disable Primary/Sprite/Cursor plane */ 296 for_each_pipe(dev_priv, pipe) { 297 vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE; 298 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE; 299 vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE; 300 vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE; 301 } 302 303 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE; 304 } 305 306 static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num) 307 { 308 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num); 309 310 kfree(port->edid); 311 port->edid = NULL; 312 313 kfree(port->dpcd); 314 port->dpcd = NULL; 315 } 316 317 static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num, 318 int type, unsigned int resolution) 319 { 320 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num); 321 322 if (WARN_ON(resolution >= GVT_EDID_NUM)) 323 return -EINVAL; 324 325 port->edid = kzalloc(sizeof(*(port->edid)), GFP_KERNEL); 326 if (!port->edid) 327 return -ENOMEM; 328 329 port->dpcd = kzalloc(sizeof(*(port->dpcd)), GFP_KERNEL); 330 if (!port->dpcd) { 331 kfree(port->edid); 332 return -ENOMEM; 333 } 334 335 memcpy(port->edid->edid_block, virtual_dp_monitor_edid[resolution], 336 EDID_SIZE); 337 port->edid->data_valid = true; 338 339 memcpy(port->dpcd->data, dpcd_fix_data, DPCD_HEADER_SIZE); 340 port->dpcd->data_valid = true; 341 port->dpcd->data[DPCD_SINK_COUNT] = 0x1; 342 port->type = type; 343 344 emulate_monitor_status_change(vgpu); 345 346 return 0; 347 } 348 349 /** 350 * intel_gvt_check_vblank_emulation - check if vblank emulation timer should 351 * be turned on/off when a virtual pipe is enabled/disabled. 352 * @gvt: a GVT device 353 * 354 * This function is used to turn on/off vblank timer according to currently 355 * enabled/disabled virtual pipes. 356 * 357 */ 358 void intel_gvt_check_vblank_emulation(struct intel_gvt *gvt) 359 { 360 struct intel_gvt_irq *irq = &gvt->irq; 361 struct intel_vgpu *vgpu; 362 int pipe, id; 363 int found = false; 364 365 mutex_lock(&gvt->lock); 366 for_each_active_vgpu(gvt, vgpu, id) { 367 for (pipe = 0; pipe < I915_MAX_PIPES; pipe++) { 368 if (pipe_is_enabled(vgpu, pipe)) { 369 found = true; 370 break; 371 } 372 } 373 if (found) 374 break; 375 } 376 377 /* all the pipes are disabled */ 378 if (!found) 379 hrtimer_cancel(&irq->vblank_timer.timer); 380 else 381 hrtimer_start(&irq->vblank_timer.timer, 382 ktime_add_ns(ktime_get(), irq->vblank_timer.period), 383 HRTIMER_MODE_ABS); 384 mutex_unlock(&gvt->lock); 385 } 386 387 static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe) 388 { 389 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 390 struct intel_vgpu_irq *irq = &vgpu->irq; 391 int vblank_event[] = { 392 [PIPE_A] = PIPE_A_VBLANK, 393 [PIPE_B] = PIPE_B_VBLANK, 394 [PIPE_C] = PIPE_C_VBLANK, 395 }; 396 int event; 397 398 if (pipe < PIPE_A || pipe > PIPE_C) 399 return; 400 401 for_each_set_bit(event, irq->flip_done_event[pipe], 402 INTEL_GVT_EVENT_MAX) { 403 clear_bit(event, irq->flip_done_event[pipe]); 404 if (!pipe_is_enabled(vgpu, pipe)) 405 continue; 406 407 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++; 408 intel_vgpu_trigger_virtual_event(vgpu, event); 409 } 410 411 if (pipe_is_enabled(vgpu, pipe)) { 412 vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(pipe))++; 413 intel_vgpu_trigger_virtual_event(vgpu, vblank_event[pipe]); 414 } 415 } 416 417 static void emulate_vblank(struct intel_vgpu *vgpu) 418 { 419 int pipe; 420 421 mutex_lock(&vgpu->vgpu_lock); 422 for_each_pipe(vgpu->gvt->dev_priv, pipe) 423 emulate_vblank_on_pipe(vgpu, pipe); 424 mutex_unlock(&vgpu->vgpu_lock); 425 } 426 427 /** 428 * intel_gvt_emulate_vblank - trigger vblank events for vGPUs on GVT device 429 * @gvt: a GVT device 430 * 431 * This function is used to trigger vblank interrupts for vGPUs on GVT device 432 * 433 */ 434 void intel_gvt_emulate_vblank(struct intel_gvt *gvt) 435 { 436 struct intel_vgpu *vgpu; 437 int id; 438 439 mutex_lock(&gvt->lock); 440 for_each_active_vgpu(gvt, vgpu, id) 441 emulate_vblank(vgpu); 442 mutex_unlock(&gvt->lock); 443 } 444 445 /** 446 * intel_vgpu_clean_display - clean vGPU virtual display emulation 447 * @vgpu: a vGPU 448 * 449 * This function is used to clean vGPU virtual display emulation stuffs 450 * 451 */ 452 void intel_vgpu_clean_display(struct intel_vgpu *vgpu) 453 { 454 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 455 456 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) 457 clean_virtual_dp_monitor(vgpu, PORT_D); 458 else 459 clean_virtual_dp_monitor(vgpu, PORT_B); 460 } 461 462 /** 463 * intel_vgpu_init_display- initialize vGPU virtual display emulation 464 * @vgpu: a vGPU 465 * 466 * This function is used to initialize vGPU virtual display emulation stuffs 467 * 468 * Returns: 469 * Zero on success, negative error code if failed. 470 * 471 */ 472 int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution) 473 { 474 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 475 476 intel_vgpu_init_i2c_edid(vgpu); 477 478 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) 479 return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D, 480 resolution); 481 else 482 return setup_virtual_dp_monitor(vgpu, PORT_B, GVT_DP_B, 483 resolution); 484 } 485 486 /** 487 * intel_vgpu_reset_display- reset vGPU virtual display emulation 488 * @vgpu: a vGPU 489 * 490 * This function is used to reset vGPU virtual display emulation stuffs 491 * 492 */ 493 void intel_vgpu_reset_display(struct intel_vgpu *vgpu) 494 { 495 emulate_monitor_status_change(vgpu); 496 } 497