xref: /openbmc/linux/drivers/gpu/drm/i915/gvt/display.c (revision 5d0e4d78)
1 /*
2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21  * SOFTWARE.
22  *
23  * Authors:
24  *    Ke Yu
25  *    Zhiyuan Lv <zhiyuan.lv@intel.com>
26  *
27  * Contributors:
28  *    Terrence Xu <terrence.xu@intel.com>
29  *    Changbin Du <changbin.du@intel.com>
30  *    Bing Niu <bing.niu@intel.com>
31  *    Zhi Wang <zhi.a.wang@intel.com>
32  *
33  */
34 
35 #include "i915_drv.h"
36 #include "gvt.h"
37 
38 static int get_edp_pipe(struct intel_vgpu *vgpu)
39 {
40 	u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP);
41 	int pipe = -1;
42 
43 	switch (data & TRANS_DDI_EDP_INPUT_MASK) {
44 	case TRANS_DDI_EDP_INPUT_A_ON:
45 	case TRANS_DDI_EDP_INPUT_A_ONOFF:
46 		pipe = PIPE_A;
47 		break;
48 	case TRANS_DDI_EDP_INPUT_B_ONOFF:
49 		pipe = PIPE_B;
50 		break;
51 	case TRANS_DDI_EDP_INPUT_C_ONOFF:
52 		pipe = PIPE_C;
53 		break;
54 	}
55 	return pipe;
56 }
57 
58 static int edp_pipe_is_enabled(struct intel_vgpu *vgpu)
59 {
60 	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
61 
62 	if (!(vgpu_vreg(vgpu, PIPECONF(_PIPE_EDP)) & PIPECONF_ENABLE))
63 		return 0;
64 
65 	if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE))
66 		return 0;
67 	return 1;
68 }
69 
70 static int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe)
71 {
72 	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
73 
74 	if (WARN_ON(pipe < PIPE_A || pipe >= I915_MAX_PIPES))
75 		return -EINVAL;
76 
77 	if (vgpu_vreg(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE)
78 		return 1;
79 
80 	if (edp_pipe_is_enabled(vgpu) &&
81 			get_edp_pipe(vgpu) == pipe)
82 		return 1;
83 	return 0;
84 }
85 
86 static unsigned char virtual_dp_monitor_edid[GVT_EDID_NUM][EDID_SIZE] = {
87 	{
88 /* EDID with 1024x768 as its resolution */
89 		/*Header*/
90 		0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
91 		/* Vendor & Product Identification */
92 		0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17,
93 		/* Version & Revision */
94 		0x01, 0x04,
95 		/* Basic Display Parameters & Features */
96 		0xa5, 0x34, 0x20, 0x78, 0x23,
97 		/* Color Characteristics */
98 		0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54,
99 		/* Established Timings: maximum resolution is 1024x768 */
100 		0x21, 0x08, 0x00,
101 		/* Standard Timings. All invalid */
102 		0x00, 0xc0, 0x00, 0xc0, 0x00, 0x40, 0x00, 0x80, 0x00, 0x00,
103 		0x00, 0x40, 0x00, 0x00, 0x00, 0x01,
104 		/* 18 Byte Data Blocks 1: invalid */
105 		0x00, 0x00, 0x80, 0xa0, 0x70, 0xb0,
106 		0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a,
107 		/* 18 Byte Data Blocks 2: invalid */
108 		0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a,
109 		0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
110 		/* 18 Byte Data Blocks 3: invalid */
111 		0x00, 0x00, 0x00, 0xfc, 0x00, 0x48,
112 		0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20,
113 		/* 18 Byte Data Blocks 4: invalid */
114 		0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30,
115 		0x44, 0x58, 0x51, 0x0a, 0x20, 0x20,
116 		/* Extension Block Count */
117 		0x00,
118 		/* Checksum */
119 		0xef,
120 	},
121 	{
122 /* EDID with 1920x1200 as its resolution */
123 		/*Header*/
124 		0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
125 		/* Vendor & Product Identification */
126 		0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17,
127 		/* Version & Revision */
128 		0x01, 0x04,
129 		/* Basic Display Parameters & Features */
130 		0xa5, 0x34, 0x20, 0x78, 0x23,
131 		/* Color Characteristics */
132 		0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54,
133 		/* Established Timings: maximum resolution is 1024x768 */
134 		0x21, 0x08, 0x00,
135 		/*
136 		 * Standard Timings.
137 		 * below new resolutions can be supported:
138 		 * 1920x1080, 1280x720, 1280x960, 1280x1024,
139 		 * 1440x900, 1600x1200, 1680x1050
140 		 */
141 		0xd1, 0xc0, 0x81, 0xc0, 0x81, 0x40, 0x81, 0x80, 0x95, 0x00,
142 		0xa9, 0x40, 0xb3, 0x00, 0x01, 0x01,
143 		/* 18 Byte Data Blocks 1: max resolution is 1920x1200 */
144 		0x28, 0x3c, 0x80, 0xa0, 0x70, 0xb0,
145 		0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a,
146 		/* 18 Byte Data Blocks 2: invalid */
147 		0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a,
148 		0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
149 		/* 18 Byte Data Blocks 3: invalid */
150 		0x00, 0x00, 0x00, 0xfc, 0x00, 0x48,
151 		0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20,
152 		/* 18 Byte Data Blocks 4: invalid */
153 		0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30,
154 		0x44, 0x58, 0x51, 0x0a, 0x20, 0x20,
155 		/* Extension Block Count */
156 		0x00,
157 		/* Checksum */
158 		0x45,
159 	},
160 };
161 
162 #define DPCD_HEADER_SIZE        0xb
163 
164 /* let the virtual display supports DP1.2 */
165 static u8 dpcd_fix_data[DPCD_HEADER_SIZE] = {
166 	0x12, 0x014, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
167 };
168 
169 static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
170 {
171 	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
172 	vgpu_vreg(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT |
173 			SDE_PORTC_HOTPLUG_CPT |
174 			SDE_PORTD_HOTPLUG_CPT);
175 
176 	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
177 		vgpu_vreg(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT |
178 				SDE_PORTE_HOTPLUG_SPT);
179 		vgpu_vreg(vgpu, SKL_FUSE_STATUS) |=
180 				SKL_FUSE_DOWNLOAD_STATUS |
181 				SKL_FUSE_PG0_DIST_STATUS |
182 				SKL_FUSE_PG1_DIST_STATUS |
183 				SKL_FUSE_PG2_DIST_STATUS;
184 		vgpu_vreg(vgpu, LCPLL1_CTL) |=
185 				LCPLL_PLL_ENABLE |
186 				LCPLL_PLL_LOCK;
187 		vgpu_vreg(vgpu, LCPLL2_CTL) |= LCPLL_PLL_ENABLE;
188 
189 	}
190 
191 	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
192 		vgpu_vreg(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED;
193 		vgpu_vreg(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
194 			~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
195 			TRANS_DDI_PORT_MASK);
196 		vgpu_vreg(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
197 			(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
198 			(PORT_B << TRANS_DDI_PORT_SHIFT) |
199 			TRANS_DDI_FUNC_ENABLE);
200 		if (IS_BROADWELL(dev_priv)) {
201 			vgpu_vreg(vgpu, PORT_CLK_SEL(PORT_B)) &=
202 				~PORT_CLK_SEL_MASK;
203 			vgpu_vreg(vgpu, PORT_CLK_SEL(PORT_B)) |=
204 				PORT_CLK_SEL_LCPLL_810;
205 		}
206 		vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE;
207 		vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE;
208 		vgpu_vreg(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT;
209 	}
210 
211 	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
212 		vgpu_vreg(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT;
213 		vgpu_vreg(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
214 			~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
215 			TRANS_DDI_PORT_MASK);
216 		vgpu_vreg(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
217 			(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
218 			(PORT_C << TRANS_DDI_PORT_SHIFT) |
219 			TRANS_DDI_FUNC_ENABLE);
220 		if (IS_BROADWELL(dev_priv)) {
221 			vgpu_vreg(vgpu, PORT_CLK_SEL(PORT_C)) &=
222 				~PORT_CLK_SEL_MASK;
223 			vgpu_vreg(vgpu, PORT_CLK_SEL(PORT_C)) |=
224 				PORT_CLK_SEL_LCPLL_810;
225 		}
226 		vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE;
227 		vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE;
228 		vgpu_vreg(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED;
229 	}
230 
231 	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D)) {
232 		vgpu_vreg(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;
233 		vgpu_vreg(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
234 			~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
235 			TRANS_DDI_PORT_MASK);
236 		vgpu_vreg(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
237 			(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
238 			(PORT_D << TRANS_DDI_PORT_SHIFT) |
239 			TRANS_DDI_FUNC_ENABLE);
240 		if (IS_BROADWELL(dev_priv)) {
241 			vgpu_vreg(vgpu, PORT_CLK_SEL(PORT_D)) &=
242 				~PORT_CLK_SEL_MASK;
243 			vgpu_vreg(vgpu, PORT_CLK_SEL(PORT_D)) |=
244 				PORT_CLK_SEL_LCPLL_810;
245 		}
246 		vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE;
247 		vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE;
248 		vgpu_vreg(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED;
249 	}
250 
251 	if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
252 			intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) {
253 		vgpu_vreg(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT;
254 	}
255 
256 	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
257 		if (IS_BROADWELL(dev_priv))
258 			vgpu_vreg(vgpu, GEN8_DE_PORT_ISR) |=
259 				GEN8_PORT_DP_A_HOTPLUG;
260 		else
261 			vgpu_vreg(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT;
262 
263 		vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED;
264 	}
265 
266 	/* Clear host CRT status, so guest couldn't detect this host CRT. */
267 	if (IS_BROADWELL(dev_priv))
268 		vgpu_vreg(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK;
269 }
270 
271 static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num)
272 {
273 	struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);
274 
275 	kfree(port->edid);
276 	port->edid = NULL;
277 
278 	kfree(port->dpcd);
279 	port->dpcd = NULL;
280 }
281 
282 static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num,
283 				    int type, unsigned int resolution)
284 {
285 	struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);
286 
287 	if (WARN_ON(resolution >= GVT_EDID_NUM))
288 		return -EINVAL;
289 
290 	port->edid = kzalloc(sizeof(*(port->edid)), GFP_KERNEL);
291 	if (!port->edid)
292 		return -ENOMEM;
293 
294 	port->dpcd = kzalloc(sizeof(*(port->dpcd)), GFP_KERNEL);
295 	if (!port->dpcd) {
296 		kfree(port->edid);
297 		return -ENOMEM;
298 	}
299 
300 	memcpy(port->edid->edid_block, virtual_dp_monitor_edid[resolution],
301 			EDID_SIZE);
302 	port->edid->data_valid = true;
303 
304 	memcpy(port->dpcd->data, dpcd_fix_data, DPCD_HEADER_SIZE);
305 	port->dpcd->data_valid = true;
306 	port->dpcd->data[DPCD_SINK_COUNT] = 0x1;
307 	port->type = type;
308 
309 	emulate_monitor_status_change(vgpu);
310 	return 0;
311 }
312 
313 /**
314  * intel_gvt_check_vblank_emulation - check if vblank emulation timer should
315  * be turned on/off when a virtual pipe is enabled/disabled.
316  * @gvt: a GVT device
317  *
318  * This function is used to turn on/off vblank timer according to currently
319  * enabled/disabled virtual pipes.
320  *
321  */
322 void intel_gvt_check_vblank_emulation(struct intel_gvt *gvt)
323 {
324 	struct intel_gvt_irq *irq = &gvt->irq;
325 	struct intel_vgpu *vgpu;
326 	bool have_enabled_pipe = false;
327 	int pipe, id;
328 
329 	if (WARN_ON(!mutex_is_locked(&gvt->lock)))
330 		return;
331 
332 	hrtimer_cancel(&irq->vblank_timer.timer);
333 
334 	for_each_active_vgpu(gvt, vgpu, id) {
335 		for (pipe = 0; pipe < I915_MAX_PIPES; pipe++) {
336 			have_enabled_pipe =
337 				pipe_is_enabled(vgpu, pipe);
338 			if (have_enabled_pipe)
339 				break;
340 		}
341 	}
342 
343 	if (have_enabled_pipe)
344 		hrtimer_start(&irq->vblank_timer.timer,
345 			ktime_add_ns(ktime_get(), irq->vblank_timer.period),
346 			HRTIMER_MODE_ABS);
347 }
348 
349 static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe)
350 {
351 	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
352 	struct intel_vgpu_irq *irq = &vgpu->irq;
353 	int vblank_event[] = {
354 		[PIPE_A] = PIPE_A_VBLANK,
355 		[PIPE_B] = PIPE_B_VBLANK,
356 		[PIPE_C] = PIPE_C_VBLANK,
357 	};
358 	int event;
359 
360 	if (pipe < PIPE_A || pipe > PIPE_C)
361 		return;
362 
363 	for_each_set_bit(event, irq->flip_done_event[pipe],
364 			INTEL_GVT_EVENT_MAX) {
365 		clear_bit(event, irq->flip_done_event[pipe]);
366 		if (!pipe_is_enabled(vgpu, pipe))
367 			continue;
368 
369 		vgpu_vreg(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++;
370 		intel_vgpu_trigger_virtual_event(vgpu, event);
371 	}
372 
373 	if (pipe_is_enabled(vgpu, pipe)) {
374 		vgpu_vreg(vgpu, PIPE_FRMCOUNT_G4X(pipe))++;
375 		intel_vgpu_trigger_virtual_event(vgpu, vblank_event[pipe]);
376 	}
377 }
378 
379 static void emulate_vblank(struct intel_vgpu *vgpu)
380 {
381 	int pipe;
382 
383 	for_each_pipe(vgpu->gvt->dev_priv, pipe)
384 		emulate_vblank_on_pipe(vgpu, pipe);
385 }
386 
387 /**
388  * intel_gvt_emulate_vblank - trigger vblank events for vGPUs on GVT device
389  * @gvt: a GVT device
390  *
391  * This function is used to trigger vblank interrupts for vGPUs on GVT device
392  *
393  */
394 void intel_gvt_emulate_vblank(struct intel_gvt *gvt)
395 {
396 	struct intel_vgpu *vgpu;
397 	int id;
398 
399 	if (WARN_ON(!mutex_is_locked(&gvt->lock)))
400 		return;
401 
402 	for_each_active_vgpu(gvt, vgpu, id)
403 		emulate_vblank(vgpu);
404 }
405 
406 /**
407  * intel_vgpu_clean_display - clean vGPU virtual display emulation
408  * @vgpu: a vGPU
409  *
410  * This function is used to clean vGPU virtual display emulation stuffs
411  *
412  */
413 void intel_vgpu_clean_display(struct intel_vgpu *vgpu)
414 {
415 	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
416 
417 	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
418 		clean_virtual_dp_monitor(vgpu, PORT_D);
419 	else
420 		clean_virtual_dp_monitor(vgpu, PORT_B);
421 }
422 
423 /**
424  * intel_vgpu_init_display- initialize vGPU virtual display emulation
425  * @vgpu: a vGPU
426  *
427  * This function is used to initialize vGPU virtual display emulation stuffs
428  *
429  * Returns:
430  * Zero on success, negative error code if failed.
431  *
432  */
433 int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution)
434 {
435 	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
436 
437 	intel_vgpu_init_i2c_edid(vgpu);
438 
439 	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
440 		return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D,
441 						resolution);
442 	else
443 		return setup_virtual_dp_monitor(vgpu, PORT_B, GVT_DP_B,
444 						resolution);
445 }
446 
447 /**
448  * intel_vgpu_reset_display- reset vGPU virtual display emulation
449  * @vgpu: a vGPU
450  *
451  * This function is used to reset vGPU virtual display emulation stuffs
452  *
453  */
454 void intel_vgpu_reset_display(struct intel_vgpu *vgpu)
455 {
456 	emulate_monitor_status_change(vgpu);
457 }
458