1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Ke Yu 25 * Zhiyuan Lv <zhiyuan.lv@intel.com> 26 * 27 * Contributors: 28 * Terrence Xu <terrence.xu@intel.com> 29 * Changbin Du <changbin.du@intel.com> 30 * Bing Niu <bing.niu@intel.com> 31 * Zhi Wang <zhi.a.wang@intel.com> 32 * 33 */ 34 35 #include "i915_drv.h" 36 #include "gvt.h" 37 38 static int get_edp_pipe(struct intel_vgpu *vgpu) 39 { 40 u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP); 41 int pipe = -1; 42 43 switch (data & TRANS_DDI_EDP_INPUT_MASK) { 44 case TRANS_DDI_EDP_INPUT_A_ON: 45 case TRANS_DDI_EDP_INPUT_A_ONOFF: 46 pipe = PIPE_A; 47 break; 48 case TRANS_DDI_EDP_INPUT_B_ONOFF: 49 pipe = PIPE_B; 50 break; 51 case TRANS_DDI_EDP_INPUT_C_ONOFF: 52 pipe = PIPE_C; 53 break; 54 } 55 return pipe; 56 } 57 58 static int edp_pipe_is_enabled(struct intel_vgpu *vgpu) 59 { 60 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 61 62 if (!(vgpu_vreg_t(vgpu, PIPECONF(_PIPE_EDP)) & PIPECONF_ENABLE)) 63 return 0; 64 65 if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE)) 66 return 0; 67 return 1; 68 } 69 70 int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe) 71 { 72 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 73 74 if (drm_WARN_ON(&dev_priv->drm, 75 pipe < PIPE_A || pipe >= I915_MAX_PIPES)) 76 return -EINVAL; 77 78 if (vgpu_vreg_t(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE) 79 return 1; 80 81 if (edp_pipe_is_enabled(vgpu) && 82 get_edp_pipe(vgpu) == pipe) 83 return 1; 84 return 0; 85 } 86 87 static unsigned char virtual_dp_monitor_edid[GVT_EDID_NUM][EDID_SIZE] = { 88 { 89 /* EDID with 1024x768 as its resolution */ 90 /*Header*/ 91 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 92 /* Vendor & Product Identification */ 93 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17, 94 /* Version & Revision */ 95 0x01, 0x04, 96 /* Basic Display Parameters & Features */ 97 0xa5, 0x34, 0x20, 0x78, 0x23, 98 /* Color Characteristics */ 99 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54, 100 /* Established Timings: maximum resolution is 1024x768 */ 101 0x21, 0x08, 0x00, 102 /* Standard Timings. All invalid */ 103 0x00, 0xc0, 0x00, 0xc0, 0x00, 0x40, 0x00, 0x80, 0x00, 0x00, 104 0x00, 0x40, 0x00, 0x00, 0x00, 0x01, 105 /* 18 Byte Data Blocks 1: invalid */ 106 0x00, 0x00, 0x80, 0xa0, 0x70, 0xb0, 107 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a, 108 /* 18 Byte Data Blocks 2: invalid */ 109 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a, 110 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 111 /* 18 Byte Data Blocks 3: invalid */ 112 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48, 113 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20, 114 /* 18 Byte Data Blocks 4: invalid */ 115 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30, 116 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20, 117 /* Extension Block Count */ 118 0x00, 119 /* Checksum */ 120 0xef, 121 }, 122 { 123 /* EDID with 1920x1200 as its resolution */ 124 /*Header*/ 125 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 126 /* Vendor & Product Identification */ 127 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17, 128 /* Version & Revision */ 129 0x01, 0x04, 130 /* Basic Display Parameters & Features */ 131 0xa5, 0x34, 0x20, 0x78, 0x23, 132 /* Color Characteristics */ 133 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54, 134 /* Established Timings: maximum resolution is 1024x768 */ 135 0x21, 0x08, 0x00, 136 /* 137 * Standard Timings. 138 * below new resolutions can be supported: 139 * 1920x1080, 1280x720, 1280x960, 1280x1024, 140 * 1440x900, 1600x1200, 1680x1050 141 */ 142 0xd1, 0xc0, 0x81, 0xc0, 0x81, 0x40, 0x81, 0x80, 0x95, 0x00, 143 0xa9, 0x40, 0xb3, 0x00, 0x01, 0x01, 144 /* 18 Byte Data Blocks 1: max resolution is 1920x1200 */ 145 0x28, 0x3c, 0x80, 0xa0, 0x70, 0xb0, 146 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a, 147 /* 18 Byte Data Blocks 2: invalid */ 148 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a, 149 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 150 /* 18 Byte Data Blocks 3: invalid */ 151 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48, 152 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20, 153 /* 18 Byte Data Blocks 4: invalid */ 154 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30, 155 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20, 156 /* Extension Block Count */ 157 0x00, 158 /* Checksum */ 159 0x45, 160 }, 161 }; 162 163 #define DPCD_HEADER_SIZE 0xb 164 165 /* let the virtual display supports DP1.2 */ 166 static u8 dpcd_fix_data[DPCD_HEADER_SIZE] = { 167 0x12, 0x014, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 168 }; 169 170 static void emulate_monitor_status_change(struct intel_vgpu *vgpu) 171 { 172 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 173 int pipe; 174 175 if (IS_BROXTON(dev_priv)) { 176 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= 177 ~(GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | 178 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | 179 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C)); 180 181 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { 182 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 183 GEN8_DE_PORT_HOTPLUG(HPD_PORT_A); 184 } 185 186 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) { 187 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 188 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B); 189 } 190 191 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) { 192 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 193 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C); 194 } 195 196 return; 197 } 198 199 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT | 200 SDE_PORTC_HOTPLUG_CPT | 201 SDE_PORTD_HOTPLUG_CPT); 202 203 if (IS_SKYLAKE(dev_priv) || 204 IS_KABYLAKE(dev_priv) || 205 IS_COFFEELAKE(dev_priv) || 206 IS_COMETLAKE(dev_priv)) { 207 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT | 208 SDE_PORTE_HOTPLUG_SPT); 209 vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |= 210 SKL_FUSE_DOWNLOAD_STATUS | 211 SKL_FUSE_PG_DIST_STATUS(SKL_PG0) | 212 SKL_FUSE_PG_DIST_STATUS(SKL_PG1) | 213 SKL_FUSE_PG_DIST_STATUS(SKL_PG2); 214 /* 215 * Only 1 PIPE enabled in current vGPU display and PIPE_A is 216 * tied to TRANSCODER_A in HW, so it's safe to assume PIPE_A, 217 * TRANSCODER_A can be enabled. PORT_x depends on the input of 218 * setup_virtual_dp_monitor, we can bind DPLL0 to any PORT_x 219 * so we fixed to DPLL0 here. 220 * Setup DPLL0: DP link clk 1620 MHz, non SSC, DP Mode 221 */ 222 vgpu_vreg_t(vgpu, DPLL_CTRL1) = 223 DPLL_CTRL1_OVERRIDE(DPLL_ID_SKL_DPLL0); 224 vgpu_vreg_t(vgpu, DPLL_CTRL1) |= 225 DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, DPLL_ID_SKL_DPLL0); 226 vgpu_vreg_t(vgpu, LCPLL1_CTL) = 227 LCPLL_PLL_ENABLE | LCPLL_PLL_LOCK; 228 vgpu_vreg_t(vgpu, DPLL_STATUS) = DPLL_LOCK(DPLL_ID_SKL_DPLL0); 229 /* 230 * Golden M/N are calculated based on: 231 * 24 bpp, 4 lanes, 154000 pixel clk (from virtual EDID), 232 * DP link clk 1620 MHz and non-constant_n. 233 * TODO: calculate DP link symbol clk and stream clk m/n. 234 */ 235 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = 63 << TU_SIZE_SHIFT; 236 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e; 237 vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000; 238 vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e; 239 vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000; 240 } 241 242 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) { 243 vgpu_vreg_t(vgpu, DPLL_CTRL2) &= 244 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_B); 245 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 246 DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_B); 247 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 248 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_B); 249 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED; 250 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &= 251 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 252 TRANS_DDI_PORT_MASK); 253 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= 254 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 255 (PORT_B << TRANS_DDI_PORT_SHIFT) | 256 TRANS_DDI_FUNC_ENABLE); 257 if (IS_BROADWELL(dev_priv)) { 258 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) &= 259 ~PORT_CLK_SEL_MASK; 260 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) |= 261 PORT_CLK_SEL_LCPLL_810; 262 } 263 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE; 264 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE; 265 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT; 266 } 267 268 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) { 269 vgpu_vreg_t(vgpu, DPLL_CTRL2) &= 270 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_C); 271 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 272 DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_C); 273 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 274 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_C); 275 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT; 276 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &= 277 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 278 TRANS_DDI_PORT_MASK); 279 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= 280 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 281 (PORT_C << TRANS_DDI_PORT_SHIFT) | 282 TRANS_DDI_FUNC_ENABLE); 283 if (IS_BROADWELL(dev_priv)) { 284 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) &= 285 ~PORT_CLK_SEL_MASK; 286 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) |= 287 PORT_CLK_SEL_LCPLL_810; 288 } 289 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE; 290 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE; 291 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED; 292 } 293 294 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D)) { 295 vgpu_vreg_t(vgpu, DPLL_CTRL2) &= 296 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_D); 297 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 298 DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_D); 299 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 300 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_D); 301 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT; 302 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &= 303 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 304 TRANS_DDI_PORT_MASK); 305 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= 306 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 307 (PORT_D << TRANS_DDI_PORT_SHIFT) | 308 TRANS_DDI_FUNC_ENABLE); 309 if (IS_BROADWELL(dev_priv)) { 310 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) &= 311 ~PORT_CLK_SEL_MASK; 312 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) |= 313 PORT_CLK_SEL_LCPLL_810; 314 } 315 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE; 316 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE; 317 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED; 318 } 319 320 if ((IS_SKYLAKE(dev_priv) || 321 IS_KABYLAKE(dev_priv) || 322 IS_COFFEELAKE(dev_priv) || 323 IS_COMETLAKE(dev_priv)) && 324 intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) { 325 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT; 326 } 327 328 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { 329 if (IS_BROADWELL(dev_priv)) 330 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 331 GEN8_DE_PORT_HOTPLUG(HPD_PORT_A); 332 else 333 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT; 334 335 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED; 336 } 337 338 /* Clear host CRT status, so guest couldn't detect this host CRT. */ 339 if (IS_BROADWELL(dev_priv)) 340 vgpu_vreg_t(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK; 341 342 /* Disable Primary/Sprite/Cursor plane */ 343 for_each_pipe(dev_priv, pipe) { 344 vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE; 345 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE; 346 vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE; 347 vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE; 348 } 349 350 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE; 351 } 352 353 static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num) 354 { 355 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num); 356 357 kfree(port->edid); 358 port->edid = NULL; 359 360 kfree(port->dpcd); 361 port->dpcd = NULL; 362 } 363 364 static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num, 365 int type, unsigned int resolution) 366 { 367 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 368 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num); 369 370 if (drm_WARN_ON(&i915->drm, resolution >= GVT_EDID_NUM)) 371 return -EINVAL; 372 373 port->edid = kzalloc(sizeof(*(port->edid)), GFP_KERNEL); 374 if (!port->edid) 375 return -ENOMEM; 376 377 port->dpcd = kzalloc(sizeof(*(port->dpcd)), GFP_KERNEL); 378 if (!port->dpcd) { 379 kfree(port->edid); 380 return -ENOMEM; 381 } 382 383 memcpy(port->edid->edid_block, virtual_dp_monitor_edid[resolution], 384 EDID_SIZE); 385 port->edid->data_valid = true; 386 387 memcpy(port->dpcd->data, dpcd_fix_data, DPCD_HEADER_SIZE); 388 port->dpcd->data_valid = true; 389 port->dpcd->data[DPCD_SINK_COUNT] = 0x1; 390 port->type = type; 391 port->id = resolution; 392 393 emulate_monitor_status_change(vgpu); 394 395 return 0; 396 } 397 398 /** 399 * intel_gvt_check_vblank_emulation - check if vblank emulation timer should 400 * be turned on/off when a virtual pipe is enabled/disabled. 401 * @gvt: a GVT device 402 * 403 * This function is used to turn on/off vblank timer according to currently 404 * enabled/disabled virtual pipes. 405 * 406 */ 407 void intel_gvt_check_vblank_emulation(struct intel_gvt *gvt) 408 { 409 struct intel_gvt_irq *irq = &gvt->irq; 410 struct intel_vgpu *vgpu; 411 int pipe, id; 412 int found = false; 413 414 mutex_lock(&gvt->lock); 415 for_each_active_vgpu(gvt, vgpu, id) { 416 for (pipe = 0; pipe < I915_MAX_PIPES; pipe++) { 417 if (pipe_is_enabled(vgpu, pipe)) { 418 found = true; 419 break; 420 } 421 } 422 if (found) 423 break; 424 } 425 426 /* all the pipes are disabled */ 427 if (!found) 428 hrtimer_cancel(&irq->vblank_timer.timer); 429 else 430 hrtimer_start(&irq->vblank_timer.timer, 431 ktime_add_ns(ktime_get(), irq->vblank_timer.period), 432 HRTIMER_MODE_ABS); 433 mutex_unlock(&gvt->lock); 434 } 435 436 static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe) 437 { 438 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 439 struct intel_vgpu_irq *irq = &vgpu->irq; 440 int vblank_event[] = { 441 [PIPE_A] = PIPE_A_VBLANK, 442 [PIPE_B] = PIPE_B_VBLANK, 443 [PIPE_C] = PIPE_C_VBLANK, 444 }; 445 int event; 446 447 if (pipe < PIPE_A || pipe > PIPE_C) 448 return; 449 450 for_each_set_bit(event, irq->flip_done_event[pipe], 451 INTEL_GVT_EVENT_MAX) { 452 clear_bit(event, irq->flip_done_event[pipe]); 453 if (!pipe_is_enabled(vgpu, pipe)) 454 continue; 455 456 intel_vgpu_trigger_virtual_event(vgpu, event); 457 } 458 459 if (pipe_is_enabled(vgpu, pipe)) { 460 vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(pipe))++; 461 intel_vgpu_trigger_virtual_event(vgpu, vblank_event[pipe]); 462 } 463 } 464 465 static void emulate_vblank(struct intel_vgpu *vgpu) 466 { 467 int pipe; 468 469 mutex_lock(&vgpu->vgpu_lock); 470 for_each_pipe(vgpu->gvt->gt->i915, pipe) 471 emulate_vblank_on_pipe(vgpu, pipe); 472 mutex_unlock(&vgpu->vgpu_lock); 473 } 474 475 /** 476 * intel_gvt_emulate_vblank - trigger vblank events for vGPUs on GVT device 477 * @gvt: a GVT device 478 * 479 * This function is used to trigger vblank interrupts for vGPUs on GVT device 480 * 481 */ 482 void intel_gvt_emulate_vblank(struct intel_gvt *gvt) 483 { 484 struct intel_vgpu *vgpu; 485 int id; 486 487 mutex_lock(&gvt->lock); 488 for_each_active_vgpu(gvt, vgpu, id) 489 emulate_vblank(vgpu); 490 mutex_unlock(&gvt->lock); 491 } 492 493 /** 494 * intel_vgpu_emulate_hotplug - trigger hotplug event for vGPU 495 * @vgpu: a vGPU 496 * @connected: link state 497 * 498 * This function is used to trigger hotplug interrupt for vGPU 499 * 500 */ 501 void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected) 502 { 503 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 504 505 /* TODO: add more platforms support */ 506 if (IS_SKYLAKE(i915) || 507 IS_KABYLAKE(i915) || 508 IS_COFFEELAKE(i915) || 509 IS_COMETLAKE(i915)) { 510 if (connected) { 511 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= 512 SFUSE_STRAP_DDID_DETECTED; 513 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT; 514 } else { 515 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= 516 ~SFUSE_STRAP_DDID_DETECTED; 517 vgpu_vreg_t(vgpu, SDEISR) &= ~SDE_PORTD_HOTPLUG_CPT; 518 } 519 vgpu_vreg_t(vgpu, SDEIIR) |= SDE_PORTD_HOTPLUG_CPT; 520 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= 521 PORTD_HOTPLUG_STATUS_MASK; 522 intel_vgpu_trigger_virtual_event(vgpu, DP_D_HOTPLUG); 523 } 524 } 525 526 /** 527 * intel_vgpu_clean_display - clean vGPU virtual display emulation 528 * @vgpu: a vGPU 529 * 530 * This function is used to clean vGPU virtual display emulation stuffs 531 * 532 */ 533 void intel_vgpu_clean_display(struct intel_vgpu *vgpu) 534 { 535 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 536 537 if (IS_SKYLAKE(dev_priv) || 538 IS_KABYLAKE(dev_priv) || 539 IS_COFFEELAKE(dev_priv) || 540 IS_COMETLAKE(dev_priv)) 541 clean_virtual_dp_monitor(vgpu, PORT_D); 542 else 543 clean_virtual_dp_monitor(vgpu, PORT_B); 544 } 545 546 /** 547 * intel_vgpu_init_display- initialize vGPU virtual display emulation 548 * @vgpu: a vGPU 549 * @resolution: resolution index for intel_vgpu_edid 550 * 551 * This function is used to initialize vGPU virtual display emulation stuffs 552 * 553 * Returns: 554 * Zero on success, negative error code if failed. 555 * 556 */ 557 int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution) 558 { 559 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 560 561 intel_vgpu_init_i2c_edid(vgpu); 562 563 if (IS_SKYLAKE(dev_priv) || 564 IS_KABYLAKE(dev_priv) || 565 IS_COFFEELAKE(dev_priv) || 566 IS_COMETLAKE(dev_priv)) 567 return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D, 568 resolution); 569 else 570 return setup_virtual_dp_monitor(vgpu, PORT_B, GVT_DP_B, 571 resolution); 572 } 573 574 /** 575 * intel_vgpu_reset_display- reset vGPU virtual display emulation 576 * @vgpu: a vGPU 577 * 578 * This function is used to reset vGPU virtual display emulation stuffs 579 * 580 */ 581 void intel_vgpu_reset_display(struct intel_vgpu *vgpu) 582 { 583 emulate_monitor_status_change(vgpu); 584 } 585