1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Ke Yu 25 * Zhiyuan Lv <zhiyuan.lv@intel.com> 26 * 27 * Contributors: 28 * Terrence Xu <terrence.xu@intel.com> 29 * Changbin Du <changbin.du@intel.com> 30 * Bing Niu <bing.niu@intel.com> 31 * Zhi Wang <zhi.a.wang@intel.com> 32 * 33 */ 34 35 #include "i915_drv.h" 36 #include "gvt.h" 37 38 static int get_edp_pipe(struct intel_vgpu *vgpu) 39 { 40 u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP); 41 int pipe = -1; 42 43 switch (data & TRANS_DDI_EDP_INPUT_MASK) { 44 case TRANS_DDI_EDP_INPUT_A_ON: 45 case TRANS_DDI_EDP_INPUT_A_ONOFF: 46 pipe = PIPE_A; 47 break; 48 case TRANS_DDI_EDP_INPUT_B_ONOFF: 49 pipe = PIPE_B; 50 break; 51 case TRANS_DDI_EDP_INPUT_C_ONOFF: 52 pipe = PIPE_C; 53 break; 54 } 55 return pipe; 56 } 57 58 static int edp_pipe_is_enabled(struct intel_vgpu *vgpu) 59 { 60 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 61 62 if (!(vgpu_vreg_t(vgpu, PIPECONF(_PIPE_EDP)) & PIPECONF_ENABLE)) 63 return 0; 64 65 if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE)) 66 return 0; 67 return 1; 68 } 69 70 int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe) 71 { 72 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 73 74 if (drm_WARN_ON(&dev_priv->drm, 75 pipe < PIPE_A || pipe >= I915_MAX_PIPES)) 76 return -EINVAL; 77 78 if (vgpu_vreg_t(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE) 79 return 1; 80 81 if (edp_pipe_is_enabled(vgpu) && 82 get_edp_pipe(vgpu) == pipe) 83 return 1; 84 return 0; 85 } 86 87 static unsigned char virtual_dp_monitor_edid[GVT_EDID_NUM][EDID_SIZE] = { 88 { 89 /* EDID with 1024x768 as its resolution */ 90 /*Header*/ 91 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 92 /* Vendor & Product Identification */ 93 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17, 94 /* Version & Revision */ 95 0x01, 0x04, 96 /* Basic Display Parameters & Features */ 97 0xa5, 0x34, 0x20, 0x78, 0x23, 98 /* Color Characteristics */ 99 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54, 100 /* Established Timings: maximum resolution is 1024x768 */ 101 0x21, 0x08, 0x00, 102 /* Standard Timings. All invalid */ 103 0x00, 0xc0, 0x00, 0xc0, 0x00, 0x40, 0x00, 0x80, 0x00, 0x00, 104 0x00, 0x40, 0x00, 0x00, 0x00, 0x01, 105 /* 18 Byte Data Blocks 1: invalid */ 106 0x00, 0x00, 0x80, 0xa0, 0x70, 0xb0, 107 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a, 108 /* 18 Byte Data Blocks 2: invalid */ 109 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a, 110 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 111 /* 18 Byte Data Blocks 3: invalid */ 112 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48, 113 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20, 114 /* 18 Byte Data Blocks 4: invalid */ 115 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30, 116 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20, 117 /* Extension Block Count */ 118 0x00, 119 /* Checksum */ 120 0xef, 121 }, 122 { 123 /* EDID with 1920x1200 as its resolution */ 124 /*Header*/ 125 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 126 /* Vendor & Product Identification */ 127 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17, 128 /* Version & Revision */ 129 0x01, 0x04, 130 /* Basic Display Parameters & Features */ 131 0xa5, 0x34, 0x20, 0x78, 0x23, 132 /* Color Characteristics */ 133 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54, 134 /* Established Timings: maximum resolution is 1024x768 */ 135 0x21, 0x08, 0x00, 136 /* 137 * Standard Timings. 138 * below new resolutions can be supported: 139 * 1920x1080, 1280x720, 1280x960, 1280x1024, 140 * 1440x900, 1600x1200, 1680x1050 141 */ 142 0xd1, 0xc0, 0x81, 0xc0, 0x81, 0x40, 0x81, 0x80, 0x95, 0x00, 143 0xa9, 0x40, 0xb3, 0x00, 0x01, 0x01, 144 /* 18 Byte Data Blocks 1: max resolution is 1920x1200 */ 145 0x28, 0x3c, 0x80, 0xa0, 0x70, 0xb0, 146 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a, 147 /* 18 Byte Data Blocks 2: invalid */ 148 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a, 149 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 150 /* 18 Byte Data Blocks 3: invalid */ 151 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48, 152 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20, 153 /* 18 Byte Data Blocks 4: invalid */ 154 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30, 155 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20, 156 /* Extension Block Count */ 157 0x00, 158 /* Checksum */ 159 0x45, 160 }, 161 }; 162 163 #define DPCD_HEADER_SIZE 0xb 164 165 /* let the virtual display supports DP1.2 */ 166 static u8 dpcd_fix_data[DPCD_HEADER_SIZE] = { 167 0x12, 0x014, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 168 }; 169 170 static void emulate_monitor_status_change(struct intel_vgpu *vgpu) 171 { 172 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 173 int pipe; 174 175 if (IS_BROXTON(dev_priv)) { 176 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~(BXT_DE_PORT_HP_DDIA | 177 BXT_DE_PORT_HP_DDIB | 178 BXT_DE_PORT_HP_DDIC); 179 180 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { 181 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 182 BXT_DE_PORT_HP_DDIA; 183 } 184 185 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) { 186 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 187 BXT_DE_PORT_HP_DDIB; 188 } 189 190 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) { 191 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 192 BXT_DE_PORT_HP_DDIC; 193 } 194 195 return; 196 } 197 198 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT | 199 SDE_PORTC_HOTPLUG_CPT | 200 SDE_PORTD_HOTPLUG_CPT); 201 202 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) || 203 IS_COFFEELAKE(dev_priv)) { 204 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT | 205 SDE_PORTE_HOTPLUG_SPT); 206 vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |= 207 SKL_FUSE_DOWNLOAD_STATUS | 208 SKL_FUSE_PG_DIST_STATUS(SKL_PG0) | 209 SKL_FUSE_PG_DIST_STATUS(SKL_PG1) | 210 SKL_FUSE_PG_DIST_STATUS(SKL_PG2); 211 vgpu_vreg_t(vgpu, LCPLL1_CTL) |= 212 LCPLL_PLL_ENABLE | 213 LCPLL_PLL_LOCK; 214 vgpu_vreg_t(vgpu, LCPLL2_CTL) |= LCPLL_PLL_ENABLE; 215 216 } 217 218 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) { 219 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED; 220 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &= 221 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 222 TRANS_DDI_PORT_MASK); 223 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= 224 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 225 (PORT_B << TRANS_DDI_PORT_SHIFT) | 226 TRANS_DDI_FUNC_ENABLE); 227 if (IS_BROADWELL(dev_priv)) { 228 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) &= 229 ~PORT_CLK_SEL_MASK; 230 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) |= 231 PORT_CLK_SEL_LCPLL_810; 232 } 233 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE; 234 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE; 235 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT; 236 } 237 238 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) { 239 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT; 240 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &= 241 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 242 TRANS_DDI_PORT_MASK); 243 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= 244 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 245 (PORT_C << TRANS_DDI_PORT_SHIFT) | 246 TRANS_DDI_FUNC_ENABLE); 247 if (IS_BROADWELL(dev_priv)) { 248 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) &= 249 ~PORT_CLK_SEL_MASK; 250 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) |= 251 PORT_CLK_SEL_LCPLL_810; 252 } 253 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE; 254 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE; 255 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED; 256 } 257 258 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D)) { 259 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT; 260 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &= 261 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 262 TRANS_DDI_PORT_MASK); 263 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= 264 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 265 (PORT_D << TRANS_DDI_PORT_SHIFT) | 266 TRANS_DDI_FUNC_ENABLE); 267 if (IS_BROADWELL(dev_priv)) { 268 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) &= 269 ~PORT_CLK_SEL_MASK; 270 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) |= 271 PORT_CLK_SEL_LCPLL_810; 272 } 273 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE; 274 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE; 275 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED; 276 } 277 278 if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) || 279 IS_COFFEELAKE(dev_priv)) && 280 intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) { 281 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT; 282 } 283 284 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { 285 if (IS_BROADWELL(dev_priv)) 286 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 287 GEN8_PORT_DP_A_HOTPLUG; 288 else 289 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT; 290 291 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED; 292 } 293 294 /* Clear host CRT status, so guest couldn't detect this host CRT. */ 295 if (IS_BROADWELL(dev_priv)) 296 vgpu_vreg_t(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK; 297 298 /* Disable Primary/Sprite/Cursor plane */ 299 for_each_pipe(dev_priv, pipe) { 300 vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE; 301 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE; 302 vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE; 303 vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE; 304 } 305 306 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE; 307 } 308 309 static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num) 310 { 311 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num); 312 313 kfree(port->edid); 314 port->edid = NULL; 315 316 kfree(port->dpcd); 317 port->dpcd = NULL; 318 } 319 320 static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num, 321 int type, unsigned int resolution) 322 { 323 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 324 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num); 325 326 if (drm_WARN_ON(&i915->drm, resolution >= GVT_EDID_NUM)) 327 return -EINVAL; 328 329 port->edid = kzalloc(sizeof(*(port->edid)), GFP_KERNEL); 330 if (!port->edid) 331 return -ENOMEM; 332 333 port->dpcd = kzalloc(sizeof(*(port->dpcd)), GFP_KERNEL); 334 if (!port->dpcd) { 335 kfree(port->edid); 336 return -ENOMEM; 337 } 338 339 memcpy(port->edid->edid_block, virtual_dp_monitor_edid[resolution], 340 EDID_SIZE); 341 port->edid->data_valid = true; 342 343 memcpy(port->dpcd->data, dpcd_fix_data, DPCD_HEADER_SIZE); 344 port->dpcd->data_valid = true; 345 port->dpcd->data[DPCD_SINK_COUNT] = 0x1; 346 port->type = type; 347 port->id = resolution; 348 349 emulate_monitor_status_change(vgpu); 350 351 return 0; 352 } 353 354 /** 355 * intel_gvt_check_vblank_emulation - check if vblank emulation timer should 356 * be turned on/off when a virtual pipe is enabled/disabled. 357 * @gvt: a GVT device 358 * 359 * This function is used to turn on/off vblank timer according to currently 360 * enabled/disabled virtual pipes. 361 * 362 */ 363 void intel_gvt_check_vblank_emulation(struct intel_gvt *gvt) 364 { 365 struct intel_gvt_irq *irq = &gvt->irq; 366 struct intel_vgpu *vgpu; 367 int pipe, id; 368 int found = false; 369 370 mutex_lock(&gvt->lock); 371 for_each_active_vgpu(gvt, vgpu, id) { 372 for (pipe = 0; pipe < I915_MAX_PIPES; pipe++) { 373 if (pipe_is_enabled(vgpu, pipe)) { 374 found = true; 375 break; 376 } 377 } 378 if (found) 379 break; 380 } 381 382 /* all the pipes are disabled */ 383 if (!found) 384 hrtimer_cancel(&irq->vblank_timer.timer); 385 else 386 hrtimer_start(&irq->vblank_timer.timer, 387 ktime_add_ns(ktime_get(), irq->vblank_timer.period), 388 HRTIMER_MODE_ABS); 389 mutex_unlock(&gvt->lock); 390 } 391 392 static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe) 393 { 394 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 395 struct intel_vgpu_irq *irq = &vgpu->irq; 396 int vblank_event[] = { 397 [PIPE_A] = PIPE_A_VBLANK, 398 [PIPE_B] = PIPE_B_VBLANK, 399 [PIPE_C] = PIPE_C_VBLANK, 400 }; 401 int event; 402 403 if (pipe < PIPE_A || pipe > PIPE_C) 404 return; 405 406 for_each_set_bit(event, irq->flip_done_event[pipe], 407 INTEL_GVT_EVENT_MAX) { 408 clear_bit(event, irq->flip_done_event[pipe]); 409 if (!pipe_is_enabled(vgpu, pipe)) 410 continue; 411 412 intel_vgpu_trigger_virtual_event(vgpu, event); 413 } 414 415 if (pipe_is_enabled(vgpu, pipe)) { 416 vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(pipe))++; 417 intel_vgpu_trigger_virtual_event(vgpu, vblank_event[pipe]); 418 } 419 } 420 421 static void emulate_vblank(struct intel_vgpu *vgpu) 422 { 423 int pipe; 424 425 mutex_lock(&vgpu->vgpu_lock); 426 for_each_pipe(vgpu->gvt->gt->i915, pipe) 427 emulate_vblank_on_pipe(vgpu, pipe); 428 mutex_unlock(&vgpu->vgpu_lock); 429 } 430 431 /** 432 * intel_gvt_emulate_vblank - trigger vblank events for vGPUs on GVT device 433 * @gvt: a GVT device 434 * 435 * This function is used to trigger vblank interrupts for vGPUs on GVT device 436 * 437 */ 438 void intel_gvt_emulate_vblank(struct intel_gvt *gvt) 439 { 440 struct intel_vgpu *vgpu; 441 int id; 442 443 mutex_lock(&gvt->lock); 444 for_each_active_vgpu(gvt, vgpu, id) 445 emulate_vblank(vgpu); 446 mutex_unlock(&gvt->lock); 447 } 448 449 /** 450 * intel_vgpu_emulate_hotplug - trigger hotplug event for vGPU 451 * @vgpu: a vGPU 452 * @connected: link state 453 * 454 * This function is used to trigger hotplug interrupt for vGPU 455 * 456 */ 457 void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected) 458 { 459 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 460 461 /* TODO: add more platforms support */ 462 if (IS_SKYLAKE(i915) || IS_KABYLAKE(i915) || 463 IS_COFFEELAKE(i915)) { 464 if (connected) { 465 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= 466 SFUSE_STRAP_DDID_DETECTED; 467 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT; 468 } else { 469 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= 470 ~SFUSE_STRAP_DDID_DETECTED; 471 vgpu_vreg_t(vgpu, SDEISR) &= ~SDE_PORTD_HOTPLUG_CPT; 472 } 473 vgpu_vreg_t(vgpu, SDEIIR) |= SDE_PORTD_HOTPLUG_CPT; 474 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= 475 PORTD_HOTPLUG_STATUS_MASK; 476 intel_vgpu_trigger_virtual_event(vgpu, DP_D_HOTPLUG); 477 } 478 } 479 480 /** 481 * intel_vgpu_clean_display - clean vGPU virtual display emulation 482 * @vgpu: a vGPU 483 * 484 * This function is used to clean vGPU virtual display emulation stuffs 485 * 486 */ 487 void intel_vgpu_clean_display(struct intel_vgpu *vgpu) 488 { 489 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 490 491 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) || 492 IS_COFFEELAKE(dev_priv)) 493 clean_virtual_dp_monitor(vgpu, PORT_D); 494 else 495 clean_virtual_dp_monitor(vgpu, PORT_B); 496 } 497 498 /** 499 * intel_vgpu_init_display- initialize vGPU virtual display emulation 500 * @vgpu: a vGPU 501 * @resolution: resolution index for intel_vgpu_edid 502 * 503 * This function is used to initialize vGPU virtual display emulation stuffs 504 * 505 * Returns: 506 * Zero on success, negative error code if failed. 507 * 508 */ 509 int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution) 510 { 511 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 512 513 intel_vgpu_init_i2c_edid(vgpu); 514 515 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) || 516 IS_COFFEELAKE(dev_priv)) 517 return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D, 518 resolution); 519 else 520 return setup_virtual_dp_monitor(vgpu, PORT_B, GVT_DP_B, 521 resolution); 522 } 523 524 /** 525 * intel_vgpu_reset_display- reset vGPU virtual display emulation 526 * @vgpu: a vGPU 527 * 528 * This function is used to reset vGPU virtual display emulation stuffs 529 * 530 */ 531 void intel_vgpu_reset_display(struct intel_vgpu *vgpu) 532 { 533 emulate_monitor_status_change(vgpu); 534 } 535