1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Ke Yu 25 * Zhiyuan Lv <zhiyuan.lv@intel.com> 26 * 27 * Contributors: 28 * Terrence Xu <terrence.xu@intel.com> 29 * Changbin Du <changbin.du@intel.com> 30 * Bing Niu <bing.niu@intel.com> 31 * Zhi Wang <zhi.a.wang@intel.com> 32 * 33 */ 34 35 #include "i915_drv.h" 36 #include "gvt.h" 37 38 static int get_edp_pipe(struct intel_vgpu *vgpu) 39 { 40 u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP); 41 int pipe = -1; 42 43 switch (data & TRANS_DDI_EDP_INPUT_MASK) { 44 case TRANS_DDI_EDP_INPUT_A_ON: 45 case TRANS_DDI_EDP_INPUT_A_ONOFF: 46 pipe = PIPE_A; 47 break; 48 case TRANS_DDI_EDP_INPUT_B_ONOFF: 49 pipe = PIPE_B; 50 break; 51 case TRANS_DDI_EDP_INPUT_C_ONOFF: 52 pipe = PIPE_C; 53 break; 54 } 55 return pipe; 56 } 57 58 static int edp_pipe_is_enabled(struct intel_vgpu *vgpu) 59 { 60 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 61 62 if (!(vgpu_vreg(vgpu, PIPECONF(_PIPE_EDP)) & PIPECONF_ENABLE)) 63 return 0; 64 65 if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE)) 66 return 0; 67 return 1; 68 } 69 70 static int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe) 71 { 72 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 73 74 if (WARN_ON(pipe < PIPE_A || pipe >= I915_MAX_PIPES)) 75 return -EINVAL; 76 77 if (vgpu_vreg(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE) 78 return 1; 79 80 if (edp_pipe_is_enabled(vgpu) && 81 get_edp_pipe(vgpu) == pipe) 82 return 1; 83 return 0; 84 } 85 86 /* EDID with 1920x1200 as its resolution */ 87 static unsigned char virtual_dp_monitor_edid[] = { 88 /*Header*/ 89 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 90 /* Vendor & Product Identification */ 91 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17, 92 /* Version & Revision */ 93 0x01, 0x04, 94 /* Basic Display Parameters & Features */ 95 0xa5, 0x34, 0x20, 0x78, 0x23, 96 /* Color Characteristics */ 97 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54, 98 /* Established Timings: maximum resolution is 1024x768 */ 99 0x21, 0x08, 0x00, 100 /* 101 * Standard Timings. 102 * below new resolutions can be supported: 103 * 1920x1080, 1280x720, 1280x960, 1280x1024, 104 * 1440x900, 1600x1200, 1680x1050 105 */ 106 0xd1, 0xc0, 0x81, 0xc0, 0x81, 0x40, 0x81, 0x80, 0x95, 0x00, 107 0xa9, 0x40, 0xb3, 0x00, 0x01, 0x01, 108 /* 18 Byte Data Blocks 1: max resolution is 1920x1200 */ 109 0x28, 0x3c, 0x80, 0xa0, 0x70, 0xb0, 110 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a, 111 /* 18 Byte Data Blocks 2: invalid */ 112 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a, 113 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 114 /* 18 Byte Data Blocks 3: invalid */ 115 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48, 116 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20, 117 /* 18 Byte Data Blocks 4: invalid */ 118 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30, 119 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20, 120 /* Extension Block Count */ 121 0x00, 122 /* Checksum */ 123 0x45, 124 }; 125 126 #define DPCD_HEADER_SIZE 0xb 127 128 static u8 dpcd_fix_data[DPCD_HEADER_SIZE] = { 129 0x11, 0x0a, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 130 }; 131 132 static void emulate_monitor_status_change(struct intel_vgpu *vgpu) 133 { 134 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 135 vgpu_vreg(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT | 136 SDE_PORTC_HOTPLUG_CPT | 137 SDE_PORTD_HOTPLUG_CPT); 138 139 if (IS_SKYLAKE(dev_priv)) 140 vgpu_vreg(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT | 141 SDE_PORTE_HOTPLUG_SPT); 142 143 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) 144 vgpu_vreg(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT; 145 146 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) 147 vgpu_vreg(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT; 148 149 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D)) 150 vgpu_vreg(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT; 151 152 if (IS_SKYLAKE(dev_priv) && 153 intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) { 154 vgpu_vreg(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT; 155 } 156 157 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { 158 if (IS_BROADWELL(dev_priv)) 159 vgpu_vreg(vgpu, GEN8_DE_PORT_ISR) |= 160 GEN8_PORT_DP_A_HOTPLUG; 161 else 162 vgpu_vreg(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT; 163 } 164 } 165 166 static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num) 167 { 168 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num); 169 170 kfree(port->edid); 171 port->edid = NULL; 172 173 kfree(port->dpcd); 174 port->dpcd = NULL; 175 } 176 177 static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num, 178 int type) 179 { 180 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num); 181 182 port->edid = kzalloc(sizeof(*(port->edid)), GFP_KERNEL); 183 if (!port->edid) 184 return -ENOMEM; 185 186 port->dpcd = kzalloc(sizeof(*(port->dpcd)), GFP_KERNEL); 187 if (!port->dpcd) { 188 kfree(port->edid); 189 return -ENOMEM; 190 } 191 192 memcpy(port->edid->edid_block, virtual_dp_monitor_edid, 193 EDID_SIZE); 194 port->edid->data_valid = true; 195 196 memcpy(port->dpcd->data, dpcd_fix_data, DPCD_HEADER_SIZE); 197 port->dpcd->data_valid = true; 198 port->dpcd->data[DPCD_SINK_COUNT] = 0x1; 199 port->type = type; 200 201 emulate_monitor_status_change(vgpu); 202 return 0; 203 } 204 205 /** 206 * intel_gvt_check_vblank_emulation - check if vblank emulation timer should 207 * be turned on/off when a virtual pipe is enabled/disabled. 208 * @gvt: a GVT device 209 * 210 * This function is used to turn on/off vblank timer according to currently 211 * enabled/disabled virtual pipes. 212 * 213 */ 214 void intel_gvt_check_vblank_emulation(struct intel_gvt *gvt) 215 { 216 struct intel_gvt_irq *irq = &gvt->irq; 217 struct intel_vgpu *vgpu; 218 bool have_enabled_pipe = false; 219 int pipe, id; 220 221 if (WARN_ON(!mutex_is_locked(&gvt->lock))) 222 return; 223 224 hrtimer_cancel(&irq->vblank_timer.timer); 225 226 for_each_active_vgpu(gvt, vgpu, id) { 227 for (pipe = 0; pipe < I915_MAX_PIPES; pipe++) { 228 have_enabled_pipe = 229 pipe_is_enabled(vgpu, pipe); 230 if (have_enabled_pipe) 231 break; 232 } 233 } 234 235 if (have_enabled_pipe) 236 hrtimer_start(&irq->vblank_timer.timer, 237 ktime_add_ns(ktime_get(), irq->vblank_timer.period), 238 HRTIMER_MODE_ABS); 239 } 240 241 static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe) 242 { 243 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 244 struct intel_vgpu_irq *irq = &vgpu->irq; 245 int vblank_event[] = { 246 [PIPE_A] = PIPE_A_VBLANK, 247 [PIPE_B] = PIPE_B_VBLANK, 248 [PIPE_C] = PIPE_C_VBLANK, 249 }; 250 int event; 251 252 if (pipe < PIPE_A || pipe > PIPE_C) 253 return; 254 255 for_each_set_bit(event, irq->flip_done_event[pipe], 256 INTEL_GVT_EVENT_MAX) { 257 clear_bit(event, irq->flip_done_event[pipe]); 258 if (!pipe_is_enabled(vgpu, pipe)) 259 continue; 260 261 vgpu_vreg(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++; 262 intel_vgpu_trigger_virtual_event(vgpu, event); 263 } 264 265 if (pipe_is_enabled(vgpu, pipe)) { 266 vgpu_vreg(vgpu, PIPE_FRMCOUNT_G4X(pipe))++; 267 intel_vgpu_trigger_virtual_event(vgpu, vblank_event[pipe]); 268 } 269 } 270 271 static void emulate_vblank(struct intel_vgpu *vgpu) 272 { 273 int pipe; 274 275 for_each_pipe(vgpu->gvt->dev_priv, pipe) 276 emulate_vblank_on_pipe(vgpu, pipe); 277 } 278 279 /** 280 * intel_gvt_emulate_vblank - trigger vblank events for vGPUs on GVT device 281 * @gvt: a GVT device 282 * 283 * This function is used to trigger vblank interrupts for vGPUs on GVT device 284 * 285 */ 286 void intel_gvt_emulate_vblank(struct intel_gvt *gvt) 287 { 288 struct intel_vgpu *vgpu; 289 int id; 290 291 if (WARN_ON(!mutex_is_locked(&gvt->lock))) 292 return; 293 294 for_each_active_vgpu(gvt, vgpu, id) 295 emulate_vblank(vgpu); 296 } 297 298 /** 299 * intel_vgpu_clean_display - clean vGPU virtual display emulation 300 * @vgpu: a vGPU 301 * 302 * This function is used to clean vGPU virtual display emulation stuffs 303 * 304 */ 305 void intel_vgpu_clean_display(struct intel_vgpu *vgpu) 306 { 307 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 308 309 if (IS_SKYLAKE(dev_priv)) 310 clean_virtual_dp_monitor(vgpu, PORT_D); 311 else 312 clean_virtual_dp_monitor(vgpu, PORT_B); 313 } 314 315 /** 316 * intel_vgpu_init_display- initialize vGPU virtual display emulation 317 * @vgpu: a vGPU 318 * 319 * This function is used to initialize vGPU virtual display emulation stuffs 320 * 321 * Returns: 322 * Zero on success, negative error code if failed. 323 * 324 */ 325 int intel_vgpu_init_display(struct intel_vgpu *vgpu) 326 { 327 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 328 329 intel_vgpu_init_i2c_edid(vgpu); 330 331 if (IS_SKYLAKE(dev_priv)) 332 return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D); 333 else 334 return setup_virtual_dp_monitor(vgpu, PORT_B, GVT_DP_B); 335 } 336 337 /** 338 * intel_vgpu_reset_display- reset vGPU virtual display emulation 339 * @vgpu: a vGPU 340 * 341 * This function is used to reset vGPU virtual display emulation stuffs 342 * 343 */ 344 void intel_vgpu_reset_display(struct intel_vgpu *vgpu) 345 { 346 emulate_monitor_status_change(vgpu); 347 } 348