1be1da707SZhi Wang /* 2be1da707SZhi Wang * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3be1da707SZhi Wang * 4be1da707SZhi Wang * Permission is hereby granted, free of charge, to any person obtaining a 5be1da707SZhi Wang * copy of this software and associated documentation files (the "Software"), 6be1da707SZhi Wang * to deal in the Software without restriction, including without limitation 7be1da707SZhi Wang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8be1da707SZhi Wang * and/or sell copies of the Software, and to permit persons to whom the 9be1da707SZhi Wang * Software is furnished to do so, subject to the following conditions: 10be1da707SZhi Wang * 11be1da707SZhi Wang * The above copyright notice and this permission notice (including the next 12be1da707SZhi Wang * paragraph) shall be included in all copies or substantial portions of the 13be1da707SZhi Wang * Software. 14be1da707SZhi Wang * 15be1da707SZhi Wang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16be1da707SZhi Wang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17be1da707SZhi Wang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18be1da707SZhi Wang * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19be1da707SZhi Wang * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20be1da707SZhi Wang * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21be1da707SZhi Wang * SOFTWARE. 22be1da707SZhi Wang * 23be1da707SZhi Wang * Authors: 24be1da707SZhi Wang * Ke Yu 25be1da707SZhi Wang * Kevin Tian <kevin.tian@intel.com> 26be1da707SZhi Wang * Zhiyuan Lv <zhiyuan.lv@intel.com> 27be1da707SZhi Wang * 28be1da707SZhi Wang * Contributors: 29be1da707SZhi Wang * Min He <min.he@intel.com> 30be1da707SZhi Wang * Ping Gao <ping.a.gao@intel.com> 31be1da707SZhi Wang * Tina Zhang <tina.zhang@intel.com> 32be1da707SZhi Wang * Yulei Zhang <yulei.zhang@intel.com> 33be1da707SZhi Wang * Zhi Wang <zhi.a.wang@intel.com> 34be1da707SZhi Wang * 35be1da707SZhi Wang */ 36be1da707SZhi Wang 37be1da707SZhi Wang #include <linux/slab.h> 38be1da707SZhi Wang #include "i915_drv.h" 39feddf6e8SZhenyu Wang #include "gvt.h" 40feddf6e8SZhenyu Wang #include "i915_pvinfo.h" 41be1da707SZhi Wang #include "trace.h" 42be1da707SZhi Wang 43be1da707SZhi Wang #define INVALID_OP (~0U) 44be1da707SZhi Wang 45be1da707SZhi Wang #define OP_LEN_MI 9 46be1da707SZhi Wang #define OP_LEN_2D 10 47be1da707SZhi Wang #define OP_LEN_3D_MEDIA 16 48be1da707SZhi Wang #define OP_LEN_MFX_VC 16 49be1da707SZhi Wang #define OP_LEN_VEBOX 16 50be1da707SZhi Wang 51be1da707SZhi Wang #define CMD_TYPE(cmd) (((cmd) >> 29) & 7) 52be1da707SZhi Wang 53be1da707SZhi Wang struct sub_op_bits { 54be1da707SZhi Wang int hi; 55be1da707SZhi Wang int low; 56be1da707SZhi Wang }; 57be1da707SZhi Wang struct decode_info { 58be1da707SZhi Wang char *name; 59be1da707SZhi Wang int op_len; 60be1da707SZhi Wang int nr_sub_op; 61be1da707SZhi Wang struct sub_op_bits *sub_op; 62be1da707SZhi Wang }; 63be1da707SZhi Wang 64be1da707SZhi Wang #define MAX_CMD_BUDGET 0x7fffffff 65be1da707SZhi Wang #define MI_WAIT_FOR_PLANE_C_FLIP_PENDING (1<<15) 66be1da707SZhi Wang #define MI_WAIT_FOR_PLANE_B_FLIP_PENDING (1<<9) 67be1da707SZhi Wang #define MI_WAIT_FOR_PLANE_A_FLIP_PENDING (1<<1) 68be1da707SZhi Wang 69be1da707SZhi Wang #define MI_WAIT_FOR_SPRITE_C_FLIP_PENDING (1<<20) 70be1da707SZhi Wang #define MI_WAIT_FOR_SPRITE_B_FLIP_PENDING (1<<10) 71be1da707SZhi Wang #define MI_WAIT_FOR_SPRITE_A_FLIP_PENDING (1<<2) 72be1da707SZhi Wang 73be1da707SZhi Wang /* Render Command Map */ 74be1da707SZhi Wang 75be1da707SZhi Wang /* MI_* command Opcode (28:23) */ 76be1da707SZhi Wang #define OP_MI_NOOP 0x0 77be1da707SZhi Wang #define OP_MI_SET_PREDICATE 0x1 /* HSW+ */ 78be1da707SZhi Wang #define OP_MI_USER_INTERRUPT 0x2 79be1da707SZhi Wang #define OP_MI_WAIT_FOR_EVENT 0x3 80be1da707SZhi Wang #define OP_MI_FLUSH 0x4 81be1da707SZhi Wang #define OP_MI_ARB_CHECK 0x5 82be1da707SZhi Wang #define OP_MI_RS_CONTROL 0x6 /* HSW+ */ 83be1da707SZhi Wang #define OP_MI_REPORT_HEAD 0x7 84be1da707SZhi Wang #define OP_MI_ARB_ON_OFF 0x8 85be1da707SZhi Wang #define OP_MI_URB_ATOMIC_ALLOC 0x9 /* HSW+ */ 86be1da707SZhi Wang #define OP_MI_BATCH_BUFFER_END 0xA 87be1da707SZhi Wang #define OP_MI_SUSPEND_FLUSH 0xB 88be1da707SZhi Wang #define OP_MI_PREDICATE 0xC /* IVB+ */ 89be1da707SZhi Wang #define OP_MI_TOPOLOGY_FILTER 0xD /* IVB+ */ 90be1da707SZhi Wang #define OP_MI_SET_APPID 0xE /* IVB+ */ 91be1da707SZhi Wang #define OP_MI_RS_CONTEXT 0xF /* HSW+ */ 92be1da707SZhi Wang #define OP_MI_LOAD_SCAN_LINES_INCL 0x12 /* HSW+ */ 93be1da707SZhi Wang #define OP_MI_DISPLAY_FLIP 0x14 94be1da707SZhi Wang #define OP_MI_SEMAPHORE_MBOX 0x16 95be1da707SZhi Wang #define OP_MI_SET_CONTEXT 0x18 96be1da707SZhi Wang #define OP_MI_MATH 0x1A 97be1da707SZhi Wang #define OP_MI_URB_CLEAR 0x19 98be1da707SZhi Wang #define OP_MI_SEMAPHORE_SIGNAL 0x1B /* BDW+ */ 99be1da707SZhi Wang #define OP_MI_SEMAPHORE_WAIT 0x1C /* BDW+ */ 100be1da707SZhi Wang 101be1da707SZhi Wang #define OP_MI_STORE_DATA_IMM 0x20 102be1da707SZhi Wang #define OP_MI_STORE_DATA_INDEX 0x21 103be1da707SZhi Wang #define OP_MI_LOAD_REGISTER_IMM 0x22 104be1da707SZhi Wang #define OP_MI_UPDATE_GTT 0x23 105be1da707SZhi Wang #define OP_MI_STORE_REGISTER_MEM 0x24 106be1da707SZhi Wang #define OP_MI_FLUSH_DW 0x26 107be1da707SZhi Wang #define OP_MI_CLFLUSH 0x27 108be1da707SZhi Wang #define OP_MI_REPORT_PERF_COUNT 0x28 109be1da707SZhi Wang #define OP_MI_LOAD_REGISTER_MEM 0x29 /* HSW+ */ 110be1da707SZhi Wang #define OP_MI_LOAD_REGISTER_REG 0x2A /* HSW+ */ 111be1da707SZhi Wang #define OP_MI_RS_STORE_DATA_IMM 0x2B /* HSW+ */ 112be1da707SZhi Wang #define OP_MI_LOAD_URB_MEM 0x2C /* HSW+ */ 113be1da707SZhi Wang #define OP_MI_STORE_URM_MEM 0x2D /* HSW+ */ 114be1da707SZhi Wang #define OP_MI_2E 0x2E /* BDW+ */ 115be1da707SZhi Wang #define OP_MI_2F 0x2F /* BDW+ */ 116be1da707SZhi Wang #define OP_MI_BATCH_BUFFER_START 0x31 117be1da707SZhi Wang 118be1da707SZhi Wang /* Bit definition for dword 0 */ 119be1da707SZhi Wang #define _CMDBIT_BB_START_IN_PPGTT (1UL << 8) 120be1da707SZhi Wang 121be1da707SZhi Wang #define OP_MI_CONDITIONAL_BATCH_BUFFER_END 0x36 122be1da707SZhi Wang 123be1da707SZhi Wang #define BATCH_BUFFER_ADDR_MASK ((1UL << 32) - (1U << 2)) 124be1da707SZhi Wang #define BATCH_BUFFER_ADDR_HIGH_MASK ((1UL << 16) - (1U)) 125be1da707SZhi Wang #define BATCH_BUFFER_ADR_SPACE_BIT(x) (((x) >> 8) & 1U) 126be1da707SZhi Wang #define BATCH_BUFFER_2ND_LEVEL_BIT(x) ((x) >> 22 & 1U) 127be1da707SZhi Wang 128be1da707SZhi Wang /* 2D command: Opcode (28:22) */ 129be1da707SZhi Wang #define OP_2D(x) ((2<<7) | x) 130be1da707SZhi Wang 131be1da707SZhi Wang #define OP_XY_SETUP_BLT OP_2D(0x1) 132be1da707SZhi Wang #define OP_XY_SETUP_CLIP_BLT OP_2D(0x3) 133be1da707SZhi Wang #define OP_XY_SETUP_MONO_PATTERN_SL_BLT OP_2D(0x11) 134be1da707SZhi Wang #define OP_XY_PIXEL_BLT OP_2D(0x24) 135be1da707SZhi Wang #define OP_XY_SCANLINES_BLT OP_2D(0x25) 136be1da707SZhi Wang #define OP_XY_TEXT_BLT OP_2D(0x26) 137be1da707SZhi Wang #define OP_XY_TEXT_IMMEDIATE_BLT OP_2D(0x31) 138be1da707SZhi Wang #define OP_XY_COLOR_BLT OP_2D(0x50) 139be1da707SZhi Wang #define OP_XY_PAT_BLT OP_2D(0x51) 140be1da707SZhi Wang #define OP_XY_MONO_PAT_BLT OP_2D(0x52) 141be1da707SZhi Wang #define OP_XY_SRC_COPY_BLT OP_2D(0x53) 142be1da707SZhi Wang #define OP_XY_MONO_SRC_COPY_BLT OP_2D(0x54) 143be1da707SZhi Wang #define OP_XY_FULL_BLT OP_2D(0x55) 144be1da707SZhi Wang #define OP_XY_FULL_MONO_SRC_BLT OP_2D(0x56) 145be1da707SZhi Wang #define OP_XY_FULL_MONO_PATTERN_BLT OP_2D(0x57) 146be1da707SZhi Wang #define OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT OP_2D(0x58) 147be1da707SZhi Wang #define OP_XY_MONO_PAT_FIXED_BLT OP_2D(0x59) 148be1da707SZhi Wang #define OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT OP_2D(0x71) 149be1da707SZhi Wang #define OP_XY_PAT_BLT_IMMEDIATE OP_2D(0x72) 150be1da707SZhi Wang #define OP_XY_SRC_COPY_CHROMA_BLT OP_2D(0x73) 151be1da707SZhi Wang #define OP_XY_FULL_IMMEDIATE_PATTERN_BLT OP_2D(0x74) 152be1da707SZhi Wang #define OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT OP_2D(0x75) 153be1da707SZhi Wang #define OP_XY_PAT_CHROMA_BLT OP_2D(0x76) 154be1da707SZhi Wang #define OP_XY_PAT_CHROMA_BLT_IMMEDIATE OP_2D(0x77) 155be1da707SZhi Wang 156be1da707SZhi Wang /* 3D/Media Command: Pipeline Type(28:27) Opcode(26:24) Sub Opcode(23:16) */ 157be1da707SZhi Wang #define OP_3D_MEDIA(sub_type, opcode, sub_opcode) \ 158be1da707SZhi Wang ((3 << 13) | ((sub_type) << 11) | ((opcode) << 8) | (sub_opcode)) 159be1da707SZhi Wang 160be1da707SZhi Wang #define OP_STATE_PREFETCH OP_3D_MEDIA(0x0, 0x0, 0x03) 161be1da707SZhi Wang 162be1da707SZhi Wang #define OP_STATE_BASE_ADDRESS OP_3D_MEDIA(0x0, 0x1, 0x01) 163be1da707SZhi Wang #define OP_STATE_SIP OP_3D_MEDIA(0x0, 0x1, 0x02) 164be1da707SZhi Wang #define OP_3D_MEDIA_0_1_4 OP_3D_MEDIA(0x0, 0x1, 0x04) 165be1da707SZhi Wang 166be1da707SZhi Wang #define OP_3DSTATE_VF_STATISTICS_GM45 OP_3D_MEDIA(0x1, 0x0, 0x0B) 167be1da707SZhi Wang 168be1da707SZhi Wang #define OP_PIPELINE_SELECT OP_3D_MEDIA(0x1, 0x1, 0x04) 169be1da707SZhi Wang 170be1da707SZhi Wang #define OP_MEDIA_VFE_STATE OP_3D_MEDIA(0x2, 0x0, 0x0) 171be1da707SZhi Wang #define OP_MEDIA_CURBE_LOAD OP_3D_MEDIA(0x2, 0x0, 0x1) 172be1da707SZhi Wang #define OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD OP_3D_MEDIA(0x2, 0x0, 0x2) 173be1da707SZhi Wang #define OP_MEDIA_GATEWAY_STATE OP_3D_MEDIA(0x2, 0x0, 0x3) 174be1da707SZhi Wang #define OP_MEDIA_STATE_FLUSH OP_3D_MEDIA(0x2, 0x0, 0x4) 175be1da707SZhi Wang 176be1da707SZhi Wang #define OP_MEDIA_OBJECT OP_3D_MEDIA(0x2, 0x1, 0x0) 177be1da707SZhi Wang #define OP_MEDIA_OBJECT_PRT OP_3D_MEDIA(0x2, 0x1, 0x2) 178be1da707SZhi Wang #define OP_MEDIA_OBJECT_WALKER OP_3D_MEDIA(0x2, 0x1, 0x3) 179be1da707SZhi Wang #define OP_GPGPU_WALKER OP_3D_MEDIA(0x2, 0x1, 0x5) 180be1da707SZhi Wang 181be1da707SZhi Wang #define OP_3DSTATE_CLEAR_PARAMS OP_3D_MEDIA(0x3, 0x0, 0x04) /* IVB+ */ 182be1da707SZhi Wang #define OP_3DSTATE_DEPTH_BUFFER OP_3D_MEDIA(0x3, 0x0, 0x05) /* IVB+ */ 183be1da707SZhi Wang #define OP_3DSTATE_STENCIL_BUFFER OP_3D_MEDIA(0x3, 0x0, 0x06) /* IVB+ */ 184be1da707SZhi Wang #define OP_3DSTATE_HIER_DEPTH_BUFFER OP_3D_MEDIA(0x3, 0x0, 0x07) /* IVB+ */ 185be1da707SZhi Wang #define OP_3DSTATE_VERTEX_BUFFERS OP_3D_MEDIA(0x3, 0x0, 0x08) 186be1da707SZhi Wang #define OP_3DSTATE_VERTEX_ELEMENTS OP_3D_MEDIA(0x3, 0x0, 0x09) 187be1da707SZhi Wang #define OP_3DSTATE_INDEX_BUFFER OP_3D_MEDIA(0x3, 0x0, 0x0A) 188be1da707SZhi Wang #define OP_3DSTATE_VF_STATISTICS OP_3D_MEDIA(0x3, 0x0, 0x0B) 189be1da707SZhi Wang #define OP_3DSTATE_VF OP_3D_MEDIA(0x3, 0x0, 0x0C) /* HSW+ */ 190be1da707SZhi Wang #define OP_3DSTATE_CC_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x0E) 191be1da707SZhi Wang #define OP_3DSTATE_SCISSOR_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x0F) 192be1da707SZhi Wang #define OP_3DSTATE_VS OP_3D_MEDIA(0x3, 0x0, 0x10) 193be1da707SZhi Wang #define OP_3DSTATE_GS OP_3D_MEDIA(0x3, 0x0, 0x11) 194be1da707SZhi Wang #define OP_3DSTATE_CLIP OP_3D_MEDIA(0x3, 0x0, 0x12) 195be1da707SZhi Wang #define OP_3DSTATE_SF OP_3D_MEDIA(0x3, 0x0, 0x13) 196be1da707SZhi Wang #define OP_3DSTATE_WM OP_3D_MEDIA(0x3, 0x0, 0x14) 197be1da707SZhi Wang #define OP_3DSTATE_CONSTANT_VS OP_3D_MEDIA(0x3, 0x0, 0x15) 198be1da707SZhi Wang #define OP_3DSTATE_CONSTANT_GS OP_3D_MEDIA(0x3, 0x0, 0x16) 199be1da707SZhi Wang #define OP_3DSTATE_CONSTANT_PS OP_3D_MEDIA(0x3, 0x0, 0x17) 200be1da707SZhi Wang #define OP_3DSTATE_SAMPLE_MASK OP_3D_MEDIA(0x3, 0x0, 0x18) 201be1da707SZhi Wang #define OP_3DSTATE_CONSTANT_HS OP_3D_MEDIA(0x3, 0x0, 0x19) /* IVB+ */ 202be1da707SZhi Wang #define OP_3DSTATE_CONSTANT_DS OP_3D_MEDIA(0x3, 0x0, 0x1A) /* IVB+ */ 203be1da707SZhi Wang #define OP_3DSTATE_HS OP_3D_MEDIA(0x3, 0x0, 0x1B) /* IVB+ */ 204be1da707SZhi Wang #define OP_3DSTATE_TE OP_3D_MEDIA(0x3, 0x0, 0x1C) /* IVB+ */ 205be1da707SZhi Wang #define OP_3DSTATE_DS OP_3D_MEDIA(0x3, 0x0, 0x1D) /* IVB+ */ 206be1da707SZhi Wang #define OP_3DSTATE_STREAMOUT OP_3D_MEDIA(0x3, 0x0, 0x1E) /* IVB+ */ 207be1da707SZhi Wang #define OP_3DSTATE_SBE OP_3D_MEDIA(0x3, 0x0, 0x1F) /* IVB+ */ 208be1da707SZhi Wang #define OP_3DSTATE_PS OP_3D_MEDIA(0x3, 0x0, 0x20) /* IVB+ */ 209be1da707SZhi Wang #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP OP_3D_MEDIA(0x3, 0x0, 0x21) /* IVB+ */ 210be1da707SZhi Wang #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC OP_3D_MEDIA(0x3, 0x0, 0x23) /* IVB+ */ 211be1da707SZhi Wang #define OP_3DSTATE_BLEND_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x24) /* IVB+ */ 212be1da707SZhi Wang #define OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x25) /* IVB+ */ 213be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_POINTERS_VS OP_3D_MEDIA(0x3, 0x0, 0x26) /* IVB+ */ 214be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_POINTERS_HS OP_3D_MEDIA(0x3, 0x0, 0x27) /* IVB+ */ 215be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_POINTERS_DS OP_3D_MEDIA(0x3, 0x0, 0x28) /* IVB+ */ 216be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_POINTERS_GS OP_3D_MEDIA(0x3, 0x0, 0x29) /* IVB+ */ 217be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_POINTERS_PS OP_3D_MEDIA(0x3, 0x0, 0x2A) /* IVB+ */ 218be1da707SZhi Wang #define OP_3DSTATE_SAMPLER_STATE_POINTERS_VS OP_3D_MEDIA(0x3, 0x0, 0x2B) /* IVB+ */ 219be1da707SZhi Wang #define OP_3DSTATE_SAMPLER_STATE_POINTERS_HS OP_3D_MEDIA(0x3, 0x0, 0x2C) /* IVB+ */ 220be1da707SZhi Wang #define OP_3DSTATE_SAMPLER_STATE_POINTERS_DS OP_3D_MEDIA(0x3, 0x0, 0x2D) /* IVB+ */ 221be1da707SZhi Wang #define OP_3DSTATE_SAMPLER_STATE_POINTERS_GS OP_3D_MEDIA(0x3, 0x0, 0x2E) /* IVB+ */ 222be1da707SZhi Wang #define OP_3DSTATE_SAMPLER_STATE_POINTERS_PS OP_3D_MEDIA(0x3, 0x0, 0x2F) /* IVB+ */ 223be1da707SZhi Wang #define OP_3DSTATE_URB_VS OP_3D_MEDIA(0x3, 0x0, 0x30) /* IVB+ */ 224be1da707SZhi Wang #define OP_3DSTATE_URB_HS OP_3D_MEDIA(0x3, 0x0, 0x31) /* IVB+ */ 225be1da707SZhi Wang #define OP_3DSTATE_URB_DS OP_3D_MEDIA(0x3, 0x0, 0x32) /* IVB+ */ 226be1da707SZhi Wang #define OP_3DSTATE_URB_GS OP_3D_MEDIA(0x3, 0x0, 0x33) /* IVB+ */ 227be1da707SZhi Wang #define OP_3DSTATE_GATHER_CONSTANT_VS OP_3D_MEDIA(0x3, 0x0, 0x34) /* HSW+ */ 228be1da707SZhi Wang #define OP_3DSTATE_GATHER_CONSTANT_GS OP_3D_MEDIA(0x3, 0x0, 0x35) /* HSW+ */ 229be1da707SZhi Wang #define OP_3DSTATE_GATHER_CONSTANT_HS OP_3D_MEDIA(0x3, 0x0, 0x36) /* HSW+ */ 230be1da707SZhi Wang #define OP_3DSTATE_GATHER_CONSTANT_DS OP_3D_MEDIA(0x3, 0x0, 0x37) /* HSW+ */ 231be1da707SZhi Wang #define OP_3DSTATE_GATHER_CONSTANT_PS OP_3D_MEDIA(0x3, 0x0, 0x38) /* HSW+ */ 232be1da707SZhi Wang #define OP_3DSTATE_DX9_CONSTANTF_VS OP_3D_MEDIA(0x3, 0x0, 0x39) /* HSW+ */ 233be1da707SZhi Wang #define OP_3DSTATE_DX9_CONSTANTF_PS OP_3D_MEDIA(0x3, 0x0, 0x3A) /* HSW+ */ 234be1da707SZhi Wang #define OP_3DSTATE_DX9_CONSTANTI_VS OP_3D_MEDIA(0x3, 0x0, 0x3B) /* HSW+ */ 235be1da707SZhi Wang #define OP_3DSTATE_DX9_CONSTANTI_PS OP_3D_MEDIA(0x3, 0x0, 0x3C) /* HSW+ */ 236be1da707SZhi Wang #define OP_3DSTATE_DX9_CONSTANTB_VS OP_3D_MEDIA(0x3, 0x0, 0x3D) /* HSW+ */ 237be1da707SZhi Wang #define OP_3DSTATE_DX9_CONSTANTB_PS OP_3D_MEDIA(0x3, 0x0, 0x3E) /* HSW+ */ 238be1da707SZhi Wang #define OP_3DSTATE_DX9_LOCAL_VALID_VS OP_3D_MEDIA(0x3, 0x0, 0x3F) /* HSW+ */ 239be1da707SZhi Wang #define OP_3DSTATE_DX9_LOCAL_VALID_PS OP_3D_MEDIA(0x3, 0x0, 0x40) /* HSW+ */ 240be1da707SZhi Wang #define OP_3DSTATE_DX9_GENERATE_ACTIVE_VS OP_3D_MEDIA(0x3, 0x0, 0x41) /* HSW+ */ 241be1da707SZhi Wang #define OP_3DSTATE_DX9_GENERATE_ACTIVE_PS OP_3D_MEDIA(0x3, 0x0, 0x42) /* HSW+ */ 242be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_EDIT_VS OP_3D_MEDIA(0x3, 0x0, 0x43) /* HSW+ */ 243be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_EDIT_GS OP_3D_MEDIA(0x3, 0x0, 0x44) /* HSW+ */ 244be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_EDIT_HS OP_3D_MEDIA(0x3, 0x0, 0x45) /* HSW+ */ 245be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_EDIT_DS OP_3D_MEDIA(0x3, 0x0, 0x46) /* HSW+ */ 246be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_EDIT_PS OP_3D_MEDIA(0x3, 0x0, 0x47) /* HSW+ */ 247be1da707SZhi Wang 248be1da707SZhi Wang #define OP_3DSTATE_VF_INSTANCING OP_3D_MEDIA(0x3, 0x0, 0x49) /* BDW+ */ 249be1da707SZhi Wang #define OP_3DSTATE_VF_SGVS OP_3D_MEDIA(0x3, 0x0, 0x4A) /* BDW+ */ 250be1da707SZhi Wang #define OP_3DSTATE_VF_TOPOLOGY OP_3D_MEDIA(0x3, 0x0, 0x4B) /* BDW+ */ 251be1da707SZhi Wang #define OP_3DSTATE_WM_CHROMAKEY OP_3D_MEDIA(0x3, 0x0, 0x4C) /* BDW+ */ 252be1da707SZhi Wang #define OP_3DSTATE_PS_BLEND OP_3D_MEDIA(0x3, 0x0, 0x4D) /* BDW+ */ 253be1da707SZhi Wang #define OP_3DSTATE_WM_DEPTH_STENCIL OP_3D_MEDIA(0x3, 0x0, 0x4E) /* BDW+ */ 254be1da707SZhi Wang #define OP_3DSTATE_PS_EXTRA OP_3D_MEDIA(0x3, 0x0, 0x4F) /* BDW+ */ 255be1da707SZhi Wang #define OP_3DSTATE_RASTER OP_3D_MEDIA(0x3, 0x0, 0x50) /* BDW+ */ 256be1da707SZhi Wang #define OP_3DSTATE_SBE_SWIZ OP_3D_MEDIA(0x3, 0x0, 0x51) /* BDW+ */ 257be1da707SZhi Wang #define OP_3DSTATE_WM_HZ_OP OP_3D_MEDIA(0x3, 0x0, 0x52) /* BDW+ */ 258be1da707SZhi Wang #define OP_3DSTATE_COMPONENT_PACKING OP_3D_MEDIA(0x3, 0x0, 0x55) /* SKL+ */ 259be1da707SZhi Wang 260be1da707SZhi Wang #define OP_3DSTATE_DRAWING_RECTANGLE OP_3D_MEDIA(0x3, 0x1, 0x00) 261be1da707SZhi Wang #define OP_3DSTATE_SAMPLER_PALETTE_LOAD0 OP_3D_MEDIA(0x3, 0x1, 0x02) 262be1da707SZhi Wang #define OP_3DSTATE_CHROMA_KEY OP_3D_MEDIA(0x3, 0x1, 0x04) 263be1da707SZhi Wang #define OP_SNB_3DSTATE_DEPTH_BUFFER OP_3D_MEDIA(0x3, 0x1, 0x05) 264be1da707SZhi Wang #define OP_3DSTATE_POLY_STIPPLE_OFFSET OP_3D_MEDIA(0x3, 0x1, 0x06) 265be1da707SZhi Wang #define OP_3DSTATE_POLY_STIPPLE_PATTERN OP_3D_MEDIA(0x3, 0x1, 0x07) 266be1da707SZhi Wang #define OP_3DSTATE_LINE_STIPPLE OP_3D_MEDIA(0x3, 0x1, 0x08) 267be1da707SZhi Wang #define OP_3DSTATE_AA_LINE_PARAMS OP_3D_MEDIA(0x3, 0x1, 0x0A) 268be1da707SZhi Wang #define OP_3DSTATE_GS_SVB_INDEX OP_3D_MEDIA(0x3, 0x1, 0x0B) 269be1da707SZhi Wang #define OP_3DSTATE_SAMPLER_PALETTE_LOAD1 OP_3D_MEDIA(0x3, 0x1, 0x0C) 270be1da707SZhi Wang #define OP_3DSTATE_MULTISAMPLE_BDW OP_3D_MEDIA(0x3, 0x0, 0x0D) 271be1da707SZhi Wang #define OP_SNB_3DSTATE_STENCIL_BUFFER OP_3D_MEDIA(0x3, 0x1, 0x0E) 272be1da707SZhi Wang #define OP_SNB_3DSTATE_HIER_DEPTH_BUFFER OP_3D_MEDIA(0x3, 0x1, 0x0F) 273be1da707SZhi Wang #define OP_SNB_3DSTATE_CLEAR_PARAMS OP_3D_MEDIA(0x3, 0x1, 0x10) 274be1da707SZhi Wang #define OP_3DSTATE_MONOFILTER_SIZE OP_3D_MEDIA(0x3, 0x1, 0x11) 275be1da707SZhi Wang #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS OP_3D_MEDIA(0x3, 0x1, 0x12) /* IVB+ */ 276be1da707SZhi Wang #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS OP_3D_MEDIA(0x3, 0x1, 0x13) /* IVB+ */ 277be1da707SZhi Wang #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS OP_3D_MEDIA(0x3, 0x1, 0x14) /* IVB+ */ 278be1da707SZhi Wang #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS OP_3D_MEDIA(0x3, 0x1, 0x15) /* IVB+ */ 279be1da707SZhi Wang #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS OP_3D_MEDIA(0x3, 0x1, 0x16) /* IVB+ */ 280be1da707SZhi Wang #define OP_3DSTATE_SO_DECL_LIST OP_3D_MEDIA(0x3, 0x1, 0x17) 281be1da707SZhi Wang #define OP_3DSTATE_SO_BUFFER OP_3D_MEDIA(0x3, 0x1, 0x18) 282be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x19) /* HSW+ */ 283be1da707SZhi Wang #define OP_3DSTATE_GATHER_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x1A) /* HSW+ */ 284be1da707SZhi Wang #define OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x1B) /* HSW+ */ 285be1da707SZhi Wang #define OP_3DSTATE_SAMPLE_PATTERN OP_3D_MEDIA(0x3, 0x1, 0x1C) 286be1da707SZhi Wang #define OP_PIPE_CONTROL OP_3D_MEDIA(0x3, 0x2, 0x00) 287be1da707SZhi Wang #define OP_3DPRIMITIVE OP_3D_MEDIA(0x3, 0x3, 0x00) 288be1da707SZhi Wang 289be1da707SZhi Wang /* VCCP Command Parser */ 290be1da707SZhi Wang 291be1da707SZhi Wang /* 292be1da707SZhi Wang * Below MFX and VBE cmd definition is from vaapi intel driver project (BSD License) 293be1da707SZhi Wang * git://anongit.freedesktop.org/vaapi/intel-driver 294be1da707SZhi Wang * src/i965_defines.h 295be1da707SZhi Wang * 296be1da707SZhi Wang */ 297be1da707SZhi Wang 298be1da707SZhi Wang #define OP_MFX(pipeline, op, sub_opa, sub_opb) \ 299be1da707SZhi Wang (3 << 13 | \ 300be1da707SZhi Wang (pipeline) << 11 | \ 301be1da707SZhi Wang (op) << 8 | \ 302be1da707SZhi Wang (sub_opa) << 5 | \ 303be1da707SZhi Wang (sub_opb)) 304be1da707SZhi Wang 305be1da707SZhi Wang #define OP_MFX_PIPE_MODE_SELECT OP_MFX(2, 0, 0, 0) /* ALL */ 306be1da707SZhi Wang #define OP_MFX_SURFACE_STATE OP_MFX(2, 0, 0, 1) /* ALL */ 307be1da707SZhi Wang #define OP_MFX_PIPE_BUF_ADDR_STATE OP_MFX(2, 0, 0, 2) /* ALL */ 308be1da707SZhi Wang #define OP_MFX_IND_OBJ_BASE_ADDR_STATE OP_MFX(2, 0, 0, 3) /* ALL */ 309be1da707SZhi Wang #define OP_MFX_BSP_BUF_BASE_ADDR_STATE OP_MFX(2, 0, 0, 4) /* ALL */ 310be1da707SZhi Wang #define OP_2_0_0_5 OP_MFX(2, 0, 0, 5) /* ALL */ 311be1da707SZhi Wang #define OP_MFX_STATE_POINTER OP_MFX(2, 0, 0, 6) /* ALL */ 312be1da707SZhi Wang #define OP_MFX_QM_STATE OP_MFX(2, 0, 0, 7) /* IVB+ */ 313be1da707SZhi Wang #define OP_MFX_FQM_STATE OP_MFX(2, 0, 0, 8) /* IVB+ */ 314be1da707SZhi Wang #define OP_MFX_PAK_INSERT_OBJECT OP_MFX(2, 0, 2, 8) /* IVB+ */ 315be1da707SZhi Wang #define OP_MFX_STITCH_OBJECT OP_MFX(2, 0, 2, 0xA) /* IVB+ */ 316be1da707SZhi Wang 317be1da707SZhi Wang #define OP_MFD_IT_OBJECT OP_MFX(2, 0, 1, 9) /* ALL */ 318be1da707SZhi Wang 319be1da707SZhi Wang #define OP_MFX_WAIT OP_MFX(1, 0, 0, 0) /* IVB+ */ 320be1da707SZhi Wang #define OP_MFX_AVC_IMG_STATE OP_MFX(2, 1, 0, 0) /* ALL */ 321be1da707SZhi Wang #define OP_MFX_AVC_QM_STATE OP_MFX(2, 1, 0, 1) /* ALL */ 322be1da707SZhi Wang #define OP_MFX_AVC_DIRECTMODE_STATE OP_MFX(2, 1, 0, 2) /* ALL */ 323be1da707SZhi Wang #define OP_MFX_AVC_SLICE_STATE OP_MFX(2, 1, 0, 3) /* ALL */ 324be1da707SZhi Wang #define OP_MFX_AVC_REF_IDX_STATE OP_MFX(2, 1, 0, 4) /* ALL */ 325be1da707SZhi Wang #define OP_MFX_AVC_WEIGHTOFFSET_STATE OP_MFX(2, 1, 0, 5) /* ALL */ 326be1da707SZhi Wang #define OP_MFD_AVC_PICID_STATE OP_MFX(2, 1, 1, 5) /* HSW+ */ 327be1da707SZhi Wang #define OP_MFD_AVC_DPB_STATE OP_MFX(2, 1, 1, 6) /* IVB+ */ 328be1da707SZhi Wang #define OP_MFD_AVC_SLICEADDR OP_MFX(2, 1, 1, 7) /* IVB+ */ 329be1da707SZhi Wang #define OP_MFD_AVC_BSD_OBJECT OP_MFX(2, 1, 1, 8) /* ALL */ 330be1da707SZhi Wang #define OP_MFC_AVC_PAK_OBJECT OP_MFX(2, 1, 2, 9) /* ALL */ 331be1da707SZhi Wang 332be1da707SZhi Wang #define OP_MFX_VC1_PRED_PIPE_STATE OP_MFX(2, 2, 0, 1) /* ALL */ 333be1da707SZhi Wang #define OP_MFX_VC1_DIRECTMODE_STATE OP_MFX(2, 2, 0, 2) /* ALL */ 334be1da707SZhi Wang #define OP_MFD_VC1_SHORT_PIC_STATE OP_MFX(2, 2, 1, 0) /* IVB+ */ 335be1da707SZhi Wang #define OP_MFD_VC1_LONG_PIC_STATE OP_MFX(2, 2, 1, 1) /* IVB+ */ 336be1da707SZhi Wang #define OP_MFD_VC1_BSD_OBJECT OP_MFX(2, 2, 1, 8) /* ALL */ 337be1da707SZhi Wang 338be1da707SZhi Wang #define OP_MFX_MPEG2_PIC_STATE OP_MFX(2, 3, 0, 0) /* ALL */ 339be1da707SZhi Wang #define OP_MFX_MPEG2_QM_STATE OP_MFX(2, 3, 0, 1) /* ALL */ 340be1da707SZhi Wang #define OP_MFD_MPEG2_BSD_OBJECT OP_MFX(2, 3, 1, 8) /* ALL */ 341be1da707SZhi Wang #define OP_MFC_MPEG2_SLICEGROUP_STATE OP_MFX(2, 3, 2, 3) /* ALL */ 342be1da707SZhi Wang #define OP_MFC_MPEG2_PAK_OBJECT OP_MFX(2, 3, 2, 9) /* ALL */ 343be1da707SZhi Wang 344be1da707SZhi Wang #define OP_MFX_2_6_0_0 OP_MFX(2, 6, 0, 0) /* IVB+ */ 345be1da707SZhi Wang #define OP_MFX_2_6_0_8 OP_MFX(2, 6, 0, 8) /* IVB+ */ 346be1da707SZhi Wang #define OP_MFX_2_6_0_9 OP_MFX(2, 6, 0, 9) /* IVB+ */ 347be1da707SZhi Wang 348be1da707SZhi Wang #define OP_MFX_JPEG_PIC_STATE OP_MFX(2, 7, 0, 0) 349be1da707SZhi Wang #define OP_MFX_JPEG_HUFF_TABLE_STATE OP_MFX(2, 7, 0, 2) 350be1da707SZhi Wang #define OP_MFD_JPEG_BSD_OBJECT OP_MFX(2, 7, 1, 8) 351be1da707SZhi Wang 352be1da707SZhi Wang #define OP_VEB(pipeline, op, sub_opa, sub_opb) \ 353be1da707SZhi Wang (3 << 13 | \ 354be1da707SZhi Wang (pipeline) << 11 | \ 355be1da707SZhi Wang (op) << 8 | \ 356be1da707SZhi Wang (sub_opa) << 5 | \ 357be1da707SZhi Wang (sub_opb)) 358be1da707SZhi Wang 359be1da707SZhi Wang #define OP_VEB_SURFACE_STATE OP_VEB(2, 4, 0, 0) 360be1da707SZhi Wang #define OP_VEB_STATE OP_VEB(2, 4, 0, 2) 361be1da707SZhi Wang #define OP_VEB_DNDI_IECP_STATE OP_VEB(2, 4, 0, 3) 362be1da707SZhi Wang 363be1da707SZhi Wang struct parser_exec_state; 364be1da707SZhi Wang 365be1da707SZhi Wang typedef int (*parser_cmd_handler)(struct parser_exec_state *s); 366be1da707SZhi Wang 367be1da707SZhi Wang #define GVT_CMD_HASH_BITS 7 368be1da707SZhi Wang 369be1da707SZhi Wang /* which DWords need address fix */ 370be1da707SZhi Wang #define ADDR_FIX_1(x1) (1 << (x1)) 371be1da707SZhi Wang #define ADDR_FIX_2(x1, x2) (ADDR_FIX_1(x1) | ADDR_FIX_1(x2)) 372be1da707SZhi Wang #define ADDR_FIX_3(x1, x2, x3) (ADDR_FIX_1(x1) | ADDR_FIX_2(x2, x3)) 373be1da707SZhi Wang #define ADDR_FIX_4(x1, x2, x3, x4) (ADDR_FIX_1(x1) | ADDR_FIX_3(x2, x3, x4)) 374be1da707SZhi Wang #define ADDR_FIX_5(x1, x2, x3, x4, x5) (ADDR_FIX_1(x1) | ADDR_FIX_4(x2, x3, x4, x5)) 375be1da707SZhi Wang 376be1da707SZhi Wang struct cmd_info { 377be1da707SZhi Wang char *name; 378be1da707SZhi Wang u32 opcode; 379be1da707SZhi Wang 380be1da707SZhi Wang #define F_LEN_MASK (1U<<0) 381be1da707SZhi Wang #define F_LEN_CONST 1U 382be1da707SZhi Wang #define F_LEN_VAR 0U 383be1da707SZhi Wang 384be1da707SZhi Wang /* 385be1da707SZhi Wang * command has its own ip advance logic 386be1da707SZhi Wang * e.g. MI_BATCH_START, MI_BATCH_END 387be1da707SZhi Wang */ 388be1da707SZhi Wang #define F_IP_ADVANCE_CUSTOM (1<<1) 389be1da707SZhi Wang 390be1da707SZhi Wang #define F_POST_HANDLE (1<<2) 391be1da707SZhi Wang u32 flag; 392be1da707SZhi Wang 393be1da707SZhi Wang #define R_RCS (1 << RCS) 394be1da707SZhi Wang #define R_VCS1 (1 << VCS) 395be1da707SZhi Wang #define R_VCS2 (1 << VCS2) 396be1da707SZhi Wang #define R_VCS (R_VCS1 | R_VCS2) 397be1da707SZhi Wang #define R_BCS (1 << BCS) 398be1da707SZhi Wang #define R_VECS (1 << VECS) 399be1da707SZhi Wang #define R_ALL (R_RCS | R_VCS | R_BCS | R_VECS) 400be1da707SZhi Wang /* rings that support this cmd: BLT/RCS/VCS/VECS */ 401be1da707SZhi Wang uint16_t rings; 402be1da707SZhi Wang 403be1da707SZhi Wang /* devices that support this cmd: SNB/IVB/HSW/... */ 404be1da707SZhi Wang uint16_t devices; 405be1da707SZhi Wang 406be1da707SZhi Wang /* which DWords are address that need fix up. 407be1da707SZhi Wang * bit 0 means a 32-bit non address operand in command 408be1da707SZhi Wang * bit 1 means address operand, which could be 32-bit 409be1da707SZhi Wang * or 64-bit depending on different architectures.( 410be1da707SZhi Wang * defined by "gmadr_bytes_in_cmd" in intel_gvt. 411be1da707SZhi Wang * No matter the address length, each address only takes 412be1da707SZhi Wang * one bit in the bitmap. 413be1da707SZhi Wang */ 414be1da707SZhi Wang uint16_t addr_bitmap; 415be1da707SZhi Wang 416be1da707SZhi Wang /* flag == F_LEN_CONST : command length 417be1da707SZhi Wang * flag == F_LEN_VAR : length bias bits 418be1da707SZhi Wang * Note: length is in DWord 419be1da707SZhi Wang */ 420be1da707SZhi Wang uint8_t len; 421be1da707SZhi Wang 422be1da707SZhi Wang parser_cmd_handler handler; 423be1da707SZhi Wang }; 424be1da707SZhi Wang 425be1da707SZhi Wang struct cmd_entry { 426be1da707SZhi Wang struct hlist_node hlist; 427be1da707SZhi Wang struct cmd_info *info; 428be1da707SZhi Wang }; 429be1da707SZhi Wang 430be1da707SZhi Wang enum { 431be1da707SZhi Wang RING_BUFFER_INSTRUCTION, 432be1da707SZhi Wang BATCH_BUFFER_INSTRUCTION, 433be1da707SZhi Wang BATCH_BUFFER_2ND_LEVEL, 434be1da707SZhi Wang }; 435be1da707SZhi Wang 436be1da707SZhi Wang enum { 437be1da707SZhi Wang GTT_BUFFER, 438be1da707SZhi Wang PPGTT_BUFFER 439be1da707SZhi Wang }; 440be1da707SZhi Wang 441be1da707SZhi Wang struct parser_exec_state { 442be1da707SZhi Wang struct intel_vgpu *vgpu; 443be1da707SZhi Wang int ring_id; 444be1da707SZhi Wang 445be1da707SZhi Wang int buf_type; 446be1da707SZhi Wang 447be1da707SZhi Wang /* batch buffer address type */ 448be1da707SZhi Wang int buf_addr_type; 449be1da707SZhi Wang 450be1da707SZhi Wang /* graphics memory address of ring buffer start */ 451be1da707SZhi Wang unsigned long ring_start; 452be1da707SZhi Wang unsigned long ring_size; 453be1da707SZhi Wang unsigned long ring_head; 454be1da707SZhi Wang unsigned long ring_tail; 455be1da707SZhi Wang 456be1da707SZhi Wang /* instruction graphics memory address */ 457be1da707SZhi Wang unsigned long ip_gma; 458be1da707SZhi Wang 459be1da707SZhi Wang /* mapped va of the instr_gma */ 460be1da707SZhi Wang void *ip_va; 461be1da707SZhi Wang void *rb_va; 462be1da707SZhi Wang 463be1da707SZhi Wang void *ret_bb_va; 464be1da707SZhi Wang /* next instruction when return from batch buffer to ring buffer */ 465be1da707SZhi Wang unsigned long ret_ip_gma_ring; 466be1da707SZhi Wang 467be1da707SZhi Wang /* next instruction when return from 2nd batch buffer to batch buffer */ 468be1da707SZhi Wang unsigned long ret_ip_gma_bb; 469be1da707SZhi Wang 470be1da707SZhi Wang /* batch buffer address type (GTT or PPGTT) 471be1da707SZhi Wang * used when ret from 2nd level batch buffer 472be1da707SZhi Wang */ 473be1da707SZhi Wang int saved_buf_addr_type; 474ef75c685Sfred gao bool is_ctx_wa; 475be1da707SZhi Wang 476be1da707SZhi Wang struct cmd_info *info; 477be1da707SZhi Wang 478be1da707SZhi Wang struct intel_vgpu_workload *workload; 479be1da707SZhi Wang }; 480be1da707SZhi Wang 481be1da707SZhi Wang #define gmadr_dw_number(s) \ 482be1da707SZhi Wang (s->vgpu->gvt->device_info.gmadr_bytes_in_cmd >> 2) 483be1da707SZhi Wang 484999ccb40SDu, Changbin static unsigned long bypass_scan_mask = 0; 485be1da707SZhi Wang 486be1da707SZhi Wang /* ring ALL, type = 0 */ 487be1da707SZhi Wang static struct sub_op_bits sub_op_mi[] = { 488be1da707SZhi Wang {31, 29}, 489be1da707SZhi Wang {28, 23}, 490be1da707SZhi Wang }; 491be1da707SZhi Wang 492be1da707SZhi Wang static struct decode_info decode_info_mi = { 493be1da707SZhi Wang "MI", 494be1da707SZhi Wang OP_LEN_MI, 495be1da707SZhi Wang ARRAY_SIZE(sub_op_mi), 496be1da707SZhi Wang sub_op_mi, 497be1da707SZhi Wang }; 498be1da707SZhi Wang 499be1da707SZhi Wang /* ring RCS, command type 2 */ 500be1da707SZhi Wang static struct sub_op_bits sub_op_2d[] = { 501be1da707SZhi Wang {31, 29}, 502be1da707SZhi Wang {28, 22}, 503be1da707SZhi Wang }; 504be1da707SZhi Wang 505be1da707SZhi Wang static struct decode_info decode_info_2d = { 506be1da707SZhi Wang "2D", 507be1da707SZhi Wang OP_LEN_2D, 508be1da707SZhi Wang ARRAY_SIZE(sub_op_2d), 509be1da707SZhi Wang sub_op_2d, 510be1da707SZhi Wang }; 511be1da707SZhi Wang 512be1da707SZhi Wang /* ring RCS, command type 3 */ 513be1da707SZhi Wang static struct sub_op_bits sub_op_3d_media[] = { 514be1da707SZhi Wang {31, 29}, 515be1da707SZhi Wang {28, 27}, 516be1da707SZhi Wang {26, 24}, 517be1da707SZhi Wang {23, 16}, 518be1da707SZhi Wang }; 519be1da707SZhi Wang 520be1da707SZhi Wang static struct decode_info decode_info_3d_media = { 521be1da707SZhi Wang "3D_Media", 522be1da707SZhi Wang OP_LEN_3D_MEDIA, 523be1da707SZhi Wang ARRAY_SIZE(sub_op_3d_media), 524be1da707SZhi Wang sub_op_3d_media, 525be1da707SZhi Wang }; 526be1da707SZhi Wang 527be1da707SZhi Wang /* ring VCS, command type 3 */ 528be1da707SZhi Wang static struct sub_op_bits sub_op_mfx_vc[] = { 529be1da707SZhi Wang {31, 29}, 530be1da707SZhi Wang {28, 27}, 531be1da707SZhi Wang {26, 24}, 532be1da707SZhi Wang {23, 21}, 533be1da707SZhi Wang {20, 16}, 534be1da707SZhi Wang }; 535be1da707SZhi Wang 536be1da707SZhi Wang static struct decode_info decode_info_mfx_vc = { 537be1da707SZhi Wang "MFX_VC", 538be1da707SZhi Wang OP_LEN_MFX_VC, 539be1da707SZhi Wang ARRAY_SIZE(sub_op_mfx_vc), 540be1da707SZhi Wang sub_op_mfx_vc, 541be1da707SZhi Wang }; 542be1da707SZhi Wang 543be1da707SZhi Wang /* ring VECS, command type 3 */ 544be1da707SZhi Wang static struct sub_op_bits sub_op_vebox[] = { 545be1da707SZhi Wang {31, 29}, 546be1da707SZhi Wang {28, 27}, 547be1da707SZhi Wang {26, 24}, 548be1da707SZhi Wang {23, 21}, 549be1da707SZhi Wang {20, 16}, 550be1da707SZhi Wang }; 551be1da707SZhi Wang 552be1da707SZhi Wang static struct decode_info decode_info_vebox = { 553be1da707SZhi Wang "VEBOX", 554be1da707SZhi Wang OP_LEN_VEBOX, 555be1da707SZhi Wang ARRAY_SIZE(sub_op_vebox), 556be1da707SZhi Wang sub_op_vebox, 557be1da707SZhi Wang }; 558be1da707SZhi Wang 559be1da707SZhi Wang static struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = { 560be1da707SZhi Wang [RCS] = { 561be1da707SZhi Wang &decode_info_mi, 562be1da707SZhi Wang NULL, 563be1da707SZhi Wang NULL, 564be1da707SZhi Wang &decode_info_3d_media, 565be1da707SZhi Wang NULL, 566be1da707SZhi Wang NULL, 567be1da707SZhi Wang NULL, 568be1da707SZhi Wang NULL, 569be1da707SZhi Wang }, 570be1da707SZhi Wang 571be1da707SZhi Wang [VCS] = { 572be1da707SZhi Wang &decode_info_mi, 573be1da707SZhi Wang NULL, 574be1da707SZhi Wang NULL, 575be1da707SZhi Wang &decode_info_mfx_vc, 576be1da707SZhi Wang NULL, 577be1da707SZhi Wang NULL, 578be1da707SZhi Wang NULL, 579be1da707SZhi Wang NULL, 580be1da707SZhi Wang }, 581be1da707SZhi Wang 582be1da707SZhi Wang [BCS] = { 583be1da707SZhi Wang &decode_info_mi, 584be1da707SZhi Wang NULL, 585be1da707SZhi Wang &decode_info_2d, 586be1da707SZhi Wang NULL, 587be1da707SZhi Wang NULL, 588be1da707SZhi Wang NULL, 589be1da707SZhi Wang NULL, 590be1da707SZhi Wang NULL, 591be1da707SZhi Wang }, 592be1da707SZhi Wang 593be1da707SZhi Wang [VECS] = { 594be1da707SZhi Wang &decode_info_mi, 595be1da707SZhi Wang NULL, 596be1da707SZhi Wang NULL, 597be1da707SZhi Wang &decode_info_vebox, 598be1da707SZhi Wang NULL, 599be1da707SZhi Wang NULL, 600be1da707SZhi Wang NULL, 601be1da707SZhi Wang NULL, 602be1da707SZhi Wang }, 603be1da707SZhi Wang 604be1da707SZhi Wang [VCS2] = { 605be1da707SZhi Wang &decode_info_mi, 606be1da707SZhi Wang NULL, 607be1da707SZhi Wang NULL, 608be1da707SZhi Wang &decode_info_mfx_vc, 609be1da707SZhi Wang NULL, 610be1da707SZhi Wang NULL, 611be1da707SZhi Wang NULL, 612be1da707SZhi Wang NULL, 613be1da707SZhi Wang }, 614be1da707SZhi Wang }; 615be1da707SZhi Wang 616be1da707SZhi Wang static inline u32 get_opcode(u32 cmd, int ring_id) 617be1da707SZhi Wang { 618be1da707SZhi Wang struct decode_info *d_info; 619be1da707SZhi Wang 620be1da707SZhi Wang d_info = ring_decode_info[ring_id][CMD_TYPE(cmd)]; 621be1da707SZhi Wang if (d_info == NULL) 622be1da707SZhi Wang return INVALID_OP; 623be1da707SZhi Wang 624be1da707SZhi Wang return cmd >> (32 - d_info->op_len); 625be1da707SZhi Wang } 626be1da707SZhi Wang 627be1da707SZhi Wang static inline struct cmd_info *find_cmd_entry(struct intel_gvt *gvt, 628be1da707SZhi Wang unsigned int opcode, int ring_id) 629be1da707SZhi Wang { 630be1da707SZhi Wang struct cmd_entry *e; 631be1da707SZhi Wang 632be1da707SZhi Wang hash_for_each_possible(gvt->cmd_table, e, hlist, opcode) { 633be1da707SZhi Wang if ((opcode == e->info->opcode) && 634be1da707SZhi Wang (e->info->rings & (1 << ring_id))) 635be1da707SZhi Wang return e->info; 636be1da707SZhi Wang } 637be1da707SZhi Wang return NULL; 638be1da707SZhi Wang } 639be1da707SZhi Wang 640be1da707SZhi Wang static inline struct cmd_info *get_cmd_info(struct intel_gvt *gvt, 641be1da707SZhi Wang u32 cmd, int ring_id) 642be1da707SZhi Wang { 643be1da707SZhi Wang u32 opcode; 644be1da707SZhi Wang 645be1da707SZhi Wang opcode = get_opcode(cmd, ring_id); 646be1da707SZhi Wang if (opcode == INVALID_OP) 647be1da707SZhi Wang return NULL; 648be1da707SZhi Wang 649be1da707SZhi Wang return find_cmd_entry(gvt, opcode, ring_id); 650be1da707SZhi Wang } 651be1da707SZhi Wang 652be1da707SZhi Wang static inline u32 sub_op_val(u32 cmd, u32 hi, u32 low) 653be1da707SZhi Wang { 654be1da707SZhi Wang return (cmd >> low) & ((1U << (hi - low + 1)) - 1); 655be1da707SZhi Wang } 656be1da707SZhi Wang 657be1da707SZhi Wang static inline void print_opcode(u32 cmd, int ring_id) 658be1da707SZhi Wang { 659be1da707SZhi Wang struct decode_info *d_info; 660be1da707SZhi Wang int i; 661be1da707SZhi Wang 662be1da707SZhi Wang d_info = ring_decode_info[ring_id][CMD_TYPE(cmd)]; 663be1da707SZhi Wang if (d_info == NULL) 664be1da707SZhi Wang return; 665be1da707SZhi Wang 666627c845cSTina Zhang gvt_dbg_cmd("opcode=0x%x %s sub_ops:", 667be1da707SZhi Wang cmd >> (32 - d_info->op_len), d_info->name); 668be1da707SZhi Wang 669be1da707SZhi Wang for (i = 0; i < d_info->nr_sub_op; i++) 670be1da707SZhi Wang pr_err("0x%x ", sub_op_val(cmd, d_info->sub_op[i].hi, 671be1da707SZhi Wang d_info->sub_op[i].low)); 672be1da707SZhi Wang 673be1da707SZhi Wang pr_err("\n"); 674be1da707SZhi Wang } 675be1da707SZhi Wang 676be1da707SZhi Wang static inline u32 *cmd_ptr(struct parser_exec_state *s, int index) 677be1da707SZhi Wang { 678be1da707SZhi Wang return s->ip_va + (index << 2); 679be1da707SZhi Wang } 680be1da707SZhi Wang 681be1da707SZhi Wang static inline u32 cmd_val(struct parser_exec_state *s, int index) 682be1da707SZhi Wang { 683be1da707SZhi Wang return *cmd_ptr(s, index); 684be1da707SZhi Wang } 685be1da707SZhi Wang 686be1da707SZhi Wang static void parser_exec_state_dump(struct parser_exec_state *s) 687be1da707SZhi Wang { 688be1da707SZhi Wang int cnt = 0; 689be1da707SZhi Wang int i; 690be1da707SZhi Wang 691627c845cSTina Zhang gvt_dbg_cmd(" vgpu%d RING%d: ring_start(%08lx) ring_end(%08lx)" 692be1da707SZhi Wang " ring_head(%08lx) ring_tail(%08lx)\n", s->vgpu->id, 693be1da707SZhi Wang s->ring_id, s->ring_start, s->ring_start + s->ring_size, 694be1da707SZhi Wang s->ring_head, s->ring_tail); 695be1da707SZhi Wang 696627c845cSTina Zhang gvt_dbg_cmd(" %s %s ip_gma(%08lx) ", 697be1da707SZhi Wang s->buf_type == RING_BUFFER_INSTRUCTION ? 698be1da707SZhi Wang "RING_BUFFER" : "BATCH_BUFFER", 699be1da707SZhi Wang s->buf_addr_type == GTT_BUFFER ? 700be1da707SZhi Wang "GTT" : "PPGTT", s->ip_gma); 701be1da707SZhi Wang 702be1da707SZhi Wang if (s->ip_va == NULL) { 703627c845cSTina Zhang gvt_dbg_cmd(" ip_va(NULL)"); 704be1da707SZhi Wang return; 705be1da707SZhi Wang } 706be1da707SZhi Wang 707627c845cSTina Zhang gvt_dbg_cmd(" ip_va=%p: %08x %08x %08x %08x\n", 708be1da707SZhi Wang s->ip_va, cmd_val(s, 0), cmd_val(s, 1), 709be1da707SZhi Wang cmd_val(s, 2), cmd_val(s, 3)); 710be1da707SZhi Wang 711be1da707SZhi Wang print_opcode(cmd_val(s, 0), s->ring_id); 712be1da707SZhi Wang 713be1da707SZhi Wang s->ip_va = (u32 *)((((u64)s->ip_va) >> 12) << 12); 714be1da707SZhi Wang 715be1da707SZhi Wang while (cnt < 1024) { 716e4aeba69SChangbin Du gvt_dbg_cmd("ip_va=%p: ", s->ip_va); 717be1da707SZhi Wang for (i = 0; i < 8; i++) 718e4aeba69SChangbin Du gvt_dbg_cmd("%08x ", cmd_val(s, i)); 719e4aeba69SChangbin Du gvt_dbg_cmd("\n"); 720be1da707SZhi Wang 721be1da707SZhi Wang s->ip_va += 8 * sizeof(u32); 722be1da707SZhi Wang cnt += 8; 723be1da707SZhi Wang } 724be1da707SZhi Wang } 725be1da707SZhi Wang 726be1da707SZhi Wang static inline void update_ip_va(struct parser_exec_state *s) 727be1da707SZhi Wang { 728be1da707SZhi Wang unsigned long len = 0; 729be1da707SZhi Wang 730be1da707SZhi Wang if (WARN_ON(s->ring_head == s->ring_tail)) 731be1da707SZhi Wang return; 732be1da707SZhi Wang 733be1da707SZhi Wang if (s->buf_type == RING_BUFFER_INSTRUCTION) { 734be1da707SZhi Wang unsigned long ring_top = s->ring_start + s->ring_size; 735be1da707SZhi Wang 736be1da707SZhi Wang if (s->ring_head > s->ring_tail) { 737be1da707SZhi Wang if (s->ip_gma >= s->ring_head && s->ip_gma < ring_top) 738be1da707SZhi Wang len = (s->ip_gma - s->ring_head); 739be1da707SZhi Wang else if (s->ip_gma >= s->ring_start && 740be1da707SZhi Wang s->ip_gma <= s->ring_tail) 741be1da707SZhi Wang len = (ring_top - s->ring_head) + 742be1da707SZhi Wang (s->ip_gma - s->ring_start); 743be1da707SZhi Wang } else 744be1da707SZhi Wang len = (s->ip_gma - s->ring_head); 745be1da707SZhi Wang 746be1da707SZhi Wang s->ip_va = s->rb_va + len; 747be1da707SZhi Wang } else {/* shadow batch buffer */ 748be1da707SZhi Wang s->ip_va = s->ret_bb_va; 749be1da707SZhi Wang } 750be1da707SZhi Wang } 751be1da707SZhi Wang 752be1da707SZhi Wang static inline int ip_gma_set(struct parser_exec_state *s, 753be1da707SZhi Wang unsigned long ip_gma) 754be1da707SZhi Wang { 755be1da707SZhi Wang WARN_ON(!IS_ALIGNED(ip_gma, 4)); 756be1da707SZhi Wang 757be1da707SZhi Wang s->ip_gma = ip_gma; 758be1da707SZhi Wang update_ip_va(s); 759be1da707SZhi Wang return 0; 760be1da707SZhi Wang } 761be1da707SZhi Wang 762be1da707SZhi Wang static inline int ip_gma_advance(struct parser_exec_state *s, 763be1da707SZhi Wang unsigned int dw_len) 764be1da707SZhi Wang { 765be1da707SZhi Wang s->ip_gma += (dw_len << 2); 766be1da707SZhi Wang 767be1da707SZhi Wang if (s->buf_type == RING_BUFFER_INSTRUCTION) { 768be1da707SZhi Wang if (s->ip_gma >= s->ring_start + s->ring_size) 769be1da707SZhi Wang s->ip_gma -= s->ring_size; 770be1da707SZhi Wang update_ip_va(s); 771be1da707SZhi Wang } else { 772be1da707SZhi Wang s->ip_va += (dw_len << 2); 773be1da707SZhi Wang } 774be1da707SZhi Wang 775be1da707SZhi Wang return 0; 776be1da707SZhi Wang } 777be1da707SZhi Wang 778be1da707SZhi Wang static inline int get_cmd_length(struct cmd_info *info, u32 cmd) 779be1da707SZhi Wang { 780be1da707SZhi Wang if ((info->flag & F_LEN_MASK) == F_LEN_CONST) 781be1da707SZhi Wang return info->len; 782be1da707SZhi Wang else 783be1da707SZhi Wang return (cmd & ((1U << info->len) - 1)) + 2; 784be1da707SZhi Wang return 0; 785be1da707SZhi Wang } 786be1da707SZhi Wang 787be1da707SZhi Wang static inline int cmd_length(struct parser_exec_state *s) 788be1da707SZhi Wang { 789be1da707SZhi Wang return get_cmd_length(s->info, cmd_val(s, 0)); 790be1da707SZhi Wang } 791be1da707SZhi Wang 792be1da707SZhi Wang /* do not remove this, some platform may need clflush here */ 793be1da707SZhi Wang #define patch_value(s, addr, val) do { \ 794be1da707SZhi Wang *addr = val; \ 795be1da707SZhi Wang } while (0) 796be1da707SZhi Wang 797be1da707SZhi Wang static bool is_shadowed_mmio(unsigned int offset) 798be1da707SZhi Wang { 799be1da707SZhi Wang bool ret = false; 800be1da707SZhi Wang 801be1da707SZhi Wang if ((offset == 0x2168) || /*BB current head register UDW */ 802be1da707SZhi Wang (offset == 0x2140) || /*BB current header register */ 803be1da707SZhi Wang (offset == 0x211c) || /*second BB header register UDW */ 804be1da707SZhi Wang (offset == 0x2114)) { /*second BB header register UDW */ 805be1da707SZhi Wang ret = true; 806be1da707SZhi Wang } 807be1da707SZhi Wang return ret; 808be1da707SZhi Wang } 809be1da707SZhi Wang 8104938ca90SZhao Yan static inline bool is_force_nonpriv_mmio(unsigned int offset) 8114938ca90SZhao Yan { 8124938ca90SZhao Yan return (offset >= 0x24d0 && offset < 0x2500); 8134938ca90SZhao Yan } 8144938ca90SZhao Yan 8154938ca90SZhao Yan static int force_nonpriv_reg_handler(struct parser_exec_state *s, 8164938ca90SZhao Yan unsigned int offset, unsigned int index) 8174938ca90SZhao Yan { 8184938ca90SZhao Yan struct intel_gvt *gvt = s->vgpu->gvt; 8194938ca90SZhao Yan unsigned int data = cmd_val(s, index + 1); 8204938ca90SZhao Yan 8214938ca90SZhao Yan if (!intel_gvt_in_force_nonpriv_whitelist(gvt, data)) { 8224938ca90SZhao Yan gvt_err("Unexpected forcenonpriv 0x%x LRI write, value=0x%x\n", 8234938ca90SZhao Yan offset, data); 8245c56883aSfred gao return -EPERM; 8254938ca90SZhao Yan } 8264938ca90SZhao Yan return 0; 8274938ca90SZhao Yan } 8284938ca90SZhao Yan 829f402f2d6SWeinan Li static inline bool is_mocs_mmio(unsigned int offset) 830f402f2d6SWeinan Li { 831f402f2d6SWeinan Li return ((offset >= 0xc800) && (offset <= 0xcff8)) || 832f402f2d6SWeinan Li ((offset >= 0xb020) && (offset <= 0xb0a0)); 833f402f2d6SWeinan Li } 834f402f2d6SWeinan Li 835f402f2d6SWeinan Li static int mocs_cmd_reg_handler(struct parser_exec_state *s, 836f402f2d6SWeinan Li unsigned int offset, unsigned int index) 837f402f2d6SWeinan Li { 838f402f2d6SWeinan Li if (!is_mocs_mmio(offset)) 839f402f2d6SWeinan Li return -EINVAL; 840f402f2d6SWeinan Li vgpu_vreg(s->vgpu, offset) = cmd_val(s, index + 1); 841f402f2d6SWeinan Li return 0; 842f402f2d6SWeinan Li } 843f402f2d6SWeinan Li 844be1da707SZhi Wang static int cmd_reg_handler(struct parser_exec_state *s, 845be1da707SZhi Wang unsigned int offset, unsigned int index, char *cmd) 846be1da707SZhi Wang { 847be1da707SZhi Wang struct intel_vgpu *vgpu = s->vgpu; 848be1da707SZhi Wang struct intel_gvt *gvt = vgpu->gvt; 849be1da707SZhi Wang 850be1da707SZhi Wang if (offset + 4 > gvt->device_info.mmio_size) { 851695fbc08STina Zhang gvt_vgpu_err("%s access to (%x) outside of MMIO range\n", 852be1da707SZhi Wang cmd, offset); 8535c56883aSfred gao return -EFAULT; 854be1da707SZhi Wang } 855be1da707SZhi Wang 856be1da707SZhi Wang if (!intel_gvt_mmio_is_cmd_access(gvt, offset)) { 857695fbc08STina Zhang gvt_vgpu_err("%s access to non-render register (%x)\n", 858695fbc08STina Zhang cmd, offset); 859be1da707SZhi Wang return 0; 860be1da707SZhi Wang } 861be1da707SZhi Wang 862be1da707SZhi Wang if (is_shadowed_mmio(offset)) { 863695fbc08STina Zhang gvt_vgpu_err("found access of shadowed MMIO %x\n", offset); 864be1da707SZhi Wang return 0; 865be1da707SZhi Wang } 866be1da707SZhi Wang 867f402f2d6SWeinan Li if (is_mocs_mmio(offset) && 868f402f2d6SWeinan Li mocs_cmd_reg_handler(s, offset, index)) 869f402f2d6SWeinan Li return -EINVAL; 870f402f2d6SWeinan Li 8714938ca90SZhao Yan if (is_force_nonpriv_mmio(offset) && 8724938ca90SZhao Yan force_nonpriv_reg_handler(s, offset, index)) 8735c56883aSfred gao return -EPERM; 8744938ca90SZhao Yan 875be1da707SZhi Wang if (offset == i915_mmio_reg_offset(DERRMR) || 876be1da707SZhi Wang offset == i915_mmio_reg_offset(FORCEWAKE_MT)) { 877be1da707SZhi Wang /* Writing to HW VGT_PVINFO_PAGE offset will be discarded */ 878be1da707SZhi Wang patch_value(s, cmd_ptr(s, index), VGT_PVINFO_PAGE); 879be1da707SZhi Wang } 880be1da707SZhi Wang 881be1da707SZhi Wang /* TODO: Update the global mask if this MMIO is a masked-MMIO */ 882be1da707SZhi Wang intel_gvt_mmio_set_cmd_accessed(gvt, offset); 883be1da707SZhi Wang return 0; 884be1da707SZhi Wang } 885be1da707SZhi Wang 886be1da707SZhi Wang #define cmd_reg(s, i) \ 887be1da707SZhi Wang (cmd_val(s, i) & GENMASK(22, 2)) 888be1da707SZhi Wang 889be1da707SZhi Wang #define cmd_reg_inhibit(s, i) \ 890be1da707SZhi Wang (cmd_val(s, i) & GENMASK(22, 18)) 891be1da707SZhi Wang 892be1da707SZhi Wang #define cmd_gma(s, i) \ 893be1da707SZhi Wang (cmd_val(s, i) & GENMASK(31, 2)) 894be1da707SZhi Wang 895be1da707SZhi Wang #define cmd_gma_hi(s, i) \ 896be1da707SZhi Wang (cmd_val(s, i) & GENMASK(15, 0)) 897be1da707SZhi Wang 898be1da707SZhi Wang static int cmd_handler_lri(struct parser_exec_state *s) 899be1da707SZhi Wang { 900be1da707SZhi Wang int i, ret = 0; 901be1da707SZhi Wang int cmd_len = cmd_length(s); 902be1da707SZhi Wang struct intel_gvt *gvt = s->vgpu->gvt; 903be1da707SZhi Wang 904be1da707SZhi Wang for (i = 1; i < cmd_len; i += 2) { 905be1da707SZhi Wang if (IS_BROADWELL(gvt->dev_priv) && 906be1da707SZhi Wang (s->ring_id != RCS)) { 907be1da707SZhi Wang if (s->ring_id == BCS && 908be1da707SZhi Wang cmd_reg(s, i) == 909be1da707SZhi Wang i915_mmio_reg_offset(DERRMR)) 910be1da707SZhi Wang ret |= 0; 911be1da707SZhi Wang else 9125c56883aSfred gao ret |= (cmd_reg_inhibit(s, i)) ? 9135c56883aSfred gao -EBADRQC : 0; 914be1da707SZhi Wang } 915be1da707SZhi Wang if (ret) 916be1da707SZhi Wang break; 917be1da707SZhi Wang ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lri"); 9185c56883aSfred gao if (ret) 9195c56883aSfred gao break; 920be1da707SZhi Wang } 921be1da707SZhi Wang return ret; 922be1da707SZhi Wang } 923be1da707SZhi Wang 924be1da707SZhi Wang static int cmd_handler_lrr(struct parser_exec_state *s) 925be1da707SZhi Wang { 926be1da707SZhi Wang int i, ret = 0; 927be1da707SZhi Wang int cmd_len = cmd_length(s); 928be1da707SZhi Wang 929be1da707SZhi Wang for (i = 1; i < cmd_len; i += 2) { 930be1da707SZhi Wang if (IS_BROADWELL(s->vgpu->gvt->dev_priv)) 931be1da707SZhi Wang ret |= ((cmd_reg_inhibit(s, i) || 932be1da707SZhi Wang (cmd_reg_inhibit(s, i + 1)))) ? 9335c56883aSfred gao -EBADRQC : 0; 934be1da707SZhi Wang if (ret) 935be1da707SZhi Wang break; 936be1da707SZhi Wang ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrr-src"); 9375c56883aSfred gao if (ret) 9385c56883aSfred gao break; 939be1da707SZhi Wang ret |= cmd_reg_handler(s, cmd_reg(s, i + 1), i, "lrr-dst"); 9405c56883aSfred gao if (ret) 9415c56883aSfred gao break; 942be1da707SZhi Wang } 943be1da707SZhi Wang return ret; 944be1da707SZhi Wang } 945be1da707SZhi Wang 946be1da707SZhi Wang static inline int cmd_address_audit(struct parser_exec_state *s, 947be1da707SZhi Wang unsigned long guest_gma, int op_size, bool index_mode); 948be1da707SZhi Wang 949be1da707SZhi Wang static int cmd_handler_lrm(struct parser_exec_state *s) 950be1da707SZhi Wang { 951be1da707SZhi Wang struct intel_gvt *gvt = s->vgpu->gvt; 952be1da707SZhi Wang int gmadr_bytes = gvt->device_info.gmadr_bytes_in_cmd; 953be1da707SZhi Wang unsigned long gma; 954be1da707SZhi Wang int i, ret = 0; 955be1da707SZhi Wang int cmd_len = cmd_length(s); 956be1da707SZhi Wang 957be1da707SZhi Wang for (i = 1; i < cmd_len;) { 958be1da707SZhi Wang if (IS_BROADWELL(gvt->dev_priv)) 9595c56883aSfred gao ret |= (cmd_reg_inhibit(s, i)) ? -EBADRQC : 0; 960be1da707SZhi Wang if (ret) 961be1da707SZhi Wang break; 962be1da707SZhi Wang ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrm"); 9635c56883aSfred gao if (ret) 9645c56883aSfred gao break; 965be1da707SZhi Wang if (cmd_val(s, 0) & (1 << 22)) { 966be1da707SZhi Wang gma = cmd_gma(s, i + 1); 967be1da707SZhi Wang if (gmadr_bytes == 8) 968be1da707SZhi Wang gma |= (cmd_gma_hi(s, i + 2)) << 32; 969be1da707SZhi Wang ret |= cmd_address_audit(s, gma, sizeof(u32), false); 9705c56883aSfred gao if (ret) 9715c56883aSfred gao break; 972be1da707SZhi Wang } 973be1da707SZhi Wang i += gmadr_dw_number(s) + 1; 974be1da707SZhi Wang } 975be1da707SZhi Wang return ret; 976be1da707SZhi Wang } 977be1da707SZhi Wang 978be1da707SZhi Wang static int cmd_handler_srm(struct parser_exec_state *s) 979be1da707SZhi Wang { 980be1da707SZhi Wang int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd; 981be1da707SZhi Wang unsigned long gma; 982be1da707SZhi Wang int i, ret = 0; 983be1da707SZhi Wang int cmd_len = cmd_length(s); 984be1da707SZhi Wang 985be1da707SZhi Wang for (i = 1; i < cmd_len;) { 986be1da707SZhi Wang ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "srm"); 9875c56883aSfred gao if (ret) 9885c56883aSfred gao break; 989be1da707SZhi Wang if (cmd_val(s, 0) & (1 << 22)) { 990be1da707SZhi Wang gma = cmd_gma(s, i + 1); 991be1da707SZhi Wang if (gmadr_bytes == 8) 992be1da707SZhi Wang gma |= (cmd_gma_hi(s, i + 2)) << 32; 993be1da707SZhi Wang ret |= cmd_address_audit(s, gma, sizeof(u32), false); 9945c56883aSfred gao if (ret) 9955c56883aSfred gao break; 996be1da707SZhi Wang } 997be1da707SZhi Wang i += gmadr_dw_number(s) + 1; 998be1da707SZhi Wang } 999be1da707SZhi Wang return ret; 1000be1da707SZhi Wang } 1001be1da707SZhi Wang 1002be1da707SZhi Wang struct cmd_interrupt_event { 1003be1da707SZhi Wang int pipe_control_notify; 1004be1da707SZhi Wang int mi_flush_dw; 1005be1da707SZhi Wang int mi_user_interrupt; 1006be1da707SZhi Wang }; 1007be1da707SZhi Wang 1008999ccb40SDu, Changbin static struct cmd_interrupt_event cmd_interrupt_events[] = { 1009be1da707SZhi Wang [RCS] = { 1010be1da707SZhi Wang .pipe_control_notify = RCS_PIPE_CONTROL, 1011be1da707SZhi Wang .mi_flush_dw = INTEL_GVT_EVENT_RESERVED, 1012be1da707SZhi Wang .mi_user_interrupt = RCS_MI_USER_INTERRUPT, 1013be1da707SZhi Wang }, 1014be1da707SZhi Wang [BCS] = { 1015be1da707SZhi Wang .pipe_control_notify = INTEL_GVT_EVENT_RESERVED, 1016be1da707SZhi Wang .mi_flush_dw = BCS_MI_FLUSH_DW, 1017be1da707SZhi Wang .mi_user_interrupt = BCS_MI_USER_INTERRUPT, 1018be1da707SZhi Wang }, 1019be1da707SZhi Wang [VCS] = { 1020be1da707SZhi Wang .pipe_control_notify = INTEL_GVT_EVENT_RESERVED, 1021be1da707SZhi Wang .mi_flush_dw = VCS_MI_FLUSH_DW, 1022be1da707SZhi Wang .mi_user_interrupt = VCS_MI_USER_INTERRUPT, 1023be1da707SZhi Wang }, 1024be1da707SZhi Wang [VCS2] = { 1025be1da707SZhi Wang .pipe_control_notify = INTEL_GVT_EVENT_RESERVED, 1026be1da707SZhi Wang .mi_flush_dw = VCS2_MI_FLUSH_DW, 1027be1da707SZhi Wang .mi_user_interrupt = VCS2_MI_USER_INTERRUPT, 1028be1da707SZhi Wang }, 1029be1da707SZhi Wang [VECS] = { 1030be1da707SZhi Wang .pipe_control_notify = INTEL_GVT_EVENT_RESERVED, 1031be1da707SZhi Wang .mi_flush_dw = VECS_MI_FLUSH_DW, 1032be1da707SZhi Wang .mi_user_interrupt = VECS_MI_USER_INTERRUPT, 1033be1da707SZhi Wang }, 1034be1da707SZhi Wang }; 1035be1da707SZhi Wang 1036be1da707SZhi Wang static int cmd_handler_pipe_control(struct parser_exec_state *s) 1037be1da707SZhi Wang { 1038be1da707SZhi Wang int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd; 1039be1da707SZhi Wang unsigned long gma; 1040be1da707SZhi Wang bool index_mode = false; 1041be1da707SZhi Wang unsigned int post_sync; 1042be1da707SZhi Wang int ret = 0; 1043be1da707SZhi Wang 1044be1da707SZhi Wang post_sync = (cmd_val(s, 1) & PIPE_CONTROL_POST_SYNC_OP_MASK) >> 14; 1045be1da707SZhi Wang 1046be1da707SZhi Wang /* LRI post sync */ 1047be1da707SZhi Wang if (cmd_val(s, 1) & PIPE_CONTROL_MMIO_WRITE) 1048be1da707SZhi Wang ret = cmd_reg_handler(s, cmd_reg(s, 2), 1, "pipe_ctrl"); 1049be1da707SZhi Wang /* post sync */ 1050be1da707SZhi Wang else if (post_sync) { 1051be1da707SZhi Wang if (post_sync == 2) 1052be1da707SZhi Wang ret = cmd_reg_handler(s, 0x2350, 1, "pipe_ctrl"); 1053be1da707SZhi Wang else if (post_sync == 3) 1054be1da707SZhi Wang ret = cmd_reg_handler(s, 0x2358, 1, "pipe_ctrl"); 1055be1da707SZhi Wang else if (post_sync == 1) { 1056be1da707SZhi Wang /* check ggtt*/ 10573f765a34SYulei Zhang if ((cmd_val(s, 1) & PIPE_CONTROL_GLOBAL_GTT_IVB)) { 1058be1da707SZhi Wang gma = cmd_val(s, 2) & GENMASK(31, 3); 1059be1da707SZhi Wang if (gmadr_bytes == 8) 1060be1da707SZhi Wang gma |= (cmd_gma_hi(s, 3)) << 32; 1061be1da707SZhi Wang /* Store Data Index */ 1062be1da707SZhi Wang if (cmd_val(s, 1) & (1 << 21)) 1063be1da707SZhi Wang index_mode = true; 1064be1da707SZhi Wang ret |= cmd_address_audit(s, gma, sizeof(u64), 1065be1da707SZhi Wang index_mode); 1066be1da707SZhi Wang } 1067be1da707SZhi Wang } 1068be1da707SZhi Wang } 1069be1da707SZhi Wang 1070be1da707SZhi Wang if (ret) 1071be1da707SZhi Wang return ret; 1072be1da707SZhi Wang 1073be1da707SZhi Wang if (cmd_val(s, 1) & PIPE_CONTROL_NOTIFY) 1074be1da707SZhi Wang set_bit(cmd_interrupt_events[s->ring_id].pipe_control_notify, 1075be1da707SZhi Wang s->workload->pending_events); 1076be1da707SZhi Wang return 0; 1077be1da707SZhi Wang } 1078be1da707SZhi Wang 1079be1da707SZhi Wang static int cmd_handler_mi_user_interrupt(struct parser_exec_state *s) 1080be1da707SZhi Wang { 1081be1da707SZhi Wang set_bit(cmd_interrupt_events[s->ring_id].mi_user_interrupt, 1082be1da707SZhi Wang s->workload->pending_events); 1083be1da707SZhi Wang return 0; 1084be1da707SZhi Wang } 1085be1da707SZhi Wang 1086be1da707SZhi Wang static int cmd_advance_default(struct parser_exec_state *s) 1087be1da707SZhi Wang { 1088be1da707SZhi Wang return ip_gma_advance(s, cmd_length(s)); 1089be1da707SZhi Wang } 1090be1da707SZhi Wang 1091be1da707SZhi Wang static int cmd_handler_mi_batch_buffer_end(struct parser_exec_state *s) 1092be1da707SZhi Wang { 1093be1da707SZhi Wang int ret; 1094be1da707SZhi Wang 1095be1da707SZhi Wang if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) { 1096be1da707SZhi Wang s->buf_type = BATCH_BUFFER_INSTRUCTION; 1097be1da707SZhi Wang ret = ip_gma_set(s, s->ret_ip_gma_bb); 1098be1da707SZhi Wang s->buf_addr_type = s->saved_buf_addr_type; 1099be1da707SZhi Wang } else { 1100be1da707SZhi Wang s->buf_type = RING_BUFFER_INSTRUCTION; 1101be1da707SZhi Wang s->buf_addr_type = GTT_BUFFER; 1102be1da707SZhi Wang if (s->ret_ip_gma_ring >= s->ring_start + s->ring_size) 1103be1da707SZhi Wang s->ret_ip_gma_ring -= s->ring_size; 1104be1da707SZhi Wang ret = ip_gma_set(s, s->ret_ip_gma_ring); 1105be1da707SZhi Wang } 1106be1da707SZhi Wang return ret; 1107be1da707SZhi Wang } 1108be1da707SZhi Wang 1109be1da707SZhi Wang struct mi_display_flip_command_info { 1110be1da707SZhi Wang int pipe; 1111be1da707SZhi Wang int plane; 1112be1da707SZhi Wang int event; 1113be1da707SZhi Wang i915_reg_t stride_reg; 1114be1da707SZhi Wang i915_reg_t ctrl_reg; 1115be1da707SZhi Wang i915_reg_t surf_reg; 1116be1da707SZhi Wang u64 stride_val; 1117be1da707SZhi Wang u64 tile_val; 1118be1da707SZhi Wang u64 surf_val; 1119be1da707SZhi Wang bool async_flip; 1120be1da707SZhi Wang }; 1121be1da707SZhi Wang 1122be1da707SZhi Wang struct plane_code_mapping { 1123be1da707SZhi Wang int pipe; 1124be1da707SZhi Wang int plane; 1125be1da707SZhi Wang int event; 1126be1da707SZhi Wang }; 1127be1da707SZhi Wang 1128be1da707SZhi Wang static int gen8_decode_mi_display_flip(struct parser_exec_state *s, 1129be1da707SZhi Wang struct mi_display_flip_command_info *info) 1130be1da707SZhi Wang { 1131be1da707SZhi Wang struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv; 1132be1da707SZhi Wang struct plane_code_mapping gen8_plane_code[] = { 1133be1da707SZhi Wang [0] = {PIPE_A, PLANE_A, PRIMARY_A_FLIP_DONE}, 1134be1da707SZhi Wang [1] = {PIPE_B, PLANE_A, PRIMARY_B_FLIP_DONE}, 1135be1da707SZhi Wang [2] = {PIPE_A, PLANE_B, SPRITE_A_FLIP_DONE}, 1136be1da707SZhi Wang [3] = {PIPE_B, PLANE_B, SPRITE_B_FLIP_DONE}, 1137be1da707SZhi Wang [4] = {PIPE_C, PLANE_A, PRIMARY_C_FLIP_DONE}, 1138be1da707SZhi Wang [5] = {PIPE_C, PLANE_B, SPRITE_C_FLIP_DONE}, 1139be1da707SZhi Wang }; 1140be1da707SZhi Wang u32 dword0, dword1, dword2; 1141be1da707SZhi Wang u32 v; 1142be1da707SZhi Wang 1143be1da707SZhi Wang dword0 = cmd_val(s, 0); 1144be1da707SZhi Wang dword1 = cmd_val(s, 1); 1145be1da707SZhi Wang dword2 = cmd_val(s, 2); 1146be1da707SZhi Wang 1147be1da707SZhi Wang v = (dword0 & GENMASK(21, 19)) >> 19; 1148be1da707SZhi Wang if (WARN_ON(v >= ARRAY_SIZE(gen8_plane_code))) 11495c56883aSfred gao return -EBADRQC; 1150be1da707SZhi Wang 1151be1da707SZhi Wang info->pipe = gen8_plane_code[v].pipe; 1152be1da707SZhi Wang info->plane = gen8_plane_code[v].plane; 1153be1da707SZhi Wang info->event = gen8_plane_code[v].event; 1154be1da707SZhi Wang info->stride_val = (dword1 & GENMASK(15, 6)) >> 6; 1155be1da707SZhi Wang info->tile_val = (dword1 & 0x1); 1156be1da707SZhi Wang info->surf_val = (dword2 & GENMASK(31, 12)) >> 12; 1157be1da707SZhi Wang info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1); 1158be1da707SZhi Wang 1159be1da707SZhi Wang if (info->plane == PLANE_A) { 1160be1da707SZhi Wang info->ctrl_reg = DSPCNTR(info->pipe); 1161be1da707SZhi Wang info->stride_reg = DSPSTRIDE(info->pipe); 1162be1da707SZhi Wang info->surf_reg = DSPSURF(info->pipe); 1163be1da707SZhi Wang } else if (info->plane == PLANE_B) { 1164be1da707SZhi Wang info->ctrl_reg = SPRCTL(info->pipe); 1165be1da707SZhi Wang info->stride_reg = SPRSTRIDE(info->pipe); 1166be1da707SZhi Wang info->surf_reg = SPRSURF(info->pipe); 1167be1da707SZhi Wang } else { 1168be1da707SZhi Wang WARN_ON(1); 11695c56883aSfred gao return -EBADRQC; 1170be1da707SZhi Wang } 1171be1da707SZhi Wang return 0; 1172be1da707SZhi Wang } 1173be1da707SZhi Wang 1174be1da707SZhi Wang static int skl_decode_mi_display_flip(struct parser_exec_state *s, 1175be1da707SZhi Wang struct mi_display_flip_command_info *info) 1176be1da707SZhi Wang { 1177be1da707SZhi Wang struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv; 1178695fbc08STina Zhang struct intel_vgpu *vgpu = s->vgpu; 1179be1da707SZhi Wang u32 dword0 = cmd_val(s, 0); 1180be1da707SZhi Wang u32 dword1 = cmd_val(s, 1); 1181be1da707SZhi Wang u32 dword2 = cmd_val(s, 2); 1182be1da707SZhi Wang u32 plane = (dword0 & GENMASK(12, 8)) >> 8; 1183be1da707SZhi Wang 11846e27d514SXu Han info->plane = PRIMARY_PLANE; 11856e27d514SXu Han 1186be1da707SZhi Wang switch (plane) { 1187be1da707SZhi Wang case MI_DISPLAY_FLIP_SKL_PLANE_1_A: 1188be1da707SZhi Wang info->pipe = PIPE_A; 1189be1da707SZhi Wang info->event = PRIMARY_A_FLIP_DONE; 1190be1da707SZhi Wang break; 1191be1da707SZhi Wang case MI_DISPLAY_FLIP_SKL_PLANE_1_B: 1192be1da707SZhi Wang info->pipe = PIPE_B; 1193be1da707SZhi Wang info->event = PRIMARY_B_FLIP_DONE; 1194be1da707SZhi Wang break; 1195be1da707SZhi Wang case MI_DISPLAY_FLIP_SKL_PLANE_1_C: 119664fafcf5SMin He info->pipe = PIPE_C; 1197be1da707SZhi Wang info->event = PRIMARY_C_FLIP_DONE; 1198be1da707SZhi Wang break; 11996e27d514SXu Han 12006e27d514SXu Han case MI_DISPLAY_FLIP_SKL_PLANE_2_A: 12016e27d514SXu Han info->pipe = PIPE_A; 12026e27d514SXu Han info->event = SPRITE_A_FLIP_DONE; 12036e27d514SXu Han info->plane = SPRITE_PLANE; 12046e27d514SXu Han break; 12056e27d514SXu Han case MI_DISPLAY_FLIP_SKL_PLANE_2_B: 12066e27d514SXu Han info->pipe = PIPE_B; 12076e27d514SXu Han info->event = SPRITE_B_FLIP_DONE; 12086e27d514SXu Han info->plane = SPRITE_PLANE; 12096e27d514SXu Han break; 12106e27d514SXu Han case MI_DISPLAY_FLIP_SKL_PLANE_2_C: 12116e27d514SXu Han info->pipe = PIPE_C; 12126e27d514SXu Han info->event = SPRITE_C_FLIP_DONE; 12136e27d514SXu Han info->plane = SPRITE_PLANE; 12146e27d514SXu Han break; 12156e27d514SXu Han 1216be1da707SZhi Wang default: 1217695fbc08STina Zhang gvt_vgpu_err("unknown plane code %d\n", plane); 12185c56883aSfred gao return -EBADRQC; 1219be1da707SZhi Wang } 1220be1da707SZhi Wang 1221be1da707SZhi Wang info->stride_val = (dword1 & GENMASK(15, 6)) >> 6; 1222be1da707SZhi Wang info->tile_val = (dword1 & GENMASK(2, 0)); 1223be1da707SZhi Wang info->surf_val = (dword2 & GENMASK(31, 12)) >> 12; 1224be1da707SZhi Wang info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1); 1225be1da707SZhi Wang 1226be1da707SZhi Wang info->ctrl_reg = DSPCNTR(info->pipe); 1227be1da707SZhi Wang info->stride_reg = DSPSTRIDE(info->pipe); 1228be1da707SZhi Wang info->surf_reg = DSPSURF(info->pipe); 1229be1da707SZhi Wang 1230be1da707SZhi Wang return 0; 1231be1da707SZhi Wang } 1232be1da707SZhi Wang 1233be1da707SZhi Wang static int gen8_check_mi_display_flip(struct parser_exec_state *s, 1234be1da707SZhi Wang struct mi_display_flip_command_info *info) 1235be1da707SZhi Wang { 1236be1da707SZhi Wang struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv; 1237be1da707SZhi Wang u32 stride, tile; 1238be1da707SZhi Wang 1239be1da707SZhi Wang if (!info->async_flip) 1240be1da707SZhi Wang return 0; 1241be1da707SZhi Wang 1242e3476c00SXu Han if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { 124390551a12SZhenyu Wang stride = vgpu_vreg_t(s->vgpu, info->stride_reg) & GENMASK(9, 0); 124490551a12SZhenyu Wang tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & 1245be1da707SZhi Wang GENMASK(12, 10)) >> 10; 1246be1da707SZhi Wang } else { 124790551a12SZhenyu Wang stride = (vgpu_vreg_t(s->vgpu, info->stride_reg) & 1248be1da707SZhi Wang GENMASK(15, 6)) >> 6; 124990551a12SZhenyu Wang tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10; 1250be1da707SZhi Wang } 1251be1da707SZhi Wang 1252be1da707SZhi Wang if (stride != info->stride_val) 1253be1da707SZhi Wang gvt_dbg_cmd("cannot change stride during async flip\n"); 1254be1da707SZhi Wang 1255be1da707SZhi Wang if (tile != info->tile_val) 1256be1da707SZhi Wang gvt_dbg_cmd("cannot change tile during async flip\n"); 1257be1da707SZhi Wang 1258be1da707SZhi Wang return 0; 1259be1da707SZhi Wang } 1260be1da707SZhi Wang 1261be1da707SZhi Wang static int gen8_update_plane_mmio_from_mi_display_flip( 1262be1da707SZhi Wang struct parser_exec_state *s, 1263be1da707SZhi Wang struct mi_display_flip_command_info *info) 1264be1da707SZhi Wang { 1265be1da707SZhi Wang struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv; 1266be1da707SZhi Wang struct intel_vgpu *vgpu = s->vgpu; 1267be1da707SZhi Wang 126890551a12SZhenyu Wang set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12), 126999c79fd4SDu, Changbin info->surf_val << 12); 1270e3476c00SXu Han if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { 127190551a12SZhenyu Wang set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(9, 0), 127299c79fd4SDu, Changbin info->stride_val); 127390551a12SZhenyu Wang set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10), 127499c79fd4SDu, Changbin info->tile_val << 10); 127599c79fd4SDu, Changbin } else { 127690551a12SZhenyu Wang set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(15, 6), 127799c79fd4SDu, Changbin info->stride_val << 6); 127890551a12SZhenyu Wang set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(10, 10), 127999c79fd4SDu, Changbin info->tile_val << 10); 128099c79fd4SDu, Changbin } 1281be1da707SZhi Wang 128290551a12SZhenyu Wang vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(info->pipe))++; 1283be1da707SZhi Wang intel_vgpu_trigger_virtual_event(vgpu, info->event); 1284be1da707SZhi Wang return 0; 1285be1da707SZhi Wang } 1286be1da707SZhi Wang 1287be1da707SZhi Wang static int decode_mi_display_flip(struct parser_exec_state *s, 1288be1da707SZhi Wang struct mi_display_flip_command_info *info) 1289be1da707SZhi Wang { 1290be1da707SZhi Wang struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv; 1291be1da707SZhi Wang 1292be1da707SZhi Wang if (IS_BROADWELL(dev_priv)) 1293be1da707SZhi Wang return gen8_decode_mi_display_flip(s, info); 1294e3476c00SXu Han if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) 1295be1da707SZhi Wang return skl_decode_mi_display_flip(s, info); 1296be1da707SZhi Wang 1297be1da707SZhi Wang return -ENODEV; 1298be1da707SZhi Wang } 1299be1da707SZhi Wang 1300be1da707SZhi Wang static int check_mi_display_flip(struct parser_exec_state *s, 1301be1da707SZhi Wang struct mi_display_flip_command_info *info) 1302be1da707SZhi Wang { 1303be1da707SZhi Wang struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv; 1304be1da707SZhi Wang 1305e3476c00SXu Han if (IS_BROADWELL(dev_priv) 1306e3476c00SXu Han || IS_SKYLAKE(dev_priv) 1307e3476c00SXu Han || IS_KABYLAKE(dev_priv)) 1308be1da707SZhi Wang return gen8_check_mi_display_flip(s, info); 1309be1da707SZhi Wang return -ENODEV; 1310be1da707SZhi Wang } 1311be1da707SZhi Wang 1312be1da707SZhi Wang static int update_plane_mmio_from_mi_display_flip( 1313be1da707SZhi Wang struct parser_exec_state *s, 1314be1da707SZhi Wang struct mi_display_flip_command_info *info) 1315be1da707SZhi Wang { 1316be1da707SZhi Wang struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv; 1317be1da707SZhi Wang 1318e3476c00SXu Han if (IS_BROADWELL(dev_priv) 1319e3476c00SXu Han || IS_SKYLAKE(dev_priv) 1320e3476c00SXu Han || IS_KABYLAKE(dev_priv)) 1321be1da707SZhi Wang return gen8_update_plane_mmio_from_mi_display_flip(s, info); 1322be1da707SZhi Wang return -ENODEV; 1323be1da707SZhi Wang } 1324be1da707SZhi Wang 1325be1da707SZhi Wang static int cmd_handler_mi_display_flip(struct parser_exec_state *s) 1326be1da707SZhi Wang { 1327be1da707SZhi Wang struct mi_display_flip_command_info info; 1328695fbc08STina Zhang struct intel_vgpu *vgpu = s->vgpu; 1329be1da707SZhi Wang int ret; 1330be1da707SZhi Wang int i; 1331be1da707SZhi Wang int len = cmd_length(s); 1332be1da707SZhi Wang 1333be1da707SZhi Wang ret = decode_mi_display_flip(s, &info); 1334be1da707SZhi Wang if (ret) { 1335695fbc08STina Zhang gvt_vgpu_err("fail to decode MI display flip command\n"); 1336be1da707SZhi Wang return ret; 1337be1da707SZhi Wang } 1338be1da707SZhi Wang 1339be1da707SZhi Wang ret = check_mi_display_flip(s, &info); 1340be1da707SZhi Wang if (ret) { 1341695fbc08STina Zhang gvt_vgpu_err("invalid MI display flip command\n"); 1342be1da707SZhi Wang return ret; 1343be1da707SZhi Wang } 1344be1da707SZhi Wang 1345be1da707SZhi Wang ret = update_plane_mmio_from_mi_display_flip(s, &info); 1346be1da707SZhi Wang if (ret) { 1347695fbc08STina Zhang gvt_vgpu_err("fail to update plane mmio\n"); 1348be1da707SZhi Wang return ret; 1349be1da707SZhi Wang } 1350be1da707SZhi Wang 1351be1da707SZhi Wang for (i = 0; i < len; i++) 1352be1da707SZhi Wang patch_value(s, cmd_ptr(s, i), MI_NOOP); 1353be1da707SZhi Wang return 0; 1354be1da707SZhi Wang } 1355be1da707SZhi Wang 1356be1da707SZhi Wang static bool is_wait_for_flip_pending(u32 cmd) 1357be1da707SZhi Wang { 1358be1da707SZhi Wang return cmd & (MI_WAIT_FOR_PLANE_A_FLIP_PENDING | 1359be1da707SZhi Wang MI_WAIT_FOR_PLANE_B_FLIP_PENDING | 1360be1da707SZhi Wang MI_WAIT_FOR_PLANE_C_FLIP_PENDING | 1361be1da707SZhi Wang MI_WAIT_FOR_SPRITE_A_FLIP_PENDING | 1362be1da707SZhi Wang MI_WAIT_FOR_SPRITE_B_FLIP_PENDING | 1363be1da707SZhi Wang MI_WAIT_FOR_SPRITE_C_FLIP_PENDING); 1364be1da707SZhi Wang } 1365be1da707SZhi Wang 1366be1da707SZhi Wang static int cmd_handler_mi_wait_for_event(struct parser_exec_state *s) 1367be1da707SZhi Wang { 1368be1da707SZhi Wang u32 cmd = cmd_val(s, 0); 1369be1da707SZhi Wang 1370be1da707SZhi Wang if (!is_wait_for_flip_pending(cmd)) 1371be1da707SZhi Wang return 0; 1372be1da707SZhi Wang 1373be1da707SZhi Wang patch_value(s, cmd_ptr(s, 0), MI_NOOP); 1374be1da707SZhi Wang return 0; 1375be1da707SZhi Wang } 1376be1da707SZhi Wang 1377be1da707SZhi Wang static unsigned long get_gma_bb_from_cmd(struct parser_exec_state *s, int index) 1378be1da707SZhi Wang { 1379be1da707SZhi Wang unsigned long addr; 1380be1da707SZhi Wang unsigned long gma_high, gma_low; 13815c56883aSfred gao struct intel_vgpu *vgpu = s->vgpu; 13825c56883aSfred gao int gmadr_bytes = vgpu->gvt->device_info.gmadr_bytes_in_cmd; 1383be1da707SZhi Wang 13845c56883aSfred gao if (WARN_ON(gmadr_bytes != 4 && gmadr_bytes != 8)) { 13855c56883aSfred gao gvt_vgpu_err("invalid gma bytes %d\n", gmadr_bytes); 1386be1da707SZhi Wang return INTEL_GVT_INVALID_ADDR; 13875c56883aSfred gao } 1388be1da707SZhi Wang 1389be1da707SZhi Wang gma_low = cmd_val(s, index) & BATCH_BUFFER_ADDR_MASK; 1390be1da707SZhi Wang if (gmadr_bytes == 4) { 1391be1da707SZhi Wang addr = gma_low; 1392be1da707SZhi Wang } else { 1393be1da707SZhi Wang gma_high = cmd_val(s, index + 1) & BATCH_BUFFER_ADDR_HIGH_MASK; 1394be1da707SZhi Wang addr = (((unsigned long)gma_high) << 32) | gma_low; 1395be1da707SZhi Wang } 1396be1da707SZhi Wang return addr; 1397be1da707SZhi Wang } 1398be1da707SZhi Wang 1399be1da707SZhi Wang static inline int cmd_address_audit(struct parser_exec_state *s, 1400be1da707SZhi Wang unsigned long guest_gma, int op_size, bool index_mode) 1401be1da707SZhi Wang { 1402be1da707SZhi Wang struct intel_vgpu *vgpu = s->vgpu; 1403be1da707SZhi Wang u32 max_surface_size = vgpu->gvt->device_info.max_surface_size; 1404be1da707SZhi Wang int i; 1405be1da707SZhi Wang int ret; 1406be1da707SZhi Wang 1407be1da707SZhi Wang if (op_size > max_surface_size) { 1408695fbc08STina Zhang gvt_vgpu_err("command address audit fail name %s\n", 1409695fbc08STina Zhang s->info->name); 14105c56883aSfred gao return -EFAULT; 1411be1da707SZhi Wang } 1412be1da707SZhi Wang 1413be1da707SZhi Wang if (index_mode) { 14149556e118SZhi Wang if (guest_gma >= I915_GTT_PAGE_SIZE / sizeof(u64)) { 14155c56883aSfred gao ret = -EFAULT; 1416be1da707SZhi Wang goto err; 1417be1da707SZhi Wang } 141864d8bb83SPing Gao } else if (!intel_gvt_ggtt_validate_range(vgpu, guest_gma, op_size)) { 14195c56883aSfred gao ret = -EFAULT; 1420be1da707SZhi Wang goto err; 1421be1da707SZhi Wang } 142264d8bb83SPing Gao 1423be1da707SZhi Wang return 0; 142464d8bb83SPing Gao 1425be1da707SZhi Wang err: 1426695fbc08STina Zhang gvt_vgpu_err("cmd_parser: Malicious %s detected, addr=0x%lx, len=%d!\n", 1427be1da707SZhi Wang s->info->name, guest_gma, op_size); 1428be1da707SZhi Wang 1429be1da707SZhi Wang pr_err("cmd dump: "); 1430be1da707SZhi Wang for (i = 0; i < cmd_length(s); i++) { 1431be1da707SZhi Wang if (!(i % 4)) 1432be1da707SZhi Wang pr_err("\n%08x ", cmd_val(s, i)); 1433be1da707SZhi Wang else 1434be1da707SZhi Wang pr_err("%08x ", cmd_val(s, i)); 1435be1da707SZhi Wang } 1436be1da707SZhi Wang pr_err("\nvgpu%d: aperture 0x%llx - 0x%llx, hidden 0x%llx - 0x%llx\n", 1437be1da707SZhi Wang vgpu->id, 1438be1da707SZhi Wang vgpu_aperture_gmadr_base(vgpu), 1439be1da707SZhi Wang vgpu_aperture_gmadr_end(vgpu), 1440be1da707SZhi Wang vgpu_hidden_gmadr_base(vgpu), 1441be1da707SZhi Wang vgpu_hidden_gmadr_end(vgpu)); 1442be1da707SZhi Wang return ret; 1443be1da707SZhi Wang } 1444be1da707SZhi Wang 1445be1da707SZhi Wang static int cmd_handler_mi_store_data_imm(struct parser_exec_state *s) 1446be1da707SZhi Wang { 1447be1da707SZhi Wang int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd; 1448be1da707SZhi Wang int op_size = (cmd_length(s) - 3) * sizeof(u32); 1449be1da707SZhi Wang int core_id = (cmd_val(s, 2) & (1 << 0)) ? 1 : 0; 1450be1da707SZhi Wang unsigned long gma, gma_low, gma_high; 1451be1da707SZhi Wang int ret = 0; 1452be1da707SZhi Wang 1453be1da707SZhi Wang /* check ppggt */ 1454be1da707SZhi Wang if (!(cmd_val(s, 0) & (1 << 22))) 1455be1da707SZhi Wang return 0; 1456be1da707SZhi Wang 1457be1da707SZhi Wang gma = cmd_val(s, 2) & GENMASK(31, 2); 1458be1da707SZhi Wang 1459be1da707SZhi Wang if (gmadr_bytes == 8) { 1460be1da707SZhi Wang gma_low = cmd_val(s, 1) & GENMASK(31, 2); 1461be1da707SZhi Wang gma_high = cmd_val(s, 2) & GENMASK(15, 0); 1462be1da707SZhi Wang gma = (gma_high << 32) | gma_low; 1463be1da707SZhi Wang core_id = (cmd_val(s, 1) & (1 << 0)) ? 1 : 0; 1464be1da707SZhi Wang } 1465be1da707SZhi Wang ret = cmd_address_audit(s, gma + op_size * core_id, op_size, false); 1466be1da707SZhi Wang return ret; 1467be1da707SZhi Wang } 1468be1da707SZhi Wang 1469be1da707SZhi Wang static inline int unexpected_cmd(struct parser_exec_state *s) 1470be1da707SZhi Wang { 1471695fbc08STina Zhang struct intel_vgpu *vgpu = s->vgpu; 1472695fbc08STina Zhang 1473695fbc08STina Zhang gvt_vgpu_err("Unexpected %s in command buffer!\n", s->info->name); 1474695fbc08STina Zhang 14755c56883aSfred gao return -EBADRQC; 1476be1da707SZhi Wang } 1477be1da707SZhi Wang 1478be1da707SZhi Wang static int cmd_handler_mi_semaphore_wait(struct parser_exec_state *s) 1479be1da707SZhi Wang { 1480be1da707SZhi Wang return unexpected_cmd(s); 1481be1da707SZhi Wang } 1482be1da707SZhi Wang 1483be1da707SZhi Wang static int cmd_handler_mi_report_perf_count(struct parser_exec_state *s) 1484be1da707SZhi Wang { 1485be1da707SZhi Wang return unexpected_cmd(s); 1486be1da707SZhi Wang } 1487be1da707SZhi Wang 1488be1da707SZhi Wang static int cmd_handler_mi_op_2e(struct parser_exec_state *s) 1489be1da707SZhi Wang { 1490be1da707SZhi Wang return unexpected_cmd(s); 1491be1da707SZhi Wang } 1492be1da707SZhi Wang 1493be1da707SZhi Wang static int cmd_handler_mi_op_2f(struct parser_exec_state *s) 1494be1da707SZhi Wang { 1495be1da707SZhi Wang int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd; 1496173bcc60SZhenyu Wang int op_size = (1 << ((cmd_val(s, 0) & GENMASK(20, 19)) >> 19)) * 1497173bcc60SZhenyu Wang sizeof(u32); 1498be1da707SZhi Wang unsigned long gma, gma_high; 1499be1da707SZhi Wang int ret = 0; 1500be1da707SZhi Wang 1501be1da707SZhi Wang if (!(cmd_val(s, 0) & (1 << 22))) 1502be1da707SZhi Wang return ret; 1503be1da707SZhi Wang 1504be1da707SZhi Wang gma = cmd_val(s, 1) & GENMASK(31, 2); 1505be1da707SZhi Wang if (gmadr_bytes == 8) { 1506be1da707SZhi Wang gma_high = cmd_val(s, 2) & GENMASK(15, 0); 1507be1da707SZhi Wang gma = (gma_high << 32) | gma; 1508be1da707SZhi Wang } 1509be1da707SZhi Wang ret = cmd_address_audit(s, gma, op_size, false); 1510be1da707SZhi Wang return ret; 1511be1da707SZhi Wang } 1512be1da707SZhi Wang 1513be1da707SZhi Wang static int cmd_handler_mi_store_data_index(struct parser_exec_state *s) 1514be1da707SZhi Wang { 1515be1da707SZhi Wang return unexpected_cmd(s); 1516be1da707SZhi Wang } 1517be1da707SZhi Wang 1518be1da707SZhi Wang static int cmd_handler_mi_clflush(struct parser_exec_state *s) 1519be1da707SZhi Wang { 1520be1da707SZhi Wang return unexpected_cmd(s); 1521be1da707SZhi Wang } 1522be1da707SZhi Wang 1523be1da707SZhi Wang static int cmd_handler_mi_conditional_batch_buffer_end( 1524be1da707SZhi Wang struct parser_exec_state *s) 1525be1da707SZhi Wang { 1526be1da707SZhi Wang return unexpected_cmd(s); 1527be1da707SZhi Wang } 1528be1da707SZhi Wang 1529be1da707SZhi Wang static int cmd_handler_mi_update_gtt(struct parser_exec_state *s) 1530be1da707SZhi Wang { 1531be1da707SZhi Wang return unexpected_cmd(s); 1532be1da707SZhi Wang } 1533be1da707SZhi Wang 1534be1da707SZhi Wang static int cmd_handler_mi_flush_dw(struct parser_exec_state *s) 1535be1da707SZhi Wang { 1536be1da707SZhi Wang int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd; 1537be1da707SZhi Wang unsigned long gma; 1538be1da707SZhi Wang bool index_mode = false; 1539be1da707SZhi Wang int ret = 0; 1540be1da707SZhi Wang 1541be1da707SZhi Wang /* Check post-sync and ppgtt bit */ 1542be1da707SZhi Wang if (((cmd_val(s, 0) >> 14) & 0x3) && (cmd_val(s, 1) & (1 << 2))) { 1543be1da707SZhi Wang gma = cmd_val(s, 1) & GENMASK(31, 3); 1544be1da707SZhi Wang if (gmadr_bytes == 8) 1545be1da707SZhi Wang gma |= (cmd_val(s, 2) & GENMASK(15, 0)) << 32; 1546be1da707SZhi Wang /* Store Data Index */ 1547be1da707SZhi Wang if (cmd_val(s, 0) & (1 << 21)) 1548be1da707SZhi Wang index_mode = true; 1549be1da707SZhi Wang ret = cmd_address_audit(s, gma, sizeof(u64), index_mode); 1550be1da707SZhi Wang } 1551be1da707SZhi Wang /* Check notify bit */ 1552be1da707SZhi Wang if ((cmd_val(s, 0) & (1 << 8))) 1553be1da707SZhi Wang set_bit(cmd_interrupt_events[s->ring_id].mi_flush_dw, 1554be1da707SZhi Wang s->workload->pending_events); 1555be1da707SZhi Wang return ret; 1556be1da707SZhi Wang } 1557be1da707SZhi Wang 1558be1da707SZhi Wang static void addr_type_update_snb(struct parser_exec_state *s) 1559be1da707SZhi Wang { 1560be1da707SZhi Wang if ((s->buf_type == RING_BUFFER_INSTRUCTION) && 1561be1da707SZhi Wang (BATCH_BUFFER_ADR_SPACE_BIT(cmd_val(s, 0)) == 1)) { 1562be1da707SZhi Wang s->buf_addr_type = PPGTT_BUFFER; 1563be1da707SZhi Wang } 1564be1da707SZhi Wang } 1565be1da707SZhi Wang 1566be1da707SZhi Wang 1567be1da707SZhi Wang static int copy_gma_to_hva(struct intel_vgpu *vgpu, struct intel_vgpu_mm *mm, 1568be1da707SZhi Wang unsigned long gma, unsigned long end_gma, void *va) 1569be1da707SZhi Wang { 1570be1da707SZhi Wang unsigned long copy_len, offset; 1571be1da707SZhi Wang unsigned long len = 0; 1572be1da707SZhi Wang unsigned long gpa; 1573be1da707SZhi Wang 1574be1da707SZhi Wang while (gma != end_gma) { 1575be1da707SZhi Wang gpa = intel_vgpu_gma_to_gpa(mm, gma); 1576be1da707SZhi Wang if (gpa == INTEL_GVT_INVALID_ADDR) { 1577695fbc08STina Zhang gvt_vgpu_err("invalid gma address: %lx\n", gma); 1578be1da707SZhi Wang return -EFAULT; 1579be1da707SZhi Wang } 1580be1da707SZhi Wang 15819556e118SZhi Wang offset = gma & (I915_GTT_PAGE_SIZE - 1); 1582be1da707SZhi Wang 15839556e118SZhi Wang copy_len = (end_gma - gma) >= (I915_GTT_PAGE_SIZE - offset) ? 15849556e118SZhi Wang I915_GTT_PAGE_SIZE - offset : end_gma - gma; 1585be1da707SZhi Wang 1586be1da707SZhi Wang intel_gvt_hypervisor_read_gpa(vgpu, gpa, va + len, copy_len); 1587be1da707SZhi Wang 1588be1da707SZhi Wang len += copy_len; 1589be1da707SZhi Wang gma += copy_len; 1590be1da707SZhi Wang } 159173dec95eSTvrtko Ursulin return len; 1592be1da707SZhi Wang } 1593be1da707SZhi Wang 1594be1da707SZhi Wang 1595be1da707SZhi Wang /* 1596be1da707SZhi Wang * Check whether a batch buffer needs to be scanned. Currently 1597be1da707SZhi Wang * the only criteria is based on privilege. 1598be1da707SZhi Wang */ 1599be1da707SZhi Wang static int batch_buffer_needs_scan(struct parser_exec_state *s) 1600be1da707SZhi Wang { 1601be1da707SZhi Wang struct intel_gvt *gvt = s->vgpu->gvt; 1602be1da707SZhi Wang 1603e3476c00SXu Han if (IS_BROADWELL(gvt->dev_priv) || IS_SKYLAKE(gvt->dev_priv) 1604e3476c00SXu Han || IS_KABYLAKE(gvt->dev_priv)) { 1605be1da707SZhi Wang /* BDW decides privilege based on address space */ 1606be1da707SZhi Wang if (cmd_val(s, 0) & (1 << 8)) 1607be1da707SZhi Wang return 0; 1608be1da707SZhi Wang } 1609be1da707SZhi Wang return 1; 1610be1da707SZhi Wang } 1611be1da707SZhi Wang 161258facf8cSZhi Wang static int find_bb_size(struct parser_exec_state *s, unsigned long *bb_size) 1613be1da707SZhi Wang { 1614be1da707SZhi Wang unsigned long gma = 0; 1615be1da707SZhi Wang struct cmd_info *info; 1616be1da707SZhi Wang uint32_t cmd_len = 0; 161758facf8cSZhi Wang bool bb_end = false; 1618695fbc08STina Zhang struct intel_vgpu *vgpu = s->vgpu; 1619be1da707SZhi Wang u32 cmd; 1620be1da707SZhi Wang 162158facf8cSZhi Wang *bb_size = 0; 162258facf8cSZhi Wang 1623be1da707SZhi Wang /* get the start gm address of the batch buffer */ 1624be1da707SZhi Wang gma = get_gma_bb_from_cmd(s, 1); 16255c56883aSfred gao if (gma == INTEL_GVT_INVALID_ADDR) 16265c56883aSfred gao return -EFAULT; 16275c56883aSfred gao 1628be1da707SZhi Wang cmd = cmd_val(s, 0); 1629be1da707SZhi Wang info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id); 1630be1da707SZhi Wang if (info == NULL) { 1631695fbc08STina Zhang gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x\n", 1632be1da707SZhi Wang cmd, get_opcode(cmd, s->ring_id)); 16335c56883aSfred gao return -EBADRQC; 1634be1da707SZhi Wang } 1635be1da707SZhi Wang do { 16365c56883aSfred gao if (copy_gma_to_hva(s->vgpu, s->vgpu->gtt.ggtt_mm, 16375c56883aSfred gao gma, gma + 4, &cmd) < 0) 16385c56883aSfred gao return -EFAULT; 1639be1da707SZhi Wang info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id); 1640be1da707SZhi Wang if (info == NULL) { 1641695fbc08STina Zhang gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x\n", 1642be1da707SZhi Wang cmd, get_opcode(cmd, s->ring_id)); 16435c56883aSfred gao return -EBADRQC; 1644be1da707SZhi Wang } 1645be1da707SZhi Wang 1646be1da707SZhi Wang if (info->opcode == OP_MI_BATCH_BUFFER_END) { 164758facf8cSZhi Wang bb_end = true; 1648be1da707SZhi Wang } else if (info->opcode == OP_MI_BATCH_BUFFER_START) { 164958facf8cSZhi Wang if (BATCH_BUFFER_2ND_LEVEL_BIT(cmd) == 0) 1650be1da707SZhi Wang /* chained batch buffer */ 165158facf8cSZhi Wang bb_end = true; 1652be1da707SZhi Wang } 1653be1da707SZhi Wang cmd_len = get_cmd_length(info, cmd) << 2; 165458facf8cSZhi Wang *bb_size += cmd_len; 1655be1da707SZhi Wang gma += cmd_len; 165658facf8cSZhi Wang } while (!bb_end); 1657be1da707SZhi Wang 165858facf8cSZhi Wang return 0; 1659be1da707SZhi Wang } 1660be1da707SZhi Wang 1661be1da707SZhi Wang static int perform_bb_shadow(struct parser_exec_state *s) 1662be1da707SZhi Wang { 1663695fbc08STina Zhang struct intel_vgpu *vgpu = s->vgpu; 1664f52c380aSZhi Wang struct intel_vgpu_shadow_bb *bb; 1665be1da707SZhi Wang unsigned long gma = 0; 166658facf8cSZhi Wang unsigned long bb_size; 1667be1da707SZhi Wang int ret = 0; 1668be1da707SZhi Wang 1669be1da707SZhi Wang /* get the start gm address of the batch buffer */ 1670be1da707SZhi Wang gma = get_gma_bb_from_cmd(s, 1); 16715c56883aSfred gao if (gma == INTEL_GVT_INVALID_ADDR) 16725c56883aSfred gao return -EFAULT; 1673be1da707SZhi Wang 167458facf8cSZhi Wang ret = find_bb_size(s, &bb_size); 167558facf8cSZhi Wang if (ret) 167658facf8cSZhi Wang return ret; 1677be1da707SZhi Wang 1678f52c380aSZhi Wang bb = kzalloc(sizeof(*bb), GFP_KERNEL); 1679f52c380aSZhi Wang if (!bb) 1680be1da707SZhi Wang return -ENOMEM; 1681be1da707SZhi Wang 1682f52c380aSZhi Wang bb->obj = i915_gem_object_create(s->vgpu->gvt->dev_priv, 1683894cf7d1SChris Wilson roundup(bb_size, PAGE_SIZE)); 1684f52c380aSZhi Wang if (IS_ERR(bb->obj)) { 1685f52c380aSZhi Wang ret = PTR_ERR(bb->obj); 1686f52c380aSZhi Wang goto err_free_bb; 1687be1da707SZhi Wang } 1688be1da707SZhi Wang 1689f52c380aSZhi Wang ret = i915_gem_obj_prepare_shmem_write(bb->obj, &bb->clflush); 1690f52c380aSZhi Wang if (ret) 1691f52c380aSZhi Wang goto err_free_obj; 1692f52c380aSZhi Wang 1693f52c380aSZhi Wang bb->va = i915_gem_object_pin_map(bb->obj, I915_MAP_WB); 1694f52c380aSZhi Wang if (IS_ERR(bb->va)) { 1695f52c380aSZhi Wang ret = PTR_ERR(bb->va); 1696f52c380aSZhi Wang goto err_finish_shmem_access; 1697be1da707SZhi Wang } 1698be1da707SZhi Wang 1699f52c380aSZhi Wang if (bb->clflush & CLFLUSH_BEFORE) { 1700f52c380aSZhi Wang drm_clflush_virt_range(bb->va, bb->obj->base.size); 1701f52c380aSZhi Wang bb->clflush &= ~CLFLUSH_BEFORE; 1702f52c380aSZhi Wang } 1703be1da707SZhi Wang 1704be1da707SZhi Wang ret = copy_gma_to_hva(s->vgpu, s->vgpu->gtt.ggtt_mm, 1705a2861504SChris Wilson gma, gma + bb_size, 1706f52c380aSZhi Wang bb->va); 17078bcad07aSZhenyu Wang if (ret < 0) { 1708695fbc08STina Zhang gvt_vgpu_err("fail to copy guest ring buffer\n"); 1709f52c380aSZhi Wang ret = -EFAULT; 1710f52c380aSZhi Wang goto err_unmap; 1711be1da707SZhi Wang } 1712be1da707SZhi Wang 1713f52c380aSZhi Wang INIT_LIST_HEAD(&bb->list); 1714f52c380aSZhi Wang list_add(&bb->list, &s->workload->shadow_bb); 1715f52c380aSZhi Wang 1716f52c380aSZhi Wang bb->accessing = true; 1717f52c380aSZhi Wang bb->bb_start_cmd_va = s->ip_va; 1718f52c380aSZhi Wang 1719ef75c685Sfred gao if ((s->buf_type == BATCH_BUFFER_INSTRUCTION) && (!s->is_ctx_wa)) 1720ef75c685Sfred gao bb->bb_offset = s->ip_va - s->rb_va; 1721ef75c685Sfred gao else 1722ef75c685Sfred gao bb->bb_offset = 0; 1723ef75c685Sfred gao 1724be1da707SZhi Wang /* 1725be1da707SZhi Wang * ip_va saves the virtual address of the shadow batch buffer, while 1726be1da707SZhi Wang * ip_gma saves the graphics address of the original batch buffer. 1727be1da707SZhi Wang * As the shadow batch buffer is just a copy from the originial one, 1728be1da707SZhi Wang * it should be right to use shadow batch buffer'va and original batch 1729be1da707SZhi Wang * buffer's gma in pair. After all, we don't want to pin the shadow 1730be1da707SZhi Wang * buffer here (too early). 1731be1da707SZhi Wang */ 1732f52c380aSZhi Wang s->ip_va = bb->va; 1733be1da707SZhi Wang s->ip_gma = gma; 1734be1da707SZhi Wang return 0; 1735f52c380aSZhi Wang err_unmap: 1736f52c380aSZhi Wang i915_gem_object_unpin_map(bb->obj); 1737f52c380aSZhi Wang err_finish_shmem_access: 1738f52c380aSZhi Wang i915_gem_obj_finish_shmem_access(bb->obj); 1739f52c380aSZhi Wang err_free_obj: 1740f52c380aSZhi Wang i915_gem_object_put(bb->obj); 1741f52c380aSZhi Wang err_free_bb: 1742f52c380aSZhi Wang kfree(bb); 1743be1da707SZhi Wang return ret; 1744be1da707SZhi Wang } 1745be1da707SZhi Wang 1746be1da707SZhi Wang static int cmd_handler_mi_batch_buffer_start(struct parser_exec_state *s) 1747be1da707SZhi Wang { 1748be1da707SZhi Wang bool second_level; 1749be1da707SZhi Wang int ret = 0; 1750695fbc08STina Zhang struct intel_vgpu *vgpu = s->vgpu; 1751be1da707SZhi Wang 1752be1da707SZhi Wang if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) { 1753695fbc08STina Zhang gvt_vgpu_err("Found MI_BATCH_BUFFER_START in 2nd level BB\n"); 17545c56883aSfred gao return -EFAULT; 1755be1da707SZhi Wang } 1756be1da707SZhi Wang 1757be1da707SZhi Wang second_level = BATCH_BUFFER_2ND_LEVEL_BIT(cmd_val(s, 0)) == 1; 1758be1da707SZhi Wang if (second_level && (s->buf_type != BATCH_BUFFER_INSTRUCTION)) { 1759695fbc08STina Zhang gvt_vgpu_err("Jumping to 2nd level BB from RB is not allowed\n"); 17605c56883aSfred gao return -EFAULT; 1761be1da707SZhi Wang } 1762be1da707SZhi Wang 1763be1da707SZhi Wang s->saved_buf_addr_type = s->buf_addr_type; 1764be1da707SZhi Wang addr_type_update_snb(s); 1765be1da707SZhi Wang if (s->buf_type == RING_BUFFER_INSTRUCTION) { 1766be1da707SZhi Wang s->ret_ip_gma_ring = s->ip_gma + cmd_length(s) * sizeof(u32); 1767be1da707SZhi Wang s->buf_type = BATCH_BUFFER_INSTRUCTION; 1768be1da707SZhi Wang } else if (second_level) { 1769be1da707SZhi Wang s->buf_type = BATCH_BUFFER_2ND_LEVEL; 1770be1da707SZhi Wang s->ret_ip_gma_bb = s->ip_gma + cmd_length(s) * sizeof(u32); 1771be1da707SZhi Wang s->ret_bb_va = s->ip_va + cmd_length(s) * sizeof(u32); 1772be1da707SZhi Wang } 1773be1da707SZhi Wang 1774be1da707SZhi Wang if (batch_buffer_needs_scan(s)) { 1775be1da707SZhi Wang ret = perform_bb_shadow(s); 1776be1da707SZhi Wang if (ret < 0) 1777695fbc08STina Zhang gvt_vgpu_err("invalid shadow batch buffer\n"); 1778be1da707SZhi Wang } else { 1779be1da707SZhi Wang /* emulate a batch buffer end to do return right */ 1780be1da707SZhi Wang ret = cmd_handler_mi_batch_buffer_end(s); 1781be1da707SZhi Wang if (ret < 0) 1782be1da707SZhi Wang return ret; 1783be1da707SZhi Wang } 1784be1da707SZhi Wang return ret; 1785be1da707SZhi Wang } 1786be1da707SZhi Wang 1787be1da707SZhi Wang static struct cmd_info cmd_info[] = { 1788be1da707SZhi Wang {"MI_NOOP", OP_MI_NOOP, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL}, 1789be1da707SZhi Wang 1790be1da707SZhi Wang {"MI_SET_PREDICATE", OP_MI_SET_PREDICATE, F_LEN_CONST, R_ALL, D_ALL, 1791be1da707SZhi Wang 0, 1, NULL}, 1792be1da707SZhi Wang 1793be1da707SZhi Wang {"MI_USER_INTERRUPT", OP_MI_USER_INTERRUPT, F_LEN_CONST, R_ALL, D_ALL, 1794be1da707SZhi Wang 0, 1, cmd_handler_mi_user_interrupt}, 1795be1da707SZhi Wang 1796be1da707SZhi Wang {"MI_WAIT_FOR_EVENT", OP_MI_WAIT_FOR_EVENT, F_LEN_CONST, R_RCS | R_BCS, 1797be1da707SZhi Wang D_ALL, 0, 1, cmd_handler_mi_wait_for_event}, 1798be1da707SZhi Wang 1799be1da707SZhi Wang {"MI_FLUSH", OP_MI_FLUSH, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL}, 1800be1da707SZhi Wang 1801be1da707SZhi Wang {"MI_ARB_CHECK", OP_MI_ARB_CHECK, F_LEN_CONST, R_ALL, D_ALL, 0, 1, 1802be1da707SZhi Wang NULL}, 1803be1da707SZhi Wang 1804be1da707SZhi Wang {"MI_RS_CONTROL", OP_MI_RS_CONTROL, F_LEN_CONST, R_RCS, D_ALL, 0, 1, 1805be1da707SZhi Wang NULL}, 1806be1da707SZhi Wang 1807be1da707SZhi Wang {"MI_REPORT_HEAD", OP_MI_REPORT_HEAD, F_LEN_CONST, R_ALL, D_ALL, 0, 1, 1808be1da707SZhi Wang NULL}, 1809be1da707SZhi Wang 1810be1da707SZhi Wang {"MI_ARB_ON_OFF", OP_MI_ARB_ON_OFF, F_LEN_CONST, R_ALL, D_ALL, 0, 1, 1811be1da707SZhi Wang NULL}, 1812be1da707SZhi Wang 1813be1da707SZhi Wang {"MI_URB_ATOMIC_ALLOC", OP_MI_URB_ATOMIC_ALLOC, F_LEN_CONST, R_RCS, 1814be1da707SZhi Wang D_ALL, 0, 1, NULL}, 1815be1da707SZhi Wang 1816be1da707SZhi Wang {"MI_BATCH_BUFFER_END", OP_MI_BATCH_BUFFER_END, 1817be1da707SZhi Wang F_IP_ADVANCE_CUSTOM | F_LEN_CONST, R_ALL, D_ALL, 0, 1, 1818be1da707SZhi Wang cmd_handler_mi_batch_buffer_end}, 1819be1da707SZhi Wang 1820be1da707SZhi Wang {"MI_SUSPEND_FLUSH", OP_MI_SUSPEND_FLUSH, F_LEN_CONST, R_ALL, D_ALL, 1821be1da707SZhi Wang 0, 1, NULL}, 1822be1da707SZhi Wang 1823be1da707SZhi Wang {"MI_PREDICATE", OP_MI_PREDICATE, F_LEN_CONST, R_RCS, D_ALL, 0, 1, 1824be1da707SZhi Wang NULL}, 1825be1da707SZhi Wang 1826be1da707SZhi Wang {"MI_TOPOLOGY_FILTER", OP_MI_TOPOLOGY_FILTER, F_LEN_CONST, R_ALL, 1827be1da707SZhi Wang D_ALL, 0, 1, NULL}, 1828be1da707SZhi Wang 1829be1da707SZhi Wang {"MI_SET_APPID", OP_MI_SET_APPID, F_LEN_CONST, R_ALL, D_ALL, 0, 1, 1830be1da707SZhi Wang NULL}, 1831be1da707SZhi Wang 1832be1da707SZhi Wang {"MI_RS_CONTEXT", OP_MI_RS_CONTEXT, F_LEN_CONST, R_RCS, D_ALL, 0, 1, 1833be1da707SZhi Wang NULL}, 1834be1da707SZhi Wang 1835be1da707SZhi Wang {"MI_DISPLAY_FLIP", OP_MI_DISPLAY_FLIP, F_LEN_VAR | F_POST_HANDLE, 1836be1da707SZhi Wang R_RCS | R_BCS, D_ALL, 0, 8, cmd_handler_mi_display_flip}, 1837be1da707SZhi Wang 1838be1da707SZhi Wang {"MI_SEMAPHORE_MBOX", OP_MI_SEMAPHORE_MBOX, F_LEN_VAR, R_ALL, D_ALL, 1839be1da707SZhi Wang 0, 8, NULL}, 1840be1da707SZhi Wang 1841be1da707SZhi Wang {"MI_MATH", OP_MI_MATH, F_LEN_VAR, R_ALL, D_ALL, 0, 8, NULL}, 1842be1da707SZhi Wang 1843be1da707SZhi Wang {"MI_URB_CLEAR", OP_MI_URB_CLEAR, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 1844be1da707SZhi Wang 1845be1da707SZhi Wang {"ME_SEMAPHORE_SIGNAL", OP_MI_SEMAPHORE_SIGNAL, F_LEN_VAR, R_ALL, 1846be1da707SZhi Wang D_BDW_PLUS, 0, 8, NULL}, 1847be1da707SZhi Wang 1848be1da707SZhi Wang {"ME_SEMAPHORE_WAIT", OP_MI_SEMAPHORE_WAIT, F_LEN_VAR, R_ALL, D_BDW_PLUS, 1849be1da707SZhi Wang ADDR_FIX_1(2), 8, cmd_handler_mi_semaphore_wait}, 1850be1da707SZhi Wang 1851be1da707SZhi Wang {"MI_STORE_DATA_IMM", OP_MI_STORE_DATA_IMM, F_LEN_VAR, R_ALL, D_BDW_PLUS, 1852be1da707SZhi Wang ADDR_FIX_1(1), 10, cmd_handler_mi_store_data_imm}, 1853be1da707SZhi Wang 1854be1da707SZhi Wang {"MI_STORE_DATA_INDEX", OP_MI_STORE_DATA_INDEX, F_LEN_VAR, R_ALL, D_ALL, 1855be1da707SZhi Wang 0, 8, cmd_handler_mi_store_data_index}, 1856be1da707SZhi Wang 1857be1da707SZhi Wang {"MI_LOAD_REGISTER_IMM", OP_MI_LOAD_REGISTER_IMM, F_LEN_VAR, R_ALL, 1858be1da707SZhi Wang D_ALL, 0, 8, cmd_handler_lri}, 1859be1da707SZhi Wang 1860be1da707SZhi Wang {"MI_UPDATE_GTT", OP_MI_UPDATE_GTT, F_LEN_VAR, R_ALL, D_BDW_PLUS, 0, 10, 1861be1da707SZhi Wang cmd_handler_mi_update_gtt}, 1862be1da707SZhi Wang 1863be1da707SZhi Wang {"MI_STORE_REGISTER_MEM", OP_MI_STORE_REGISTER_MEM, F_LEN_VAR, R_ALL, 1864be1da707SZhi Wang D_ALL, ADDR_FIX_1(2), 8, cmd_handler_srm}, 1865be1da707SZhi Wang 1866be1da707SZhi Wang {"MI_FLUSH_DW", OP_MI_FLUSH_DW, F_LEN_VAR, R_ALL, D_ALL, 0, 6, 1867be1da707SZhi Wang cmd_handler_mi_flush_dw}, 1868be1da707SZhi Wang 1869be1da707SZhi Wang {"MI_CLFLUSH", OP_MI_CLFLUSH, F_LEN_VAR, R_ALL, D_ALL, ADDR_FIX_1(1), 1870be1da707SZhi Wang 10, cmd_handler_mi_clflush}, 1871be1da707SZhi Wang 1872be1da707SZhi Wang {"MI_REPORT_PERF_COUNT", OP_MI_REPORT_PERF_COUNT, F_LEN_VAR, R_ALL, 1873be1da707SZhi Wang D_ALL, ADDR_FIX_1(1), 6, cmd_handler_mi_report_perf_count}, 1874be1da707SZhi Wang 1875be1da707SZhi Wang {"MI_LOAD_REGISTER_MEM", OP_MI_LOAD_REGISTER_MEM, F_LEN_VAR, R_ALL, 1876be1da707SZhi Wang D_ALL, ADDR_FIX_1(2), 8, cmd_handler_lrm}, 1877be1da707SZhi Wang 1878be1da707SZhi Wang {"MI_LOAD_REGISTER_REG", OP_MI_LOAD_REGISTER_REG, F_LEN_VAR, R_ALL, 1879be1da707SZhi Wang D_ALL, 0, 8, cmd_handler_lrr}, 1880be1da707SZhi Wang 1881be1da707SZhi Wang {"MI_RS_STORE_DATA_IMM", OP_MI_RS_STORE_DATA_IMM, F_LEN_VAR, R_RCS, 1882be1da707SZhi Wang D_ALL, 0, 8, NULL}, 1883be1da707SZhi Wang 1884be1da707SZhi Wang {"MI_LOAD_URB_MEM", OP_MI_LOAD_URB_MEM, F_LEN_VAR, R_RCS, D_ALL, 1885be1da707SZhi Wang ADDR_FIX_1(2), 8, NULL}, 1886be1da707SZhi Wang 1887be1da707SZhi Wang {"MI_STORE_URM_MEM", OP_MI_STORE_URM_MEM, F_LEN_VAR, R_RCS, D_ALL, 1888be1da707SZhi Wang ADDR_FIX_1(2), 8, NULL}, 1889be1da707SZhi Wang 1890be1da707SZhi Wang {"MI_OP_2E", OP_MI_2E, F_LEN_VAR, R_ALL, D_BDW_PLUS, ADDR_FIX_2(1, 2), 1891be1da707SZhi Wang 8, cmd_handler_mi_op_2e}, 1892be1da707SZhi Wang 1893be1da707SZhi Wang {"MI_OP_2F", OP_MI_2F, F_LEN_VAR, R_ALL, D_BDW_PLUS, ADDR_FIX_1(1), 1894be1da707SZhi Wang 8, cmd_handler_mi_op_2f}, 1895be1da707SZhi Wang 1896be1da707SZhi Wang {"MI_BATCH_BUFFER_START", OP_MI_BATCH_BUFFER_START, 1897be1da707SZhi Wang F_IP_ADVANCE_CUSTOM, R_ALL, D_ALL, 0, 8, 1898be1da707SZhi Wang cmd_handler_mi_batch_buffer_start}, 1899be1da707SZhi Wang 1900be1da707SZhi Wang {"MI_CONDITIONAL_BATCH_BUFFER_END", OP_MI_CONDITIONAL_BATCH_BUFFER_END, 1901be1da707SZhi Wang F_LEN_VAR, R_ALL, D_ALL, ADDR_FIX_1(2), 8, 1902be1da707SZhi Wang cmd_handler_mi_conditional_batch_buffer_end}, 1903be1da707SZhi Wang 1904be1da707SZhi Wang {"MI_LOAD_SCAN_LINES_INCL", OP_MI_LOAD_SCAN_LINES_INCL, F_LEN_CONST, 1905be1da707SZhi Wang R_RCS | R_BCS, D_ALL, 0, 2, NULL}, 1906be1da707SZhi Wang 1907be1da707SZhi Wang {"XY_SETUP_BLT", OP_XY_SETUP_BLT, F_LEN_VAR, R_BCS, D_ALL, 1908be1da707SZhi Wang ADDR_FIX_2(4, 7), 8, NULL}, 1909be1da707SZhi Wang 1910be1da707SZhi Wang {"XY_SETUP_CLIP_BLT", OP_XY_SETUP_CLIP_BLT, F_LEN_VAR, R_BCS, D_ALL, 1911be1da707SZhi Wang 0, 8, NULL}, 1912be1da707SZhi Wang 1913be1da707SZhi Wang {"XY_SETUP_MONO_PATTERN_SL_BLT", OP_XY_SETUP_MONO_PATTERN_SL_BLT, 1914be1da707SZhi Wang F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL}, 1915be1da707SZhi Wang 1916be1da707SZhi Wang {"XY_PIXEL_BLT", OP_XY_PIXEL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL}, 1917be1da707SZhi Wang 1918be1da707SZhi Wang {"XY_SCANLINES_BLT", OP_XY_SCANLINES_BLT, F_LEN_VAR, R_BCS, D_ALL, 1919be1da707SZhi Wang 0, 8, NULL}, 1920be1da707SZhi Wang 1921be1da707SZhi Wang {"XY_TEXT_BLT", OP_XY_TEXT_BLT, F_LEN_VAR, R_BCS, D_ALL, 1922be1da707SZhi Wang ADDR_FIX_1(3), 8, NULL}, 1923be1da707SZhi Wang 1924be1da707SZhi Wang {"XY_TEXT_IMMEDIATE_BLT", OP_XY_TEXT_IMMEDIATE_BLT, F_LEN_VAR, R_BCS, 1925be1da707SZhi Wang D_ALL, 0, 8, NULL}, 1926be1da707SZhi Wang 1927be1da707SZhi Wang {"XY_COLOR_BLT", OP_XY_COLOR_BLT, F_LEN_VAR, R_BCS, D_ALL, 1928be1da707SZhi Wang ADDR_FIX_1(4), 8, NULL}, 1929be1da707SZhi Wang 1930be1da707SZhi Wang {"XY_PAT_BLT", OP_XY_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL, 1931be1da707SZhi Wang ADDR_FIX_2(4, 5), 8, NULL}, 1932be1da707SZhi Wang 1933be1da707SZhi Wang {"XY_MONO_PAT_BLT", OP_XY_MONO_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL, 1934be1da707SZhi Wang ADDR_FIX_1(4), 8, NULL}, 1935be1da707SZhi Wang 1936be1da707SZhi Wang {"XY_SRC_COPY_BLT", OP_XY_SRC_COPY_BLT, F_LEN_VAR, R_BCS, D_ALL, 1937be1da707SZhi Wang ADDR_FIX_2(4, 7), 8, NULL}, 1938be1da707SZhi Wang 1939be1da707SZhi Wang {"XY_MONO_SRC_COPY_BLT", OP_XY_MONO_SRC_COPY_BLT, F_LEN_VAR, R_BCS, 1940be1da707SZhi Wang D_ALL, ADDR_FIX_2(4, 5), 8, NULL}, 1941be1da707SZhi Wang 1942be1da707SZhi Wang {"XY_FULL_BLT", OP_XY_FULL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL}, 1943be1da707SZhi Wang 1944be1da707SZhi Wang {"XY_FULL_MONO_SRC_BLT", OP_XY_FULL_MONO_SRC_BLT, F_LEN_VAR, R_BCS, 1945be1da707SZhi Wang D_ALL, ADDR_FIX_3(4, 5, 8), 8, NULL}, 1946be1da707SZhi Wang 1947be1da707SZhi Wang {"XY_FULL_MONO_PATTERN_BLT", OP_XY_FULL_MONO_PATTERN_BLT, F_LEN_VAR, 1948be1da707SZhi Wang R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL}, 1949be1da707SZhi Wang 1950be1da707SZhi Wang {"XY_FULL_MONO_PATTERN_MONO_SRC_BLT", 1951be1da707SZhi Wang OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT, 1952be1da707SZhi Wang F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL}, 1953be1da707SZhi Wang 1954be1da707SZhi Wang {"XY_MONO_PAT_FIXED_BLT", OP_XY_MONO_PAT_FIXED_BLT, F_LEN_VAR, R_BCS, 1955be1da707SZhi Wang D_ALL, ADDR_FIX_1(4), 8, NULL}, 1956be1da707SZhi Wang 1957be1da707SZhi Wang {"XY_MONO_SRC_COPY_IMMEDIATE_BLT", OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT, 1958be1da707SZhi Wang F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL}, 1959be1da707SZhi Wang 1960be1da707SZhi Wang {"XY_PAT_BLT_IMMEDIATE", OP_XY_PAT_BLT_IMMEDIATE, F_LEN_VAR, R_BCS, 1961be1da707SZhi Wang D_ALL, ADDR_FIX_1(4), 8, NULL}, 1962be1da707SZhi Wang 1963be1da707SZhi Wang {"XY_SRC_COPY_CHROMA_BLT", OP_XY_SRC_COPY_CHROMA_BLT, F_LEN_VAR, R_BCS, 1964be1da707SZhi Wang D_ALL, ADDR_FIX_2(4, 7), 8, NULL}, 1965be1da707SZhi Wang 1966be1da707SZhi Wang {"XY_FULL_IMMEDIATE_PATTERN_BLT", OP_XY_FULL_IMMEDIATE_PATTERN_BLT, 1967be1da707SZhi Wang F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL}, 1968be1da707SZhi Wang 1969be1da707SZhi Wang {"XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT", 1970be1da707SZhi Wang OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT, 1971be1da707SZhi Wang F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL}, 1972be1da707SZhi Wang 1973be1da707SZhi Wang {"XY_PAT_CHROMA_BLT", OP_XY_PAT_CHROMA_BLT, F_LEN_VAR, R_BCS, D_ALL, 1974be1da707SZhi Wang ADDR_FIX_2(4, 5), 8, NULL}, 1975be1da707SZhi Wang 1976be1da707SZhi Wang {"XY_PAT_CHROMA_BLT_IMMEDIATE", OP_XY_PAT_CHROMA_BLT_IMMEDIATE, 1977be1da707SZhi Wang F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL}, 1978be1da707SZhi Wang 1979be1da707SZhi Wang {"3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP", 1980be1da707SZhi Wang OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP, 1981be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 1982be1da707SZhi Wang 1983be1da707SZhi Wang {"3DSTATE_VIEWPORT_STATE_POINTERS_CC", 1984be1da707SZhi Wang OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC, 1985be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 1986be1da707SZhi Wang 1987be1da707SZhi Wang {"3DSTATE_BLEND_STATE_POINTERS", 1988be1da707SZhi Wang OP_3DSTATE_BLEND_STATE_POINTERS, 1989be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 1990be1da707SZhi Wang 1991be1da707SZhi Wang {"3DSTATE_DEPTH_STENCIL_STATE_POINTERS", 1992be1da707SZhi Wang OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS, 1993be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 1994be1da707SZhi Wang 1995be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_POINTERS_VS", 1996be1da707SZhi Wang OP_3DSTATE_BINDING_TABLE_POINTERS_VS, 1997be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 1998be1da707SZhi Wang 1999be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_POINTERS_HS", 2000be1da707SZhi Wang OP_3DSTATE_BINDING_TABLE_POINTERS_HS, 2001be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2002be1da707SZhi Wang 2003be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_POINTERS_DS", 2004be1da707SZhi Wang OP_3DSTATE_BINDING_TABLE_POINTERS_DS, 2005be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2006be1da707SZhi Wang 2007be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_POINTERS_GS", 2008be1da707SZhi Wang OP_3DSTATE_BINDING_TABLE_POINTERS_GS, 2009be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2010be1da707SZhi Wang 2011be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_POINTERS_PS", 2012be1da707SZhi Wang OP_3DSTATE_BINDING_TABLE_POINTERS_PS, 2013be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2014be1da707SZhi Wang 2015be1da707SZhi Wang {"3DSTATE_SAMPLER_STATE_POINTERS_VS", 2016be1da707SZhi Wang OP_3DSTATE_SAMPLER_STATE_POINTERS_VS, 2017be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2018be1da707SZhi Wang 2019be1da707SZhi Wang {"3DSTATE_SAMPLER_STATE_POINTERS_HS", 2020be1da707SZhi Wang OP_3DSTATE_SAMPLER_STATE_POINTERS_HS, 2021be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2022be1da707SZhi Wang 2023be1da707SZhi Wang {"3DSTATE_SAMPLER_STATE_POINTERS_DS", 2024be1da707SZhi Wang OP_3DSTATE_SAMPLER_STATE_POINTERS_DS, 2025be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2026be1da707SZhi Wang 2027be1da707SZhi Wang {"3DSTATE_SAMPLER_STATE_POINTERS_GS", 2028be1da707SZhi Wang OP_3DSTATE_SAMPLER_STATE_POINTERS_GS, 2029be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2030be1da707SZhi Wang 2031be1da707SZhi Wang {"3DSTATE_SAMPLER_STATE_POINTERS_PS", 2032be1da707SZhi Wang OP_3DSTATE_SAMPLER_STATE_POINTERS_PS, 2033be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2034be1da707SZhi Wang 2035be1da707SZhi Wang {"3DSTATE_URB_VS", OP_3DSTATE_URB_VS, F_LEN_VAR, R_RCS, D_ALL, 2036be1da707SZhi Wang 0, 8, NULL}, 2037be1da707SZhi Wang 2038be1da707SZhi Wang {"3DSTATE_URB_HS", OP_3DSTATE_URB_HS, F_LEN_VAR, R_RCS, D_ALL, 2039be1da707SZhi Wang 0, 8, NULL}, 2040be1da707SZhi Wang 2041be1da707SZhi Wang {"3DSTATE_URB_DS", OP_3DSTATE_URB_DS, F_LEN_VAR, R_RCS, D_ALL, 2042be1da707SZhi Wang 0, 8, NULL}, 2043be1da707SZhi Wang 2044be1da707SZhi Wang {"3DSTATE_URB_GS", OP_3DSTATE_URB_GS, F_LEN_VAR, R_RCS, D_ALL, 2045be1da707SZhi Wang 0, 8, NULL}, 2046be1da707SZhi Wang 2047be1da707SZhi Wang {"3DSTATE_GATHER_CONSTANT_VS", OP_3DSTATE_GATHER_CONSTANT_VS, 2048be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2049be1da707SZhi Wang 2050be1da707SZhi Wang {"3DSTATE_GATHER_CONSTANT_GS", OP_3DSTATE_GATHER_CONSTANT_GS, 2051be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2052be1da707SZhi Wang 2053be1da707SZhi Wang {"3DSTATE_GATHER_CONSTANT_HS", OP_3DSTATE_GATHER_CONSTANT_HS, 2054be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2055be1da707SZhi Wang 2056be1da707SZhi Wang {"3DSTATE_GATHER_CONSTANT_DS", OP_3DSTATE_GATHER_CONSTANT_DS, 2057be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2058be1da707SZhi Wang 2059be1da707SZhi Wang {"3DSTATE_GATHER_CONSTANT_PS", OP_3DSTATE_GATHER_CONSTANT_PS, 2060be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2061be1da707SZhi Wang 2062be1da707SZhi Wang {"3DSTATE_DX9_CONSTANTF_VS", OP_3DSTATE_DX9_CONSTANTF_VS, 2063be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL}, 2064be1da707SZhi Wang 2065be1da707SZhi Wang {"3DSTATE_DX9_CONSTANTF_PS", OP_3DSTATE_DX9_CONSTANTF_PS, 2066be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL}, 2067be1da707SZhi Wang 2068be1da707SZhi Wang {"3DSTATE_DX9_CONSTANTI_VS", OP_3DSTATE_DX9_CONSTANTI_VS, 2069be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2070be1da707SZhi Wang 2071be1da707SZhi Wang {"3DSTATE_DX9_CONSTANTI_PS", OP_3DSTATE_DX9_CONSTANTI_PS, 2072be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2073be1da707SZhi Wang 2074be1da707SZhi Wang {"3DSTATE_DX9_CONSTANTB_VS", OP_3DSTATE_DX9_CONSTANTB_VS, 2075be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2076be1da707SZhi Wang 2077be1da707SZhi Wang {"3DSTATE_DX9_CONSTANTB_PS", OP_3DSTATE_DX9_CONSTANTB_PS, 2078be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2079be1da707SZhi Wang 2080be1da707SZhi Wang {"3DSTATE_DX9_LOCAL_VALID_VS", OP_3DSTATE_DX9_LOCAL_VALID_VS, 2081be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2082be1da707SZhi Wang 2083be1da707SZhi Wang {"3DSTATE_DX9_LOCAL_VALID_PS", OP_3DSTATE_DX9_LOCAL_VALID_PS, 2084be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2085be1da707SZhi Wang 2086be1da707SZhi Wang {"3DSTATE_DX9_GENERATE_ACTIVE_VS", OP_3DSTATE_DX9_GENERATE_ACTIVE_VS, 2087be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2088be1da707SZhi Wang 2089be1da707SZhi Wang {"3DSTATE_DX9_GENERATE_ACTIVE_PS", OP_3DSTATE_DX9_GENERATE_ACTIVE_PS, 2090be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2091be1da707SZhi Wang 2092be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_EDIT_VS", OP_3DSTATE_BINDING_TABLE_EDIT_VS, 2093be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL}, 2094be1da707SZhi Wang 2095be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_EDIT_GS", OP_3DSTATE_BINDING_TABLE_EDIT_GS, 2096be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL}, 2097be1da707SZhi Wang 2098be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_EDIT_HS", OP_3DSTATE_BINDING_TABLE_EDIT_HS, 2099be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL}, 2100be1da707SZhi Wang 2101be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_EDIT_DS", OP_3DSTATE_BINDING_TABLE_EDIT_DS, 2102be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL}, 2103be1da707SZhi Wang 2104be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_EDIT_PS", OP_3DSTATE_BINDING_TABLE_EDIT_PS, 2105be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL}, 2106be1da707SZhi Wang 2107be1da707SZhi Wang {"3DSTATE_VF_INSTANCING", OP_3DSTATE_VF_INSTANCING, F_LEN_VAR, R_RCS, 2108be1da707SZhi Wang D_BDW_PLUS, 0, 8, NULL}, 2109be1da707SZhi Wang 2110be1da707SZhi Wang {"3DSTATE_VF_SGVS", OP_3DSTATE_VF_SGVS, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8, 2111be1da707SZhi Wang NULL}, 2112be1da707SZhi Wang 2113be1da707SZhi Wang {"3DSTATE_VF_TOPOLOGY", OP_3DSTATE_VF_TOPOLOGY, F_LEN_VAR, R_RCS, 2114be1da707SZhi Wang D_BDW_PLUS, 0, 8, NULL}, 2115be1da707SZhi Wang 2116be1da707SZhi Wang {"3DSTATE_WM_CHROMAKEY", OP_3DSTATE_WM_CHROMAKEY, F_LEN_VAR, R_RCS, 2117be1da707SZhi Wang D_BDW_PLUS, 0, 8, NULL}, 2118be1da707SZhi Wang 2119be1da707SZhi Wang {"3DSTATE_PS_BLEND", OP_3DSTATE_PS_BLEND, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 2120be1da707SZhi Wang 8, NULL}, 2121be1da707SZhi Wang 2122be1da707SZhi Wang {"3DSTATE_WM_DEPTH_STENCIL", OP_3DSTATE_WM_DEPTH_STENCIL, F_LEN_VAR, 2123be1da707SZhi Wang R_RCS, D_BDW_PLUS, 0, 8, NULL}, 2124be1da707SZhi Wang 2125be1da707SZhi Wang {"3DSTATE_PS_EXTRA", OP_3DSTATE_PS_EXTRA, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 2126be1da707SZhi Wang 8, NULL}, 2127be1da707SZhi Wang 2128be1da707SZhi Wang {"3DSTATE_RASTER", OP_3DSTATE_RASTER, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8, 2129be1da707SZhi Wang NULL}, 2130be1da707SZhi Wang 2131be1da707SZhi Wang {"3DSTATE_SBE_SWIZ", OP_3DSTATE_SBE_SWIZ, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8, 2132be1da707SZhi Wang NULL}, 2133be1da707SZhi Wang 2134be1da707SZhi Wang {"3DSTATE_WM_HZ_OP", OP_3DSTATE_WM_HZ_OP, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8, 2135be1da707SZhi Wang NULL}, 2136be1da707SZhi Wang 2137be1da707SZhi Wang {"3DSTATE_VERTEX_BUFFERS", OP_3DSTATE_VERTEX_BUFFERS, F_LEN_VAR, R_RCS, 2138be1da707SZhi Wang D_BDW_PLUS, 0, 8, NULL}, 2139be1da707SZhi Wang 2140be1da707SZhi Wang {"3DSTATE_VERTEX_ELEMENTS", OP_3DSTATE_VERTEX_ELEMENTS, F_LEN_VAR, 2141be1da707SZhi Wang R_RCS, D_ALL, 0, 8, NULL}, 2142be1da707SZhi Wang 2143be1da707SZhi Wang {"3DSTATE_INDEX_BUFFER", OP_3DSTATE_INDEX_BUFFER, F_LEN_VAR, R_RCS, 2144be1da707SZhi Wang D_BDW_PLUS, ADDR_FIX_1(2), 8, NULL}, 2145be1da707SZhi Wang 2146be1da707SZhi Wang {"3DSTATE_VF_STATISTICS", OP_3DSTATE_VF_STATISTICS, F_LEN_CONST, 2147be1da707SZhi Wang R_RCS, D_ALL, 0, 1, NULL}, 2148be1da707SZhi Wang 2149be1da707SZhi Wang {"3DSTATE_VF", OP_3DSTATE_VF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2150be1da707SZhi Wang 2151be1da707SZhi Wang {"3DSTATE_CC_STATE_POINTERS", OP_3DSTATE_CC_STATE_POINTERS, F_LEN_VAR, 2152be1da707SZhi Wang R_RCS, D_ALL, 0, 8, NULL}, 2153be1da707SZhi Wang 2154be1da707SZhi Wang {"3DSTATE_SCISSOR_STATE_POINTERS", OP_3DSTATE_SCISSOR_STATE_POINTERS, 2155be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2156be1da707SZhi Wang 2157be1da707SZhi Wang {"3DSTATE_GS", OP_3DSTATE_GS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2158be1da707SZhi Wang 2159be1da707SZhi Wang {"3DSTATE_CLIP", OP_3DSTATE_CLIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2160be1da707SZhi Wang 2161be1da707SZhi Wang {"3DSTATE_WM", OP_3DSTATE_WM, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2162be1da707SZhi Wang 2163be1da707SZhi Wang {"3DSTATE_CONSTANT_GS", OP_3DSTATE_CONSTANT_GS, F_LEN_VAR, R_RCS, 2164be1da707SZhi Wang D_BDW_PLUS, 0, 8, NULL}, 2165be1da707SZhi Wang 2166be1da707SZhi Wang {"3DSTATE_CONSTANT_PS", OP_3DSTATE_CONSTANT_PS, F_LEN_VAR, R_RCS, 2167be1da707SZhi Wang D_BDW_PLUS, 0, 8, NULL}, 2168be1da707SZhi Wang 2169be1da707SZhi Wang {"3DSTATE_SAMPLE_MASK", OP_3DSTATE_SAMPLE_MASK, F_LEN_VAR, R_RCS, 2170be1da707SZhi Wang D_ALL, 0, 8, NULL}, 2171be1da707SZhi Wang 2172be1da707SZhi Wang {"3DSTATE_CONSTANT_HS", OP_3DSTATE_CONSTANT_HS, F_LEN_VAR, R_RCS, 2173be1da707SZhi Wang D_BDW_PLUS, 0, 8, NULL}, 2174be1da707SZhi Wang 2175be1da707SZhi Wang {"3DSTATE_CONSTANT_DS", OP_3DSTATE_CONSTANT_DS, F_LEN_VAR, R_RCS, 2176be1da707SZhi Wang D_BDW_PLUS, 0, 8, NULL}, 2177be1da707SZhi Wang 2178be1da707SZhi Wang {"3DSTATE_HS", OP_3DSTATE_HS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2179be1da707SZhi Wang 2180be1da707SZhi Wang {"3DSTATE_TE", OP_3DSTATE_TE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2181be1da707SZhi Wang 2182be1da707SZhi Wang {"3DSTATE_DS", OP_3DSTATE_DS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2183be1da707SZhi Wang 2184be1da707SZhi Wang {"3DSTATE_STREAMOUT", OP_3DSTATE_STREAMOUT, F_LEN_VAR, R_RCS, 2185be1da707SZhi Wang D_ALL, 0, 8, NULL}, 2186be1da707SZhi Wang 2187be1da707SZhi Wang {"3DSTATE_SBE", OP_3DSTATE_SBE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2188be1da707SZhi Wang 2189be1da707SZhi Wang {"3DSTATE_PS", OP_3DSTATE_PS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2190be1da707SZhi Wang 2191be1da707SZhi Wang {"3DSTATE_DRAWING_RECTANGLE", OP_3DSTATE_DRAWING_RECTANGLE, F_LEN_VAR, 2192be1da707SZhi Wang R_RCS, D_ALL, 0, 8, NULL}, 2193be1da707SZhi Wang 2194be1da707SZhi Wang {"3DSTATE_SAMPLER_PALETTE_LOAD0", OP_3DSTATE_SAMPLER_PALETTE_LOAD0, 2195be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2196be1da707SZhi Wang 2197be1da707SZhi Wang {"3DSTATE_CHROMA_KEY", OP_3DSTATE_CHROMA_KEY, F_LEN_VAR, R_RCS, D_ALL, 2198be1da707SZhi Wang 0, 8, NULL}, 2199be1da707SZhi Wang 2200be1da707SZhi Wang {"3DSTATE_DEPTH_BUFFER", OP_3DSTATE_DEPTH_BUFFER, F_LEN_VAR, R_RCS, 2201be1da707SZhi Wang D_ALL, ADDR_FIX_1(2), 8, NULL}, 2202be1da707SZhi Wang 2203be1da707SZhi Wang {"3DSTATE_POLY_STIPPLE_OFFSET", OP_3DSTATE_POLY_STIPPLE_OFFSET, 2204be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2205be1da707SZhi Wang 2206be1da707SZhi Wang {"3DSTATE_POLY_STIPPLE_PATTERN", OP_3DSTATE_POLY_STIPPLE_PATTERN, 2207be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2208be1da707SZhi Wang 2209be1da707SZhi Wang {"3DSTATE_LINE_STIPPLE", OP_3DSTATE_LINE_STIPPLE, F_LEN_VAR, R_RCS, 2210be1da707SZhi Wang D_ALL, 0, 8, NULL}, 2211be1da707SZhi Wang 2212be1da707SZhi Wang {"3DSTATE_AA_LINE_PARAMS", OP_3DSTATE_AA_LINE_PARAMS, F_LEN_VAR, R_RCS, 2213be1da707SZhi Wang D_ALL, 0, 8, NULL}, 2214be1da707SZhi Wang 2215be1da707SZhi Wang {"3DSTATE_GS_SVB_INDEX", OP_3DSTATE_GS_SVB_INDEX, F_LEN_VAR, R_RCS, 2216be1da707SZhi Wang D_ALL, 0, 8, NULL}, 2217be1da707SZhi Wang 2218be1da707SZhi Wang {"3DSTATE_SAMPLER_PALETTE_LOAD1", OP_3DSTATE_SAMPLER_PALETTE_LOAD1, 2219be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2220be1da707SZhi Wang 2221be1da707SZhi Wang {"3DSTATE_MULTISAMPLE", OP_3DSTATE_MULTISAMPLE_BDW, F_LEN_VAR, R_RCS, 2222be1da707SZhi Wang D_BDW_PLUS, 0, 8, NULL}, 2223be1da707SZhi Wang 2224be1da707SZhi Wang {"3DSTATE_STENCIL_BUFFER", OP_3DSTATE_STENCIL_BUFFER, F_LEN_VAR, R_RCS, 2225be1da707SZhi Wang D_ALL, ADDR_FIX_1(2), 8, NULL}, 2226be1da707SZhi Wang 2227be1da707SZhi Wang {"3DSTATE_HIER_DEPTH_BUFFER", OP_3DSTATE_HIER_DEPTH_BUFFER, F_LEN_VAR, 2228be1da707SZhi Wang R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL}, 2229be1da707SZhi Wang 2230be1da707SZhi Wang {"3DSTATE_CLEAR_PARAMS", OP_3DSTATE_CLEAR_PARAMS, F_LEN_VAR, 2231be1da707SZhi Wang R_RCS, D_ALL, 0, 8, NULL}, 2232be1da707SZhi Wang 2233be1da707SZhi Wang {"3DSTATE_PUSH_CONSTANT_ALLOC_VS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS, 2234be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2235be1da707SZhi Wang 2236be1da707SZhi Wang {"3DSTATE_PUSH_CONSTANT_ALLOC_HS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS, 2237be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2238be1da707SZhi Wang 2239be1da707SZhi Wang {"3DSTATE_PUSH_CONSTANT_ALLOC_DS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS, 2240be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2241be1da707SZhi Wang 2242be1da707SZhi Wang {"3DSTATE_PUSH_CONSTANT_ALLOC_GS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS, 2243be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2244be1da707SZhi Wang 2245be1da707SZhi Wang {"3DSTATE_PUSH_CONSTANT_ALLOC_PS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS, 2246be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2247be1da707SZhi Wang 2248be1da707SZhi Wang {"3DSTATE_MONOFILTER_SIZE", OP_3DSTATE_MONOFILTER_SIZE, F_LEN_VAR, 2249be1da707SZhi Wang R_RCS, D_ALL, 0, 8, NULL}, 2250be1da707SZhi Wang 2251be1da707SZhi Wang {"3DSTATE_SO_DECL_LIST", OP_3DSTATE_SO_DECL_LIST, F_LEN_VAR, R_RCS, 2252be1da707SZhi Wang D_ALL, 0, 9, NULL}, 2253be1da707SZhi Wang 2254be1da707SZhi Wang {"3DSTATE_SO_BUFFER", OP_3DSTATE_SO_BUFFER, F_LEN_VAR, R_RCS, D_BDW_PLUS, 2255be1da707SZhi Wang ADDR_FIX_2(2, 4), 8, NULL}, 2256be1da707SZhi Wang 2257be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_POOL_ALLOC", 2258be1da707SZhi Wang OP_3DSTATE_BINDING_TABLE_POOL_ALLOC, 2259be1da707SZhi Wang F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL}, 2260be1da707SZhi Wang 2261be1da707SZhi Wang {"3DSTATE_GATHER_POOL_ALLOC", OP_3DSTATE_GATHER_POOL_ALLOC, 2262be1da707SZhi Wang F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL}, 2263be1da707SZhi Wang 2264be1da707SZhi Wang {"3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC", 2265be1da707SZhi Wang OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC, 2266be1da707SZhi Wang F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL}, 2267be1da707SZhi Wang 2268be1da707SZhi Wang {"3DSTATE_SAMPLE_PATTERN", OP_3DSTATE_SAMPLE_PATTERN, F_LEN_VAR, R_RCS, 2269be1da707SZhi Wang D_BDW_PLUS, 0, 8, NULL}, 2270be1da707SZhi Wang 2271be1da707SZhi Wang {"PIPE_CONTROL", OP_PIPE_CONTROL, F_LEN_VAR, R_RCS, D_ALL, 2272be1da707SZhi Wang ADDR_FIX_1(2), 8, cmd_handler_pipe_control}, 2273be1da707SZhi Wang 2274be1da707SZhi Wang {"3DPRIMITIVE", OP_3DPRIMITIVE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2275be1da707SZhi Wang 2276be1da707SZhi Wang {"PIPELINE_SELECT", OP_PIPELINE_SELECT, F_LEN_CONST, R_RCS, D_ALL, 0, 2277be1da707SZhi Wang 1, NULL}, 2278be1da707SZhi Wang 2279be1da707SZhi Wang {"STATE_PREFETCH", OP_STATE_PREFETCH, F_LEN_VAR, R_RCS, D_ALL, 2280be1da707SZhi Wang ADDR_FIX_1(1), 8, NULL}, 2281be1da707SZhi Wang 2282be1da707SZhi Wang {"STATE_SIP", OP_STATE_SIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2283be1da707SZhi Wang 2284be1da707SZhi Wang {"STATE_BASE_ADDRESS", OP_STATE_BASE_ADDRESS, F_LEN_VAR, R_RCS, D_BDW_PLUS, 2285be1da707SZhi Wang ADDR_FIX_5(1, 3, 4, 5, 6), 8, NULL}, 2286be1da707SZhi Wang 2287be1da707SZhi Wang {"OP_3D_MEDIA_0_1_4", OP_3D_MEDIA_0_1_4, F_LEN_VAR, R_RCS, D_ALL, 2288be1da707SZhi Wang ADDR_FIX_1(1), 8, NULL}, 2289be1da707SZhi Wang 2290be1da707SZhi Wang {"3DSTATE_VS", OP_3DSTATE_VS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2291be1da707SZhi Wang 2292be1da707SZhi Wang {"3DSTATE_SF", OP_3DSTATE_SF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2293be1da707SZhi Wang 2294be1da707SZhi Wang {"3DSTATE_CONSTANT_VS", OP_3DSTATE_CONSTANT_VS, F_LEN_VAR, R_RCS, D_BDW_PLUS, 2295be1da707SZhi Wang 0, 8, NULL}, 2296be1da707SZhi Wang 2297be1da707SZhi Wang {"3DSTATE_COMPONENT_PACKING", OP_3DSTATE_COMPONENT_PACKING, F_LEN_VAR, R_RCS, 2298be1da707SZhi Wang D_SKL_PLUS, 0, 8, NULL}, 2299be1da707SZhi Wang 2300be1da707SZhi Wang {"MEDIA_INTERFACE_DESCRIPTOR_LOAD", OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD, 2301be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL}, 2302be1da707SZhi Wang 2303be1da707SZhi Wang {"MEDIA_GATEWAY_STATE", OP_MEDIA_GATEWAY_STATE, F_LEN_VAR, R_RCS, D_ALL, 2304be1da707SZhi Wang 0, 16, NULL}, 2305be1da707SZhi Wang 2306be1da707SZhi Wang {"MEDIA_STATE_FLUSH", OP_MEDIA_STATE_FLUSH, F_LEN_VAR, R_RCS, D_ALL, 2307be1da707SZhi Wang 0, 16, NULL}, 2308be1da707SZhi Wang 2309be1da707SZhi Wang {"MEDIA_OBJECT", OP_MEDIA_OBJECT, F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL}, 2310be1da707SZhi Wang 2311be1da707SZhi Wang {"MEDIA_CURBE_LOAD", OP_MEDIA_CURBE_LOAD, F_LEN_VAR, R_RCS, D_ALL, 2312be1da707SZhi Wang 0, 16, NULL}, 2313be1da707SZhi Wang 2314be1da707SZhi Wang {"MEDIA_OBJECT_PRT", OP_MEDIA_OBJECT_PRT, F_LEN_VAR, R_RCS, D_ALL, 2315be1da707SZhi Wang 0, 16, NULL}, 2316be1da707SZhi Wang 2317be1da707SZhi Wang {"MEDIA_OBJECT_WALKER", OP_MEDIA_OBJECT_WALKER, F_LEN_VAR, R_RCS, D_ALL, 2318be1da707SZhi Wang 0, 16, NULL}, 2319be1da707SZhi Wang 2320be1da707SZhi Wang {"GPGPU_WALKER", OP_GPGPU_WALKER, F_LEN_VAR, R_RCS, D_ALL, 2321be1da707SZhi Wang 0, 8, NULL}, 2322be1da707SZhi Wang 2323be1da707SZhi Wang {"MEDIA_VFE_STATE", OP_MEDIA_VFE_STATE, F_LEN_VAR, R_RCS, D_ALL, 0, 16, 2324be1da707SZhi Wang NULL}, 2325be1da707SZhi Wang 2326be1da707SZhi Wang {"3DSTATE_VF_STATISTICS_GM45", OP_3DSTATE_VF_STATISTICS_GM45, 2327be1da707SZhi Wang F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL}, 2328be1da707SZhi Wang 2329be1da707SZhi Wang {"MFX_PIPE_MODE_SELECT", OP_MFX_PIPE_MODE_SELECT, F_LEN_VAR, 2330be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2331be1da707SZhi Wang 2332be1da707SZhi Wang {"MFX_SURFACE_STATE", OP_MFX_SURFACE_STATE, F_LEN_VAR, 2333be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2334be1da707SZhi Wang 2335be1da707SZhi Wang {"MFX_PIPE_BUF_ADDR_STATE", OP_MFX_PIPE_BUF_ADDR_STATE, F_LEN_VAR, 2336be1da707SZhi Wang R_VCS, D_BDW_PLUS, 0, 12, NULL}, 2337be1da707SZhi Wang 2338be1da707SZhi Wang {"MFX_IND_OBJ_BASE_ADDR_STATE", OP_MFX_IND_OBJ_BASE_ADDR_STATE, 2339be1da707SZhi Wang F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL}, 2340be1da707SZhi Wang 2341be1da707SZhi Wang {"MFX_BSP_BUF_BASE_ADDR_STATE", OP_MFX_BSP_BUF_BASE_ADDR_STATE, 2342be1da707SZhi Wang F_LEN_VAR, R_VCS, D_BDW_PLUS, ADDR_FIX_3(1, 3, 5), 12, NULL}, 2343be1da707SZhi Wang 2344be1da707SZhi Wang {"OP_2_0_0_5", OP_2_0_0_5, F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL}, 2345be1da707SZhi Wang 2346be1da707SZhi Wang {"MFX_STATE_POINTER", OP_MFX_STATE_POINTER, F_LEN_VAR, 2347be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2348be1da707SZhi Wang 2349be1da707SZhi Wang {"MFX_QM_STATE", OP_MFX_QM_STATE, F_LEN_VAR, 2350be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2351be1da707SZhi Wang 2352be1da707SZhi Wang {"MFX_FQM_STATE", OP_MFX_FQM_STATE, F_LEN_VAR, 2353be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2354be1da707SZhi Wang 2355be1da707SZhi Wang {"MFX_PAK_INSERT_OBJECT", OP_MFX_PAK_INSERT_OBJECT, F_LEN_VAR, 2356be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2357be1da707SZhi Wang 2358be1da707SZhi Wang {"MFX_STITCH_OBJECT", OP_MFX_STITCH_OBJECT, F_LEN_VAR, 2359be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2360be1da707SZhi Wang 2361be1da707SZhi Wang {"MFD_IT_OBJECT", OP_MFD_IT_OBJECT, F_LEN_VAR, 2362be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2363be1da707SZhi Wang 2364be1da707SZhi Wang {"MFX_WAIT", OP_MFX_WAIT, F_LEN_VAR, 2365be1da707SZhi Wang R_VCS, D_ALL, 0, 6, NULL}, 2366be1da707SZhi Wang 2367be1da707SZhi Wang {"MFX_AVC_IMG_STATE", OP_MFX_AVC_IMG_STATE, F_LEN_VAR, 2368be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2369be1da707SZhi Wang 2370be1da707SZhi Wang {"MFX_AVC_QM_STATE", OP_MFX_AVC_QM_STATE, F_LEN_VAR, 2371be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2372be1da707SZhi Wang 2373be1da707SZhi Wang {"MFX_AVC_DIRECTMODE_STATE", OP_MFX_AVC_DIRECTMODE_STATE, F_LEN_VAR, 2374be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2375be1da707SZhi Wang 2376be1da707SZhi Wang {"MFX_AVC_SLICE_STATE", OP_MFX_AVC_SLICE_STATE, F_LEN_VAR, 2377be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2378be1da707SZhi Wang 2379be1da707SZhi Wang {"MFX_AVC_REF_IDX_STATE", OP_MFX_AVC_REF_IDX_STATE, F_LEN_VAR, 2380be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2381be1da707SZhi Wang 2382be1da707SZhi Wang {"MFX_AVC_WEIGHTOFFSET_STATE", OP_MFX_AVC_WEIGHTOFFSET_STATE, F_LEN_VAR, 2383be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2384be1da707SZhi Wang 2385be1da707SZhi Wang {"MFD_AVC_PICID_STATE", OP_MFD_AVC_PICID_STATE, F_LEN_VAR, 2386be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2387be1da707SZhi Wang {"MFD_AVC_DPB_STATE", OP_MFD_AVC_DPB_STATE, F_LEN_VAR, 2388be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2389be1da707SZhi Wang 2390be1da707SZhi Wang {"MFD_AVC_BSD_OBJECT", OP_MFD_AVC_BSD_OBJECT, F_LEN_VAR, 2391be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2392be1da707SZhi Wang 2393be1da707SZhi Wang {"MFD_AVC_SLICEADDR", OP_MFD_AVC_SLICEADDR, F_LEN_VAR, 2394be1da707SZhi Wang R_VCS, D_ALL, ADDR_FIX_1(2), 12, NULL}, 2395be1da707SZhi Wang 2396be1da707SZhi Wang {"MFC_AVC_PAK_OBJECT", OP_MFC_AVC_PAK_OBJECT, F_LEN_VAR, 2397be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2398be1da707SZhi Wang 2399be1da707SZhi Wang {"MFX_VC1_PRED_PIPE_STATE", OP_MFX_VC1_PRED_PIPE_STATE, F_LEN_VAR, 2400be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2401be1da707SZhi Wang 2402be1da707SZhi Wang {"MFX_VC1_DIRECTMODE_STATE", OP_MFX_VC1_DIRECTMODE_STATE, F_LEN_VAR, 2403be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2404be1da707SZhi Wang 2405be1da707SZhi Wang {"MFD_VC1_SHORT_PIC_STATE", OP_MFD_VC1_SHORT_PIC_STATE, F_LEN_VAR, 2406be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2407be1da707SZhi Wang 2408be1da707SZhi Wang {"MFD_VC1_LONG_PIC_STATE", OP_MFD_VC1_LONG_PIC_STATE, F_LEN_VAR, 2409be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2410be1da707SZhi Wang 2411be1da707SZhi Wang {"MFD_VC1_BSD_OBJECT", OP_MFD_VC1_BSD_OBJECT, F_LEN_VAR, 2412be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2413be1da707SZhi Wang 2414be1da707SZhi Wang {"MFC_MPEG2_SLICEGROUP_STATE", OP_MFC_MPEG2_SLICEGROUP_STATE, F_LEN_VAR, 2415be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2416be1da707SZhi Wang 2417be1da707SZhi Wang {"MFC_MPEG2_PAK_OBJECT", OP_MFC_MPEG2_PAK_OBJECT, F_LEN_VAR, 2418be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2419be1da707SZhi Wang 2420be1da707SZhi Wang {"MFX_MPEG2_PIC_STATE", OP_MFX_MPEG2_PIC_STATE, F_LEN_VAR, 2421be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2422be1da707SZhi Wang 2423be1da707SZhi Wang {"MFX_MPEG2_QM_STATE", OP_MFX_MPEG2_QM_STATE, F_LEN_VAR, 2424be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2425be1da707SZhi Wang 2426be1da707SZhi Wang {"MFD_MPEG2_BSD_OBJECT", OP_MFD_MPEG2_BSD_OBJECT, F_LEN_VAR, 2427be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2428be1da707SZhi Wang 2429be1da707SZhi Wang {"MFX_2_6_0_0", OP_MFX_2_6_0_0, F_LEN_VAR, R_VCS, D_ALL, 2430be1da707SZhi Wang 0, 16, NULL}, 2431be1da707SZhi Wang 2432be1da707SZhi Wang {"MFX_2_6_0_9", OP_MFX_2_6_0_9, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL}, 2433be1da707SZhi Wang 2434be1da707SZhi Wang {"MFX_2_6_0_8", OP_MFX_2_6_0_8, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL}, 2435be1da707SZhi Wang 2436be1da707SZhi Wang {"MFX_JPEG_PIC_STATE", OP_MFX_JPEG_PIC_STATE, F_LEN_VAR, 2437be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2438be1da707SZhi Wang 2439be1da707SZhi Wang {"MFX_JPEG_HUFF_TABLE_STATE", OP_MFX_JPEG_HUFF_TABLE_STATE, F_LEN_VAR, 2440be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2441be1da707SZhi Wang 2442be1da707SZhi Wang {"MFD_JPEG_BSD_OBJECT", OP_MFD_JPEG_BSD_OBJECT, F_LEN_VAR, 2443be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2444be1da707SZhi Wang 2445be1da707SZhi Wang {"VEBOX_STATE", OP_VEB_STATE, F_LEN_VAR, R_VECS, D_ALL, 0, 12, NULL}, 2446be1da707SZhi Wang 2447be1da707SZhi Wang {"VEBOX_SURFACE_STATE", OP_VEB_SURFACE_STATE, F_LEN_VAR, R_VECS, D_ALL, 2448be1da707SZhi Wang 0, 12, NULL}, 2449be1da707SZhi Wang 2450be1da707SZhi Wang {"VEB_DI_IECP", OP_VEB_DNDI_IECP_STATE, F_LEN_VAR, R_VECS, D_BDW_PLUS, 2451be1da707SZhi Wang 0, 20, NULL}, 2452be1da707SZhi Wang }; 2453be1da707SZhi Wang 2454be1da707SZhi Wang static void add_cmd_entry(struct intel_gvt *gvt, struct cmd_entry *e) 2455be1da707SZhi Wang { 2456be1da707SZhi Wang hash_add(gvt->cmd_table, &e->hlist, e->info->opcode); 2457be1da707SZhi Wang } 2458be1da707SZhi Wang 2459be1da707SZhi Wang /* call the cmd handler, and advance ip */ 2460be1da707SZhi Wang static int cmd_parser_exec(struct parser_exec_state *s) 2461be1da707SZhi Wang { 2462ffc19776SChangbin Du struct intel_vgpu *vgpu = s->vgpu; 2463be1da707SZhi Wang struct cmd_info *info; 2464be1da707SZhi Wang u32 cmd; 2465be1da707SZhi Wang int ret = 0; 2466be1da707SZhi Wang 2467be1da707SZhi Wang cmd = cmd_val(s, 0); 2468be1da707SZhi Wang 2469be1da707SZhi Wang info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id); 2470be1da707SZhi Wang if (info == NULL) { 2471695fbc08STina Zhang gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x\n", 2472be1da707SZhi Wang cmd, get_opcode(cmd, s->ring_id)); 24735c56883aSfred gao return -EBADRQC; 2474be1da707SZhi Wang } 2475be1da707SZhi Wang 2476be1da707SZhi Wang s->info = info; 2477be1da707SZhi Wang 2478ffc19776SChangbin Du trace_gvt_command(vgpu->id, s->ring_id, s->ip_gma, s->ip_va, 2479ffc19776SChangbin Du cmd_length(s), s->buf_type); 2480be1da707SZhi Wang 2481be1da707SZhi Wang if (info->handler) { 2482be1da707SZhi Wang ret = info->handler(s); 2483be1da707SZhi Wang if (ret < 0) { 2484695fbc08STina Zhang gvt_vgpu_err("%s handler error\n", info->name); 2485be1da707SZhi Wang return ret; 2486be1da707SZhi Wang } 2487be1da707SZhi Wang } 2488be1da707SZhi Wang 2489be1da707SZhi Wang if (!(info->flag & F_IP_ADVANCE_CUSTOM)) { 2490be1da707SZhi Wang ret = cmd_advance_default(s); 2491be1da707SZhi Wang if (ret) { 2492695fbc08STina Zhang gvt_vgpu_err("%s IP advance error\n", info->name); 2493be1da707SZhi Wang return ret; 2494be1da707SZhi Wang } 2495be1da707SZhi Wang } 2496be1da707SZhi Wang return 0; 2497be1da707SZhi Wang } 2498be1da707SZhi Wang 2499be1da707SZhi Wang static inline bool gma_out_of_range(unsigned long gma, 2500be1da707SZhi Wang unsigned long gma_head, unsigned int gma_tail) 2501be1da707SZhi Wang { 2502be1da707SZhi Wang if (gma_tail >= gma_head) 2503be1da707SZhi Wang return (gma < gma_head) || (gma > gma_tail); 2504be1da707SZhi Wang else 2505be1da707SZhi Wang return (gma > gma_tail) && (gma < gma_head); 2506be1da707SZhi Wang } 2507be1da707SZhi Wang 25085c56883aSfred gao /* Keep the consistent return type, e.g EBADRQC for unknown 25095c56883aSfred gao * cmd, EFAULT for invalid address, EPERM for nonpriv. later 25105c56883aSfred gao * works as the input of VM healthy status. 25115c56883aSfred gao */ 2512be1da707SZhi Wang static int command_scan(struct parser_exec_state *s, 2513be1da707SZhi Wang unsigned long rb_head, unsigned long rb_tail, 2514be1da707SZhi Wang unsigned long rb_start, unsigned long rb_len) 2515be1da707SZhi Wang { 2516be1da707SZhi Wang 2517be1da707SZhi Wang unsigned long gma_head, gma_tail, gma_bottom; 2518be1da707SZhi Wang int ret = 0; 2519695fbc08STina Zhang struct intel_vgpu *vgpu = s->vgpu; 2520be1da707SZhi Wang 2521be1da707SZhi Wang gma_head = rb_start + rb_head; 2522be1da707SZhi Wang gma_tail = rb_start + rb_tail; 2523be1da707SZhi Wang gma_bottom = rb_start + rb_len; 2524be1da707SZhi Wang 2525be1da707SZhi Wang while (s->ip_gma != gma_tail) { 2526be1da707SZhi Wang if (s->buf_type == RING_BUFFER_INSTRUCTION) { 2527be1da707SZhi Wang if (!(s->ip_gma >= rb_start) || 2528be1da707SZhi Wang !(s->ip_gma < gma_bottom)) { 2529695fbc08STina Zhang gvt_vgpu_err("ip_gma %lx out of ring scope." 2530be1da707SZhi Wang "(base:0x%lx, bottom: 0x%lx)\n", 2531be1da707SZhi Wang s->ip_gma, rb_start, 2532be1da707SZhi Wang gma_bottom); 2533be1da707SZhi Wang parser_exec_state_dump(s); 25345c56883aSfred gao return -EFAULT; 2535be1da707SZhi Wang } 2536be1da707SZhi Wang if (gma_out_of_range(s->ip_gma, gma_head, gma_tail)) { 2537695fbc08STina Zhang gvt_vgpu_err("ip_gma %lx out of range." 2538be1da707SZhi Wang "base 0x%lx head 0x%lx tail 0x%lx\n", 2539be1da707SZhi Wang s->ip_gma, rb_start, 2540be1da707SZhi Wang rb_head, rb_tail); 2541be1da707SZhi Wang parser_exec_state_dump(s); 2542be1da707SZhi Wang break; 2543be1da707SZhi Wang } 2544be1da707SZhi Wang } 2545be1da707SZhi Wang ret = cmd_parser_exec(s); 2546be1da707SZhi Wang if (ret) { 2547695fbc08STina Zhang gvt_vgpu_err("cmd parser error\n"); 2548be1da707SZhi Wang parser_exec_state_dump(s); 2549be1da707SZhi Wang break; 2550be1da707SZhi Wang } 2551be1da707SZhi Wang } 2552be1da707SZhi Wang 2553be1da707SZhi Wang return ret; 2554be1da707SZhi Wang } 2555be1da707SZhi Wang 2556be1da707SZhi Wang static int scan_workload(struct intel_vgpu_workload *workload) 2557be1da707SZhi Wang { 2558be1da707SZhi Wang unsigned long gma_head, gma_tail, gma_bottom; 2559be1da707SZhi Wang struct parser_exec_state s; 2560be1da707SZhi Wang int ret = 0; 2561be1da707SZhi Wang 2562be1da707SZhi Wang /* ring base is page aligned */ 25639556e118SZhi Wang if (WARN_ON(!IS_ALIGNED(workload->rb_start, I915_GTT_PAGE_SIZE))) 2564be1da707SZhi Wang return -EINVAL; 2565be1da707SZhi Wang 2566be1da707SZhi Wang gma_head = workload->rb_start + workload->rb_head; 2567be1da707SZhi Wang gma_tail = workload->rb_start + workload->rb_tail; 2568be1da707SZhi Wang gma_bottom = workload->rb_start + _RING_CTL_BUF_SIZE(workload->rb_ctl); 2569be1da707SZhi Wang 2570be1da707SZhi Wang s.buf_type = RING_BUFFER_INSTRUCTION; 2571be1da707SZhi Wang s.buf_addr_type = GTT_BUFFER; 2572be1da707SZhi Wang s.vgpu = workload->vgpu; 2573be1da707SZhi Wang s.ring_id = workload->ring_id; 2574be1da707SZhi Wang s.ring_start = workload->rb_start; 2575be1da707SZhi Wang s.ring_size = _RING_CTL_BUF_SIZE(workload->rb_ctl); 2576be1da707SZhi Wang s.ring_head = gma_head; 2577be1da707SZhi Wang s.ring_tail = gma_tail; 2578be1da707SZhi Wang s.rb_va = workload->shadow_ring_buffer_va; 2579be1da707SZhi Wang s.workload = workload; 2580ef75c685Sfred gao s.is_ctx_wa = false; 2581be1da707SZhi Wang 25820aaee4ccSPei Zhang if ((bypass_scan_mask & (1 << workload->ring_id)) || 25830aaee4ccSPei Zhang gma_head == gma_tail) 2584be1da707SZhi Wang return 0; 2585be1da707SZhi Wang 25863364bf5fSPing Gao if (!intel_gvt_ggtt_validate_range(s.vgpu, s.ring_start, s.ring_size)) { 25873364bf5fSPing Gao ret = -EINVAL; 25883364bf5fSPing Gao goto out; 25893364bf5fSPing Gao } 25903364bf5fSPing Gao 2591be1da707SZhi Wang ret = ip_gma_set(&s, gma_head); 2592be1da707SZhi Wang if (ret) 2593be1da707SZhi Wang goto out; 2594be1da707SZhi Wang 2595be1da707SZhi Wang ret = command_scan(&s, workload->rb_head, workload->rb_tail, 2596be1da707SZhi Wang workload->rb_start, _RING_CTL_BUF_SIZE(workload->rb_ctl)); 2597be1da707SZhi Wang 2598be1da707SZhi Wang out: 2599be1da707SZhi Wang return ret; 2600be1da707SZhi Wang } 2601be1da707SZhi Wang 2602be1da707SZhi Wang static int scan_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx) 2603be1da707SZhi Wang { 2604be1da707SZhi Wang 2605be1da707SZhi Wang unsigned long gma_head, gma_tail, gma_bottom, ring_size, ring_tail; 2606be1da707SZhi Wang struct parser_exec_state s; 2607be1da707SZhi Wang int ret = 0; 2608c10c1255STina Zhang struct intel_vgpu_workload *workload = container_of(wa_ctx, 2609c10c1255STina Zhang struct intel_vgpu_workload, 2610c10c1255STina Zhang wa_ctx); 2611be1da707SZhi Wang 2612be1da707SZhi Wang /* ring base is page aligned */ 26139556e118SZhi Wang if (WARN_ON(!IS_ALIGNED(wa_ctx->indirect_ctx.guest_gma, 26149556e118SZhi Wang I915_GTT_PAGE_SIZE))) 2615be1da707SZhi Wang return -EINVAL; 2616be1da707SZhi Wang 2617be1da707SZhi Wang ring_tail = wa_ctx->indirect_ctx.size + 3 * sizeof(uint32_t); 2618be1da707SZhi Wang ring_size = round_up(wa_ctx->indirect_ctx.size + CACHELINE_BYTES, 2619be1da707SZhi Wang PAGE_SIZE); 2620be1da707SZhi Wang gma_head = wa_ctx->indirect_ctx.guest_gma; 2621be1da707SZhi Wang gma_tail = wa_ctx->indirect_ctx.guest_gma + ring_tail; 2622be1da707SZhi Wang gma_bottom = wa_ctx->indirect_ctx.guest_gma + ring_size; 2623be1da707SZhi Wang 2624be1da707SZhi Wang s.buf_type = RING_BUFFER_INSTRUCTION; 2625be1da707SZhi Wang s.buf_addr_type = GTT_BUFFER; 2626c10c1255STina Zhang s.vgpu = workload->vgpu; 2627c10c1255STina Zhang s.ring_id = workload->ring_id; 2628be1da707SZhi Wang s.ring_start = wa_ctx->indirect_ctx.guest_gma; 2629be1da707SZhi Wang s.ring_size = ring_size; 2630be1da707SZhi Wang s.ring_head = gma_head; 2631be1da707SZhi Wang s.ring_tail = gma_tail; 2632be1da707SZhi Wang s.rb_va = wa_ctx->indirect_ctx.shadow_va; 2633c10c1255STina Zhang s.workload = workload; 2634ef75c685Sfred gao s.is_ctx_wa = true; 2635be1da707SZhi Wang 26363364bf5fSPing Gao if (!intel_gvt_ggtt_validate_range(s.vgpu, s.ring_start, s.ring_size)) { 26373364bf5fSPing Gao ret = -EINVAL; 26383364bf5fSPing Gao goto out; 26393364bf5fSPing Gao } 26403364bf5fSPing Gao 2641be1da707SZhi Wang ret = ip_gma_set(&s, gma_head); 2642be1da707SZhi Wang if (ret) 2643be1da707SZhi Wang goto out; 2644be1da707SZhi Wang 2645be1da707SZhi Wang ret = command_scan(&s, 0, ring_tail, 2646be1da707SZhi Wang wa_ctx->indirect_ctx.guest_gma, ring_size); 2647be1da707SZhi Wang out: 2648be1da707SZhi Wang return ret; 2649be1da707SZhi Wang } 2650be1da707SZhi Wang 2651be1da707SZhi Wang static int shadow_workload_ring_buffer(struct intel_vgpu_workload *workload) 2652be1da707SZhi Wang { 2653be1da707SZhi Wang struct intel_vgpu *vgpu = workload->vgpu; 2654325eb94aSZhi Wang struct intel_vgpu_submission *s = &vgpu->submission; 2655be1da707SZhi Wang unsigned long gma_head, gma_tail, gma_top, guest_rb_size; 26560a53bc07Sfred gao void *shadow_ring_buffer_va; 26570a53bc07Sfred gao int ring_id = workload->ring_id; 2658be1da707SZhi Wang int ret; 2659be1da707SZhi Wang 2660be1da707SZhi Wang guest_rb_size = _RING_CTL_BUF_SIZE(workload->rb_ctl); 2661be1da707SZhi Wang 2662be1da707SZhi Wang /* calculate workload ring buffer size */ 2663be1da707SZhi Wang workload->rb_len = (workload->rb_tail + guest_rb_size - 2664be1da707SZhi Wang workload->rb_head) % guest_rb_size; 2665be1da707SZhi Wang 2666be1da707SZhi Wang gma_head = workload->rb_start + workload->rb_head; 2667be1da707SZhi Wang gma_tail = workload->rb_start + workload->rb_tail; 2668be1da707SZhi Wang gma_top = workload->rb_start + guest_rb_size; 2669be1da707SZhi Wang 2670325eb94aSZhi Wang if (workload->rb_len > s->ring_scan_buffer_size[ring_id]) { 26718cf80a2eSZhi Wang void *p; 2672bf4097eaSZhi Wang 26730a53bc07Sfred gao /* realloc the new ring buffer if needed */ 2674325eb94aSZhi Wang p = krealloc(s->ring_scan_buffer[ring_id], workload->rb_len, 26758cf80a2eSZhi Wang GFP_KERNEL); 2676bf4097eaSZhi Wang if (!p) { 26778cf80a2eSZhi Wang gvt_vgpu_err("fail to re-alloc ring scan buffer\n"); 26780a53bc07Sfred gao return -ENOMEM; 26790a53bc07Sfred gao } 2680325eb94aSZhi Wang s->ring_scan_buffer[ring_id] = p; 2681325eb94aSZhi Wang s->ring_scan_buffer_size[ring_id] = workload->rb_len; 26820a53bc07Sfred gao } 26830a53bc07Sfred gao 2684325eb94aSZhi Wang shadow_ring_buffer_va = s->ring_scan_buffer[ring_id]; 2685be1da707SZhi Wang 2686be1da707SZhi Wang /* get shadow ring buffer va */ 26870a53bc07Sfred gao workload->shadow_ring_buffer_va = shadow_ring_buffer_va; 2688be1da707SZhi Wang 2689be1da707SZhi Wang /* head > tail --> copy head <-> top */ 2690be1da707SZhi Wang if (gma_head > gma_tail) { 2691be1da707SZhi Wang ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm, 26920a53bc07Sfred gao gma_head, gma_top, shadow_ring_buffer_va); 26938bcad07aSZhenyu Wang if (ret < 0) { 2694695fbc08STina Zhang gvt_vgpu_err("fail to copy guest ring buffer\n"); 2695be1da707SZhi Wang return ret; 2696be1da707SZhi Wang } 26970a53bc07Sfred gao shadow_ring_buffer_va += ret; 2698be1da707SZhi Wang gma_head = workload->rb_start; 2699be1da707SZhi Wang } 2700be1da707SZhi Wang 2701be1da707SZhi Wang /* copy head or start <-> tail */ 27020a53bc07Sfred gao ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm, gma_head, gma_tail, 27030a53bc07Sfred gao shadow_ring_buffer_va); 27048bcad07aSZhenyu Wang if (ret < 0) { 2705695fbc08STina Zhang gvt_vgpu_err("fail to copy guest ring buffer\n"); 2706be1da707SZhi Wang return ret; 2707be1da707SZhi Wang } 2708be1da707SZhi Wang return 0; 2709be1da707SZhi Wang } 2710be1da707SZhi Wang 271189ea20b9SPing Gao int intel_gvt_scan_and_shadow_ringbuffer(struct intel_vgpu_workload *workload) 2712be1da707SZhi Wang { 2713be1da707SZhi Wang int ret; 2714695fbc08STina Zhang struct intel_vgpu *vgpu = workload->vgpu; 2715be1da707SZhi Wang 2716be1da707SZhi Wang ret = shadow_workload_ring_buffer(workload); 2717be1da707SZhi Wang if (ret) { 2718695fbc08STina Zhang gvt_vgpu_err("fail to shadow workload ring_buffer\n"); 2719be1da707SZhi Wang return ret; 2720be1da707SZhi Wang } 2721be1da707SZhi Wang 2722be1da707SZhi Wang ret = scan_workload(workload); 2723be1da707SZhi Wang if (ret) { 2724695fbc08STina Zhang gvt_vgpu_err("scan workload error\n"); 2725be1da707SZhi Wang return ret; 2726be1da707SZhi Wang } 2727be1da707SZhi Wang return 0; 2728be1da707SZhi Wang } 2729be1da707SZhi Wang 2730be1da707SZhi Wang static int shadow_indirect_ctx(struct intel_shadow_wa_ctx *wa_ctx) 2731be1da707SZhi Wang { 2732be1da707SZhi Wang int ctx_size = wa_ctx->indirect_ctx.size; 2733be1da707SZhi Wang unsigned long guest_gma = wa_ctx->indirect_ctx.guest_gma; 2734c10c1255STina Zhang struct intel_vgpu_workload *workload = container_of(wa_ctx, 2735c10c1255STina Zhang struct intel_vgpu_workload, 2736c10c1255STina Zhang wa_ctx); 2737c10c1255STina Zhang struct intel_vgpu *vgpu = workload->vgpu; 2738894cf7d1SChris Wilson struct drm_i915_gem_object *obj; 2739be1da707SZhi Wang int ret = 0; 2740bcd0aedeSChris Wilson void *map; 2741be1da707SZhi Wang 2742c10c1255STina Zhang obj = i915_gem_object_create(workload->vgpu->gvt->dev_priv, 2743894cf7d1SChris Wilson roundup(ctx_size + CACHELINE_BYTES, 2744894cf7d1SChris Wilson PAGE_SIZE)); 2745894cf7d1SChris Wilson if (IS_ERR(obj)) 2746894cf7d1SChris Wilson return PTR_ERR(obj); 2747be1da707SZhi Wang 2748be1da707SZhi Wang /* get the va of the shadow batch buffer */ 2749bcd0aedeSChris Wilson map = i915_gem_object_pin_map(obj, I915_MAP_WB); 2750bcd0aedeSChris Wilson if (IS_ERR(map)) { 2751695fbc08STina Zhang gvt_vgpu_err("failed to vmap shadow indirect ctx\n"); 2752bcd0aedeSChris Wilson ret = PTR_ERR(map); 2753bcd0aedeSChris Wilson goto put_obj; 2754be1da707SZhi Wang } 2755be1da707SZhi Wang 2756894cf7d1SChris Wilson ret = i915_gem_object_set_to_cpu_domain(obj, false); 2757be1da707SZhi Wang if (ret) { 2758695fbc08STina Zhang gvt_vgpu_err("failed to set shadow indirect ctx to CPU\n"); 2759be1da707SZhi Wang goto unmap_src; 2760be1da707SZhi Wang } 2761be1da707SZhi Wang 2762c10c1255STina Zhang ret = copy_gma_to_hva(workload->vgpu, 2763c10c1255STina Zhang workload->vgpu->gtt.ggtt_mm, 2764bcd0aedeSChris Wilson guest_gma, guest_gma + ctx_size, 2765bcd0aedeSChris Wilson map); 27668bcad07aSZhenyu Wang if (ret < 0) { 2767695fbc08STina Zhang gvt_vgpu_err("fail to copy guest indirect ctx\n"); 2768894cf7d1SChris Wilson goto unmap_src; 2769be1da707SZhi Wang } 2770be1da707SZhi Wang 2771894cf7d1SChris Wilson wa_ctx->indirect_ctx.obj = obj; 2772bcd0aedeSChris Wilson wa_ctx->indirect_ctx.shadow_va = map; 2773be1da707SZhi Wang return 0; 2774be1da707SZhi Wang 2775be1da707SZhi Wang unmap_src: 2776bcd0aedeSChris Wilson i915_gem_object_unpin_map(obj); 2777894cf7d1SChris Wilson put_obj: 2778ffeaf9aaSfred gao i915_gem_object_put(obj); 2779be1da707SZhi Wang return ret; 2780be1da707SZhi Wang } 2781be1da707SZhi Wang 2782be1da707SZhi Wang static int combine_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx) 2783be1da707SZhi Wang { 2784be1da707SZhi Wang uint32_t per_ctx_start[CACHELINE_DWORDS] = {0}; 2785be1da707SZhi Wang unsigned char *bb_start_sva; 2786be1da707SZhi Wang 27878f63fc2bSZhenyu Wang if (!wa_ctx->per_ctx.valid) 27888f63fc2bSZhenyu Wang return 0; 27898f63fc2bSZhenyu Wang 2790be1da707SZhi Wang per_ctx_start[0] = 0x18800001; 2791be1da707SZhi Wang per_ctx_start[1] = wa_ctx->per_ctx.guest_gma; 2792be1da707SZhi Wang 2793be1da707SZhi Wang bb_start_sva = (unsigned char *)wa_ctx->indirect_ctx.shadow_va + 2794be1da707SZhi Wang wa_ctx->indirect_ctx.size; 2795be1da707SZhi Wang 2796be1da707SZhi Wang memcpy(bb_start_sva, per_ctx_start, CACHELINE_BYTES); 2797be1da707SZhi Wang 2798be1da707SZhi Wang return 0; 2799be1da707SZhi Wang } 2800be1da707SZhi Wang 2801be1da707SZhi Wang int intel_gvt_scan_and_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx) 2802be1da707SZhi Wang { 2803be1da707SZhi Wang int ret; 2804c10c1255STina Zhang struct intel_vgpu_workload *workload = container_of(wa_ctx, 2805c10c1255STina Zhang struct intel_vgpu_workload, 2806c10c1255STina Zhang wa_ctx); 2807c10c1255STina Zhang struct intel_vgpu *vgpu = workload->vgpu; 2808be1da707SZhi Wang 2809be1da707SZhi Wang if (wa_ctx->indirect_ctx.size == 0) 2810be1da707SZhi Wang return 0; 2811be1da707SZhi Wang 2812be1da707SZhi Wang ret = shadow_indirect_ctx(wa_ctx); 2813be1da707SZhi Wang if (ret) { 2814695fbc08STina Zhang gvt_vgpu_err("fail to shadow indirect ctx\n"); 2815be1da707SZhi Wang return ret; 2816be1da707SZhi Wang } 2817be1da707SZhi Wang 2818be1da707SZhi Wang combine_wa_ctx(wa_ctx); 2819be1da707SZhi Wang 2820be1da707SZhi Wang ret = scan_wa_ctx(wa_ctx); 2821be1da707SZhi Wang if (ret) { 2822695fbc08STina Zhang gvt_vgpu_err("scan wa ctx error\n"); 2823be1da707SZhi Wang return ret; 2824be1da707SZhi Wang } 2825be1da707SZhi Wang 2826be1da707SZhi Wang return 0; 2827be1da707SZhi Wang } 2828be1da707SZhi Wang 2829be1da707SZhi Wang static struct cmd_info *find_cmd_entry_any_ring(struct intel_gvt *gvt, 283065e74392SChangbin Du unsigned int opcode, unsigned long rings) 2831be1da707SZhi Wang { 2832be1da707SZhi Wang struct cmd_info *info = NULL; 2833be1da707SZhi Wang unsigned int ring; 2834be1da707SZhi Wang 283565e74392SChangbin Du for_each_set_bit(ring, &rings, I915_NUM_ENGINES) { 2836be1da707SZhi Wang info = find_cmd_entry(gvt, opcode, ring); 2837be1da707SZhi Wang if (info) 2838be1da707SZhi Wang break; 2839be1da707SZhi Wang } 2840be1da707SZhi Wang return info; 2841be1da707SZhi Wang } 2842be1da707SZhi Wang 2843be1da707SZhi Wang static int init_cmd_table(struct intel_gvt *gvt) 2844be1da707SZhi Wang { 2845be1da707SZhi Wang int i; 2846be1da707SZhi Wang struct cmd_entry *e; 2847be1da707SZhi Wang struct cmd_info *info; 2848be1da707SZhi Wang unsigned int gen_type; 2849be1da707SZhi Wang 2850be1da707SZhi Wang gen_type = intel_gvt_get_device_type(gvt); 2851be1da707SZhi Wang 2852be1da707SZhi Wang for (i = 0; i < ARRAY_SIZE(cmd_info); i++) { 2853be1da707SZhi Wang if (!(cmd_info[i].devices & gen_type)) 2854be1da707SZhi Wang continue; 2855be1da707SZhi Wang 2856be1da707SZhi Wang e = kzalloc(sizeof(*e), GFP_KERNEL); 2857be1da707SZhi Wang if (!e) 2858be1da707SZhi Wang return -ENOMEM; 2859be1da707SZhi Wang 2860be1da707SZhi Wang e->info = &cmd_info[i]; 2861be1da707SZhi Wang info = find_cmd_entry_any_ring(gvt, 2862be1da707SZhi Wang e->info->opcode, e->info->rings); 2863be1da707SZhi Wang if (info) { 2864be1da707SZhi Wang gvt_err("%s %s duplicated\n", e->info->name, 2865be1da707SZhi Wang info->name); 2866be1da707SZhi Wang return -EEXIST; 2867be1da707SZhi Wang } 2868be1da707SZhi Wang 2869be1da707SZhi Wang INIT_HLIST_NODE(&e->hlist); 2870be1da707SZhi Wang add_cmd_entry(gvt, e); 2871be1da707SZhi Wang gvt_dbg_cmd("add %-30s op %04x flag %x devs %02x rings %02x\n", 2872be1da707SZhi Wang e->info->name, e->info->opcode, e->info->flag, 2873be1da707SZhi Wang e->info->devices, e->info->rings); 2874be1da707SZhi Wang } 2875be1da707SZhi Wang return 0; 2876be1da707SZhi Wang } 2877be1da707SZhi Wang 2878be1da707SZhi Wang static void clean_cmd_table(struct intel_gvt *gvt) 2879be1da707SZhi Wang { 2880be1da707SZhi Wang struct hlist_node *tmp; 2881be1da707SZhi Wang struct cmd_entry *e; 2882be1da707SZhi Wang int i; 2883be1da707SZhi Wang 2884be1da707SZhi Wang hash_for_each_safe(gvt->cmd_table, i, tmp, e, hlist) 2885be1da707SZhi Wang kfree(e); 2886be1da707SZhi Wang 2887be1da707SZhi Wang hash_init(gvt->cmd_table); 2888be1da707SZhi Wang } 2889be1da707SZhi Wang 2890be1da707SZhi Wang void intel_gvt_clean_cmd_parser(struct intel_gvt *gvt) 2891be1da707SZhi Wang { 2892be1da707SZhi Wang clean_cmd_table(gvt); 2893be1da707SZhi Wang } 2894be1da707SZhi Wang 2895be1da707SZhi Wang int intel_gvt_init_cmd_parser(struct intel_gvt *gvt) 2896be1da707SZhi Wang { 2897be1da707SZhi Wang int ret; 2898be1da707SZhi Wang 2899be1da707SZhi Wang ret = init_cmd_table(gvt); 2900be1da707SZhi Wang if (ret) { 2901be1da707SZhi Wang intel_gvt_clean_cmd_parser(gvt); 2902be1da707SZhi Wang return ret; 2903be1da707SZhi Wang } 2904be1da707SZhi Wang return 0; 2905be1da707SZhi Wang } 2906