1be1da707SZhi Wang /* 2be1da707SZhi Wang * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3be1da707SZhi Wang * 4be1da707SZhi Wang * Permission is hereby granted, free of charge, to any person obtaining a 5be1da707SZhi Wang * copy of this software and associated documentation files (the "Software"), 6be1da707SZhi Wang * to deal in the Software without restriction, including without limitation 7be1da707SZhi Wang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8be1da707SZhi Wang * and/or sell copies of the Software, and to permit persons to whom the 9be1da707SZhi Wang * Software is furnished to do so, subject to the following conditions: 10be1da707SZhi Wang * 11be1da707SZhi Wang * The above copyright notice and this permission notice (including the next 12be1da707SZhi Wang * paragraph) shall be included in all copies or substantial portions of the 13be1da707SZhi Wang * Software. 14be1da707SZhi Wang * 15be1da707SZhi Wang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16be1da707SZhi Wang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17be1da707SZhi Wang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18be1da707SZhi Wang * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19be1da707SZhi Wang * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20be1da707SZhi Wang * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21be1da707SZhi Wang * SOFTWARE. 22be1da707SZhi Wang * 23be1da707SZhi Wang * Authors: 24be1da707SZhi Wang * Ke Yu 25be1da707SZhi Wang * Kevin Tian <kevin.tian@intel.com> 26be1da707SZhi Wang * Zhiyuan Lv <zhiyuan.lv@intel.com> 27be1da707SZhi Wang * 28be1da707SZhi Wang * Contributors: 29be1da707SZhi Wang * Min He <min.he@intel.com> 30be1da707SZhi Wang * Ping Gao <ping.a.gao@intel.com> 31be1da707SZhi Wang * Tina Zhang <tina.zhang@intel.com> 32be1da707SZhi Wang * Yulei Zhang <yulei.zhang@intel.com> 33be1da707SZhi Wang * Zhi Wang <zhi.a.wang@intel.com> 34be1da707SZhi Wang * 35be1da707SZhi Wang */ 36be1da707SZhi Wang 37be1da707SZhi Wang #include <linux/slab.h> 382871ea85SChris Wilson 39be1da707SZhi Wang #include "i915_drv.h" 40202b1f4cSMatt Roper #include "gt/intel_engine_regs.h" 4145233ab2SChris Wilson #include "gt/intel_gpu_commands.h" 420d6419e9SMatt Roper #include "gt/intel_gt_regs.h" 43493f30cdSYan Zhao #include "gt/intel_lrc.h" 442871ea85SChris Wilson #include "gt/intel_ring.h" 45493f30cdSYan Zhao #include "gt/intel_gt_requests.h" 4697ea6565SChris Wilson #include "gt/shmem_utils.h" 47feddf6e8SZhenyu Wang #include "gvt.h" 48feddf6e8SZhenyu Wang #include "i915_pvinfo.h" 49be1da707SZhi Wang #include "trace.h" 50be1da707SZhi Wang 51493f30cdSYan Zhao #include "gem/i915_gem_context.h" 52493f30cdSYan Zhao #include "gem/i915_gem_pm.h" 53493f30cdSYan Zhao #include "gt/intel_context.h" 54493f30cdSYan Zhao 55be1da707SZhi Wang #define INVALID_OP (~0U) 56be1da707SZhi Wang 57be1da707SZhi Wang #define OP_LEN_MI 9 58be1da707SZhi Wang #define OP_LEN_2D 10 59be1da707SZhi Wang #define OP_LEN_3D_MEDIA 16 60be1da707SZhi Wang #define OP_LEN_MFX_VC 16 61be1da707SZhi Wang #define OP_LEN_VEBOX 16 62be1da707SZhi Wang 63be1da707SZhi Wang #define CMD_TYPE(cmd) (((cmd) >> 29) & 7) 64be1da707SZhi Wang 65be1da707SZhi Wang struct sub_op_bits { 66be1da707SZhi Wang int hi; 67be1da707SZhi Wang int low; 68be1da707SZhi Wang }; 69be1da707SZhi Wang struct decode_info { 70ed8cce30SJani Nikula const char *name; 71be1da707SZhi Wang int op_len; 72be1da707SZhi Wang int nr_sub_op; 73ed8cce30SJani Nikula const struct sub_op_bits *sub_op; 74be1da707SZhi Wang }; 75be1da707SZhi Wang 76be1da707SZhi Wang #define MAX_CMD_BUDGET 0x7fffffff 77be1da707SZhi Wang #define MI_WAIT_FOR_PLANE_C_FLIP_PENDING (1<<15) 78be1da707SZhi Wang #define MI_WAIT_FOR_PLANE_B_FLIP_PENDING (1<<9) 79be1da707SZhi Wang #define MI_WAIT_FOR_PLANE_A_FLIP_PENDING (1<<1) 80be1da707SZhi Wang 81be1da707SZhi Wang #define MI_WAIT_FOR_SPRITE_C_FLIP_PENDING (1<<20) 82be1da707SZhi Wang #define MI_WAIT_FOR_SPRITE_B_FLIP_PENDING (1<<10) 83be1da707SZhi Wang #define MI_WAIT_FOR_SPRITE_A_FLIP_PENDING (1<<2) 84be1da707SZhi Wang 85be1da707SZhi Wang /* Render Command Map */ 86be1da707SZhi Wang 87be1da707SZhi Wang /* MI_* command Opcode (28:23) */ 88be1da707SZhi Wang #define OP_MI_NOOP 0x0 89be1da707SZhi Wang #define OP_MI_SET_PREDICATE 0x1 /* HSW+ */ 90be1da707SZhi Wang #define OP_MI_USER_INTERRUPT 0x2 91be1da707SZhi Wang #define OP_MI_WAIT_FOR_EVENT 0x3 92be1da707SZhi Wang #define OP_MI_FLUSH 0x4 93be1da707SZhi Wang #define OP_MI_ARB_CHECK 0x5 94be1da707SZhi Wang #define OP_MI_RS_CONTROL 0x6 /* HSW+ */ 95be1da707SZhi Wang #define OP_MI_REPORT_HEAD 0x7 96be1da707SZhi Wang #define OP_MI_ARB_ON_OFF 0x8 97be1da707SZhi Wang #define OP_MI_URB_ATOMIC_ALLOC 0x9 /* HSW+ */ 98be1da707SZhi Wang #define OP_MI_BATCH_BUFFER_END 0xA 99be1da707SZhi Wang #define OP_MI_SUSPEND_FLUSH 0xB 100be1da707SZhi Wang #define OP_MI_PREDICATE 0xC /* IVB+ */ 101be1da707SZhi Wang #define OP_MI_TOPOLOGY_FILTER 0xD /* IVB+ */ 102be1da707SZhi Wang #define OP_MI_SET_APPID 0xE /* IVB+ */ 103be1da707SZhi Wang #define OP_MI_RS_CONTEXT 0xF /* HSW+ */ 104be1da707SZhi Wang #define OP_MI_LOAD_SCAN_LINES_INCL 0x12 /* HSW+ */ 105be1da707SZhi Wang #define OP_MI_DISPLAY_FLIP 0x14 106be1da707SZhi Wang #define OP_MI_SEMAPHORE_MBOX 0x16 107be1da707SZhi Wang #define OP_MI_SET_CONTEXT 0x18 108be1da707SZhi Wang #define OP_MI_MATH 0x1A 109be1da707SZhi Wang #define OP_MI_URB_CLEAR 0x19 110be1da707SZhi Wang #define OP_MI_SEMAPHORE_SIGNAL 0x1B /* BDW+ */ 111be1da707SZhi Wang #define OP_MI_SEMAPHORE_WAIT 0x1C /* BDW+ */ 112be1da707SZhi Wang 113be1da707SZhi Wang #define OP_MI_STORE_DATA_IMM 0x20 114be1da707SZhi Wang #define OP_MI_STORE_DATA_INDEX 0x21 115be1da707SZhi Wang #define OP_MI_LOAD_REGISTER_IMM 0x22 116be1da707SZhi Wang #define OP_MI_UPDATE_GTT 0x23 117be1da707SZhi Wang #define OP_MI_STORE_REGISTER_MEM 0x24 118be1da707SZhi Wang #define OP_MI_FLUSH_DW 0x26 119be1da707SZhi Wang #define OP_MI_CLFLUSH 0x27 120be1da707SZhi Wang #define OP_MI_REPORT_PERF_COUNT 0x28 121be1da707SZhi Wang #define OP_MI_LOAD_REGISTER_MEM 0x29 /* HSW+ */ 122be1da707SZhi Wang #define OP_MI_LOAD_REGISTER_REG 0x2A /* HSW+ */ 123be1da707SZhi Wang #define OP_MI_RS_STORE_DATA_IMM 0x2B /* HSW+ */ 124be1da707SZhi Wang #define OP_MI_LOAD_URB_MEM 0x2C /* HSW+ */ 125be1da707SZhi Wang #define OP_MI_STORE_URM_MEM 0x2D /* HSW+ */ 126be1da707SZhi Wang #define OP_MI_2E 0x2E /* BDW+ */ 127be1da707SZhi Wang #define OP_MI_2F 0x2F /* BDW+ */ 128be1da707SZhi Wang #define OP_MI_BATCH_BUFFER_START 0x31 129be1da707SZhi Wang 130be1da707SZhi Wang /* Bit definition for dword 0 */ 131be1da707SZhi Wang #define _CMDBIT_BB_START_IN_PPGTT (1UL << 8) 132be1da707SZhi Wang 133be1da707SZhi Wang #define OP_MI_CONDITIONAL_BATCH_BUFFER_END 0x36 134be1da707SZhi Wang 135be1da707SZhi Wang #define BATCH_BUFFER_ADDR_MASK ((1UL << 32) - (1U << 2)) 136be1da707SZhi Wang #define BATCH_BUFFER_ADDR_HIGH_MASK ((1UL << 16) - (1U)) 137be1da707SZhi Wang #define BATCH_BUFFER_ADR_SPACE_BIT(x) (((x) >> 8) & 1U) 138be1da707SZhi Wang #define BATCH_BUFFER_2ND_LEVEL_BIT(x) ((x) >> 22 & 1U) 139be1da707SZhi Wang 140be1da707SZhi Wang /* 2D command: Opcode (28:22) */ 141be1da707SZhi Wang #define OP_2D(x) ((2<<7) | x) 142be1da707SZhi Wang 143be1da707SZhi Wang #define OP_XY_SETUP_BLT OP_2D(0x1) 144be1da707SZhi Wang #define OP_XY_SETUP_CLIP_BLT OP_2D(0x3) 145be1da707SZhi Wang #define OP_XY_SETUP_MONO_PATTERN_SL_BLT OP_2D(0x11) 146be1da707SZhi Wang #define OP_XY_PIXEL_BLT OP_2D(0x24) 147be1da707SZhi Wang #define OP_XY_SCANLINES_BLT OP_2D(0x25) 148be1da707SZhi Wang #define OP_XY_TEXT_BLT OP_2D(0x26) 149be1da707SZhi Wang #define OP_XY_TEXT_IMMEDIATE_BLT OP_2D(0x31) 150be1da707SZhi Wang #define OP_XY_COLOR_BLT OP_2D(0x50) 151be1da707SZhi Wang #define OP_XY_PAT_BLT OP_2D(0x51) 152be1da707SZhi Wang #define OP_XY_MONO_PAT_BLT OP_2D(0x52) 153be1da707SZhi Wang #define OP_XY_SRC_COPY_BLT OP_2D(0x53) 154be1da707SZhi Wang #define OP_XY_MONO_SRC_COPY_BLT OP_2D(0x54) 155be1da707SZhi Wang #define OP_XY_FULL_BLT OP_2D(0x55) 156be1da707SZhi Wang #define OP_XY_FULL_MONO_SRC_BLT OP_2D(0x56) 157be1da707SZhi Wang #define OP_XY_FULL_MONO_PATTERN_BLT OP_2D(0x57) 158be1da707SZhi Wang #define OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT OP_2D(0x58) 159be1da707SZhi Wang #define OP_XY_MONO_PAT_FIXED_BLT OP_2D(0x59) 160be1da707SZhi Wang #define OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT OP_2D(0x71) 161be1da707SZhi Wang #define OP_XY_PAT_BLT_IMMEDIATE OP_2D(0x72) 162be1da707SZhi Wang #define OP_XY_SRC_COPY_CHROMA_BLT OP_2D(0x73) 163be1da707SZhi Wang #define OP_XY_FULL_IMMEDIATE_PATTERN_BLT OP_2D(0x74) 164be1da707SZhi Wang #define OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT OP_2D(0x75) 165be1da707SZhi Wang #define OP_XY_PAT_CHROMA_BLT OP_2D(0x76) 166be1da707SZhi Wang #define OP_XY_PAT_CHROMA_BLT_IMMEDIATE OP_2D(0x77) 167be1da707SZhi Wang 168be1da707SZhi Wang /* 3D/Media Command: Pipeline Type(28:27) Opcode(26:24) Sub Opcode(23:16) */ 169be1da707SZhi Wang #define OP_3D_MEDIA(sub_type, opcode, sub_opcode) \ 170be1da707SZhi Wang ((3 << 13) | ((sub_type) << 11) | ((opcode) << 8) | (sub_opcode)) 171be1da707SZhi Wang 172be1da707SZhi Wang #define OP_STATE_PREFETCH OP_3D_MEDIA(0x0, 0x0, 0x03) 173be1da707SZhi Wang 174be1da707SZhi Wang #define OP_STATE_BASE_ADDRESS OP_3D_MEDIA(0x0, 0x1, 0x01) 175be1da707SZhi Wang #define OP_STATE_SIP OP_3D_MEDIA(0x0, 0x1, 0x02) 176be1da707SZhi Wang #define OP_3D_MEDIA_0_1_4 OP_3D_MEDIA(0x0, 0x1, 0x04) 1772484b172SYan Zhao #define OP_SWTESS_BASE_ADDRESS OP_3D_MEDIA(0x0, 0x1, 0x03) 178be1da707SZhi Wang 179be1da707SZhi Wang #define OP_3DSTATE_VF_STATISTICS_GM45 OP_3D_MEDIA(0x1, 0x0, 0x0B) 180be1da707SZhi Wang 181be1da707SZhi Wang #define OP_PIPELINE_SELECT OP_3D_MEDIA(0x1, 0x1, 0x04) 182be1da707SZhi Wang 183be1da707SZhi Wang #define OP_MEDIA_VFE_STATE OP_3D_MEDIA(0x2, 0x0, 0x0) 184be1da707SZhi Wang #define OP_MEDIA_CURBE_LOAD OP_3D_MEDIA(0x2, 0x0, 0x1) 185be1da707SZhi Wang #define OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD OP_3D_MEDIA(0x2, 0x0, 0x2) 186be1da707SZhi Wang #define OP_MEDIA_GATEWAY_STATE OP_3D_MEDIA(0x2, 0x0, 0x3) 187be1da707SZhi Wang #define OP_MEDIA_STATE_FLUSH OP_3D_MEDIA(0x2, 0x0, 0x4) 18802b966c1SColin Xu #define OP_MEDIA_POOL_STATE OP_3D_MEDIA(0x2, 0x0, 0x5) 189be1da707SZhi Wang 190be1da707SZhi Wang #define OP_MEDIA_OBJECT OP_3D_MEDIA(0x2, 0x1, 0x0) 191be1da707SZhi Wang #define OP_MEDIA_OBJECT_PRT OP_3D_MEDIA(0x2, 0x1, 0x2) 192be1da707SZhi Wang #define OP_MEDIA_OBJECT_WALKER OP_3D_MEDIA(0x2, 0x1, 0x3) 193be1da707SZhi Wang #define OP_GPGPU_WALKER OP_3D_MEDIA(0x2, 0x1, 0x5) 194be1da707SZhi Wang 195be1da707SZhi Wang #define OP_3DSTATE_CLEAR_PARAMS OP_3D_MEDIA(0x3, 0x0, 0x04) /* IVB+ */ 196be1da707SZhi Wang #define OP_3DSTATE_DEPTH_BUFFER OP_3D_MEDIA(0x3, 0x0, 0x05) /* IVB+ */ 197be1da707SZhi Wang #define OP_3DSTATE_STENCIL_BUFFER OP_3D_MEDIA(0x3, 0x0, 0x06) /* IVB+ */ 198be1da707SZhi Wang #define OP_3DSTATE_HIER_DEPTH_BUFFER OP_3D_MEDIA(0x3, 0x0, 0x07) /* IVB+ */ 199be1da707SZhi Wang #define OP_3DSTATE_VERTEX_BUFFERS OP_3D_MEDIA(0x3, 0x0, 0x08) 200be1da707SZhi Wang #define OP_3DSTATE_VERTEX_ELEMENTS OP_3D_MEDIA(0x3, 0x0, 0x09) 201be1da707SZhi Wang #define OP_3DSTATE_INDEX_BUFFER OP_3D_MEDIA(0x3, 0x0, 0x0A) 202be1da707SZhi Wang #define OP_3DSTATE_VF_STATISTICS OP_3D_MEDIA(0x3, 0x0, 0x0B) 203be1da707SZhi Wang #define OP_3DSTATE_VF OP_3D_MEDIA(0x3, 0x0, 0x0C) /* HSW+ */ 204be1da707SZhi Wang #define OP_3DSTATE_CC_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x0E) 205be1da707SZhi Wang #define OP_3DSTATE_SCISSOR_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x0F) 206be1da707SZhi Wang #define OP_3DSTATE_VS OP_3D_MEDIA(0x3, 0x0, 0x10) 207be1da707SZhi Wang #define OP_3DSTATE_GS OP_3D_MEDIA(0x3, 0x0, 0x11) 208be1da707SZhi Wang #define OP_3DSTATE_CLIP OP_3D_MEDIA(0x3, 0x0, 0x12) 209be1da707SZhi Wang #define OP_3DSTATE_SF OP_3D_MEDIA(0x3, 0x0, 0x13) 210be1da707SZhi Wang #define OP_3DSTATE_WM OP_3D_MEDIA(0x3, 0x0, 0x14) 211be1da707SZhi Wang #define OP_3DSTATE_CONSTANT_VS OP_3D_MEDIA(0x3, 0x0, 0x15) 212be1da707SZhi Wang #define OP_3DSTATE_CONSTANT_GS OP_3D_MEDIA(0x3, 0x0, 0x16) 213be1da707SZhi Wang #define OP_3DSTATE_CONSTANT_PS OP_3D_MEDIA(0x3, 0x0, 0x17) 214be1da707SZhi Wang #define OP_3DSTATE_SAMPLE_MASK OP_3D_MEDIA(0x3, 0x0, 0x18) 215be1da707SZhi Wang #define OP_3DSTATE_CONSTANT_HS OP_3D_MEDIA(0x3, 0x0, 0x19) /* IVB+ */ 216be1da707SZhi Wang #define OP_3DSTATE_CONSTANT_DS OP_3D_MEDIA(0x3, 0x0, 0x1A) /* IVB+ */ 217be1da707SZhi Wang #define OP_3DSTATE_HS OP_3D_MEDIA(0x3, 0x0, 0x1B) /* IVB+ */ 218be1da707SZhi Wang #define OP_3DSTATE_TE OP_3D_MEDIA(0x3, 0x0, 0x1C) /* IVB+ */ 219be1da707SZhi Wang #define OP_3DSTATE_DS OP_3D_MEDIA(0x3, 0x0, 0x1D) /* IVB+ */ 220be1da707SZhi Wang #define OP_3DSTATE_STREAMOUT OP_3D_MEDIA(0x3, 0x0, 0x1E) /* IVB+ */ 221be1da707SZhi Wang #define OP_3DSTATE_SBE OP_3D_MEDIA(0x3, 0x0, 0x1F) /* IVB+ */ 222be1da707SZhi Wang #define OP_3DSTATE_PS OP_3D_MEDIA(0x3, 0x0, 0x20) /* IVB+ */ 223be1da707SZhi Wang #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP OP_3D_MEDIA(0x3, 0x0, 0x21) /* IVB+ */ 224be1da707SZhi Wang #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC OP_3D_MEDIA(0x3, 0x0, 0x23) /* IVB+ */ 225be1da707SZhi Wang #define OP_3DSTATE_BLEND_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x24) /* IVB+ */ 226be1da707SZhi Wang #define OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x25) /* IVB+ */ 227be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_POINTERS_VS OP_3D_MEDIA(0x3, 0x0, 0x26) /* IVB+ */ 228be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_POINTERS_HS OP_3D_MEDIA(0x3, 0x0, 0x27) /* IVB+ */ 229be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_POINTERS_DS OP_3D_MEDIA(0x3, 0x0, 0x28) /* IVB+ */ 230be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_POINTERS_GS OP_3D_MEDIA(0x3, 0x0, 0x29) /* IVB+ */ 231be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_POINTERS_PS OP_3D_MEDIA(0x3, 0x0, 0x2A) /* IVB+ */ 232be1da707SZhi Wang #define OP_3DSTATE_SAMPLER_STATE_POINTERS_VS OP_3D_MEDIA(0x3, 0x0, 0x2B) /* IVB+ */ 233be1da707SZhi Wang #define OP_3DSTATE_SAMPLER_STATE_POINTERS_HS OP_3D_MEDIA(0x3, 0x0, 0x2C) /* IVB+ */ 234be1da707SZhi Wang #define OP_3DSTATE_SAMPLER_STATE_POINTERS_DS OP_3D_MEDIA(0x3, 0x0, 0x2D) /* IVB+ */ 235be1da707SZhi Wang #define OP_3DSTATE_SAMPLER_STATE_POINTERS_GS OP_3D_MEDIA(0x3, 0x0, 0x2E) /* IVB+ */ 236be1da707SZhi Wang #define OP_3DSTATE_SAMPLER_STATE_POINTERS_PS OP_3D_MEDIA(0x3, 0x0, 0x2F) /* IVB+ */ 237be1da707SZhi Wang #define OP_3DSTATE_URB_VS OP_3D_MEDIA(0x3, 0x0, 0x30) /* IVB+ */ 238be1da707SZhi Wang #define OP_3DSTATE_URB_HS OP_3D_MEDIA(0x3, 0x0, 0x31) /* IVB+ */ 239be1da707SZhi Wang #define OP_3DSTATE_URB_DS OP_3D_MEDIA(0x3, 0x0, 0x32) /* IVB+ */ 240be1da707SZhi Wang #define OP_3DSTATE_URB_GS OP_3D_MEDIA(0x3, 0x0, 0x33) /* IVB+ */ 241be1da707SZhi Wang #define OP_3DSTATE_GATHER_CONSTANT_VS OP_3D_MEDIA(0x3, 0x0, 0x34) /* HSW+ */ 242be1da707SZhi Wang #define OP_3DSTATE_GATHER_CONSTANT_GS OP_3D_MEDIA(0x3, 0x0, 0x35) /* HSW+ */ 243be1da707SZhi Wang #define OP_3DSTATE_GATHER_CONSTANT_HS OP_3D_MEDIA(0x3, 0x0, 0x36) /* HSW+ */ 244be1da707SZhi Wang #define OP_3DSTATE_GATHER_CONSTANT_DS OP_3D_MEDIA(0x3, 0x0, 0x37) /* HSW+ */ 245be1da707SZhi Wang #define OP_3DSTATE_GATHER_CONSTANT_PS OP_3D_MEDIA(0x3, 0x0, 0x38) /* HSW+ */ 246be1da707SZhi Wang #define OP_3DSTATE_DX9_CONSTANTF_VS OP_3D_MEDIA(0x3, 0x0, 0x39) /* HSW+ */ 247be1da707SZhi Wang #define OP_3DSTATE_DX9_CONSTANTF_PS OP_3D_MEDIA(0x3, 0x0, 0x3A) /* HSW+ */ 248be1da707SZhi Wang #define OP_3DSTATE_DX9_CONSTANTI_VS OP_3D_MEDIA(0x3, 0x0, 0x3B) /* HSW+ */ 249be1da707SZhi Wang #define OP_3DSTATE_DX9_CONSTANTI_PS OP_3D_MEDIA(0x3, 0x0, 0x3C) /* HSW+ */ 250be1da707SZhi Wang #define OP_3DSTATE_DX9_CONSTANTB_VS OP_3D_MEDIA(0x3, 0x0, 0x3D) /* HSW+ */ 251be1da707SZhi Wang #define OP_3DSTATE_DX9_CONSTANTB_PS OP_3D_MEDIA(0x3, 0x0, 0x3E) /* HSW+ */ 252be1da707SZhi Wang #define OP_3DSTATE_DX9_LOCAL_VALID_VS OP_3D_MEDIA(0x3, 0x0, 0x3F) /* HSW+ */ 253be1da707SZhi Wang #define OP_3DSTATE_DX9_LOCAL_VALID_PS OP_3D_MEDIA(0x3, 0x0, 0x40) /* HSW+ */ 254be1da707SZhi Wang #define OP_3DSTATE_DX9_GENERATE_ACTIVE_VS OP_3D_MEDIA(0x3, 0x0, 0x41) /* HSW+ */ 255be1da707SZhi Wang #define OP_3DSTATE_DX9_GENERATE_ACTIVE_PS OP_3D_MEDIA(0x3, 0x0, 0x42) /* HSW+ */ 256be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_EDIT_VS OP_3D_MEDIA(0x3, 0x0, 0x43) /* HSW+ */ 257be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_EDIT_GS OP_3D_MEDIA(0x3, 0x0, 0x44) /* HSW+ */ 258be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_EDIT_HS OP_3D_MEDIA(0x3, 0x0, 0x45) /* HSW+ */ 259be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_EDIT_DS OP_3D_MEDIA(0x3, 0x0, 0x46) /* HSW+ */ 260be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_EDIT_PS OP_3D_MEDIA(0x3, 0x0, 0x47) /* HSW+ */ 261be1da707SZhi Wang 262be1da707SZhi Wang #define OP_3DSTATE_VF_INSTANCING OP_3D_MEDIA(0x3, 0x0, 0x49) /* BDW+ */ 263be1da707SZhi Wang #define OP_3DSTATE_VF_SGVS OP_3D_MEDIA(0x3, 0x0, 0x4A) /* BDW+ */ 264be1da707SZhi Wang #define OP_3DSTATE_VF_TOPOLOGY OP_3D_MEDIA(0x3, 0x0, 0x4B) /* BDW+ */ 265be1da707SZhi Wang #define OP_3DSTATE_WM_CHROMAKEY OP_3D_MEDIA(0x3, 0x0, 0x4C) /* BDW+ */ 266be1da707SZhi Wang #define OP_3DSTATE_PS_BLEND OP_3D_MEDIA(0x3, 0x0, 0x4D) /* BDW+ */ 267be1da707SZhi Wang #define OP_3DSTATE_WM_DEPTH_STENCIL OP_3D_MEDIA(0x3, 0x0, 0x4E) /* BDW+ */ 268be1da707SZhi Wang #define OP_3DSTATE_PS_EXTRA OP_3D_MEDIA(0x3, 0x0, 0x4F) /* BDW+ */ 269be1da707SZhi Wang #define OP_3DSTATE_RASTER OP_3D_MEDIA(0x3, 0x0, 0x50) /* BDW+ */ 270be1da707SZhi Wang #define OP_3DSTATE_SBE_SWIZ OP_3D_MEDIA(0x3, 0x0, 0x51) /* BDW+ */ 271be1da707SZhi Wang #define OP_3DSTATE_WM_HZ_OP OP_3D_MEDIA(0x3, 0x0, 0x52) /* BDW+ */ 272be1da707SZhi Wang #define OP_3DSTATE_COMPONENT_PACKING OP_3D_MEDIA(0x3, 0x0, 0x55) /* SKL+ */ 273be1da707SZhi Wang 274be1da707SZhi Wang #define OP_3DSTATE_DRAWING_RECTANGLE OP_3D_MEDIA(0x3, 0x1, 0x00) 275be1da707SZhi Wang #define OP_3DSTATE_SAMPLER_PALETTE_LOAD0 OP_3D_MEDIA(0x3, 0x1, 0x02) 276be1da707SZhi Wang #define OP_3DSTATE_CHROMA_KEY OP_3D_MEDIA(0x3, 0x1, 0x04) 277be1da707SZhi Wang #define OP_SNB_3DSTATE_DEPTH_BUFFER OP_3D_MEDIA(0x3, 0x1, 0x05) 278be1da707SZhi Wang #define OP_3DSTATE_POLY_STIPPLE_OFFSET OP_3D_MEDIA(0x3, 0x1, 0x06) 279be1da707SZhi Wang #define OP_3DSTATE_POLY_STIPPLE_PATTERN OP_3D_MEDIA(0x3, 0x1, 0x07) 280be1da707SZhi Wang #define OP_3DSTATE_LINE_STIPPLE OP_3D_MEDIA(0x3, 0x1, 0x08) 281be1da707SZhi Wang #define OP_3DSTATE_AA_LINE_PARAMS OP_3D_MEDIA(0x3, 0x1, 0x0A) 282be1da707SZhi Wang #define OP_3DSTATE_GS_SVB_INDEX OP_3D_MEDIA(0x3, 0x1, 0x0B) 283be1da707SZhi Wang #define OP_3DSTATE_SAMPLER_PALETTE_LOAD1 OP_3D_MEDIA(0x3, 0x1, 0x0C) 284be1da707SZhi Wang #define OP_3DSTATE_MULTISAMPLE_BDW OP_3D_MEDIA(0x3, 0x0, 0x0D) 285be1da707SZhi Wang #define OP_SNB_3DSTATE_STENCIL_BUFFER OP_3D_MEDIA(0x3, 0x1, 0x0E) 286be1da707SZhi Wang #define OP_SNB_3DSTATE_HIER_DEPTH_BUFFER OP_3D_MEDIA(0x3, 0x1, 0x0F) 287be1da707SZhi Wang #define OP_SNB_3DSTATE_CLEAR_PARAMS OP_3D_MEDIA(0x3, 0x1, 0x10) 288be1da707SZhi Wang #define OP_3DSTATE_MONOFILTER_SIZE OP_3D_MEDIA(0x3, 0x1, 0x11) 289be1da707SZhi Wang #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS OP_3D_MEDIA(0x3, 0x1, 0x12) /* IVB+ */ 290be1da707SZhi Wang #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS OP_3D_MEDIA(0x3, 0x1, 0x13) /* IVB+ */ 291be1da707SZhi Wang #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS OP_3D_MEDIA(0x3, 0x1, 0x14) /* IVB+ */ 292be1da707SZhi Wang #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS OP_3D_MEDIA(0x3, 0x1, 0x15) /* IVB+ */ 293be1da707SZhi Wang #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS OP_3D_MEDIA(0x3, 0x1, 0x16) /* IVB+ */ 294be1da707SZhi Wang #define OP_3DSTATE_SO_DECL_LIST OP_3D_MEDIA(0x3, 0x1, 0x17) 295be1da707SZhi Wang #define OP_3DSTATE_SO_BUFFER OP_3D_MEDIA(0x3, 0x1, 0x18) 296be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x19) /* HSW+ */ 297be1da707SZhi Wang #define OP_3DSTATE_GATHER_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x1A) /* HSW+ */ 298be1da707SZhi Wang #define OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x1B) /* HSW+ */ 299be1da707SZhi Wang #define OP_3DSTATE_SAMPLE_PATTERN OP_3D_MEDIA(0x3, 0x1, 0x1C) 300be1da707SZhi Wang #define OP_PIPE_CONTROL OP_3D_MEDIA(0x3, 0x2, 0x00) 301be1da707SZhi Wang #define OP_3DPRIMITIVE OP_3D_MEDIA(0x3, 0x3, 0x00) 302be1da707SZhi Wang 303be1da707SZhi Wang /* VCCP Command Parser */ 304be1da707SZhi Wang 305be1da707SZhi Wang /* 306be1da707SZhi Wang * Below MFX and VBE cmd definition is from vaapi intel driver project (BSD License) 307be1da707SZhi Wang * git://anongit.freedesktop.org/vaapi/intel-driver 308be1da707SZhi Wang * src/i965_defines.h 309be1da707SZhi Wang * 310be1da707SZhi Wang */ 311be1da707SZhi Wang 312be1da707SZhi Wang #define OP_MFX(pipeline, op, sub_opa, sub_opb) \ 313be1da707SZhi Wang (3 << 13 | \ 314be1da707SZhi Wang (pipeline) << 11 | \ 315be1da707SZhi Wang (op) << 8 | \ 316be1da707SZhi Wang (sub_opa) << 5 | \ 317be1da707SZhi Wang (sub_opb)) 318be1da707SZhi Wang 319be1da707SZhi Wang #define OP_MFX_PIPE_MODE_SELECT OP_MFX(2, 0, 0, 0) /* ALL */ 320be1da707SZhi Wang #define OP_MFX_SURFACE_STATE OP_MFX(2, 0, 0, 1) /* ALL */ 321be1da707SZhi Wang #define OP_MFX_PIPE_BUF_ADDR_STATE OP_MFX(2, 0, 0, 2) /* ALL */ 322be1da707SZhi Wang #define OP_MFX_IND_OBJ_BASE_ADDR_STATE OP_MFX(2, 0, 0, 3) /* ALL */ 323be1da707SZhi Wang #define OP_MFX_BSP_BUF_BASE_ADDR_STATE OP_MFX(2, 0, 0, 4) /* ALL */ 324be1da707SZhi Wang #define OP_2_0_0_5 OP_MFX(2, 0, 0, 5) /* ALL */ 325be1da707SZhi Wang #define OP_MFX_STATE_POINTER OP_MFX(2, 0, 0, 6) /* ALL */ 326be1da707SZhi Wang #define OP_MFX_QM_STATE OP_MFX(2, 0, 0, 7) /* IVB+ */ 327be1da707SZhi Wang #define OP_MFX_FQM_STATE OP_MFX(2, 0, 0, 8) /* IVB+ */ 328be1da707SZhi Wang #define OP_MFX_PAK_INSERT_OBJECT OP_MFX(2, 0, 2, 8) /* IVB+ */ 329be1da707SZhi Wang #define OP_MFX_STITCH_OBJECT OP_MFX(2, 0, 2, 0xA) /* IVB+ */ 330be1da707SZhi Wang 331be1da707SZhi Wang #define OP_MFD_IT_OBJECT OP_MFX(2, 0, 1, 9) /* ALL */ 332be1da707SZhi Wang 333be1da707SZhi Wang #define OP_MFX_WAIT OP_MFX(1, 0, 0, 0) /* IVB+ */ 334be1da707SZhi Wang #define OP_MFX_AVC_IMG_STATE OP_MFX(2, 1, 0, 0) /* ALL */ 335be1da707SZhi Wang #define OP_MFX_AVC_QM_STATE OP_MFX(2, 1, 0, 1) /* ALL */ 336be1da707SZhi Wang #define OP_MFX_AVC_DIRECTMODE_STATE OP_MFX(2, 1, 0, 2) /* ALL */ 337be1da707SZhi Wang #define OP_MFX_AVC_SLICE_STATE OP_MFX(2, 1, 0, 3) /* ALL */ 338be1da707SZhi Wang #define OP_MFX_AVC_REF_IDX_STATE OP_MFX(2, 1, 0, 4) /* ALL */ 339be1da707SZhi Wang #define OP_MFX_AVC_WEIGHTOFFSET_STATE OP_MFX(2, 1, 0, 5) /* ALL */ 340be1da707SZhi Wang #define OP_MFD_AVC_PICID_STATE OP_MFX(2, 1, 1, 5) /* HSW+ */ 341be1da707SZhi Wang #define OP_MFD_AVC_DPB_STATE OP_MFX(2, 1, 1, 6) /* IVB+ */ 342be1da707SZhi Wang #define OP_MFD_AVC_SLICEADDR OP_MFX(2, 1, 1, 7) /* IVB+ */ 343be1da707SZhi Wang #define OP_MFD_AVC_BSD_OBJECT OP_MFX(2, 1, 1, 8) /* ALL */ 344be1da707SZhi Wang #define OP_MFC_AVC_PAK_OBJECT OP_MFX(2, 1, 2, 9) /* ALL */ 345be1da707SZhi Wang 346be1da707SZhi Wang #define OP_MFX_VC1_PRED_PIPE_STATE OP_MFX(2, 2, 0, 1) /* ALL */ 347be1da707SZhi Wang #define OP_MFX_VC1_DIRECTMODE_STATE OP_MFX(2, 2, 0, 2) /* ALL */ 348be1da707SZhi Wang #define OP_MFD_VC1_SHORT_PIC_STATE OP_MFX(2, 2, 1, 0) /* IVB+ */ 349be1da707SZhi Wang #define OP_MFD_VC1_LONG_PIC_STATE OP_MFX(2, 2, 1, 1) /* IVB+ */ 350be1da707SZhi Wang #define OP_MFD_VC1_BSD_OBJECT OP_MFX(2, 2, 1, 8) /* ALL */ 351be1da707SZhi Wang 352be1da707SZhi Wang #define OP_MFX_MPEG2_PIC_STATE OP_MFX(2, 3, 0, 0) /* ALL */ 353be1da707SZhi Wang #define OP_MFX_MPEG2_QM_STATE OP_MFX(2, 3, 0, 1) /* ALL */ 354be1da707SZhi Wang #define OP_MFD_MPEG2_BSD_OBJECT OP_MFX(2, 3, 1, 8) /* ALL */ 355be1da707SZhi Wang #define OP_MFC_MPEG2_SLICEGROUP_STATE OP_MFX(2, 3, 2, 3) /* ALL */ 356be1da707SZhi Wang #define OP_MFC_MPEG2_PAK_OBJECT OP_MFX(2, 3, 2, 9) /* ALL */ 357be1da707SZhi Wang 358be1da707SZhi Wang #define OP_MFX_2_6_0_0 OP_MFX(2, 6, 0, 0) /* IVB+ */ 359be1da707SZhi Wang #define OP_MFX_2_6_0_8 OP_MFX(2, 6, 0, 8) /* IVB+ */ 360be1da707SZhi Wang #define OP_MFX_2_6_0_9 OP_MFX(2, 6, 0, 9) /* IVB+ */ 361be1da707SZhi Wang 362be1da707SZhi Wang #define OP_MFX_JPEG_PIC_STATE OP_MFX(2, 7, 0, 0) 363be1da707SZhi Wang #define OP_MFX_JPEG_HUFF_TABLE_STATE OP_MFX(2, 7, 0, 2) 364be1da707SZhi Wang #define OP_MFD_JPEG_BSD_OBJECT OP_MFX(2, 7, 1, 8) 365be1da707SZhi Wang 366be1da707SZhi Wang #define OP_VEB(pipeline, op, sub_opa, sub_opb) \ 367be1da707SZhi Wang (3 << 13 | \ 368be1da707SZhi Wang (pipeline) << 11 | \ 369be1da707SZhi Wang (op) << 8 | \ 370be1da707SZhi Wang (sub_opa) << 5 | \ 371be1da707SZhi Wang (sub_opb)) 372be1da707SZhi Wang 373be1da707SZhi Wang #define OP_VEB_SURFACE_STATE OP_VEB(2, 4, 0, 0) 374be1da707SZhi Wang #define OP_VEB_STATE OP_VEB(2, 4, 0, 2) 375be1da707SZhi Wang #define OP_VEB_DNDI_IECP_STATE OP_VEB(2, 4, 0, 3) 376be1da707SZhi Wang 377be1da707SZhi Wang struct parser_exec_state; 378be1da707SZhi Wang 379be1da707SZhi Wang typedef int (*parser_cmd_handler)(struct parser_exec_state *s); 380be1da707SZhi Wang 381be1da707SZhi Wang #define GVT_CMD_HASH_BITS 7 382be1da707SZhi Wang 383be1da707SZhi Wang /* which DWords need address fix */ 384be1da707SZhi Wang #define ADDR_FIX_1(x1) (1 << (x1)) 385be1da707SZhi Wang #define ADDR_FIX_2(x1, x2) (ADDR_FIX_1(x1) | ADDR_FIX_1(x2)) 386be1da707SZhi Wang #define ADDR_FIX_3(x1, x2, x3) (ADDR_FIX_1(x1) | ADDR_FIX_2(x2, x3)) 387be1da707SZhi Wang #define ADDR_FIX_4(x1, x2, x3, x4) (ADDR_FIX_1(x1) | ADDR_FIX_3(x2, x3, x4)) 388be1da707SZhi Wang #define ADDR_FIX_5(x1, x2, x3, x4, x5) (ADDR_FIX_1(x1) | ADDR_FIX_4(x2, x3, x4, x5)) 389be1da707SZhi Wang 39000a33be4SGao, Fred #define DWORD_FIELD(dword, end, start) \ 39100a33be4SGao, Fred FIELD_GET(GENMASK(end, start), cmd_val(s, dword)) 39200a33be4SGao, Fred 3931e2adc0dSGao, Fred #define OP_LENGTH_BIAS 2 3941e2adc0dSGao, Fred #define CMD_LEN(value) (value + OP_LENGTH_BIAS) 3951e2adc0dSGao, Fred 3961e2adc0dSGao, Fred static int gvt_check_valid_cmd_length(int len, int valid_len) 3971e2adc0dSGao, Fred { 3981e2adc0dSGao, Fred if (valid_len != len) { 3991e2adc0dSGao, Fred gvt_err("len is not valid: len=%u valid_len=%u\n", 4001e2adc0dSGao, Fred len, valid_len); 4011e2adc0dSGao, Fred return -EFAULT; 4021e2adc0dSGao, Fred } 4031e2adc0dSGao, Fred return 0; 4041e2adc0dSGao, Fred } 4051e2adc0dSGao, Fred 406be1da707SZhi Wang struct cmd_info { 407b007065aSJani Nikula const char *name; 408be1da707SZhi Wang u32 opcode; 409be1da707SZhi Wang 4104f870f1fSGao, Fred #define F_LEN_MASK 3U 411be1da707SZhi Wang #define F_LEN_CONST 1U 412be1da707SZhi Wang #define F_LEN_VAR 0U 4134f870f1fSGao, Fred /* value is const although LEN maybe variable */ 4144f870f1fSGao, Fred #define F_LEN_VAR_FIXED (1<<1) 415be1da707SZhi Wang 416be1da707SZhi Wang /* 417be1da707SZhi Wang * command has its own ip advance logic 418be1da707SZhi Wang * e.g. MI_BATCH_START, MI_BATCH_END 419be1da707SZhi Wang */ 4204f870f1fSGao, Fred #define F_IP_ADVANCE_CUSTOM (1<<2) 421be1da707SZhi Wang u32 flag; 422be1da707SZhi Wang 4238a68d464SChris Wilson #define R_RCS BIT(RCS0) 4248a68d464SChris Wilson #define R_VCS1 BIT(VCS0) 4258a68d464SChris Wilson #define R_VCS2 BIT(VCS1) 426be1da707SZhi Wang #define R_VCS (R_VCS1 | R_VCS2) 4278a68d464SChris Wilson #define R_BCS BIT(BCS0) 4288a68d464SChris Wilson #define R_VECS BIT(VECS0) 429be1da707SZhi Wang #define R_ALL (R_RCS | R_VCS | R_BCS | R_VECS) 430be1da707SZhi Wang /* rings that support this cmd: BLT/RCS/VCS/VECS */ 4312e679d48SJani Nikula u16 rings; 432be1da707SZhi Wang 433be1da707SZhi Wang /* devices that support this cmd: SNB/IVB/HSW/... */ 4342e679d48SJani Nikula u16 devices; 435be1da707SZhi Wang 436be1da707SZhi Wang /* which DWords are address that need fix up. 437be1da707SZhi Wang * bit 0 means a 32-bit non address operand in command 438be1da707SZhi Wang * bit 1 means address operand, which could be 32-bit 439be1da707SZhi Wang * or 64-bit depending on different architectures.( 440be1da707SZhi Wang * defined by "gmadr_bytes_in_cmd" in intel_gvt. 441be1da707SZhi Wang * No matter the address length, each address only takes 442be1da707SZhi Wang * one bit in the bitmap. 443be1da707SZhi Wang */ 4442e679d48SJani Nikula u16 addr_bitmap; 445be1da707SZhi Wang 446be1da707SZhi Wang /* flag == F_LEN_CONST : command length 447be1da707SZhi Wang * flag == F_LEN_VAR : length bias bits 448be1da707SZhi Wang * Note: length is in DWord 449be1da707SZhi Wang */ 4504f870f1fSGao, Fred u32 len; 451be1da707SZhi Wang 452be1da707SZhi Wang parser_cmd_handler handler; 4534f870f1fSGao, Fred 4544f870f1fSGao, Fred /* valid length in DWord */ 4554f870f1fSGao, Fred u32 valid_len; 456be1da707SZhi Wang }; 457be1da707SZhi Wang 458be1da707SZhi Wang struct cmd_entry { 459be1da707SZhi Wang struct hlist_node hlist; 460b007065aSJani Nikula const struct cmd_info *info; 461be1da707SZhi Wang }; 462be1da707SZhi Wang 463be1da707SZhi Wang enum { 464be1da707SZhi Wang RING_BUFFER_INSTRUCTION, 465be1da707SZhi Wang BATCH_BUFFER_INSTRUCTION, 466be1da707SZhi Wang BATCH_BUFFER_2ND_LEVEL, 467493f30cdSYan Zhao RING_BUFFER_CTX, 468be1da707SZhi Wang }; 469be1da707SZhi Wang 470be1da707SZhi Wang enum { 471be1da707SZhi Wang GTT_BUFFER, 472be1da707SZhi Wang PPGTT_BUFFER 473be1da707SZhi Wang }; 474be1da707SZhi Wang 475be1da707SZhi Wang struct parser_exec_state { 476be1da707SZhi Wang struct intel_vgpu *vgpu; 4778fde4107SChris Wilson const struct intel_engine_cs *engine; 478be1da707SZhi Wang 479be1da707SZhi Wang int buf_type; 480be1da707SZhi Wang 481be1da707SZhi Wang /* batch buffer address type */ 482be1da707SZhi Wang int buf_addr_type; 483be1da707SZhi Wang 484be1da707SZhi Wang /* graphics memory address of ring buffer start */ 485be1da707SZhi Wang unsigned long ring_start; 486be1da707SZhi Wang unsigned long ring_size; 487be1da707SZhi Wang unsigned long ring_head; 488be1da707SZhi Wang unsigned long ring_tail; 489be1da707SZhi Wang 490be1da707SZhi Wang /* instruction graphics memory address */ 491be1da707SZhi Wang unsigned long ip_gma; 492be1da707SZhi Wang 493be1da707SZhi Wang /* mapped va of the instr_gma */ 494be1da707SZhi Wang void *ip_va; 495be1da707SZhi Wang void *rb_va; 496be1da707SZhi Wang 497be1da707SZhi Wang void *ret_bb_va; 498be1da707SZhi Wang /* next instruction when return from batch buffer to ring buffer */ 499be1da707SZhi Wang unsigned long ret_ip_gma_ring; 500be1da707SZhi Wang 501be1da707SZhi Wang /* next instruction when return from 2nd batch buffer to batch buffer */ 502be1da707SZhi Wang unsigned long ret_ip_gma_bb; 503be1da707SZhi Wang 504be1da707SZhi Wang /* batch buffer address type (GTT or PPGTT) 505be1da707SZhi Wang * used when ret from 2nd level batch buffer 506be1da707SZhi Wang */ 507be1da707SZhi Wang int saved_buf_addr_type; 508ef75c685Sfred gao bool is_ctx_wa; 509493f30cdSYan Zhao bool is_init_ctx; 510be1da707SZhi Wang 511b007065aSJani Nikula const struct cmd_info *info; 512be1da707SZhi Wang 513be1da707SZhi Wang struct intel_vgpu_workload *workload; 514be1da707SZhi Wang }; 515be1da707SZhi Wang 516be1da707SZhi Wang #define gmadr_dw_number(s) \ 517be1da707SZhi Wang (s->vgpu->gvt->device_info.gmadr_bytes_in_cmd >> 2) 518be1da707SZhi Wang 519999ccb40SDu, Changbin static unsigned long bypass_scan_mask = 0; 520be1da707SZhi Wang 521be1da707SZhi Wang /* ring ALL, type = 0 */ 522ed8cce30SJani Nikula static const struct sub_op_bits sub_op_mi[] = { 523be1da707SZhi Wang {31, 29}, 524be1da707SZhi Wang {28, 23}, 525be1da707SZhi Wang }; 526be1da707SZhi Wang 527ed8cce30SJani Nikula static const struct decode_info decode_info_mi = { 528be1da707SZhi Wang "MI", 529be1da707SZhi Wang OP_LEN_MI, 530be1da707SZhi Wang ARRAY_SIZE(sub_op_mi), 531be1da707SZhi Wang sub_op_mi, 532be1da707SZhi Wang }; 533be1da707SZhi Wang 534be1da707SZhi Wang /* ring RCS, command type 2 */ 535ed8cce30SJani Nikula static const struct sub_op_bits sub_op_2d[] = { 536be1da707SZhi Wang {31, 29}, 537be1da707SZhi Wang {28, 22}, 538be1da707SZhi Wang }; 539be1da707SZhi Wang 540ed8cce30SJani Nikula static const struct decode_info decode_info_2d = { 541be1da707SZhi Wang "2D", 542be1da707SZhi Wang OP_LEN_2D, 543be1da707SZhi Wang ARRAY_SIZE(sub_op_2d), 544be1da707SZhi Wang sub_op_2d, 545be1da707SZhi Wang }; 546be1da707SZhi Wang 547be1da707SZhi Wang /* ring RCS, command type 3 */ 548ed8cce30SJani Nikula static const struct sub_op_bits sub_op_3d_media[] = { 549be1da707SZhi Wang {31, 29}, 550be1da707SZhi Wang {28, 27}, 551be1da707SZhi Wang {26, 24}, 552be1da707SZhi Wang {23, 16}, 553be1da707SZhi Wang }; 554be1da707SZhi Wang 555ed8cce30SJani Nikula static const struct decode_info decode_info_3d_media = { 556be1da707SZhi Wang "3D_Media", 557be1da707SZhi Wang OP_LEN_3D_MEDIA, 558be1da707SZhi Wang ARRAY_SIZE(sub_op_3d_media), 559be1da707SZhi Wang sub_op_3d_media, 560be1da707SZhi Wang }; 561be1da707SZhi Wang 562be1da707SZhi Wang /* ring VCS, command type 3 */ 563ed8cce30SJani Nikula static const struct sub_op_bits sub_op_mfx_vc[] = { 564be1da707SZhi Wang {31, 29}, 565be1da707SZhi Wang {28, 27}, 566be1da707SZhi Wang {26, 24}, 567be1da707SZhi Wang {23, 21}, 568be1da707SZhi Wang {20, 16}, 569be1da707SZhi Wang }; 570be1da707SZhi Wang 571ed8cce30SJani Nikula static const struct decode_info decode_info_mfx_vc = { 572be1da707SZhi Wang "MFX_VC", 573be1da707SZhi Wang OP_LEN_MFX_VC, 574be1da707SZhi Wang ARRAY_SIZE(sub_op_mfx_vc), 575be1da707SZhi Wang sub_op_mfx_vc, 576be1da707SZhi Wang }; 577be1da707SZhi Wang 578be1da707SZhi Wang /* ring VECS, command type 3 */ 579ed8cce30SJani Nikula static const struct sub_op_bits sub_op_vebox[] = { 580be1da707SZhi Wang {31, 29}, 581be1da707SZhi Wang {28, 27}, 582be1da707SZhi Wang {26, 24}, 583be1da707SZhi Wang {23, 21}, 584be1da707SZhi Wang {20, 16}, 585be1da707SZhi Wang }; 586be1da707SZhi Wang 587ed8cce30SJani Nikula static const struct decode_info decode_info_vebox = { 588be1da707SZhi Wang "VEBOX", 589be1da707SZhi Wang OP_LEN_VEBOX, 590be1da707SZhi Wang ARRAY_SIZE(sub_op_vebox), 591be1da707SZhi Wang sub_op_vebox, 592be1da707SZhi Wang }; 593be1da707SZhi Wang 594ed8cce30SJani Nikula static const struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = { 5958a68d464SChris Wilson [RCS0] = { 596be1da707SZhi Wang &decode_info_mi, 597be1da707SZhi Wang NULL, 598be1da707SZhi Wang NULL, 599be1da707SZhi Wang &decode_info_3d_media, 600be1da707SZhi Wang NULL, 601be1da707SZhi Wang NULL, 602be1da707SZhi Wang NULL, 603be1da707SZhi Wang NULL, 604be1da707SZhi Wang }, 605be1da707SZhi Wang 6068a68d464SChris Wilson [VCS0] = { 607be1da707SZhi Wang &decode_info_mi, 608be1da707SZhi Wang NULL, 609be1da707SZhi Wang NULL, 610be1da707SZhi Wang &decode_info_mfx_vc, 611be1da707SZhi Wang NULL, 612be1da707SZhi Wang NULL, 613be1da707SZhi Wang NULL, 614be1da707SZhi Wang NULL, 615be1da707SZhi Wang }, 616be1da707SZhi Wang 6178a68d464SChris Wilson [BCS0] = { 618be1da707SZhi Wang &decode_info_mi, 619be1da707SZhi Wang NULL, 620be1da707SZhi Wang &decode_info_2d, 621be1da707SZhi Wang NULL, 622be1da707SZhi Wang NULL, 623be1da707SZhi Wang NULL, 624be1da707SZhi Wang NULL, 625be1da707SZhi Wang NULL, 626be1da707SZhi Wang }, 627be1da707SZhi Wang 6288a68d464SChris Wilson [VECS0] = { 629be1da707SZhi Wang &decode_info_mi, 630be1da707SZhi Wang NULL, 631be1da707SZhi Wang NULL, 632be1da707SZhi Wang &decode_info_vebox, 633be1da707SZhi Wang NULL, 634be1da707SZhi Wang NULL, 635be1da707SZhi Wang NULL, 636be1da707SZhi Wang NULL, 637be1da707SZhi Wang }, 638be1da707SZhi Wang 6398a68d464SChris Wilson [VCS1] = { 640be1da707SZhi Wang &decode_info_mi, 641be1da707SZhi Wang NULL, 642be1da707SZhi Wang NULL, 643be1da707SZhi Wang &decode_info_mfx_vc, 644be1da707SZhi Wang NULL, 645be1da707SZhi Wang NULL, 646be1da707SZhi Wang NULL, 647be1da707SZhi Wang NULL, 648be1da707SZhi Wang }, 649be1da707SZhi Wang }; 650be1da707SZhi Wang 6518fde4107SChris Wilson static inline u32 get_opcode(u32 cmd, const struct intel_engine_cs *engine) 652be1da707SZhi Wang { 653ed8cce30SJani Nikula const struct decode_info *d_info; 654be1da707SZhi Wang 6558fde4107SChris Wilson d_info = ring_decode_info[engine->id][CMD_TYPE(cmd)]; 656be1da707SZhi Wang if (d_info == NULL) 657be1da707SZhi Wang return INVALID_OP; 658be1da707SZhi Wang 659be1da707SZhi Wang return cmd >> (32 - d_info->op_len); 660be1da707SZhi Wang } 661be1da707SZhi Wang 6628fde4107SChris Wilson static inline const struct cmd_info * 6638fde4107SChris Wilson find_cmd_entry(struct intel_gvt *gvt, unsigned int opcode, 6648fde4107SChris Wilson const struct intel_engine_cs *engine) 665be1da707SZhi Wang { 666be1da707SZhi Wang struct cmd_entry *e; 667be1da707SZhi Wang 668be1da707SZhi Wang hash_for_each_possible(gvt->cmd_table, e, hlist, opcode) { 6698fde4107SChris Wilson if (opcode == e->info->opcode && 6708fde4107SChris Wilson e->info->rings & engine->mask) 671be1da707SZhi Wang return e->info; 672be1da707SZhi Wang } 673be1da707SZhi Wang return NULL; 674be1da707SZhi Wang } 675be1da707SZhi Wang 6768fde4107SChris Wilson static inline const struct cmd_info * 6778fde4107SChris Wilson get_cmd_info(struct intel_gvt *gvt, u32 cmd, 6788fde4107SChris Wilson const struct intel_engine_cs *engine) 679be1da707SZhi Wang { 680be1da707SZhi Wang u32 opcode; 681be1da707SZhi Wang 6828fde4107SChris Wilson opcode = get_opcode(cmd, engine); 683be1da707SZhi Wang if (opcode == INVALID_OP) 684be1da707SZhi Wang return NULL; 685be1da707SZhi Wang 6868fde4107SChris Wilson return find_cmd_entry(gvt, opcode, engine); 687be1da707SZhi Wang } 688be1da707SZhi Wang 689be1da707SZhi Wang static inline u32 sub_op_val(u32 cmd, u32 hi, u32 low) 690be1da707SZhi Wang { 691be1da707SZhi Wang return (cmd >> low) & ((1U << (hi - low + 1)) - 1); 692be1da707SZhi Wang } 693be1da707SZhi Wang 6948fde4107SChris Wilson static inline void print_opcode(u32 cmd, const struct intel_engine_cs *engine) 695be1da707SZhi Wang { 696ed8cce30SJani Nikula const struct decode_info *d_info; 697be1da707SZhi Wang int i; 698be1da707SZhi Wang 6998fde4107SChris Wilson d_info = ring_decode_info[engine->id][CMD_TYPE(cmd)]; 700be1da707SZhi Wang if (d_info == NULL) 701be1da707SZhi Wang return; 702be1da707SZhi Wang 703627c845cSTina Zhang gvt_dbg_cmd("opcode=0x%x %s sub_ops:", 704be1da707SZhi Wang cmd >> (32 - d_info->op_len), d_info->name); 705be1da707SZhi Wang 706be1da707SZhi Wang for (i = 0; i < d_info->nr_sub_op; i++) 707be1da707SZhi Wang pr_err("0x%x ", sub_op_val(cmd, d_info->sub_op[i].hi, 708be1da707SZhi Wang d_info->sub_op[i].low)); 709be1da707SZhi Wang 710be1da707SZhi Wang pr_err("\n"); 711be1da707SZhi Wang } 712be1da707SZhi Wang 713be1da707SZhi Wang static inline u32 *cmd_ptr(struct parser_exec_state *s, int index) 714be1da707SZhi Wang { 715be1da707SZhi Wang return s->ip_va + (index << 2); 716be1da707SZhi Wang } 717be1da707SZhi Wang 718be1da707SZhi Wang static inline u32 cmd_val(struct parser_exec_state *s, int index) 719be1da707SZhi Wang { 720be1da707SZhi Wang return *cmd_ptr(s, index); 721be1da707SZhi Wang } 722be1da707SZhi Wang 723493f30cdSYan Zhao static inline bool is_init_ctx(struct parser_exec_state *s) 724493f30cdSYan Zhao { 725493f30cdSYan Zhao return (s->buf_type == RING_BUFFER_CTX && s->is_init_ctx); 726493f30cdSYan Zhao } 727493f30cdSYan Zhao 728be1da707SZhi Wang static void parser_exec_state_dump(struct parser_exec_state *s) 729be1da707SZhi Wang { 730be1da707SZhi Wang int cnt = 0; 731be1da707SZhi Wang int i; 732be1da707SZhi Wang 7338fde4107SChris Wilson gvt_dbg_cmd(" vgpu%d RING%s: ring_start(%08lx) ring_end(%08lx)" 7348fde4107SChris Wilson " ring_head(%08lx) ring_tail(%08lx)\n", 7358fde4107SChris Wilson s->vgpu->id, s->engine->name, 7368fde4107SChris Wilson s->ring_start, s->ring_start + s->ring_size, 737be1da707SZhi Wang s->ring_head, s->ring_tail); 738be1da707SZhi Wang 739627c845cSTina Zhang gvt_dbg_cmd(" %s %s ip_gma(%08lx) ", 740be1da707SZhi Wang s->buf_type == RING_BUFFER_INSTRUCTION ? 741493f30cdSYan Zhao "RING_BUFFER" : ((s->buf_type == RING_BUFFER_CTX) ? 742493f30cdSYan Zhao "CTX_BUFFER" : "BATCH_BUFFER"), 743be1da707SZhi Wang s->buf_addr_type == GTT_BUFFER ? 744be1da707SZhi Wang "GTT" : "PPGTT", s->ip_gma); 745be1da707SZhi Wang 746be1da707SZhi Wang if (s->ip_va == NULL) { 747627c845cSTina Zhang gvt_dbg_cmd(" ip_va(NULL)"); 748be1da707SZhi Wang return; 749be1da707SZhi Wang } 750be1da707SZhi Wang 751627c845cSTina Zhang gvt_dbg_cmd(" ip_va=%p: %08x %08x %08x %08x\n", 752be1da707SZhi Wang s->ip_va, cmd_val(s, 0), cmd_val(s, 1), 753be1da707SZhi Wang cmd_val(s, 2), cmd_val(s, 3)); 754be1da707SZhi Wang 7558fde4107SChris Wilson print_opcode(cmd_val(s, 0), s->engine); 756be1da707SZhi Wang 757be1da707SZhi Wang s->ip_va = (u32 *)((((u64)s->ip_va) >> 12) << 12); 758be1da707SZhi Wang 759be1da707SZhi Wang while (cnt < 1024) { 760e4aeba69SChangbin Du gvt_dbg_cmd("ip_va=%p: ", s->ip_va); 761be1da707SZhi Wang for (i = 0; i < 8; i++) 762e4aeba69SChangbin Du gvt_dbg_cmd("%08x ", cmd_val(s, i)); 763e4aeba69SChangbin Du gvt_dbg_cmd("\n"); 764be1da707SZhi Wang 765be1da707SZhi Wang s->ip_va += 8 * sizeof(u32); 766be1da707SZhi Wang cnt += 8; 767be1da707SZhi Wang } 768be1da707SZhi Wang } 769be1da707SZhi Wang 770be1da707SZhi Wang static inline void update_ip_va(struct parser_exec_state *s) 771be1da707SZhi Wang { 772be1da707SZhi Wang unsigned long len = 0; 773be1da707SZhi Wang 774be1da707SZhi Wang if (WARN_ON(s->ring_head == s->ring_tail)) 775be1da707SZhi Wang return; 776be1da707SZhi Wang 777493f30cdSYan Zhao if (s->buf_type == RING_BUFFER_INSTRUCTION || 778493f30cdSYan Zhao s->buf_type == RING_BUFFER_CTX) { 779be1da707SZhi Wang unsigned long ring_top = s->ring_start + s->ring_size; 780be1da707SZhi Wang 781be1da707SZhi Wang if (s->ring_head > s->ring_tail) { 782be1da707SZhi Wang if (s->ip_gma >= s->ring_head && s->ip_gma < ring_top) 783be1da707SZhi Wang len = (s->ip_gma - s->ring_head); 784be1da707SZhi Wang else if (s->ip_gma >= s->ring_start && 785be1da707SZhi Wang s->ip_gma <= s->ring_tail) 786be1da707SZhi Wang len = (ring_top - s->ring_head) + 787be1da707SZhi Wang (s->ip_gma - s->ring_start); 788be1da707SZhi Wang } else 789be1da707SZhi Wang len = (s->ip_gma - s->ring_head); 790be1da707SZhi Wang 791be1da707SZhi Wang s->ip_va = s->rb_va + len; 792be1da707SZhi Wang } else {/* shadow batch buffer */ 793be1da707SZhi Wang s->ip_va = s->ret_bb_va; 794be1da707SZhi Wang } 795be1da707SZhi Wang } 796be1da707SZhi Wang 797be1da707SZhi Wang static inline int ip_gma_set(struct parser_exec_state *s, 798be1da707SZhi Wang unsigned long ip_gma) 799be1da707SZhi Wang { 800be1da707SZhi Wang WARN_ON(!IS_ALIGNED(ip_gma, 4)); 801be1da707SZhi Wang 802be1da707SZhi Wang s->ip_gma = ip_gma; 803be1da707SZhi Wang update_ip_va(s); 804be1da707SZhi Wang return 0; 805be1da707SZhi Wang } 806be1da707SZhi Wang 807be1da707SZhi Wang static inline int ip_gma_advance(struct parser_exec_state *s, 808be1da707SZhi Wang unsigned int dw_len) 809be1da707SZhi Wang { 810be1da707SZhi Wang s->ip_gma += (dw_len << 2); 811be1da707SZhi Wang 812be1da707SZhi Wang if (s->buf_type == RING_BUFFER_INSTRUCTION) { 813be1da707SZhi Wang if (s->ip_gma >= s->ring_start + s->ring_size) 814be1da707SZhi Wang s->ip_gma -= s->ring_size; 815be1da707SZhi Wang update_ip_va(s); 816be1da707SZhi Wang } else { 817be1da707SZhi Wang s->ip_va += (dw_len << 2); 818be1da707SZhi Wang } 819be1da707SZhi Wang 820be1da707SZhi Wang return 0; 821be1da707SZhi Wang } 822be1da707SZhi Wang 823b007065aSJani Nikula static inline int get_cmd_length(const struct cmd_info *info, u32 cmd) 824be1da707SZhi Wang { 825be1da707SZhi Wang if ((info->flag & F_LEN_MASK) == F_LEN_CONST) 826be1da707SZhi Wang return info->len; 827be1da707SZhi Wang else 828be1da707SZhi Wang return (cmd & ((1U << info->len) - 1)) + 2; 829be1da707SZhi Wang return 0; 830be1da707SZhi Wang } 831be1da707SZhi Wang 832be1da707SZhi Wang static inline int cmd_length(struct parser_exec_state *s) 833be1da707SZhi Wang { 834be1da707SZhi Wang return get_cmd_length(s->info, cmd_val(s, 0)); 835be1da707SZhi Wang } 836be1da707SZhi Wang 837be1da707SZhi Wang /* do not remove this, some platform may need clflush here */ 838be1da707SZhi Wang #define patch_value(s, addr, val) do { \ 839be1da707SZhi Wang *addr = val; \ 840be1da707SZhi Wang } while (0) 841be1da707SZhi Wang 842f402f2d6SWeinan Li static inline bool is_mocs_mmio(unsigned int offset) 843f402f2d6SWeinan Li { 844f402f2d6SWeinan Li return ((offset >= 0xc800) && (offset <= 0xcff8)) || 845f402f2d6SWeinan Li ((offset >= 0xb020) && (offset <= 0xb0a0)); 846f402f2d6SWeinan Li } 847f402f2d6SWeinan Li 848bec3df93SZhenyu Wang static int is_cmd_update_pdps(unsigned int offset, 849bec3df93SZhenyu Wang struct parser_exec_state *s) 850bec3df93SZhenyu Wang { 851bec3df93SZhenyu Wang u32 base = s->workload->engine->mmio_base; 852bec3df93SZhenyu Wang return i915_mmio_reg_equal(_MMIO(offset), GEN8_RING_PDP_UDW(base, 0)); 853bec3df93SZhenyu Wang } 854bec3df93SZhenyu Wang 855bec3df93SZhenyu Wang static int cmd_pdp_mmio_update_handler(struct parser_exec_state *s, 856bec3df93SZhenyu Wang unsigned int offset, unsigned int index) 857bec3df93SZhenyu Wang { 858bec3df93SZhenyu Wang struct intel_vgpu *vgpu = s->vgpu; 859bec3df93SZhenyu Wang struct intel_vgpu_mm *shadow_mm = s->workload->shadow_mm; 860bec3df93SZhenyu Wang struct intel_vgpu_mm *mm; 861bec3df93SZhenyu Wang u64 pdps[GEN8_3LVL_PDPES]; 862bec3df93SZhenyu Wang 863bec3df93SZhenyu Wang if (shadow_mm->ppgtt_mm.root_entry_type == 864bec3df93SZhenyu Wang GTT_TYPE_PPGTT_ROOT_L4_ENTRY) { 865bec3df93SZhenyu Wang pdps[0] = (u64)cmd_val(s, 2) << 32; 866bec3df93SZhenyu Wang pdps[0] |= cmd_val(s, 4); 867bec3df93SZhenyu Wang 868bec3df93SZhenyu Wang mm = intel_vgpu_find_ppgtt_mm(vgpu, pdps); 869bec3df93SZhenyu Wang if (!mm) { 870bec3df93SZhenyu Wang gvt_vgpu_err("failed to get the 4-level shadow vm\n"); 871bec3df93SZhenyu Wang return -EINVAL; 872bec3df93SZhenyu Wang } 873bec3df93SZhenyu Wang intel_vgpu_mm_get(mm); 874bec3df93SZhenyu Wang list_add_tail(&mm->ppgtt_mm.link, 875bec3df93SZhenyu Wang &s->workload->lri_shadow_mm); 876bec3df93SZhenyu Wang *cmd_ptr(s, 2) = upper_32_bits(mm->ppgtt_mm.shadow_pdps[0]); 877bec3df93SZhenyu Wang *cmd_ptr(s, 4) = lower_32_bits(mm->ppgtt_mm.shadow_pdps[0]); 878bec3df93SZhenyu Wang } else { 879bec3df93SZhenyu Wang /* Currently all guests use PML4 table and now can't 880bec3df93SZhenyu Wang * have a guest with 3-level table but uses LRI for 881bec3df93SZhenyu Wang * PPGTT update. So this is simply un-testable. */ 882bec3df93SZhenyu Wang GEM_BUG_ON(1); 883bec3df93SZhenyu Wang gvt_vgpu_err("invalid shared shadow vm type\n"); 884bec3df93SZhenyu Wang return -EINVAL; 885bec3df93SZhenyu Wang } 886bec3df93SZhenyu Wang return 0; 887bec3df93SZhenyu Wang } 888bec3df93SZhenyu Wang 889be1da707SZhi Wang static int cmd_reg_handler(struct parser_exec_state *s, 890be1da707SZhi Wang unsigned int offset, unsigned int index, char *cmd) 891be1da707SZhi Wang { 892be1da707SZhi Wang struct intel_vgpu *vgpu = s->vgpu; 893be1da707SZhi Wang struct intel_gvt *gvt = vgpu->gvt; 8946cef21a1SHang Yuan u32 ctx_sr_ctl; 89502dd2b12SYan Zhao u32 *vreg, vreg_old; 896be1da707SZhi Wang 897be1da707SZhi Wang if (offset + 4 > gvt->device_info.mmio_size) { 898695fbc08STina Zhang gvt_vgpu_err("%s access to (%x) outside of MMIO range\n", 899be1da707SZhi Wang cmd, offset); 9005c56883aSfred gao return -EFAULT; 901be1da707SZhi Wang } 902be1da707SZhi Wang 903493f30cdSYan Zhao if (is_init_ctx(s)) { 904b7ccb10eSYan Zhao struct intel_gvt_mmio_info *mmio_info; 905b7ccb10eSYan Zhao 906493f30cdSYan Zhao intel_gvt_mmio_set_cmd_accessible(gvt, offset); 907b7ccb10eSYan Zhao mmio_info = intel_gvt_find_mmio_info(gvt, offset); 908b7ccb10eSYan Zhao if (mmio_info && mmio_info->write) 909b7ccb10eSYan Zhao intel_gvt_mmio_set_cmd_write_patch(gvt, offset); 910493f30cdSYan Zhao return 0; 911493f30cdSYan Zhao } 912493f30cdSYan Zhao 9137e93a080SYan Zhao if (!intel_gvt_mmio_is_cmd_accessible(gvt, offset)) { 914695fbc08STina Zhang gvt_vgpu_err("%s access to non-render register (%x)\n", 915695fbc08STina Zhang cmd, offset); 9168d458ea0SZhao Yan return -EBADRQC; 917be1da707SZhi Wang } 918be1da707SZhi Wang 919f18d417aSYan Zhao if (!strncmp(cmd, "srm", 3) || 920f18d417aSYan Zhao !strncmp(cmd, "lrm", 3)) { 9216b5b2a5bSZhenyu Wang if (offset == i915_mmio_reg_offset(GEN8_L3SQCREG4) || 9226b5b2a5bSZhenyu Wang offset == 0x21f0 || 9236b5b2a5bSZhenyu Wang (IS_BROADWELL(gvt->gt->i915) && 9246b5b2a5bSZhenyu Wang offset == i915_mmio_reg_offset(INSTPM))) 9256b5b2a5bSZhenyu Wang return 0; 9266b5b2a5bSZhenyu Wang else { 927f18d417aSYan Zhao gvt_vgpu_err("%s access to register (%x)\n", 928f18d417aSYan Zhao cmd, offset); 929f18d417aSYan Zhao return -EPERM; 9306b5b2a5bSZhenyu Wang } 931f18d417aSYan Zhao } 932f18d417aSYan Zhao 93373a37a43SYan Zhao if (!strncmp(cmd, "lrr-src", 7) || 93473a37a43SYan Zhao !strncmp(cmd, "lrr-dst", 7)) { 9356b5b2a5bSZhenyu Wang if (IS_BROADWELL(gvt->gt->i915) && offset == 0x215c) 9366b5b2a5bSZhenyu Wang return 0; 9376b5b2a5bSZhenyu Wang else { 9386b5b2a5bSZhenyu Wang gvt_vgpu_err("not allowed cmd %s reg (%x)\n", cmd, offset); 93973a37a43SYan Zhao return -EPERM; 94073a37a43SYan Zhao } 9416b5b2a5bSZhenyu Wang } 94273a37a43SYan Zhao 943252cec9fSYan Zhao if (!strncmp(cmd, "pipe_ctrl", 9)) { 944252cec9fSYan Zhao /* TODO: add LRI POST logic here */ 945252cec9fSYan Zhao return 0; 946252cec9fSYan Zhao } 947252cec9fSYan Zhao 94802dd2b12SYan Zhao if (strncmp(cmd, "lri", 3)) 94902dd2b12SYan Zhao return -EPERM; 95002dd2b12SYan Zhao 95102dd2b12SYan Zhao /* below are all lri handlers */ 95202dd2b12SYan Zhao vreg = &vgpu_vreg(s->vgpu, offset); 95302dd2b12SYan Zhao 954bec3df93SZhenyu Wang if (is_cmd_update_pdps(offset, s) && 955bec3df93SZhenyu Wang cmd_pdp_mmio_update_handler(s, offset, index)) 956bec3df93SZhenyu Wang return -EINVAL; 957bec3df93SZhenyu Wang 95802dd2b12SYan Zhao if (offset == i915_mmio_reg_offset(DERRMR) || 95902dd2b12SYan Zhao offset == i915_mmio_reg_offset(FORCEWAKE_MT)) { 96002dd2b12SYan Zhao /* Writing to HW VGT_PVINFO_PAGE offset will be discarded */ 96102dd2b12SYan Zhao patch_value(s, cmd_ptr(s, index), VGT_PVINFO_PAGE); 96202dd2b12SYan Zhao } 96302dd2b12SYan Zhao 96402dd2b12SYan Zhao if (is_mocs_mmio(offset)) 96502dd2b12SYan Zhao *vreg = cmd_val(s, index + 1); 96602dd2b12SYan Zhao 96702dd2b12SYan Zhao vreg_old = *vreg; 96802dd2b12SYan Zhao 96902dd2b12SYan Zhao if (intel_gvt_mmio_is_cmd_write_patch(gvt, offset)) { 97002dd2b12SYan Zhao u32 cmdval_new, cmdval; 97102dd2b12SYan Zhao struct intel_gvt_mmio_info *mmio_info; 97202dd2b12SYan Zhao 97302dd2b12SYan Zhao cmdval = cmd_val(s, index + 1); 97402dd2b12SYan Zhao 97502dd2b12SYan Zhao mmio_info = intel_gvt_find_mmio_info(gvt, offset); 97602dd2b12SYan Zhao if (!mmio_info) { 97702dd2b12SYan Zhao cmdval_new = cmdval; 97802dd2b12SYan Zhao } else { 97902dd2b12SYan Zhao u64 ro_mask = mmio_info->ro_mask; 98002dd2b12SYan Zhao int ret; 98102dd2b12SYan Zhao 98202dd2b12SYan Zhao if (likely(!ro_mask)) 98302dd2b12SYan Zhao ret = mmio_info->write(s->vgpu, offset, 98402dd2b12SYan Zhao &cmdval, 4); 98502dd2b12SYan Zhao else { 98602dd2b12SYan Zhao gvt_vgpu_err("try to write RO reg %x\n", 98702dd2b12SYan Zhao offset); 98802dd2b12SYan Zhao ret = -EBADRQC; 98902dd2b12SYan Zhao } 99002dd2b12SYan Zhao if (ret) 99102dd2b12SYan Zhao return ret; 99202dd2b12SYan Zhao cmdval_new = *vreg; 99302dd2b12SYan Zhao } 99402dd2b12SYan Zhao if (cmdval_new != cmdval) 99502dd2b12SYan Zhao patch_value(s, cmd_ptr(s, index+1), cmdval_new); 99602dd2b12SYan Zhao } 99702dd2b12SYan Zhao 99802dd2b12SYan Zhao /* only patch cmd. restore vreg value if changed in mmio write handler*/ 99902dd2b12SYan Zhao *vreg = vreg_old; 100002dd2b12SYan Zhao 10016cef21a1SHang Yuan /* TODO 1002df2ea3c2SYan Zhao * In order to let workload with inhibit context to generate 1003df2ea3c2SYan Zhao * correct image data into memory, vregs values will be loaded to 1004df2ea3c2SYan Zhao * hw via LRIs in the workload with inhibit context. But as 1005df2ea3c2SYan Zhao * indirect context is loaded prior to LRIs in workload, we don't 1006df2ea3c2SYan Zhao * want reg values specified in indirect context overwritten by 1007df2ea3c2SYan Zhao * LRIs in workloads. So, when scanning an indirect context, we 1008df2ea3c2SYan Zhao * update reg values in it into vregs, so LRIs in workload with 1009df2ea3c2SYan Zhao * inhibit context will restore with correct values 10106cef21a1SHang Yuan */ 1011d8d12312SLucas De Marchi if (GRAPHICS_VER(s->engine->i915) == 9 && 101256d44649SYan Zhao intel_gvt_mmio_is_sr_in_ctx(gvt, offset) && 10136cef21a1SHang Yuan !strncmp(cmd, "lri", 3)) { 1014*e3d7640eSChristoph Hellwig intel_gvt_read_gpa(s->vgpu, 10156cef21a1SHang Yuan s->workload->ring_context_gpa + 12, &ctx_sr_ctl, 4); 10166cef21a1SHang Yuan /* check inhibit context */ 10176cef21a1SHang Yuan if (ctx_sr_ctl & 1) { 10186cef21a1SHang Yuan u32 data = cmd_val(s, index + 1); 10196cef21a1SHang Yuan 10206cef21a1SHang Yuan if (intel_gvt_mmio_has_mode_mask(s->vgpu->gvt, offset)) 10216cef21a1SHang Yuan intel_vgpu_mask_mmio_write(vgpu, 10226cef21a1SHang Yuan offset, &data, 4); 10236cef21a1SHang Yuan else 10246cef21a1SHang Yuan vgpu_vreg(vgpu, offset) = data; 10256cef21a1SHang Yuan } 10266cef21a1SHang Yuan } 10276cef21a1SHang Yuan 1028be1da707SZhi Wang return 0; 1029be1da707SZhi Wang } 1030be1da707SZhi Wang 1031be1da707SZhi Wang #define cmd_reg(s, i) \ 1032be1da707SZhi Wang (cmd_val(s, i) & GENMASK(22, 2)) 1033be1da707SZhi Wang 1034be1da707SZhi Wang #define cmd_reg_inhibit(s, i) \ 1035be1da707SZhi Wang (cmd_val(s, i) & GENMASK(22, 18)) 1036be1da707SZhi Wang 1037be1da707SZhi Wang #define cmd_gma(s, i) \ 1038be1da707SZhi Wang (cmd_val(s, i) & GENMASK(31, 2)) 1039be1da707SZhi Wang 1040be1da707SZhi Wang #define cmd_gma_hi(s, i) \ 1041be1da707SZhi Wang (cmd_val(s, i) & GENMASK(15, 0)) 1042be1da707SZhi Wang 1043be1da707SZhi Wang static int cmd_handler_lri(struct parser_exec_state *s) 1044be1da707SZhi Wang { 1045be1da707SZhi Wang int i, ret = 0; 1046be1da707SZhi Wang int cmd_len = cmd_length(s); 1047be1da707SZhi Wang 1048be1da707SZhi Wang for (i = 1; i < cmd_len; i += 2) { 10498fde4107SChris Wilson if (IS_BROADWELL(s->engine->i915) && s->engine->id != RCS0) { 10508fde4107SChris Wilson if (s->engine->id == BCS0 && 10518a68d464SChris Wilson cmd_reg(s, i) == i915_mmio_reg_offset(DERRMR)) 1052be1da707SZhi Wang ret |= 0; 1053be1da707SZhi Wang else 10548a68d464SChris Wilson ret |= cmd_reg_inhibit(s, i) ? -EBADRQC : 0; 1055be1da707SZhi Wang } 1056be1da707SZhi Wang if (ret) 1057be1da707SZhi Wang break; 1058be1da707SZhi Wang ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lri"); 10595c56883aSfred gao if (ret) 10605c56883aSfred gao break; 1061be1da707SZhi Wang } 1062be1da707SZhi Wang return ret; 1063be1da707SZhi Wang } 1064be1da707SZhi Wang 1065be1da707SZhi Wang static int cmd_handler_lrr(struct parser_exec_state *s) 1066be1da707SZhi Wang { 1067be1da707SZhi Wang int i, ret = 0; 1068be1da707SZhi Wang int cmd_len = cmd_length(s); 1069be1da707SZhi Wang 1070be1da707SZhi Wang for (i = 1; i < cmd_len; i += 2) { 10718fde4107SChris Wilson if (IS_BROADWELL(s->engine->i915)) 1072be1da707SZhi Wang ret |= ((cmd_reg_inhibit(s, i) || 1073be1da707SZhi Wang (cmd_reg_inhibit(s, i + 1)))) ? 10745c56883aSfred gao -EBADRQC : 0; 1075be1da707SZhi Wang if (ret) 1076be1da707SZhi Wang break; 1077be1da707SZhi Wang ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrr-src"); 10785c56883aSfred gao if (ret) 10795c56883aSfred gao break; 1080be1da707SZhi Wang ret |= cmd_reg_handler(s, cmd_reg(s, i + 1), i, "lrr-dst"); 10815c56883aSfred gao if (ret) 10825c56883aSfred gao break; 1083be1da707SZhi Wang } 1084be1da707SZhi Wang return ret; 1085be1da707SZhi Wang } 1086be1da707SZhi Wang 1087be1da707SZhi Wang static inline int cmd_address_audit(struct parser_exec_state *s, 1088be1da707SZhi Wang unsigned long guest_gma, int op_size, bool index_mode); 1089be1da707SZhi Wang 1090be1da707SZhi Wang static int cmd_handler_lrm(struct parser_exec_state *s) 1091be1da707SZhi Wang { 1092be1da707SZhi Wang struct intel_gvt *gvt = s->vgpu->gvt; 1093be1da707SZhi Wang int gmadr_bytes = gvt->device_info.gmadr_bytes_in_cmd; 1094be1da707SZhi Wang unsigned long gma; 1095be1da707SZhi Wang int i, ret = 0; 1096be1da707SZhi Wang int cmd_len = cmd_length(s); 1097be1da707SZhi Wang 1098be1da707SZhi Wang for (i = 1; i < cmd_len;) { 10998fde4107SChris Wilson if (IS_BROADWELL(s->engine->i915)) 11005c56883aSfred gao ret |= (cmd_reg_inhibit(s, i)) ? -EBADRQC : 0; 1101be1da707SZhi Wang if (ret) 1102be1da707SZhi Wang break; 1103be1da707SZhi Wang ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrm"); 11045c56883aSfred gao if (ret) 11055c56883aSfred gao break; 1106be1da707SZhi Wang if (cmd_val(s, 0) & (1 << 22)) { 1107be1da707SZhi Wang gma = cmd_gma(s, i + 1); 1108be1da707SZhi Wang if (gmadr_bytes == 8) 1109be1da707SZhi Wang gma |= (cmd_gma_hi(s, i + 2)) << 32; 1110be1da707SZhi Wang ret |= cmd_address_audit(s, gma, sizeof(u32), false); 11115c56883aSfred gao if (ret) 11125c56883aSfred gao break; 1113be1da707SZhi Wang } 1114be1da707SZhi Wang i += gmadr_dw_number(s) + 1; 1115be1da707SZhi Wang } 1116be1da707SZhi Wang return ret; 1117be1da707SZhi Wang } 1118be1da707SZhi Wang 1119be1da707SZhi Wang static int cmd_handler_srm(struct parser_exec_state *s) 1120be1da707SZhi Wang { 1121be1da707SZhi Wang int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd; 1122be1da707SZhi Wang unsigned long gma; 1123be1da707SZhi Wang int i, ret = 0; 1124be1da707SZhi Wang int cmd_len = cmd_length(s); 1125be1da707SZhi Wang 1126be1da707SZhi Wang for (i = 1; i < cmd_len;) { 1127be1da707SZhi Wang ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "srm"); 11285c56883aSfred gao if (ret) 11295c56883aSfred gao break; 1130be1da707SZhi Wang if (cmd_val(s, 0) & (1 << 22)) { 1131be1da707SZhi Wang gma = cmd_gma(s, i + 1); 1132be1da707SZhi Wang if (gmadr_bytes == 8) 1133be1da707SZhi Wang gma |= (cmd_gma_hi(s, i + 2)) << 32; 1134be1da707SZhi Wang ret |= cmd_address_audit(s, gma, sizeof(u32), false); 11355c56883aSfred gao if (ret) 11365c56883aSfred gao break; 1137be1da707SZhi Wang } 1138be1da707SZhi Wang i += gmadr_dw_number(s) + 1; 1139be1da707SZhi Wang } 1140be1da707SZhi Wang return ret; 1141be1da707SZhi Wang } 1142be1da707SZhi Wang 1143be1da707SZhi Wang struct cmd_interrupt_event { 1144be1da707SZhi Wang int pipe_control_notify; 1145be1da707SZhi Wang int mi_flush_dw; 1146be1da707SZhi Wang int mi_user_interrupt; 1147be1da707SZhi Wang }; 1148be1da707SZhi Wang 11490b782e66SRikard Falkeborn static const struct cmd_interrupt_event cmd_interrupt_events[] = { 11508a68d464SChris Wilson [RCS0] = { 1151be1da707SZhi Wang .pipe_control_notify = RCS_PIPE_CONTROL, 1152be1da707SZhi Wang .mi_flush_dw = INTEL_GVT_EVENT_RESERVED, 1153be1da707SZhi Wang .mi_user_interrupt = RCS_MI_USER_INTERRUPT, 1154be1da707SZhi Wang }, 11558a68d464SChris Wilson [BCS0] = { 1156be1da707SZhi Wang .pipe_control_notify = INTEL_GVT_EVENT_RESERVED, 1157be1da707SZhi Wang .mi_flush_dw = BCS_MI_FLUSH_DW, 1158be1da707SZhi Wang .mi_user_interrupt = BCS_MI_USER_INTERRUPT, 1159be1da707SZhi Wang }, 11608a68d464SChris Wilson [VCS0] = { 1161be1da707SZhi Wang .pipe_control_notify = INTEL_GVT_EVENT_RESERVED, 1162be1da707SZhi Wang .mi_flush_dw = VCS_MI_FLUSH_DW, 1163be1da707SZhi Wang .mi_user_interrupt = VCS_MI_USER_INTERRUPT, 1164be1da707SZhi Wang }, 11658a68d464SChris Wilson [VCS1] = { 1166be1da707SZhi Wang .pipe_control_notify = INTEL_GVT_EVENT_RESERVED, 1167be1da707SZhi Wang .mi_flush_dw = VCS2_MI_FLUSH_DW, 1168be1da707SZhi Wang .mi_user_interrupt = VCS2_MI_USER_INTERRUPT, 1169be1da707SZhi Wang }, 11708a68d464SChris Wilson [VECS0] = { 1171be1da707SZhi Wang .pipe_control_notify = INTEL_GVT_EVENT_RESERVED, 1172be1da707SZhi Wang .mi_flush_dw = VECS_MI_FLUSH_DW, 1173be1da707SZhi Wang .mi_user_interrupt = VECS_MI_USER_INTERRUPT, 1174be1da707SZhi Wang }, 1175be1da707SZhi Wang }; 1176be1da707SZhi Wang 1177be1da707SZhi Wang static int cmd_handler_pipe_control(struct parser_exec_state *s) 1178be1da707SZhi Wang { 1179be1da707SZhi Wang int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd; 1180be1da707SZhi Wang unsigned long gma; 1181be1da707SZhi Wang bool index_mode = false; 1182be1da707SZhi Wang unsigned int post_sync; 1183be1da707SZhi Wang int ret = 0; 1184ac071578SXiaolin Zhang u32 hws_pga, val; 1185be1da707SZhi Wang 1186be1da707SZhi Wang post_sync = (cmd_val(s, 1) & PIPE_CONTROL_POST_SYNC_OP_MASK) >> 14; 1187be1da707SZhi Wang 1188be1da707SZhi Wang /* LRI post sync */ 1189be1da707SZhi Wang if (cmd_val(s, 1) & PIPE_CONTROL_MMIO_WRITE) 1190be1da707SZhi Wang ret = cmd_reg_handler(s, cmd_reg(s, 2), 1, "pipe_ctrl"); 1191be1da707SZhi Wang /* post sync */ 1192be1da707SZhi Wang else if (post_sync) { 1193be1da707SZhi Wang if (post_sync == 2) 1194be1da707SZhi Wang ret = cmd_reg_handler(s, 0x2350, 1, "pipe_ctrl"); 1195be1da707SZhi Wang else if (post_sync == 3) 1196be1da707SZhi Wang ret = cmd_reg_handler(s, 0x2358, 1, "pipe_ctrl"); 1197be1da707SZhi Wang else if (post_sync == 1) { 1198be1da707SZhi Wang /* check ggtt*/ 11993f765a34SYulei Zhang if ((cmd_val(s, 1) & PIPE_CONTROL_GLOBAL_GTT_IVB)) { 1200be1da707SZhi Wang gma = cmd_val(s, 2) & GENMASK(31, 3); 1201be1da707SZhi Wang if (gmadr_bytes == 8) 1202be1da707SZhi Wang gma |= (cmd_gma_hi(s, 3)) << 32; 1203be1da707SZhi Wang /* Store Data Index */ 1204be1da707SZhi Wang if (cmd_val(s, 1) & (1 << 21)) 1205be1da707SZhi Wang index_mode = true; 1206be1da707SZhi Wang ret |= cmd_address_audit(s, gma, sizeof(u64), 1207be1da707SZhi Wang index_mode); 1208ac071578SXiaolin Zhang if (ret) 1209ac071578SXiaolin Zhang return ret; 1210ac071578SXiaolin Zhang if (index_mode) { 12118fde4107SChris Wilson hws_pga = s->vgpu->hws_pga[s->engine->id]; 1212ac071578SXiaolin Zhang gma = hws_pga + gma; 1213ac071578SXiaolin Zhang patch_value(s, cmd_ptr(s, 2), gma); 1214ac071578SXiaolin Zhang val = cmd_val(s, 1) & (~(1 << 21)); 1215ac071578SXiaolin Zhang patch_value(s, cmd_ptr(s, 1), val); 1216ac071578SXiaolin Zhang } 1217be1da707SZhi Wang } 1218be1da707SZhi Wang } 1219be1da707SZhi Wang } 1220be1da707SZhi Wang 1221be1da707SZhi Wang if (ret) 1222be1da707SZhi Wang return ret; 1223be1da707SZhi Wang 1224be1da707SZhi Wang if (cmd_val(s, 1) & PIPE_CONTROL_NOTIFY) 12258fde4107SChris Wilson set_bit(cmd_interrupt_events[s->engine->id].pipe_control_notify, 1226be1da707SZhi Wang s->workload->pending_events); 1227be1da707SZhi Wang return 0; 1228be1da707SZhi Wang } 1229be1da707SZhi Wang 1230be1da707SZhi Wang static int cmd_handler_mi_user_interrupt(struct parser_exec_state *s) 1231be1da707SZhi Wang { 12328fde4107SChris Wilson set_bit(cmd_interrupt_events[s->engine->id].mi_user_interrupt, 1233be1da707SZhi Wang s->workload->pending_events); 12345da795b0SZhipeng Gong patch_value(s, cmd_ptr(s, 0), MI_NOOP); 1235be1da707SZhi Wang return 0; 1236be1da707SZhi Wang } 1237be1da707SZhi Wang 1238be1da707SZhi Wang static int cmd_advance_default(struct parser_exec_state *s) 1239be1da707SZhi Wang { 1240be1da707SZhi Wang return ip_gma_advance(s, cmd_length(s)); 1241be1da707SZhi Wang } 1242be1da707SZhi Wang 1243be1da707SZhi Wang static int cmd_handler_mi_batch_buffer_end(struct parser_exec_state *s) 1244be1da707SZhi Wang { 1245be1da707SZhi Wang int ret; 1246be1da707SZhi Wang 1247be1da707SZhi Wang if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) { 1248be1da707SZhi Wang s->buf_type = BATCH_BUFFER_INSTRUCTION; 1249be1da707SZhi Wang ret = ip_gma_set(s, s->ret_ip_gma_bb); 1250be1da707SZhi Wang s->buf_addr_type = s->saved_buf_addr_type; 1251493f30cdSYan Zhao } else if (s->buf_type == RING_BUFFER_CTX) { 1252493f30cdSYan Zhao ret = ip_gma_set(s, s->ring_tail); 1253be1da707SZhi Wang } else { 1254be1da707SZhi Wang s->buf_type = RING_BUFFER_INSTRUCTION; 1255be1da707SZhi Wang s->buf_addr_type = GTT_BUFFER; 1256be1da707SZhi Wang if (s->ret_ip_gma_ring >= s->ring_start + s->ring_size) 1257be1da707SZhi Wang s->ret_ip_gma_ring -= s->ring_size; 1258be1da707SZhi Wang ret = ip_gma_set(s, s->ret_ip_gma_ring); 1259be1da707SZhi Wang } 1260be1da707SZhi Wang return ret; 1261be1da707SZhi Wang } 1262be1da707SZhi Wang 1263be1da707SZhi Wang struct mi_display_flip_command_info { 1264be1da707SZhi Wang int pipe; 1265be1da707SZhi Wang int plane; 1266be1da707SZhi Wang int event; 1267be1da707SZhi Wang i915_reg_t stride_reg; 1268be1da707SZhi Wang i915_reg_t ctrl_reg; 1269be1da707SZhi Wang i915_reg_t surf_reg; 1270be1da707SZhi Wang u64 stride_val; 1271be1da707SZhi Wang u64 tile_val; 1272be1da707SZhi Wang u64 surf_val; 1273be1da707SZhi Wang bool async_flip; 1274be1da707SZhi Wang }; 1275be1da707SZhi Wang 1276be1da707SZhi Wang struct plane_code_mapping { 1277be1da707SZhi Wang int pipe; 1278be1da707SZhi Wang int plane; 1279be1da707SZhi Wang int event; 1280be1da707SZhi Wang }; 1281be1da707SZhi Wang 1282be1da707SZhi Wang static int gen8_decode_mi_display_flip(struct parser_exec_state *s, 1283be1da707SZhi Wang struct mi_display_flip_command_info *info) 1284be1da707SZhi Wang { 12858fde4107SChris Wilson struct drm_i915_private *dev_priv = s->engine->i915; 1286be1da707SZhi Wang struct plane_code_mapping gen8_plane_code[] = { 1287be1da707SZhi Wang [0] = {PIPE_A, PLANE_A, PRIMARY_A_FLIP_DONE}, 1288be1da707SZhi Wang [1] = {PIPE_B, PLANE_A, PRIMARY_B_FLIP_DONE}, 1289be1da707SZhi Wang [2] = {PIPE_A, PLANE_B, SPRITE_A_FLIP_DONE}, 1290be1da707SZhi Wang [3] = {PIPE_B, PLANE_B, SPRITE_B_FLIP_DONE}, 1291be1da707SZhi Wang [4] = {PIPE_C, PLANE_A, PRIMARY_C_FLIP_DONE}, 1292be1da707SZhi Wang [5] = {PIPE_C, PLANE_B, SPRITE_C_FLIP_DONE}, 1293be1da707SZhi Wang }; 1294be1da707SZhi Wang u32 dword0, dword1, dword2; 1295be1da707SZhi Wang u32 v; 1296be1da707SZhi Wang 1297be1da707SZhi Wang dword0 = cmd_val(s, 0); 1298be1da707SZhi Wang dword1 = cmd_val(s, 1); 1299be1da707SZhi Wang dword2 = cmd_val(s, 2); 1300be1da707SZhi Wang 1301be1da707SZhi Wang v = (dword0 & GENMASK(21, 19)) >> 19; 1302db19c724SPankaj Bharadiya if (drm_WARN_ON(&dev_priv->drm, v >= ARRAY_SIZE(gen8_plane_code))) 13035c56883aSfred gao return -EBADRQC; 1304be1da707SZhi Wang 1305be1da707SZhi Wang info->pipe = gen8_plane_code[v].pipe; 1306be1da707SZhi Wang info->plane = gen8_plane_code[v].plane; 1307be1da707SZhi Wang info->event = gen8_plane_code[v].event; 1308be1da707SZhi Wang info->stride_val = (dword1 & GENMASK(15, 6)) >> 6; 1309be1da707SZhi Wang info->tile_val = (dword1 & 0x1); 1310be1da707SZhi Wang info->surf_val = (dword2 & GENMASK(31, 12)) >> 12; 1311be1da707SZhi Wang info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1); 1312be1da707SZhi Wang 1313be1da707SZhi Wang if (info->plane == PLANE_A) { 1314be1da707SZhi Wang info->ctrl_reg = DSPCNTR(info->pipe); 1315be1da707SZhi Wang info->stride_reg = DSPSTRIDE(info->pipe); 1316be1da707SZhi Wang info->surf_reg = DSPSURF(info->pipe); 1317be1da707SZhi Wang } else if (info->plane == PLANE_B) { 1318be1da707SZhi Wang info->ctrl_reg = SPRCTL(info->pipe); 1319be1da707SZhi Wang info->stride_reg = SPRSTRIDE(info->pipe); 1320be1da707SZhi Wang info->surf_reg = SPRSURF(info->pipe); 1321be1da707SZhi Wang } else { 1322db19c724SPankaj Bharadiya drm_WARN_ON(&dev_priv->drm, 1); 13235c56883aSfred gao return -EBADRQC; 1324be1da707SZhi Wang } 1325be1da707SZhi Wang return 0; 1326be1da707SZhi Wang } 1327be1da707SZhi Wang 1328be1da707SZhi Wang static int skl_decode_mi_display_flip(struct parser_exec_state *s, 1329be1da707SZhi Wang struct mi_display_flip_command_info *info) 1330be1da707SZhi Wang { 13318fde4107SChris Wilson struct drm_i915_private *dev_priv = s->engine->i915; 1332695fbc08STina Zhang struct intel_vgpu *vgpu = s->vgpu; 1333be1da707SZhi Wang u32 dword0 = cmd_val(s, 0); 1334be1da707SZhi Wang u32 dword1 = cmd_val(s, 1); 1335be1da707SZhi Wang u32 dword2 = cmd_val(s, 2); 1336be1da707SZhi Wang u32 plane = (dword0 & GENMASK(12, 8)) >> 8; 1337be1da707SZhi Wang 13386e27d514SXu Han info->plane = PRIMARY_PLANE; 13396e27d514SXu Han 1340be1da707SZhi Wang switch (plane) { 1341be1da707SZhi Wang case MI_DISPLAY_FLIP_SKL_PLANE_1_A: 1342be1da707SZhi Wang info->pipe = PIPE_A; 1343be1da707SZhi Wang info->event = PRIMARY_A_FLIP_DONE; 1344be1da707SZhi Wang break; 1345be1da707SZhi Wang case MI_DISPLAY_FLIP_SKL_PLANE_1_B: 1346be1da707SZhi Wang info->pipe = PIPE_B; 1347be1da707SZhi Wang info->event = PRIMARY_B_FLIP_DONE; 1348be1da707SZhi Wang break; 1349be1da707SZhi Wang case MI_DISPLAY_FLIP_SKL_PLANE_1_C: 135064fafcf5SMin He info->pipe = PIPE_C; 1351be1da707SZhi Wang info->event = PRIMARY_C_FLIP_DONE; 1352be1da707SZhi Wang break; 13536e27d514SXu Han 13546e27d514SXu Han case MI_DISPLAY_FLIP_SKL_PLANE_2_A: 13556e27d514SXu Han info->pipe = PIPE_A; 13566e27d514SXu Han info->event = SPRITE_A_FLIP_DONE; 13576e27d514SXu Han info->plane = SPRITE_PLANE; 13586e27d514SXu Han break; 13596e27d514SXu Han case MI_DISPLAY_FLIP_SKL_PLANE_2_B: 13606e27d514SXu Han info->pipe = PIPE_B; 13616e27d514SXu Han info->event = SPRITE_B_FLIP_DONE; 13626e27d514SXu Han info->plane = SPRITE_PLANE; 13636e27d514SXu Han break; 13646e27d514SXu Han case MI_DISPLAY_FLIP_SKL_PLANE_2_C: 13656e27d514SXu Han info->pipe = PIPE_C; 13666e27d514SXu Han info->event = SPRITE_C_FLIP_DONE; 13676e27d514SXu Han info->plane = SPRITE_PLANE; 13686e27d514SXu Han break; 13696e27d514SXu Han 1370be1da707SZhi Wang default: 1371695fbc08STina Zhang gvt_vgpu_err("unknown plane code %d\n", plane); 13725c56883aSfred gao return -EBADRQC; 1373be1da707SZhi Wang } 1374be1da707SZhi Wang 1375be1da707SZhi Wang info->stride_val = (dword1 & GENMASK(15, 6)) >> 6; 1376be1da707SZhi Wang info->tile_val = (dword1 & GENMASK(2, 0)); 1377be1da707SZhi Wang info->surf_val = (dword2 & GENMASK(31, 12)) >> 12; 1378be1da707SZhi Wang info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1); 1379be1da707SZhi Wang 1380be1da707SZhi Wang info->ctrl_reg = DSPCNTR(info->pipe); 1381be1da707SZhi Wang info->stride_reg = DSPSTRIDE(info->pipe); 1382be1da707SZhi Wang info->surf_reg = DSPSURF(info->pipe); 1383be1da707SZhi Wang 1384be1da707SZhi Wang return 0; 1385be1da707SZhi Wang } 1386be1da707SZhi Wang 1387be1da707SZhi Wang static int gen8_check_mi_display_flip(struct parser_exec_state *s, 1388be1da707SZhi Wang struct mi_display_flip_command_info *info) 1389be1da707SZhi Wang { 1390be1da707SZhi Wang u32 stride, tile; 1391be1da707SZhi Wang 1392be1da707SZhi Wang if (!info->async_flip) 1393be1da707SZhi Wang return 0; 1394be1da707SZhi Wang 1395d8d12312SLucas De Marchi if (GRAPHICS_VER(s->engine->i915) >= 9) { 139690551a12SZhenyu Wang stride = vgpu_vreg_t(s->vgpu, info->stride_reg) & GENMASK(9, 0); 139790551a12SZhenyu Wang tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & 1398be1da707SZhi Wang GENMASK(12, 10)) >> 10; 1399be1da707SZhi Wang } else { 140090551a12SZhenyu Wang stride = (vgpu_vreg_t(s->vgpu, info->stride_reg) & 1401be1da707SZhi Wang GENMASK(15, 6)) >> 6; 140290551a12SZhenyu Wang tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10; 1403be1da707SZhi Wang } 1404be1da707SZhi Wang 1405be1da707SZhi Wang if (stride != info->stride_val) 1406be1da707SZhi Wang gvt_dbg_cmd("cannot change stride during async flip\n"); 1407be1da707SZhi Wang 1408be1da707SZhi Wang if (tile != info->tile_val) 1409be1da707SZhi Wang gvt_dbg_cmd("cannot change tile during async flip\n"); 1410be1da707SZhi Wang 1411be1da707SZhi Wang return 0; 1412be1da707SZhi Wang } 1413be1da707SZhi Wang 1414be1da707SZhi Wang static int gen8_update_plane_mmio_from_mi_display_flip( 1415be1da707SZhi Wang struct parser_exec_state *s, 1416be1da707SZhi Wang struct mi_display_flip_command_info *info) 1417be1da707SZhi Wang { 14188fde4107SChris Wilson struct drm_i915_private *dev_priv = s->engine->i915; 1419be1da707SZhi Wang struct intel_vgpu *vgpu = s->vgpu; 1420be1da707SZhi Wang 142190551a12SZhenyu Wang set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12), 142299c79fd4SDu, Changbin info->surf_val << 12); 1423d8d12312SLucas De Marchi if (GRAPHICS_VER(dev_priv) >= 9) { 142490551a12SZhenyu Wang set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(9, 0), 142599c79fd4SDu, Changbin info->stride_val); 142690551a12SZhenyu Wang set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10), 142799c79fd4SDu, Changbin info->tile_val << 10); 142899c79fd4SDu, Changbin } else { 142990551a12SZhenyu Wang set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(15, 6), 143099c79fd4SDu, Changbin info->stride_val << 6); 143190551a12SZhenyu Wang set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(10, 10), 143299c79fd4SDu, Changbin info->tile_val << 10); 143399c79fd4SDu, Changbin } 1434be1da707SZhi Wang 1435d39af942SColin Xu if (info->plane == PLANE_PRIMARY) 1436d39af942SColin Xu vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(info->pipe))++; 1437d39af942SColin Xu 1438d39af942SColin Xu if (info->async_flip) 1439be1da707SZhi Wang intel_vgpu_trigger_virtual_event(vgpu, info->event); 1440d39af942SColin Xu else 1441d39af942SColin Xu set_bit(info->event, vgpu->irq.flip_done_event[info->pipe]); 1442d39af942SColin Xu 1443be1da707SZhi Wang return 0; 1444be1da707SZhi Wang } 1445be1da707SZhi Wang 1446be1da707SZhi Wang static int decode_mi_display_flip(struct parser_exec_state *s, 1447be1da707SZhi Wang struct mi_display_flip_command_info *info) 1448be1da707SZhi Wang { 14498fde4107SChris Wilson if (IS_BROADWELL(s->engine->i915)) 1450be1da707SZhi Wang return gen8_decode_mi_display_flip(s, info); 1451d8d12312SLucas De Marchi if (GRAPHICS_VER(s->engine->i915) >= 9) 1452be1da707SZhi Wang return skl_decode_mi_display_flip(s, info); 1453be1da707SZhi Wang 1454be1da707SZhi Wang return -ENODEV; 1455be1da707SZhi Wang } 1456be1da707SZhi Wang 1457be1da707SZhi Wang static int check_mi_display_flip(struct parser_exec_state *s, 1458be1da707SZhi Wang struct mi_display_flip_command_info *info) 1459be1da707SZhi Wang { 1460be1da707SZhi Wang return gen8_check_mi_display_flip(s, info); 1461be1da707SZhi Wang } 1462be1da707SZhi Wang 1463be1da707SZhi Wang static int update_plane_mmio_from_mi_display_flip( 1464be1da707SZhi Wang struct parser_exec_state *s, 1465be1da707SZhi Wang struct mi_display_flip_command_info *info) 1466be1da707SZhi Wang { 1467be1da707SZhi Wang return gen8_update_plane_mmio_from_mi_display_flip(s, info); 1468be1da707SZhi Wang } 1469be1da707SZhi Wang 1470be1da707SZhi Wang static int cmd_handler_mi_display_flip(struct parser_exec_state *s) 1471be1da707SZhi Wang { 1472be1da707SZhi Wang struct mi_display_flip_command_info info; 1473695fbc08STina Zhang struct intel_vgpu *vgpu = s->vgpu; 1474be1da707SZhi Wang int ret; 1475be1da707SZhi Wang int i; 1476be1da707SZhi Wang int len = cmd_length(s); 147700a33be4SGao, Fred u32 valid_len = CMD_LEN(1); 147800a33be4SGao, Fred 147900a33be4SGao, Fred /* Flip Type == Stereo 3D Flip */ 148000a33be4SGao, Fred if (DWORD_FIELD(2, 1, 0) == 2) 148100a33be4SGao, Fred valid_len++; 148200a33be4SGao, Fred ret = gvt_check_valid_cmd_length(cmd_length(s), 148300a33be4SGao, Fred valid_len); 148400a33be4SGao, Fred if (ret) 148500a33be4SGao, Fred return ret; 1486be1da707SZhi Wang 1487be1da707SZhi Wang ret = decode_mi_display_flip(s, &info); 1488be1da707SZhi Wang if (ret) { 1489695fbc08STina Zhang gvt_vgpu_err("fail to decode MI display flip command\n"); 1490be1da707SZhi Wang return ret; 1491be1da707SZhi Wang } 1492be1da707SZhi Wang 1493be1da707SZhi Wang ret = check_mi_display_flip(s, &info); 1494be1da707SZhi Wang if (ret) { 1495695fbc08STina Zhang gvt_vgpu_err("invalid MI display flip command\n"); 1496be1da707SZhi Wang return ret; 1497be1da707SZhi Wang } 1498be1da707SZhi Wang 1499be1da707SZhi Wang ret = update_plane_mmio_from_mi_display_flip(s, &info); 1500be1da707SZhi Wang if (ret) { 1501695fbc08STina Zhang gvt_vgpu_err("fail to update plane mmio\n"); 1502be1da707SZhi Wang return ret; 1503be1da707SZhi Wang } 1504be1da707SZhi Wang 1505be1da707SZhi Wang for (i = 0; i < len; i++) 1506be1da707SZhi Wang patch_value(s, cmd_ptr(s, i), MI_NOOP); 1507be1da707SZhi Wang return 0; 1508be1da707SZhi Wang } 1509be1da707SZhi Wang 1510be1da707SZhi Wang static bool is_wait_for_flip_pending(u32 cmd) 1511be1da707SZhi Wang { 1512be1da707SZhi Wang return cmd & (MI_WAIT_FOR_PLANE_A_FLIP_PENDING | 1513be1da707SZhi Wang MI_WAIT_FOR_PLANE_B_FLIP_PENDING | 1514be1da707SZhi Wang MI_WAIT_FOR_PLANE_C_FLIP_PENDING | 1515be1da707SZhi Wang MI_WAIT_FOR_SPRITE_A_FLIP_PENDING | 1516be1da707SZhi Wang MI_WAIT_FOR_SPRITE_B_FLIP_PENDING | 1517be1da707SZhi Wang MI_WAIT_FOR_SPRITE_C_FLIP_PENDING); 1518be1da707SZhi Wang } 1519be1da707SZhi Wang 1520be1da707SZhi Wang static int cmd_handler_mi_wait_for_event(struct parser_exec_state *s) 1521be1da707SZhi Wang { 1522be1da707SZhi Wang u32 cmd = cmd_val(s, 0); 1523be1da707SZhi Wang 1524be1da707SZhi Wang if (!is_wait_for_flip_pending(cmd)) 1525be1da707SZhi Wang return 0; 1526be1da707SZhi Wang 1527be1da707SZhi Wang patch_value(s, cmd_ptr(s, 0), MI_NOOP); 1528be1da707SZhi Wang return 0; 1529be1da707SZhi Wang } 1530be1da707SZhi Wang 1531be1da707SZhi Wang static unsigned long get_gma_bb_from_cmd(struct parser_exec_state *s, int index) 1532be1da707SZhi Wang { 1533be1da707SZhi Wang unsigned long addr; 1534be1da707SZhi Wang unsigned long gma_high, gma_low; 15355c56883aSfred gao struct intel_vgpu *vgpu = s->vgpu; 15365c56883aSfred gao int gmadr_bytes = vgpu->gvt->device_info.gmadr_bytes_in_cmd; 1537be1da707SZhi Wang 15385c56883aSfred gao if (WARN_ON(gmadr_bytes != 4 && gmadr_bytes != 8)) { 15395c56883aSfred gao gvt_vgpu_err("invalid gma bytes %d\n", gmadr_bytes); 1540be1da707SZhi Wang return INTEL_GVT_INVALID_ADDR; 15415c56883aSfred gao } 1542be1da707SZhi Wang 1543be1da707SZhi Wang gma_low = cmd_val(s, index) & BATCH_BUFFER_ADDR_MASK; 1544be1da707SZhi Wang if (gmadr_bytes == 4) { 1545be1da707SZhi Wang addr = gma_low; 1546be1da707SZhi Wang } else { 1547be1da707SZhi Wang gma_high = cmd_val(s, index + 1) & BATCH_BUFFER_ADDR_HIGH_MASK; 1548be1da707SZhi Wang addr = (((unsigned long)gma_high) << 32) | gma_low; 1549be1da707SZhi Wang } 1550be1da707SZhi Wang return addr; 1551be1da707SZhi Wang } 1552be1da707SZhi Wang 1553be1da707SZhi Wang static inline int cmd_address_audit(struct parser_exec_state *s, 1554be1da707SZhi Wang unsigned long guest_gma, int op_size, bool index_mode) 1555be1da707SZhi Wang { 1556be1da707SZhi Wang struct intel_vgpu *vgpu = s->vgpu; 1557be1da707SZhi Wang u32 max_surface_size = vgpu->gvt->device_info.max_surface_size; 1558be1da707SZhi Wang int i; 1559be1da707SZhi Wang int ret; 1560be1da707SZhi Wang 1561be1da707SZhi Wang if (op_size > max_surface_size) { 1562695fbc08STina Zhang gvt_vgpu_err("command address audit fail name %s\n", 1563695fbc08STina Zhang s->info->name); 15645c56883aSfred gao return -EFAULT; 1565be1da707SZhi Wang } 1566be1da707SZhi Wang 1567be1da707SZhi Wang if (index_mode) { 156813bcb80bSZhenyu Wang if (guest_gma >= I915_GTT_PAGE_SIZE) { 15695c56883aSfred gao ret = -EFAULT; 1570be1da707SZhi Wang goto err; 1571be1da707SZhi Wang } 157264d8bb83SPing Gao } else if (!intel_gvt_ggtt_validate_range(vgpu, guest_gma, op_size)) { 15735c56883aSfred gao ret = -EFAULT; 1574be1da707SZhi Wang goto err; 1575be1da707SZhi Wang } 157664d8bb83SPing Gao 1577be1da707SZhi Wang return 0; 157864d8bb83SPing Gao 1579be1da707SZhi Wang err: 1580695fbc08STina Zhang gvt_vgpu_err("cmd_parser: Malicious %s detected, addr=0x%lx, len=%d!\n", 1581be1da707SZhi Wang s->info->name, guest_gma, op_size); 1582be1da707SZhi Wang 1583be1da707SZhi Wang pr_err("cmd dump: "); 1584be1da707SZhi Wang for (i = 0; i < cmd_length(s); i++) { 1585be1da707SZhi Wang if (!(i % 4)) 1586be1da707SZhi Wang pr_err("\n%08x ", cmd_val(s, i)); 1587be1da707SZhi Wang else 1588be1da707SZhi Wang pr_err("%08x ", cmd_val(s, i)); 1589be1da707SZhi Wang } 1590be1da707SZhi Wang pr_err("\nvgpu%d: aperture 0x%llx - 0x%llx, hidden 0x%llx - 0x%llx\n", 1591be1da707SZhi Wang vgpu->id, 1592be1da707SZhi Wang vgpu_aperture_gmadr_base(vgpu), 1593be1da707SZhi Wang vgpu_aperture_gmadr_end(vgpu), 1594be1da707SZhi Wang vgpu_hidden_gmadr_base(vgpu), 1595be1da707SZhi Wang vgpu_hidden_gmadr_end(vgpu)); 1596be1da707SZhi Wang return ret; 1597be1da707SZhi Wang } 1598be1da707SZhi Wang 1599be1da707SZhi Wang static int cmd_handler_mi_store_data_imm(struct parser_exec_state *s) 1600be1da707SZhi Wang { 1601be1da707SZhi Wang int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd; 1602be1da707SZhi Wang int op_size = (cmd_length(s) - 3) * sizeof(u32); 1603be1da707SZhi Wang int core_id = (cmd_val(s, 2) & (1 << 0)) ? 1 : 0; 1604be1da707SZhi Wang unsigned long gma, gma_low, gma_high; 160500a33be4SGao, Fred u32 valid_len = CMD_LEN(2); 1606be1da707SZhi Wang int ret = 0; 1607be1da707SZhi Wang 1608be1da707SZhi Wang /* check ppggt */ 1609be1da707SZhi Wang if (!(cmd_val(s, 0) & (1 << 22))) 1610be1da707SZhi Wang return 0; 1611be1da707SZhi Wang 161200a33be4SGao, Fred /* check if QWORD */ 161300a33be4SGao, Fred if (DWORD_FIELD(0, 21, 21)) 161400a33be4SGao, Fred valid_len++; 161500a33be4SGao, Fred ret = gvt_check_valid_cmd_length(cmd_length(s), 161600a33be4SGao, Fred valid_len); 161700a33be4SGao, Fred if (ret) 161800a33be4SGao, Fred return ret; 161900a33be4SGao, Fred 1620be1da707SZhi Wang gma = cmd_val(s, 2) & GENMASK(31, 2); 1621be1da707SZhi Wang 1622be1da707SZhi Wang if (gmadr_bytes == 8) { 1623be1da707SZhi Wang gma_low = cmd_val(s, 1) & GENMASK(31, 2); 1624be1da707SZhi Wang gma_high = cmd_val(s, 2) & GENMASK(15, 0); 1625be1da707SZhi Wang gma = (gma_high << 32) | gma_low; 1626be1da707SZhi Wang core_id = (cmd_val(s, 1) & (1 << 0)) ? 1 : 0; 1627be1da707SZhi Wang } 1628be1da707SZhi Wang ret = cmd_address_audit(s, gma + op_size * core_id, op_size, false); 1629be1da707SZhi Wang return ret; 1630be1da707SZhi Wang } 1631be1da707SZhi Wang 1632be1da707SZhi Wang static inline int unexpected_cmd(struct parser_exec_state *s) 1633be1da707SZhi Wang { 1634695fbc08STina Zhang struct intel_vgpu *vgpu = s->vgpu; 1635695fbc08STina Zhang 1636695fbc08STina Zhang gvt_vgpu_err("Unexpected %s in command buffer!\n", s->info->name); 1637695fbc08STina Zhang 16385c56883aSfred gao return -EBADRQC; 1639be1da707SZhi Wang } 1640be1da707SZhi Wang 1641be1da707SZhi Wang static int cmd_handler_mi_semaphore_wait(struct parser_exec_state *s) 1642be1da707SZhi Wang { 1643be1da707SZhi Wang return unexpected_cmd(s); 1644be1da707SZhi Wang } 1645be1da707SZhi Wang 1646be1da707SZhi Wang static int cmd_handler_mi_report_perf_count(struct parser_exec_state *s) 1647be1da707SZhi Wang { 1648be1da707SZhi Wang return unexpected_cmd(s); 1649be1da707SZhi Wang } 1650be1da707SZhi Wang 1651be1da707SZhi Wang static int cmd_handler_mi_op_2e(struct parser_exec_state *s) 1652be1da707SZhi Wang { 1653be1da707SZhi Wang return unexpected_cmd(s); 1654be1da707SZhi Wang } 1655be1da707SZhi Wang 1656be1da707SZhi Wang static int cmd_handler_mi_op_2f(struct parser_exec_state *s) 1657be1da707SZhi Wang { 1658be1da707SZhi Wang int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd; 1659173bcc60SZhenyu Wang int op_size = (1 << ((cmd_val(s, 0) & GENMASK(20, 19)) >> 19)) * 1660173bcc60SZhenyu Wang sizeof(u32); 1661be1da707SZhi Wang unsigned long gma, gma_high; 166200a33be4SGao, Fred u32 valid_len = CMD_LEN(1); 1663be1da707SZhi Wang int ret = 0; 1664be1da707SZhi Wang 1665be1da707SZhi Wang if (!(cmd_val(s, 0) & (1 << 22))) 1666be1da707SZhi Wang return ret; 1667be1da707SZhi Wang 166892b1aa77SZhenyu Wang /* check inline data */ 166992b1aa77SZhenyu Wang if (cmd_val(s, 0) & BIT(18)) 167092b1aa77SZhenyu Wang valid_len = CMD_LEN(9); 167100a33be4SGao, Fred ret = gvt_check_valid_cmd_length(cmd_length(s), 167200a33be4SGao, Fred valid_len); 167300a33be4SGao, Fred if (ret) 167400a33be4SGao, Fred return ret; 167500a33be4SGao, Fred 1676be1da707SZhi Wang gma = cmd_val(s, 1) & GENMASK(31, 2); 1677be1da707SZhi Wang if (gmadr_bytes == 8) { 1678be1da707SZhi Wang gma_high = cmd_val(s, 2) & GENMASK(15, 0); 1679be1da707SZhi Wang gma = (gma_high << 32) | gma; 1680be1da707SZhi Wang } 1681be1da707SZhi Wang ret = cmd_address_audit(s, gma, op_size, false); 1682be1da707SZhi Wang return ret; 1683be1da707SZhi Wang } 1684be1da707SZhi Wang 1685be1da707SZhi Wang static int cmd_handler_mi_store_data_index(struct parser_exec_state *s) 1686be1da707SZhi Wang { 1687be1da707SZhi Wang return unexpected_cmd(s); 1688be1da707SZhi Wang } 1689be1da707SZhi Wang 1690be1da707SZhi Wang static int cmd_handler_mi_clflush(struct parser_exec_state *s) 1691be1da707SZhi Wang { 1692be1da707SZhi Wang return unexpected_cmd(s); 1693be1da707SZhi Wang } 1694be1da707SZhi Wang 1695be1da707SZhi Wang static int cmd_handler_mi_conditional_batch_buffer_end( 1696be1da707SZhi Wang struct parser_exec_state *s) 1697be1da707SZhi Wang { 1698be1da707SZhi Wang return unexpected_cmd(s); 1699be1da707SZhi Wang } 1700be1da707SZhi Wang 1701be1da707SZhi Wang static int cmd_handler_mi_update_gtt(struct parser_exec_state *s) 1702be1da707SZhi Wang { 1703be1da707SZhi Wang return unexpected_cmd(s); 1704be1da707SZhi Wang } 1705be1da707SZhi Wang 1706be1da707SZhi Wang static int cmd_handler_mi_flush_dw(struct parser_exec_state *s) 1707be1da707SZhi Wang { 1708be1da707SZhi Wang int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd; 1709be1da707SZhi Wang unsigned long gma; 1710be1da707SZhi Wang bool index_mode = false; 1711be1da707SZhi Wang int ret = 0; 1712ac071578SXiaolin Zhang u32 hws_pga, val; 171300a33be4SGao, Fred u32 valid_len = CMD_LEN(2); 171400a33be4SGao, Fred 171500a33be4SGao, Fred ret = gvt_check_valid_cmd_length(cmd_length(s), 171600a33be4SGao, Fred valid_len); 171700a33be4SGao, Fred if (ret) { 171800a33be4SGao, Fred /* Check again for Qword */ 171900a33be4SGao, Fred ret = gvt_check_valid_cmd_length(cmd_length(s), 172000a33be4SGao, Fred ++valid_len); 172100a33be4SGao, Fred return ret; 172200a33be4SGao, Fred } 1723be1da707SZhi Wang 1724be1da707SZhi Wang /* Check post-sync and ppgtt bit */ 1725be1da707SZhi Wang if (((cmd_val(s, 0) >> 14) & 0x3) && (cmd_val(s, 1) & (1 << 2))) { 1726be1da707SZhi Wang gma = cmd_val(s, 1) & GENMASK(31, 3); 1727be1da707SZhi Wang if (gmadr_bytes == 8) 1728be1da707SZhi Wang gma |= (cmd_val(s, 2) & GENMASK(15, 0)) << 32; 1729be1da707SZhi Wang /* Store Data Index */ 1730be1da707SZhi Wang if (cmd_val(s, 0) & (1 << 21)) 1731be1da707SZhi Wang index_mode = true; 1732be1da707SZhi Wang ret = cmd_address_audit(s, gma, sizeof(u64), index_mode); 1733ac071578SXiaolin Zhang if (ret) 1734ac071578SXiaolin Zhang return ret; 1735ac071578SXiaolin Zhang if (index_mode) { 17368fde4107SChris Wilson hws_pga = s->vgpu->hws_pga[s->engine->id]; 1737ac071578SXiaolin Zhang gma = hws_pga + gma; 1738ac071578SXiaolin Zhang patch_value(s, cmd_ptr(s, 1), gma); 1739ac071578SXiaolin Zhang val = cmd_val(s, 0) & (~(1 << 21)); 1740ac071578SXiaolin Zhang patch_value(s, cmd_ptr(s, 0), val); 1741ac071578SXiaolin Zhang } 1742be1da707SZhi Wang } 1743be1da707SZhi Wang /* Check notify bit */ 1744be1da707SZhi Wang if ((cmd_val(s, 0) & (1 << 8))) 17458fde4107SChris Wilson set_bit(cmd_interrupt_events[s->engine->id].mi_flush_dw, 1746be1da707SZhi Wang s->workload->pending_events); 1747be1da707SZhi Wang return ret; 1748be1da707SZhi Wang } 1749be1da707SZhi Wang 1750be1da707SZhi Wang static void addr_type_update_snb(struct parser_exec_state *s) 1751be1da707SZhi Wang { 1752be1da707SZhi Wang if ((s->buf_type == RING_BUFFER_INSTRUCTION) && 1753be1da707SZhi Wang (BATCH_BUFFER_ADR_SPACE_BIT(cmd_val(s, 0)) == 1)) { 1754be1da707SZhi Wang s->buf_addr_type = PPGTT_BUFFER; 1755be1da707SZhi Wang } 1756be1da707SZhi Wang } 1757be1da707SZhi Wang 1758be1da707SZhi Wang 1759be1da707SZhi Wang static int copy_gma_to_hva(struct intel_vgpu *vgpu, struct intel_vgpu_mm *mm, 1760be1da707SZhi Wang unsigned long gma, unsigned long end_gma, void *va) 1761be1da707SZhi Wang { 1762be1da707SZhi Wang unsigned long copy_len, offset; 1763be1da707SZhi Wang unsigned long len = 0; 1764be1da707SZhi Wang unsigned long gpa; 1765be1da707SZhi Wang 1766be1da707SZhi Wang while (gma != end_gma) { 1767be1da707SZhi Wang gpa = intel_vgpu_gma_to_gpa(mm, gma); 1768be1da707SZhi Wang if (gpa == INTEL_GVT_INVALID_ADDR) { 1769695fbc08STina Zhang gvt_vgpu_err("invalid gma address: %lx\n", gma); 1770be1da707SZhi Wang return -EFAULT; 1771be1da707SZhi Wang } 1772be1da707SZhi Wang 17739556e118SZhi Wang offset = gma & (I915_GTT_PAGE_SIZE - 1); 1774be1da707SZhi Wang 17759556e118SZhi Wang copy_len = (end_gma - gma) >= (I915_GTT_PAGE_SIZE - offset) ? 17769556e118SZhi Wang I915_GTT_PAGE_SIZE - offset : end_gma - gma; 1777be1da707SZhi Wang 1778*e3d7640eSChristoph Hellwig intel_gvt_read_gpa(vgpu, gpa, va + len, copy_len); 1779be1da707SZhi Wang 1780be1da707SZhi Wang len += copy_len; 1781be1da707SZhi Wang gma += copy_len; 1782be1da707SZhi Wang } 178373dec95eSTvrtko Ursulin return len; 1784be1da707SZhi Wang } 1785be1da707SZhi Wang 1786be1da707SZhi Wang 1787be1da707SZhi Wang /* 1788be1da707SZhi Wang * Check whether a batch buffer needs to be scanned. Currently 1789be1da707SZhi Wang * the only criteria is based on privilege. 1790be1da707SZhi Wang */ 1791be1da707SZhi Wang static int batch_buffer_needs_scan(struct parser_exec_state *s) 1792be1da707SZhi Wang { 1793f093f182SColin Xu /* Decide privilege based on address space */ 17948fde4107SChris Wilson if (cmd_val(s, 0) & BIT(8) && 17958fde4107SChris Wilson !(s->vgpu->scan_nonprivbb & s->engine->mask)) 1796be1da707SZhi Wang return 0; 17978fde4107SChris Wilson 1798be1da707SZhi Wang return 1; 1799be1da707SZhi Wang } 1800be1da707SZhi Wang 18018fde4107SChris Wilson static const char *repr_addr_type(unsigned int type) 18028fde4107SChris Wilson { 18038fde4107SChris Wilson return type == PPGTT_BUFFER ? "ppgtt" : "ggtt"; 18048fde4107SChris Wilson } 18058fde4107SChris Wilson 1806220b65d8STina Zhang static int find_bb_size(struct parser_exec_state *s, 1807220b65d8STina Zhang unsigned long *bb_size, 1808220b65d8STina Zhang unsigned long *bb_end_cmd_offset) 1809be1da707SZhi Wang { 1810be1da707SZhi Wang unsigned long gma = 0; 1811b007065aSJani Nikula const struct cmd_info *info; 18122e679d48SJani Nikula u32 cmd_len = 0; 181358facf8cSZhi Wang bool bb_end = false; 1814695fbc08STina Zhang struct intel_vgpu *vgpu = s->vgpu; 1815be1da707SZhi Wang u32 cmd; 181696bebe39SZhao Yan struct intel_vgpu_mm *mm = (s->buf_addr_type == GTT_BUFFER) ? 181796bebe39SZhao Yan s->vgpu->gtt.ggtt_mm : s->workload->shadow_mm; 1818be1da707SZhi Wang 181958facf8cSZhi Wang *bb_size = 0; 1820220b65d8STina Zhang *bb_end_cmd_offset = 0; 182158facf8cSZhi Wang 1822be1da707SZhi Wang /* get the start gm address of the batch buffer */ 1823be1da707SZhi Wang gma = get_gma_bb_from_cmd(s, 1); 18245c56883aSfred gao if (gma == INTEL_GVT_INVALID_ADDR) 18255c56883aSfred gao return -EFAULT; 18265c56883aSfred gao 1827be1da707SZhi Wang cmd = cmd_val(s, 0); 18288fde4107SChris Wilson info = get_cmd_info(s->vgpu->gvt, cmd, s->engine); 1829be1da707SZhi Wang if (info == NULL) { 18308fde4107SChris Wilson gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %s, workload=%p\n", 18318fde4107SChris Wilson cmd, get_opcode(cmd, s->engine), 18328fde4107SChris Wilson repr_addr_type(s->buf_addr_type), 18338fde4107SChris Wilson s->engine->name, s->workload); 18345c56883aSfred gao return -EBADRQC; 1835be1da707SZhi Wang } 1836be1da707SZhi Wang do { 183796bebe39SZhao Yan if (copy_gma_to_hva(s->vgpu, mm, 18385c56883aSfred gao gma, gma + 4, &cmd) < 0) 18395c56883aSfred gao return -EFAULT; 18408fde4107SChris Wilson info = get_cmd_info(s->vgpu->gvt, cmd, s->engine); 1841be1da707SZhi Wang if (info == NULL) { 18428fde4107SChris Wilson gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %s, workload=%p\n", 18438fde4107SChris Wilson cmd, get_opcode(cmd, s->engine), 18448fde4107SChris Wilson repr_addr_type(s->buf_addr_type), 18458fde4107SChris Wilson s->engine->name, s->workload); 18465c56883aSfred gao return -EBADRQC; 1847be1da707SZhi Wang } 1848be1da707SZhi Wang 1849be1da707SZhi Wang if (info->opcode == OP_MI_BATCH_BUFFER_END) { 185058facf8cSZhi Wang bb_end = true; 1851be1da707SZhi Wang } else if (info->opcode == OP_MI_BATCH_BUFFER_START) { 185258facf8cSZhi Wang if (BATCH_BUFFER_2ND_LEVEL_BIT(cmd) == 0) 1853be1da707SZhi Wang /* chained batch buffer */ 185458facf8cSZhi Wang bb_end = true; 1855be1da707SZhi Wang } 1856220b65d8STina Zhang 1857220b65d8STina Zhang if (bb_end) 1858220b65d8STina Zhang *bb_end_cmd_offset = *bb_size; 1859220b65d8STina Zhang 1860be1da707SZhi Wang cmd_len = get_cmd_length(info, cmd) << 2; 186158facf8cSZhi Wang *bb_size += cmd_len; 1862be1da707SZhi Wang gma += cmd_len; 186358facf8cSZhi Wang } while (!bb_end); 1864be1da707SZhi Wang 186558facf8cSZhi Wang return 0; 1866be1da707SZhi Wang } 1867be1da707SZhi Wang 1868220b65d8STina Zhang static int audit_bb_end(struct parser_exec_state *s, void *va) 1869220b65d8STina Zhang { 1870220b65d8STina Zhang struct intel_vgpu *vgpu = s->vgpu; 1871220b65d8STina Zhang u32 cmd = *(u32 *)va; 1872220b65d8STina Zhang const struct cmd_info *info; 1873220b65d8STina Zhang 18748fde4107SChris Wilson info = get_cmd_info(s->vgpu->gvt, cmd, s->engine); 1875220b65d8STina Zhang if (info == NULL) { 18768fde4107SChris Wilson gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %s, workload=%p\n", 18778fde4107SChris Wilson cmd, get_opcode(cmd, s->engine), 18788fde4107SChris Wilson repr_addr_type(s->buf_addr_type), 18798fde4107SChris Wilson s->engine->name, s->workload); 1880220b65d8STina Zhang return -EBADRQC; 1881220b65d8STina Zhang } 1882220b65d8STina Zhang 1883220b65d8STina Zhang if ((info->opcode == OP_MI_BATCH_BUFFER_END) || 1884220b65d8STina Zhang ((info->opcode == OP_MI_BATCH_BUFFER_START) && 1885220b65d8STina Zhang (BATCH_BUFFER_2ND_LEVEL_BIT(cmd) == 0))) 1886220b65d8STina Zhang return 0; 1887220b65d8STina Zhang 1888220b65d8STina Zhang return -EBADRQC; 1889220b65d8STina Zhang } 1890220b65d8STina Zhang 1891be1da707SZhi Wang static int perform_bb_shadow(struct parser_exec_state *s) 1892be1da707SZhi Wang { 1893695fbc08STina Zhang struct intel_vgpu *vgpu = s->vgpu; 1894f52c380aSZhi Wang struct intel_vgpu_shadow_bb *bb; 1895be1da707SZhi Wang unsigned long gma = 0; 189658facf8cSZhi Wang unsigned long bb_size; 1897220b65d8STina Zhang unsigned long bb_end_cmd_offset; 1898be1da707SZhi Wang int ret = 0; 189996bebe39SZhao Yan struct intel_vgpu_mm *mm = (s->buf_addr_type == GTT_BUFFER) ? 190096bebe39SZhao Yan s->vgpu->gtt.ggtt_mm : s->workload->shadow_mm; 19018475355fSChris Wilson unsigned long start_offset = 0; 1902be1da707SZhi Wang 1903be1da707SZhi Wang /* get the start gm address of the batch buffer */ 1904be1da707SZhi Wang gma = get_gma_bb_from_cmd(s, 1); 19055c56883aSfred gao if (gma == INTEL_GVT_INVALID_ADDR) 19065c56883aSfred gao return -EFAULT; 1907be1da707SZhi Wang 1908220b65d8STina Zhang ret = find_bb_size(s, &bb_size, &bb_end_cmd_offset); 190958facf8cSZhi Wang if (ret) 191058facf8cSZhi Wang return ret; 1911be1da707SZhi Wang 1912f52c380aSZhi Wang bb = kzalloc(sizeof(*bb), GFP_KERNEL); 1913f52c380aSZhi Wang if (!bb) 1914be1da707SZhi Wang return -ENOMEM; 1915be1da707SZhi Wang 191696bebe39SZhao Yan bb->ppgtt = (s->buf_addr_type == GTT_BUFFER) ? false : true; 191796bebe39SZhao Yan 19188475355fSChris Wilson /* the start_offset stores the batch buffer's start gma's 191996bebe39SZhao Yan * offset relative to page boundary. so for non-privileged batch 192096bebe39SZhao Yan * buffer, the shadowed gem object holds exactly the same page 192196bebe39SZhao Yan * layout as original gem object. This is for the convience of 192296bebe39SZhao Yan * replacing the whole non-privilged batch buffer page to this 192396bebe39SZhao Yan * shadowed one in PPGTT at the same gma address. (this replacing 192496bebe39SZhao Yan * action is not implemented yet now, but may be necessary in 192596bebe39SZhao Yan * future). 192696bebe39SZhao Yan * for prileged batch buffer, we just change start gma address to 192796bebe39SZhao Yan * that of shadowed page. 192896bebe39SZhao Yan */ 192996bebe39SZhao Yan if (bb->ppgtt) 19308475355fSChris Wilson start_offset = gma & ~I915_GTT_PAGE_MASK; 193196bebe39SZhao Yan 19328fde4107SChris Wilson bb->obj = i915_gem_object_create_shmem(s->engine->i915, 19338475355fSChris Wilson round_up(bb_size + start_offset, 19348475355fSChris Wilson PAGE_SIZE)); 1935f52c380aSZhi Wang if (IS_ERR(bb->obj)) { 1936f52c380aSZhi Wang ret = PTR_ERR(bb->obj); 1937f52c380aSZhi Wang goto err_free_bb; 1938be1da707SZhi Wang } 1939be1da707SZhi Wang 1940f52c380aSZhi Wang bb->va = i915_gem_object_pin_map(bb->obj, I915_MAP_WB); 1941f52c380aSZhi Wang if (IS_ERR(bb->va)) { 1942f52c380aSZhi Wang ret = PTR_ERR(bb->va); 1943033ef711SChris Wilson goto err_free_obj; 1944f52c380aSZhi Wang } 1945be1da707SZhi Wang 194696bebe39SZhao Yan ret = copy_gma_to_hva(s->vgpu, mm, 1947a2861504SChris Wilson gma, gma + bb_size, 19488475355fSChris Wilson bb->va + start_offset); 19498bcad07aSZhenyu Wang if (ret < 0) { 1950695fbc08STina Zhang gvt_vgpu_err("fail to copy guest ring buffer\n"); 1951f52c380aSZhi Wang ret = -EFAULT; 1952f52c380aSZhi Wang goto err_unmap; 1953be1da707SZhi Wang } 1954be1da707SZhi Wang 1955220b65d8STina Zhang ret = audit_bb_end(s, bb->va + start_offset + bb_end_cmd_offset); 1956220b65d8STina Zhang if (ret) 1957220b65d8STina Zhang goto err_unmap; 1958220b65d8STina Zhang 19591af343cdSMaarten Lankhorst i915_gem_object_unlock(bb->obj); 1960f52c380aSZhi Wang INIT_LIST_HEAD(&bb->list); 1961f52c380aSZhi Wang list_add(&bb->list, &s->workload->shadow_bb); 1962f52c380aSZhi Wang 1963f52c380aSZhi Wang bb->bb_start_cmd_va = s->ip_va; 1964f52c380aSZhi Wang 1965ef75c685Sfred gao if ((s->buf_type == BATCH_BUFFER_INSTRUCTION) && (!s->is_ctx_wa)) 1966ef75c685Sfred gao bb->bb_offset = s->ip_va - s->rb_va; 1967ef75c685Sfred gao else 1968ef75c685Sfred gao bb->bb_offset = 0; 1969ef75c685Sfred gao 1970be1da707SZhi Wang /* 1971be1da707SZhi Wang * ip_va saves the virtual address of the shadow batch buffer, while 1972be1da707SZhi Wang * ip_gma saves the graphics address of the original batch buffer. 1973be1da707SZhi Wang * As the shadow batch buffer is just a copy from the originial one, 1974be1da707SZhi Wang * it should be right to use shadow batch buffer'va and original batch 1975be1da707SZhi Wang * buffer's gma in pair. After all, we don't want to pin the shadow 1976be1da707SZhi Wang * buffer here (too early). 1977be1da707SZhi Wang */ 19788475355fSChris Wilson s->ip_va = bb->va + start_offset; 1979be1da707SZhi Wang s->ip_gma = gma; 1980be1da707SZhi Wang return 0; 1981f52c380aSZhi Wang err_unmap: 1982f52c380aSZhi Wang i915_gem_object_unpin_map(bb->obj); 1983f52c380aSZhi Wang err_free_obj: 1984f52c380aSZhi Wang i915_gem_object_put(bb->obj); 1985f52c380aSZhi Wang err_free_bb: 1986f52c380aSZhi Wang kfree(bb); 1987be1da707SZhi Wang return ret; 1988be1da707SZhi Wang } 1989be1da707SZhi Wang 1990be1da707SZhi Wang static int cmd_handler_mi_batch_buffer_start(struct parser_exec_state *s) 1991be1da707SZhi Wang { 1992be1da707SZhi Wang bool second_level; 1993be1da707SZhi Wang int ret = 0; 1994695fbc08STina Zhang struct intel_vgpu *vgpu = s->vgpu; 1995be1da707SZhi Wang 1996be1da707SZhi Wang if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) { 1997695fbc08STina Zhang gvt_vgpu_err("Found MI_BATCH_BUFFER_START in 2nd level BB\n"); 19985c56883aSfred gao return -EFAULT; 1999be1da707SZhi Wang } 2000be1da707SZhi Wang 2001be1da707SZhi Wang second_level = BATCH_BUFFER_2ND_LEVEL_BIT(cmd_val(s, 0)) == 1; 2002be1da707SZhi Wang if (second_level && (s->buf_type != BATCH_BUFFER_INSTRUCTION)) { 2003695fbc08STina Zhang gvt_vgpu_err("Jumping to 2nd level BB from RB is not allowed\n"); 20045c56883aSfred gao return -EFAULT; 2005be1da707SZhi Wang } 2006be1da707SZhi Wang 2007be1da707SZhi Wang s->saved_buf_addr_type = s->buf_addr_type; 2008be1da707SZhi Wang addr_type_update_snb(s); 2009be1da707SZhi Wang if (s->buf_type == RING_BUFFER_INSTRUCTION) { 2010be1da707SZhi Wang s->ret_ip_gma_ring = s->ip_gma + cmd_length(s) * sizeof(u32); 2011be1da707SZhi Wang s->buf_type = BATCH_BUFFER_INSTRUCTION; 2012be1da707SZhi Wang } else if (second_level) { 2013be1da707SZhi Wang s->buf_type = BATCH_BUFFER_2ND_LEVEL; 2014be1da707SZhi Wang s->ret_ip_gma_bb = s->ip_gma + cmd_length(s) * sizeof(u32); 2015be1da707SZhi Wang s->ret_bb_va = s->ip_va + cmd_length(s) * sizeof(u32); 2016be1da707SZhi Wang } 2017be1da707SZhi Wang 2018be1da707SZhi Wang if (batch_buffer_needs_scan(s)) { 2019be1da707SZhi Wang ret = perform_bb_shadow(s); 2020be1da707SZhi Wang if (ret < 0) 2021695fbc08STina Zhang gvt_vgpu_err("invalid shadow batch buffer\n"); 2022be1da707SZhi Wang } else { 2023be1da707SZhi Wang /* emulate a batch buffer end to do return right */ 2024be1da707SZhi Wang ret = cmd_handler_mi_batch_buffer_end(s); 2025be1da707SZhi Wang if (ret < 0) 2026be1da707SZhi Wang return ret; 2027be1da707SZhi Wang } 2028be1da707SZhi Wang return ret; 2029be1da707SZhi Wang } 2030be1da707SZhi Wang 2031db47685dSZhao Yan static int mi_noop_index; 2032db47685dSZhao Yan 2033b007065aSJani Nikula static const struct cmd_info cmd_info[] = { 2034be1da707SZhi Wang {"MI_NOOP", OP_MI_NOOP, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL}, 2035be1da707SZhi Wang 2036be1da707SZhi Wang {"MI_SET_PREDICATE", OP_MI_SET_PREDICATE, F_LEN_CONST, R_ALL, D_ALL, 2037be1da707SZhi Wang 0, 1, NULL}, 2038be1da707SZhi Wang 2039be1da707SZhi Wang {"MI_USER_INTERRUPT", OP_MI_USER_INTERRUPT, F_LEN_CONST, R_ALL, D_ALL, 2040be1da707SZhi Wang 0, 1, cmd_handler_mi_user_interrupt}, 2041be1da707SZhi Wang 2042be1da707SZhi Wang {"MI_WAIT_FOR_EVENT", OP_MI_WAIT_FOR_EVENT, F_LEN_CONST, R_RCS | R_BCS, 2043be1da707SZhi Wang D_ALL, 0, 1, cmd_handler_mi_wait_for_event}, 2044be1da707SZhi Wang 2045be1da707SZhi Wang {"MI_FLUSH", OP_MI_FLUSH, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL}, 2046be1da707SZhi Wang 2047be1da707SZhi Wang {"MI_ARB_CHECK", OP_MI_ARB_CHECK, F_LEN_CONST, R_ALL, D_ALL, 0, 1, 2048be1da707SZhi Wang NULL}, 2049be1da707SZhi Wang 2050be1da707SZhi Wang {"MI_RS_CONTROL", OP_MI_RS_CONTROL, F_LEN_CONST, R_RCS, D_ALL, 0, 1, 2051be1da707SZhi Wang NULL}, 2052be1da707SZhi Wang 2053be1da707SZhi Wang {"MI_REPORT_HEAD", OP_MI_REPORT_HEAD, F_LEN_CONST, R_ALL, D_ALL, 0, 1, 2054be1da707SZhi Wang NULL}, 2055be1da707SZhi Wang 2056be1da707SZhi Wang {"MI_ARB_ON_OFF", OP_MI_ARB_ON_OFF, F_LEN_CONST, R_ALL, D_ALL, 0, 1, 2057be1da707SZhi Wang NULL}, 2058be1da707SZhi Wang 2059be1da707SZhi Wang {"MI_URB_ATOMIC_ALLOC", OP_MI_URB_ATOMIC_ALLOC, F_LEN_CONST, R_RCS, 2060be1da707SZhi Wang D_ALL, 0, 1, NULL}, 2061be1da707SZhi Wang 2062be1da707SZhi Wang {"MI_BATCH_BUFFER_END", OP_MI_BATCH_BUFFER_END, 2063be1da707SZhi Wang F_IP_ADVANCE_CUSTOM | F_LEN_CONST, R_ALL, D_ALL, 0, 1, 2064be1da707SZhi Wang cmd_handler_mi_batch_buffer_end}, 2065be1da707SZhi Wang 2066be1da707SZhi Wang {"MI_SUSPEND_FLUSH", OP_MI_SUSPEND_FLUSH, F_LEN_CONST, R_ALL, D_ALL, 2067be1da707SZhi Wang 0, 1, NULL}, 2068be1da707SZhi Wang 2069be1da707SZhi Wang {"MI_PREDICATE", OP_MI_PREDICATE, F_LEN_CONST, R_RCS, D_ALL, 0, 1, 2070be1da707SZhi Wang NULL}, 2071be1da707SZhi Wang 2072be1da707SZhi Wang {"MI_TOPOLOGY_FILTER", OP_MI_TOPOLOGY_FILTER, F_LEN_CONST, R_ALL, 2073be1da707SZhi Wang D_ALL, 0, 1, NULL}, 2074be1da707SZhi Wang 2075be1da707SZhi Wang {"MI_SET_APPID", OP_MI_SET_APPID, F_LEN_CONST, R_ALL, D_ALL, 0, 1, 2076be1da707SZhi Wang NULL}, 2077be1da707SZhi Wang 2078be1da707SZhi Wang {"MI_RS_CONTEXT", OP_MI_RS_CONTEXT, F_LEN_CONST, R_RCS, D_ALL, 0, 1, 2079be1da707SZhi Wang NULL}, 2080be1da707SZhi Wang 20814f870f1fSGao, Fred {"MI_DISPLAY_FLIP", OP_MI_DISPLAY_FLIP, F_LEN_VAR, 2082be1da707SZhi Wang R_RCS | R_BCS, D_ALL, 0, 8, cmd_handler_mi_display_flip}, 2083be1da707SZhi Wang 20841e2adc0dSGao, Fred {"MI_SEMAPHORE_MBOX", OP_MI_SEMAPHORE_MBOX, F_LEN_VAR | F_LEN_VAR_FIXED, 20851e2adc0dSGao, Fred R_ALL, D_ALL, 0, 8, NULL, CMD_LEN(1)}, 2086be1da707SZhi Wang 2087be1da707SZhi Wang {"MI_MATH", OP_MI_MATH, F_LEN_VAR, R_ALL, D_ALL, 0, 8, NULL}, 2088be1da707SZhi Wang 20891e2adc0dSGao, Fred {"MI_URB_CLEAR", OP_MI_URB_CLEAR, F_LEN_VAR | F_LEN_VAR_FIXED, R_RCS, 20901e2adc0dSGao, Fred D_ALL, 0, 8, NULL, CMD_LEN(0)}, 2091be1da707SZhi Wang 20921e2adc0dSGao, Fred {"MI_SEMAPHORE_SIGNAL", OP_MI_SEMAPHORE_SIGNAL, 20931e2adc0dSGao, Fred F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_BDW_PLUS, 0, 8, 20941e2adc0dSGao, Fred NULL, CMD_LEN(0)}, 2095be1da707SZhi Wang 20961e2adc0dSGao, Fred {"MI_SEMAPHORE_WAIT", OP_MI_SEMAPHORE_WAIT, 20971e2adc0dSGao, Fred F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_BDW_PLUS, ADDR_FIX_1(2), 20981e2adc0dSGao, Fred 8, cmd_handler_mi_semaphore_wait, CMD_LEN(2)}, 2099be1da707SZhi Wang 2100be1da707SZhi Wang {"MI_STORE_DATA_IMM", OP_MI_STORE_DATA_IMM, F_LEN_VAR, R_ALL, D_BDW_PLUS, 2101be1da707SZhi Wang ADDR_FIX_1(1), 10, cmd_handler_mi_store_data_imm}, 2102be1da707SZhi Wang 2103be1da707SZhi Wang {"MI_STORE_DATA_INDEX", OP_MI_STORE_DATA_INDEX, F_LEN_VAR, R_ALL, D_ALL, 2104be1da707SZhi Wang 0, 8, cmd_handler_mi_store_data_index}, 2105be1da707SZhi Wang 2106be1da707SZhi Wang {"MI_LOAD_REGISTER_IMM", OP_MI_LOAD_REGISTER_IMM, F_LEN_VAR, R_ALL, 2107be1da707SZhi Wang D_ALL, 0, 8, cmd_handler_lri}, 2108be1da707SZhi Wang 2109be1da707SZhi Wang {"MI_UPDATE_GTT", OP_MI_UPDATE_GTT, F_LEN_VAR, R_ALL, D_BDW_PLUS, 0, 10, 2110be1da707SZhi Wang cmd_handler_mi_update_gtt}, 2111be1da707SZhi Wang 21121e2adc0dSGao, Fred {"MI_STORE_REGISTER_MEM", OP_MI_STORE_REGISTER_MEM, 21131e2adc0dSGao, Fred F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(2), 8, 21141e2adc0dSGao, Fred cmd_handler_srm, CMD_LEN(2)}, 2115be1da707SZhi Wang 2116be1da707SZhi Wang {"MI_FLUSH_DW", OP_MI_FLUSH_DW, F_LEN_VAR, R_ALL, D_ALL, 0, 6, 2117be1da707SZhi Wang cmd_handler_mi_flush_dw}, 2118be1da707SZhi Wang 2119be1da707SZhi Wang {"MI_CLFLUSH", OP_MI_CLFLUSH, F_LEN_VAR, R_ALL, D_ALL, ADDR_FIX_1(1), 2120be1da707SZhi Wang 10, cmd_handler_mi_clflush}, 2121be1da707SZhi Wang 21221e2adc0dSGao, Fred {"MI_REPORT_PERF_COUNT", OP_MI_REPORT_PERF_COUNT, 21231e2adc0dSGao, Fred F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(1), 6, 21241e2adc0dSGao, Fred cmd_handler_mi_report_perf_count, CMD_LEN(2)}, 2125be1da707SZhi Wang 21261e2adc0dSGao, Fred {"MI_LOAD_REGISTER_MEM", OP_MI_LOAD_REGISTER_MEM, 21271e2adc0dSGao, Fred F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(2), 8, 21281e2adc0dSGao, Fred cmd_handler_lrm, CMD_LEN(2)}, 2129be1da707SZhi Wang 21301e2adc0dSGao, Fred {"MI_LOAD_REGISTER_REG", OP_MI_LOAD_REGISTER_REG, 21311e2adc0dSGao, Fred F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, 0, 8, 21321e2adc0dSGao, Fred cmd_handler_lrr, CMD_LEN(1)}, 2133be1da707SZhi Wang 21341e2adc0dSGao, Fred {"MI_RS_STORE_DATA_IMM", OP_MI_RS_STORE_DATA_IMM, 21351e2adc0dSGao, Fred F_LEN_VAR | F_LEN_VAR_FIXED, R_RCS, D_ALL, 0, 21361e2adc0dSGao, Fred 8, NULL, CMD_LEN(2)}, 2137be1da707SZhi Wang 21381e2adc0dSGao, Fred {"MI_LOAD_URB_MEM", OP_MI_LOAD_URB_MEM, F_LEN_VAR | F_LEN_VAR_FIXED, 21391e2adc0dSGao, Fred R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL, CMD_LEN(2)}, 2140be1da707SZhi Wang 2141be1da707SZhi Wang {"MI_STORE_URM_MEM", OP_MI_STORE_URM_MEM, F_LEN_VAR, R_RCS, D_ALL, 2142be1da707SZhi Wang ADDR_FIX_1(2), 8, NULL}, 2143be1da707SZhi Wang 21441e2adc0dSGao, Fred {"MI_OP_2E", OP_MI_2E, F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_BDW_PLUS, 21451e2adc0dSGao, Fred ADDR_FIX_2(1, 2), 8, cmd_handler_mi_op_2e, CMD_LEN(3)}, 2146be1da707SZhi Wang 2147be1da707SZhi Wang {"MI_OP_2F", OP_MI_2F, F_LEN_VAR, R_ALL, D_BDW_PLUS, ADDR_FIX_1(1), 2148be1da707SZhi Wang 8, cmd_handler_mi_op_2f}, 2149be1da707SZhi Wang 2150be1da707SZhi Wang {"MI_BATCH_BUFFER_START", OP_MI_BATCH_BUFFER_START, 2151be1da707SZhi Wang F_IP_ADVANCE_CUSTOM, R_ALL, D_ALL, 0, 8, 2152be1da707SZhi Wang cmd_handler_mi_batch_buffer_start}, 2153be1da707SZhi Wang 2154be1da707SZhi Wang {"MI_CONDITIONAL_BATCH_BUFFER_END", OP_MI_CONDITIONAL_BATCH_BUFFER_END, 21551e2adc0dSGao, Fred F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(2), 8, 21561e2adc0dSGao, Fred cmd_handler_mi_conditional_batch_buffer_end, CMD_LEN(2)}, 2157be1da707SZhi Wang 2158be1da707SZhi Wang {"MI_LOAD_SCAN_LINES_INCL", OP_MI_LOAD_SCAN_LINES_INCL, F_LEN_CONST, 2159be1da707SZhi Wang R_RCS | R_BCS, D_ALL, 0, 2, NULL}, 2160be1da707SZhi Wang 2161be1da707SZhi Wang {"XY_SETUP_BLT", OP_XY_SETUP_BLT, F_LEN_VAR, R_BCS, D_ALL, 2162be1da707SZhi Wang ADDR_FIX_2(4, 7), 8, NULL}, 2163be1da707SZhi Wang 2164be1da707SZhi Wang {"XY_SETUP_CLIP_BLT", OP_XY_SETUP_CLIP_BLT, F_LEN_VAR, R_BCS, D_ALL, 2165be1da707SZhi Wang 0, 8, NULL}, 2166be1da707SZhi Wang 2167be1da707SZhi Wang {"XY_SETUP_MONO_PATTERN_SL_BLT", OP_XY_SETUP_MONO_PATTERN_SL_BLT, 2168be1da707SZhi Wang F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL}, 2169be1da707SZhi Wang 2170be1da707SZhi Wang {"XY_PIXEL_BLT", OP_XY_PIXEL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL}, 2171be1da707SZhi Wang 2172be1da707SZhi Wang {"XY_SCANLINES_BLT", OP_XY_SCANLINES_BLT, F_LEN_VAR, R_BCS, D_ALL, 2173be1da707SZhi Wang 0, 8, NULL}, 2174be1da707SZhi Wang 2175be1da707SZhi Wang {"XY_TEXT_BLT", OP_XY_TEXT_BLT, F_LEN_VAR, R_BCS, D_ALL, 2176be1da707SZhi Wang ADDR_FIX_1(3), 8, NULL}, 2177be1da707SZhi Wang 2178be1da707SZhi Wang {"XY_TEXT_IMMEDIATE_BLT", OP_XY_TEXT_IMMEDIATE_BLT, F_LEN_VAR, R_BCS, 2179be1da707SZhi Wang D_ALL, 0, 8, NULL}, 2180be1da707SZhi Wang 2181be1da707SZhi Wang {"XY_COLOR_BLT", OP_XY_COLOR_BLT, F_LEN_VAR, R_BCS, D_ALL, 2182be1da707SZhi Wang ADDR_FIX_1(4), 8, NULL}, 2183be1da707SZhi Wang 2184be1da707SZhi Wang {"XY_PAT_BLT", OP_XY_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL, 2185be1da707SZhi Wang ADDR_FIX_2(4, 5), 8, NULL}, 2186be1da707SZhi Wang 2187be1da707SZhi Wang {"XY_MONO_PAT_BLT", OP_XY_MONO_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL, 2188be1da707SZhi Wang ADDR_FIX_1(4), 8, NULL}, 2189be1da707SZhi Wang 2190be1da707SZhi Wang {"XY_SRC_COPY_BLT", OP_XY_SRC_COPY_BLT, F_LEN_VAR, R_BCS, D_ALL, 2191be1da707SZhi Wang ADDR_FIX_2(4, 7), 8, NULL}, 2192be1da707SZhi Wang 2193be1da707SZhi Wang {"XY_MONO_SRC_COPY_BLT", OP_XY_MONO_SRC_COPY_BLT, F_LEN_VAR, R_BCS, 2194be1da707SZhi Wang D_ALL, ADDR_FIX_2(4, 5), 8, NULL}, 2195be1da707SZhi Wang 2196be1da707SZhi Wang {"XY_FULL_BLT", OP_XY_FULL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL}, 2197be1da707SZhi Wang 2198be1da707SZhi Wang {"XY_FULL_MONO_SRC_BLT", OP_XY_FULL_MONO_SRC_BLT, F_LEN_VAR, R_BCS, 2199be1da707SZhi Wang D_ALL, ADDR_FIX_3(4, 5, 8), 8, NULL}, 2200be1da707SZhi Wang 2201be1da707SZhi Wang {"XY_FULL_MONO_PATTERN_BLT", OP_XY_FULL_MONO_PATTERN_BLT, F_LEN_VAR, 2202be1da707SZhi Wang R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL}, 2203be1da707SZhi Wang 2204be1da707SZhi Wang {"XY_FULL_MONO_PATTERN_MONO_SRC_BLT", 2205be1da707SZhi Wang OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT, 2206be1da707SZhi Wang F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL}, 2207be1da707SZhi Wang 2208be1da707SZhi Wang {"XY_MONO_PAT_FIXED_BLT", OP_XY_MONO_PAT_FIXED_BLT, F_LEN_VAR, R_BCS, 2209be1da707SZhi Wang D_ALL, ADDR_FIX_1(4), 8, NULL}, 2210be1da707SZhi Wang 2211be1da707SZhi Wang {"XY_MONO_SRC_COPY_IMMEDIATE_BLT", OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT, 2212be1da707SZhi Wang F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL}, 2213be1da707SZhi Wang 2214be1da707SZhi Wang {"XY_PAT_BLT_IMMEDIATE", OP_XY_PAT_BLT_IMMEDIATE, F_LEN_VAR, R_BCS, 2215be1da707SZhi Wang D_ALL, ADDR_FIX_1(4), 8, NULL}, 2216be1da707SZhi Wang 2217be1da707SZhi Wang {"XY_SRC_COPY_CHROMA_BLT", OP_XY_SRC_COPY_CHROMA_BLT, F_LEN_VAR, R_BCS, 2218be1da707SZhi Wang D_ALL, ADDR_FIX_2(4, 7), 8, NULL}, 2219be1da707SZhi Wang 2220be1da707SZhi Wang {"XY_FULL_IMMEDIATE_PATTERN_BLT", OP_XY_FULL_IMMEDIATE_PATTERN_BLT, 2221be1da707SZhi Wang F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL}, 2222be1da707SZhi Wang 2223be1da707SZhi Wang {"XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT", 2224be1da707SZhi Wang OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT, 2225be1da707SZhi Wang F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL}, 2226be1da707SZhi Wang 2227be1da707SZhi Wang {"XY_PAT_CHROMA_BLT", OP_XY_PAT_CHROMA_BLT, F_LEN_VAR, R_BCS, D_ALL, 2228be1da707SZhi Wang ADDR_FIX_2(4, 5), 8, NULL}, 2229be1da707SZhi Wang 2230be1da707SZhi Wang {"XY_PAT_CHROMA_BLT_IMMEDIATE", OP_XY_PAT_CHROMA_BLT_IMMEDIATE, 2231be1da707SZhi Wang F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL}, 2232be1da707SZhi Wang 2233be1da707SZhi Wang {"3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP", 2234be1da707SZhi Wang OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP, 2235be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2236be1da707SZhi Wang 2237be1da707SZhi Wang {"3DSTATE_VIEWPORT_STATE_POINTERS_CC", 2238be1da707SZhi Wang OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC, 2239be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2240be1da707SZhi Wang 2241be1da707SZhi Wang {"3DSTATE_BLEND_STATE_POINTERS", 2242be1da707SZhi Wang OP_3DSTATE_BLEND_STATE_POINTERS, 2243be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2244be1da707SZhi Wang 2245be1da707SZhi Wang {"3DSTATE_DEPTH_STENCIL_STATE_POINTERS", 2246be1da707SZhi Wang OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS, 2247be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2248be1da707SZhi Wang 2249be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_POINTERS_VS", 2250be1da707SZhi Wang OP_3DSTATE_BINDING_TABLE_POINTERS_VS, 2251be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2252be1da707SZhi Wang 2253be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_POINTERS_HS", 2254be1da707SZhi Wang OP_3DSTATE_BINDING_TABLE_POINTERS_HS, 2255be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2256be1da707SZhi Wang 2257be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_POINTERS_DS", 2258be1da707SZhi Wang OP_3DSTATE_BINDING_TABLE_POINTERS_DS, 2259be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2260be1da707SZhi Wang 2261be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_POINTERS_GS", 2262be1da707SZhi Wang OP_3DSTATE_BINDING_TABLE_POINTERS_GS, 2263be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2264be1da707SZhi Wang 2265be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_POINTERS_PS", 2266be1da707SZhi Wang OP_3DSTATE_BINDING_TABLE_POINTERS_PS, 2267be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2268be1da707SZhi Wang 2269be1da707SZhi Wang {"3DSTATE_SAMPLER_STATE_POINTERS_VS", 2270be1da707SZhi Wang OP_3DSTATE_SAMPLER_STATE_POINTERS_VS, 2271be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2272be1da707SZhi Wang 2273be1da707SZhi Wang {"3DSTATE_SAMPLER_STATE_POINTERS_HS", 2274be1da707SZhi Wang OP_3DSTATE_SAMPLER_STATE_POINTERS_HS, 2275be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2276be1da707SZhi Wang 2277be1da707SZhi Wang {"3DSTATE_SAMPLER_STATE_POINTERS_DS", 2278be1da707SZhi Wang OP_3DSTATE_SAMPLER_STATE_POINTERS_DS, 2279be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2280be1da707SZhi Wang 2281be1da707SZhi Wang {"3DSTATE_SAMPLER_STATE_POINTERS_GS", 2282be1da707SZhi Wang OP_3DSTATE_SAMPLER_STATE_POINTERS_GS, 2283be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2284be1da707SZhi Wang 2285be1da707SZhi Wang {"3DSTATE_SAMPLER_STATE_POINTERS_PS", 2286be1da707SZhi Wang OP_3DSTATE_SAMPLER_STATE_POINTERS_PS, 2287be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2288be1da707SZhi Wang 2289be1da707SZhi Wang {"3DSTATE_URB_VS", OP_3DSTATE_URB_VS, F_LEN_VAR, R_RCS, D_ALL, 2290be1da707SZhi Wang 0, 8, NULL}, 2291be1da707SZhi Wang 2292be1da707SZhi Wang {"3DSTATE_URB_HS", OP_3DSTATE_URB_HS, F_LEN_VAR, R_RCS, D_ALL, 2293be1da707SZhi Wang 0, 8, NULL}, 2294be1da707SZhi Wang 2295be1da707SZhi Wang {"3DSTATE_URB_DS", OP_3DSTATE_URB_DS, F_LEN_VAR, R_RCS, D_ALL, 2296be1da707SZhi Wang 0, 8, NULL}, 2297be1da707SZhi Wang 2298be1da707SZhi Wang {"3DSTATE_URB_GS", OP_3DSTATE_URB_GS, F_LEN_VAR, R_RCS, D_ALL, 2299be1da707SZhi Wang 0, 8, NULL}, 2300be1da707SZhi Wang 2301be1da707SZhi Wang {"3DSTATE_GATHER_CONSTANT_VS", OP_3DSTATE_GATHER_CONSTANT_VS, 2302be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2303be1da707SZhi Wang 2304be1da707SZhi Wang {"3DSTATE_GATHER_CONSTANT_GS", OP_3DSTATE_GATHER_CONSTANT_GS, 2305be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2306be1da707SZhi Wang 2307be1da707SZhi Wang {"3DSTATE_GATHER_CONSTANT_HS", OP_3DSTATE_GATHER_CONSTANT_HS, 2308be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2309be1da707SZhi Wang 2310be1da707SZhi Wang {"3DSTATE_GATHER_CONSTANT_DS", OP_3DSTATE_GATHER_CONSTANT_DS, 2311be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2312be1da707SZhi Wang 2313be1da707SZhi Wang {"3DSTATE_GATHER_CONSTANT_PS", OP_3DSTATE_GATHER_CONSTANT_PS, 2314be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2315be1da707SZhi Wang 2316be1da707SZhi Wang {"3DSTATE_DX9_CONSTANTF_VS", OP_3DSTATE_DX9_CONSTANTF_VS, 2317be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL}, 2318be1da707SZhi Wang 2319be1da707SZhi Wang {"3DSTATE_DX9_CONSTANTF_PS", OP_3DSTATE_DX9_CONSTANTF_PS, 2320be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL}, 2321be1da707SZhi Wang 2322be1da707SZhi Wang {"3DSTATE_DX9_CONSTANTI_VS", OP_3DSTATE_DX9_CONSTANTI_VS, 2323be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2324be1da707SZhi Wang 2325be1da707SZhi Wang {"3DSTATE_DX9_CONSTANTI_PS", OP_3DSTATE_DX9_CONSTANTI_PS, 2326be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2327be1da707SZhi Wang 2328be1da707SZhi Wang {"3DSTATE_DX9_CONSTANTB_VS", OP_3DSTATE_DX9_CONSTANTB_VS, 2329be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2330be1da707SZhi Wang 2331be1da707SZhi Wang {"3DSTATE_DX9_CONSTANTB_PS", OP_3DSTATE_DX9_CONSTANTB_PS, 2332be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2333be1da707SZhi Wang 2334be1da707SZhi Wang {"3DSTATE_DX9_LOCAL_VALID_VS", OP_3DSTATE_DX9_LOCAL_VALID_VS, 2335be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2336be1da707SZhi Wang 2337be1da707SZhi Wang {"3DSTATE_DX9_LOCAL_VALID_PS", OP_3DSTATE_DX9_LOCAL_VALID_PS, 2338be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2339be1da707SZhi Wang 2340be1da707SZhi Wang {"3DSTATE_DX9_GENERATE_ACTIVE_VS", OP_3DSTATE_DX9_GENERATE_ACTIVE_VS, 2341be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2342be1da707SZhi Wang 2343be1da707SZhi Wang {"3DSTATE_DX9_GENERATE_ACTIVE_PS", OP_3DSTATE_DX9_GENERATE_ACTIVE_PS, 2344be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2345be1da707SZhi Wang 2346be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_EDIT_VS", OP_3DSTATE_BINDING_TABLE_EDIT_VS, 2347be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL}, 2348be1da707SZhi Wang 2349be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_EDIT_GS", OP_3DSTATE_BINDING_TABLE_EDIT_GS, 2350be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL}, 2351be1da707SZhi Wang 2352be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_EDIT_HS", OP_3DSTATE_BINDING_TABLE_EDIT_HS, 2353be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL}, 2354be1da707SZhi Wang 2355be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_EDIT_DS", OP_3DSTATE_BINDING_TABLE_EDIT_DS, 2356be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL}, 2357be1da707SZhi Wang 2358be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_EDIT_PS", OP_3DSTATE_BINDING_TABLE_EDIT_PS, 2359be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL}, 2360be1da707SZhi Wang 2361be1da707SZhi Wang {"3DSTATE_VF_INSTANCING", OP_3DSTATE_VF_INSTANCING, F_LEN_VAR, R_RCS, 2362be1da707SZhi Wang D_BDW_PLUS, 0, 8, NULL}, 2363be1da707SZhi Wang 2364be1da707SZhi Wang {"3DSTATE_VF_SGVS", OP_3DSTATE_VF_SGVS, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8, 2365be1da707SZhi Wang NULL}, 2366be1da707SZhi Wang 2367be1da707SZhi Wang {"3DSTATE_VF_TOPOLOGY", OP_3DSTATE_VF_TOPOLOGY, F_LEN_VAR, R_RCS, 2368be1da707SZhi Wang D_BDW_PLUS, 0, 8, NULL}, 2369be1da707SZhi Wang 2370be1da707SZhi Wang {"3DSTATE_WM_CHROMAKEY", OP_3DSTATE_WM_CHROMAKEY, F_LEN_VAR, R_RCS, 2371be1da707SZhi Wang D_BDW_PLUS, 0, 8, NULL}, 2372be1da707SZhi Wang 2373be1da707SZhi Wang {"3DSTATE_PS_BLEND", OP_3DSTATE_PS_BLEND, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 2374be1da707SZhi Wang 8, NULL}, 2375be1da707SZhi Wang 2376be1da707SZhi Wang {"3DSTATE_WM_DEPTH_STENCIL", OP_3DSTATE_WM_DEPTH_STENCIL, F_LEN_VAR, 2377be1da707SZhi Wang R_RCS, D_BDW_PLUS, 0, 8, NULL}, 2378be1da707SZhi Wang 2379be1da707SZhi Wang {"3DSTATE_PS_EXTRA", OP_3DSTATE_PS_EXTRA, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 2380be1da707SZhi Wang 8, NULL}, 2381be1da707SZhi Wang 2382be1da707SZhi Wang {"3DSTATE_RASTER", OP_3DSTATE_RASTER, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8, 2383be1da707SZhi Wang NULL}, 2384be1da707SZhi Wang 2385be1da707SZhi Wang {"3DSTATE_SBE_SWIZ", OP_3DSTATE_SBE_SWIZ, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8, 2386be1da707SZhi Wang NULL}, 2387be1da707SZhi Wang 2388be1da707SZhi Wang {"3DSTATE_WM_HZ_OP", OP_3DSTATE_WM_HZ_OP, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8, 2389be1da707SZhi Wang NULL}, 2390be1da707SZhi Wang 2391be1da707SZhi Wang {"3DSTATE_VERTEX_BUFFERS", OP_3DSTATE_VERTEX_BUFFERS, F_LEN_VAR, R_RCS, 2392be1da707SZhi Wang D_BDW_PLUS, 0, 8, NULL}, 2393be1da707SZhi Wang 2394be1da707SZhi Wang {"3DSTATE_VERTEX_ELEMENTS", OP_3DSTATE_VERTEX_ELEMENTS, F_LEN_VAR, 2395be1da707SZhi Wang R_RCS, D_ALL, 0, 8, NULL}, 2396be1da707SZhi Wang 2397be1da707SZhi Wang {"3DSTATE_INDEX_BUFFER", OP_3DSTATE_INDEX_BUFFER, F_LEN_VAR, R_RCS, 2398be1da707SZhi Wang D_BDW_PLUS, ADDR_FIX_1(2), 8, NULL}, 2399be1da707SZhi Wang 2400be1da707SZhi Wang {"3DSTATE_VF_STATISTICS", OP_3DSTATE_VF_STATISTICS, F_LEN_CONST, 2401be1da707SZhi Wang R_RCS, D_ALL, 0, 1, NULL}, 2402be1da707SZhi Wang 2403be1da707SZhi Wang {"3DSTATE_VF", OP_3DSTATE_VF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2404be1da707SZhi Wang 2405be1da707SZhi Wang {"3DSTATE_CC_STATE_POINTERS", OP_3DSTATE_CC_STATE_POINTERS, F_LEN_VAR, 2406be1da707SZhi Wang R_RCS, D_ALL, 0, 8, NULL}, 2407be1da707SZhi Wang 2408be1da707SZhi Wang {"3DSTATE_SCISSOR_STATE_POINTERS", OP_3DSTATE_SCISSOR_STATE_POINTERS, 2409be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2410be1da707SZhi Wang 2411be1da707SZhi Wang {"3DSTATE_GS", OP_3DSTATE_GS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2412be1da707SZhi Wang 2413be1da707SZhi Wang {"3DSTATE_CLIP", OP_3DSTATE_CLIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2414be1da707SZhi Wang 2415be1da707SZhi Wang {"3DSTATE_WM", OP_3DSTATE_WM, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2416be1da707SZhi Wang 2417be1da707SZhi Wang {"3DSTATE_CONSTANT_GS", OP_3DSTATE_CONSTANT_GS, F_LEN_VAR, R_RCS, 2418be1da707SZhi Wang D_BDW_PLUS, 0, 8, NULL}, 2419be1da707SZhi Wang 2420be1da707SZhi Wang {"3DSTATE_CONSTANT_PS", OP_3DSTATE_CONSTANT_PS, F_LEN_VAR, R_RCS, 2421be1da707SZhi Wang D_BDW_PLUS, 0, 8, NULL}, 2422be1da707SZhi Wang 2423be1da707SZhi Wang {"3DSTATE_SAMPLE_MASK", OP_3DSTATE_SAMPLE_MASK, F_LEN_VAR, R_RCS, 2424be1da707SZhi Wang D_ALL, 0, 8, NULL}, 2425be1da707SZhi Wang 2426be1da707SZhi Wang {"3DSTATE_CONSTANT_HS", OP_3DSTATE_CONSTANT_HS, F_LEN_VAR, R_RCS, 2427be1da707SZhi Wang D_BDW_PLUS, 0, 8, NULL}, 2428be1da707SZhi Wang 2429be1da707SZhi Wang {"3DSTATE_CONSTANT_DS", OP_3DSTATE_CONSTANT_DS, F_LEN_VAR, R_RCS, 2430be1da707SZhi Wang D_BDW_PLUS, 0, 8, NULL}, 2431be1da707SZhi Wang 2432be1da707SZhi Wang {"3DSTATE_HS", OP_3DSTATE_HS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2433be1da707SZhi Wang 2434be1da707SZhi Wang {"3DSTATE_TE", OP_3DSTATE_TE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2435be1da707SZhi Wang 2436be1da707SZhi Wang {"3DSTATE_DS", OP_3DSTATE_DS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2437be1da707SZhi Wang 2438be1da707SZhi Wang {"3DSTATE_STREAMOUT", OP_3DSTATE_STREAMOUT, F_LEN_VAR, R_RCS, 2439be1da707SZhi Wang D_ALL, 0, 8, NULL}, 2440be1da707SZhi Wang 2441be1da707SZhi Wang {"3DSTATE_SBE", OP_3DSTATE_SBE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2442be1da707SZhi Wang 2443be1da707SZhi Wang {"3DSTATE_PS", OP_3DSTATE_PS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2444be1da707SZhi Wang 2445be1da707SZhi Wang {"3DSTATE_DRAWING_RECTANGLE", OP_3DSTATE_DRAWING_RECTANGLE, F_LEN_VAR, 2446be1da707SZhi Wang R_RCS, D_ALL, 0, 8, NULL}, 2447be1da707SZhi Wang 2448be1da707SZhi Wang {"3DSTATE_SAMPLER_PALETTE_LOAD0", OP_3DSTATE_SAMPLER_PALETTE_LOAD0, 2449be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2450be1da707SZhi Wang 2451be1da707SZhi Wang {"3DSTATE_CHROMA_KEY", OP_3DSTATE_CHROMA_KEY, F_LEN_VAR, R_RCS, D_ALL, 2452be1da707SZhi Wang 0, 8, NULL}, 2453be1da707SZhi Wang 2454be1da707SZhi Wang {"3DSTATE_DEPTH_BUFFER", OP_3DSTATE_DEPTH_BUFFER, F_LEN_VAR, R_RCS, 2455be1da707SZhi Wang D_ALL, ADDR_FIX_1(2), 8, NULL}, 2456be1da707SZhi Wang 2457be1da707SZhi Wang {"3DSTATE_POLY_STIPPLE_OFFSET", OP_3DSTATE_POLY_STIPPLE_OFFSET, 2458be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2459be1da707SZhi Wang 2460be1da707SZhi Wang {"3DSTATE_POLY_STIPPLE_PATTERN", OP_3DSTATE_POLY_STIPPLE_PATTERN, 2461be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2462be1da707SZhi Wang 2463be1da707SZhi Wang {"3DSTATE_LINE_STIPPLE", OP_3DSTATE_LINE_STIPPLE, F_LEN_VAR, R_RCS, 2464be1da707SZhi Wang D_ALL, 0, 8, NULL}, 2465be1da707SZhi Wang 2466be1da707SZhi Wang {"3DSTATE_AA_LINE_PARAMS", OP_3DSTATE_AA_LINE_PARAMS, F_LEN_VAR, R_RCS, 2467be1da707SZhi Wang D_ALL, 0, 8, NULL}, 2468be1da707SZhi Wang 2469be1da707SZhi Wang {"3DSTATE_GS_SVB_INDEX", OP_3DSTATE_GS_SVB_INDEX, F_LEN_VAR, R_RCS, 2470be1da707SZhi Wang D_ALL, 0, 8, NULL}, 2471be1da707SZhi Wang 2472be1da707SZhi Wang {"3DSTATE_SAMPLER_PALETTE_LOAD1", OP_3DSTATE_SAMPLER_PALETTE_LOAD1, 2473be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2474be1da707SZhi Wang 2475be1da707SZhi Wang {"3DSTATE_MULTISAMPLE", OP_3DSTATE_MULTISAMPLE_BDW, F_LEN_VAR, R_RCS, 2476be1da707SZhi Wang D_BDW_PLUS, 0, 8, NULL}, 2477be1da707SZhi Wang 2478be1da707SZhi Wang {"3DSTATE_STENCIL_BUFFER", OP_3DSTATE_STENCIL_BUFFER, F_LEN_VAR, R_RCS, 2479be1da707SZhi Wang D_ALL, ADDR_FIX_1(2), 8, NULL}, 2480be1da707SZhi Wang 2481be1da707SZhi Wang {"3DSTATE_HIER_DEPTH_BUFFER", OP_3DSTATE_HIER_DEPTH_BUFFER, F_LEN_VAR, 2482be1da707SZhi Wang R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL}, 2483be1da707SZhi Wang 2484be1da707SZhi Wang {"3DSTATE_CLEAR_PARAMS", OP_3DSTATE_CLEAR_PARAMS, F_LEN_VAR, 2485be1da707SZhi Wang R_RCS, D_ALL, 0, 8, NULL}, 2486be1da707SZhi Wang 2487be1da707SZhi Wang {"3DSTATE_PUSH_CONSTANT_ALLOC_VS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS, 2488be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2489be1da707SZhi Wang 2490be1da707SZhi Wang {"3DSTATE_PUSH_CONSTANT_ALLOC_HS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS, 2491be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2492be1da707SZhi Wang 2493be1da707SZhi Wang {"3DSTATE_PUSH_CONSTANT_ALLOC_DS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS, 2494be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2495be1da707SZhi Wang 2496be1da707SZhi Wang {"3DSTATE_PUSH_CONSTANT_ALLOC_GS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS, 2497be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2498be1da707SZhi Wang 2499be1da707SZhi Wang {"3DSTATE_PUSH_CONSTANT_ALLOC_PS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS, 2500be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2501be1da707SZhi Wang 2502be1da707SZhi Wang {"3DSTATE_MONOFILTER_SIZE", OP_3DSTATE_MONOFILTER_SIZE, F_LEN_VAR, 2503be1da707SZhi Wang R_RCS, D_ALL, 0, 8, NULL}, 2504be1da707SZhi Wang 2505be1da707SZhi Wang {"3DSTATE_SO_DECL_LIST", OP_3DSTATE_SO_DECL_LIST, F_LEN_VAR, R_RCS, 2506be1da707SZhi Wang D_ALL, 0, 9, NULL}, 2507be1da707SZhi Wang 2508be1da707SZhi Wang {"3DSTATE_SO_BUFFER", OP_3DSTATE_SO_BUFFER, F_LEN_VAR, R_RCS, D_BDW_PLUS, 2509be1da707SZhi Wang ADDR_FIX_2(2, 4), 8, NULL}, 2510be1da707SZhi Wang 2511be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_POOL_ALLOC", 2512be1da707SZhi Wang OP_3DSTATE_BINDING_TABLE_POOL_ALLOC, 2513be1da707SZhi Wang F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL}, 2514be1da707SZhi Wang 2515be1da707SZhi Wang {"3DSTATE_GATHER_POOL_ALLOC", OP_3DSTATE_GATHER_POOL_ALLOC, 2516be1da707SZhi Wang F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL}, 2517be1da707SZhi Wang 2518be1da707SZhi Wang {"3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC", 2519be1da707SZhi Wang OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC, 2520be1da707SZhi Wang F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL}, 2521be1da707SZhi Wang 2522be1da707SZhi Wang {"3DSTATE_SAMPLE_PATTERN", OP_3DSTATE_SAMPLE_PATTERN, F_LEN_VAR, R_RCS, 2523be1da707SZhi Wang D_BDW_PLUS, 0, 8, NULL}, 2524be1da707SZhi Wang 2525be1da707SZhi Wang {"PIPE_CONTROL", OP_PIPE_CONTROL, F_LEN_VAR, R_RCS, D_ALL, 2526be1da707SZhi Wang ADDR_FIX_1(2), 8, cmd_handler_pipe_control}, 2527be1da707SZhi Wang 2528be1da707SZhi Wang {"3DPRIMITIVE", OP_3DPRIMITIVE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2529be1da707SZhi Wang 2530be1da707SZhi Wang {"PIPELINE_SELECT", OP_PIPELINE_SELECT, F_LEN_CONST, R_RCS, D_ALL, 0, 2531be1da707SZhi Wang 1, NULL}, 2532be1da707SZhi Wang 2533be1da707SZhi Wang {"STATE_PREFETCH", OP_STATE_PREFETCH, F_LEN_VAR, R_RCS, D_ALL, 2534be1da707SZhi Wang ADDR_FIX_1(1), 8, NULL}, 2535be1da707SZhi Wang 2536be1da707SZhi Wang {"STATE_SIP", OP_STATE_SIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2537be1da707SZhi Wang 2538be1da707SZhi Wang {"STATE_BASE_ADDRESS", OP_STATE_BASE_ADDRESS, F_LEN_VAR, R_RCS, D_BDW_PLUS, 2539be1da707SZhi Wang ADDR_FIX_5(1, 3, 4, 5, 6), 8, NULL}, 2540be1da707SZhi Wang 2541be1da707SZhi Wang {"OP_3D_MEDIA_0_1_4", OP_3D_MEDIA_0_1_4, F_LEN_VAR, R_RCS, D_ALL, 2542be1da707SZhi Wang ADDR_FIX_1(1), 8, NULL}, 2543be1da707SZhi Wang 25442484b172SYan Zhao {"OP_SWTESS_BASE_ADDRESS", OP_SWTESS_BASE_ADDRESS, 25452484b172SYan Zhao F_LEN_VAR, R_RCS, D_ALL, ADDR_FIX_2(1, 2), 3, NULL}, 25462484b172SYan Zhao 2547be1da707SZhi Wang {"3DSTATE_VS", OP_3DSTATE_VS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2548be1da707SZhi Wang 2549be1da707SZhi Wang {"3DSTATE_SF", OP_3DSTATE_SF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2550be1da707SZhi Wang 2551be1da707SZhi Wang {"3DSTATE_CONSTANT_VS", OP_3DSTATE_CONSTANT_VS, F_LEN_VAR, R_RCS, D_BDW_PLUS, 2552be1da707SZhi Wang 0, 8, NULL}, 2553be1da707SZhi Wang 2554be1da707SZhi Wang {"3DSTATE_COMPONENT_PACKING", OP_3DSTATE_COMPONENT_PACKING, F_LEN_VAR, R_RCS, 2555be1da707SZhi Wang D_SKL_PLUS, 0, 8, NULL}, 2556be1da707SZhi Wang 2557be1da707SZhi Wang {"MEDIA_INTERFACE_DESCRIPTOR_LOAD", OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD, 2558be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL}, 2559be1da707SZhi Wang 2560be1da707SZhi Wang {"MEDIA_GATEWAY_STATE", OP_MEDIA_GATEWAY_STATE, F_LEN_VAR, R_RCS, D_ALL, 2561be1da707SZhi Wang 0, 16, NULL}, 2562be1da707SZhi Wang 2563be1da707SZhi Wang {"MEDIA_STATE_FLUSH", OP_MEDIA_STATE_FLUSH, F_LEN_VAR, R_RCS, D_ALL, 2564be1da707SZhi Wang 0, 16, NULL}, 2565be1da707SZhi Wang 256602b966c1SColin Xu {"MEDIA_POOL_STATE", OP_MEDIA_POOL_STATE, F_LEN_VAR, R_RCS, D_ALL, 256702b966c1SColin Xu 0, 16, NULL}, 256802b966c1SColin Xu 2569be1da707SZhi Wang {"MEDIA_OBJECT", OP_MEDIA_OBJECT, F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL}, 2570be1da707SZhi Wang 2571be1da707SZhi Wang {"MEDIA_CURBE_LOAD", OP_MEDIA_CURBE_LOAD, F_LEN_VAR, R_RCS, D_ALL, 2572be1da707SZhi Wang 0, 16, NULL}, 2573be1da707SZhi Wang 2574be1da707SZhi Wang {"MEDIA_OBJECT_PRT", OP_MEDIA_OBJECT_PRT, F_LEN_VAR, R_RCS, D_ALL, 2575be1da707SZhi Wang 0, 16, NULL}, 2576be1da707SZhi Wang 2577be1da707SZhi Wang {"MEDIA_OBJECT_WALKER", OP_MEDIA_OBJECT_WALKER, F_LEN_VAR, R_RCS, D_ALL, 2578be1da707SZhi Wang 0, 16, NULL}, 2579be1da707SZhi Wang 2580be1da707SZhi Wang {"GPGPU_WALKER", OP_GPGPU_WALKER, F_LEN_VAR, R_RCS, D_ALL, 2581be1da707SZhi Wang 0, 8, NULL}, 2582be1da707SZhi Wang 2583be1da707SZhi Wang {"MEDIA_VFE_STATE", OP_MEDIA_VFE_STATE, F_LEN_VAR, R_RCS, D_ALL, 0, 16, 2584be1da707SZhi Wang NULL}, 2585be1da707SZhi Wang 2586be1da707SZhi Wang {"3DSTATE_VF_STATISTICS_GM45", OP_3DSTATE_VF_STATISTICS_GM45, 2587be1da707SZhi Wang F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL}, 2588be1da707SZhi Wang 2589be1da707SZhi Wang {"MFX_PIPE_MODE_SELECT", OP_MFX_PIPE_MODE_SELECT, F_LEN_VAR, 2590be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2591be1da707SZhi Wang 2592be1da707SZhi Wang {"MFX_SURFACE_STATE", OP_MFX_SURFACE_STATE, F_LEN_VAR, 2593be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2594be1da707SZhi Wang 2595be1da707SZhi Wang {"MFX_PIPE_BUF_ADDR_STATE", OP_MFX_PIPE_BUF_ADDR_STATE, F_LEN_VAR, 2596be1da707SZhi Wang R_VCS, D_BDW_PLUS, 0, 12, NULL}, 2597be1da707SZhi Wang 2598be1da707SZhi Wang {"MFX_IND_OBJ_BASE_ADDR_STATE", OP_MFX_IND_OBJ_BASE_ADDR_STATE, 2599be1da707SZhi Wang F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL}, 2600be1da707SZhi Wang 2601be1da707SZhi Wang {"MFX_BSP_BUF_BASE_ADDR_STATE", OP_MFX_BSP_BUF_BASE_ADDR_STATE, 2602be1da707SZhi Wang F_LEN_VAR, R_VCS, D_BDW_PLUS, ADDR_FIX_3(1, 3, 5), 12, NULL}, 2603be1da707SZhi Wang 2604be1da707SZhi Wang {"OP_2_0_0_5", OP_2_0_0_5, F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL}, 2605be1da707SZhi Wang 2606be1da707SZhi Wang {"MFX_STATE_POINTER", OP_MFX_STATE_POINTER, F_LEN_VAR, 2607be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2608be1da707SZhi Wang 2609be1da707SZhi Wang {"MFX_QM_STATE", OP_MFX_QM_STATE, F_LEN_VAR, 2610be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2611be1da707SZhi Wang 2612be1da707SZhi Wang {"MFX_FQM_STATE", OP_MFX_FQM_STATE, F_LEN_VAR, 2613be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2614be1da707SZhi Wang 2615be1da707SZhi Wang {"MFX_PAK_INSERT_OBJECT", OP_MFX_PAK_INSERT_OBJECT, F_LEN_VAR, 2616be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2617be1da707SZhi Wang 2618be1da707SZhi Wang {"MFX_STITCH_OBJECT", OP_MFX_STITCH_OBJECT, F_LEN_VAR, 2619be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2620be1da707SZhi Wang 2621be1da707SZhi Wang {"MFD_IT_OBJECT", OP_MFD_IT_OBJECT, F_LEN_VAR, 2622be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2623be1da707SZhi Wang 2624be1da707SZhi Wang {"MFX_WAIT", OP_MFX_WAIT, F_LEN_VAR, 2625be1da707SZhi Wang R_VCS, D_ALL, 0, 6, NULL}, 2626be1da707SZhi Wang 2627be1da707SZhi Wang {"MFX_AVC_IMG_STATE", OP_MFX_AVC_IMG_STATE, F_LEN_VAR, 2628be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2629be1da707SZhi Wang 2630be1da707SZhi Wang {"MFX_AVC_QM_STATE", OP_MFX_AVC_QM_STATE, F_LEN_VAR, 2631be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2632be1da707SZhi Wang 2633be1da707SZhi Wang {"MFX_AVC_DIRECTMODE_STATE", OP_MFX_AVC_DIRECTMODE_STATE, F_LEN_VAR, 2634be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2635be1da707SZhi Wang 2636be1da707SZhi Wang {"MFX_AVC_SLICE_STATE", OP_MFX_AVC_SLICE_STATE, F_LEN_VAR, 2637be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2638be1da707SZhi Wang 2639be1da707SZhi Wang {"MFX_AVC_REF_IDX_STATE", OP_MFX_AVC_REF_IDX_STATE, F_LEN_VAR, 2640be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2641be1da707SZhi Wang 2642be1da707SZhi Wang {"MFX_AVC_WEIGHTOFFSET_STATE", OP_MFX_AVC_WEIGHTOFFSET_STATE, F_LEN_VAR, 2643be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2644be1da707SZhi Wang 2645be1da707SZhi Wang {"MFD_AVC_PICID_STATE", OP_MFD_AVC_PICID_STATE, F_LEN_VAR, 2646be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2647be1da707SZhi Wang {"MFD_AVC_DPB_STATE", OP_MFD_AVC_DPB_STATE, F_LEN_VAR, 2648be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2649be1da707SZhi Wang 2650be1da707SZhi Wang {"MFD_AVC_BSD_OBJECT", OP_MFD_AVC_BSD_OBJECT, F_LEN_VAR, 2651be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2652be1da707SZhi Wang 2653be1da707SZhi Wang {"MFD_AVC_SLICEADDR", OP_MFD_AVC_SLICEADDR, F_LEN_VAR, 2654be1da707SZhi Wang R_VCS, D_ALL, ADDR_FIX_1(2), 12, NULL}, 2655be1da707SZhi Wang 2656be1da707SZhi Wang {"MFC_AVC_PAK_OBJECT", OP_MFC_AVC_PAK_OBJECT, F_LEN_VAR, 2657be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2658be1da707SZhi Wang 2659be1da707SZhi Wang {"MFX_VC1_PRED_PIPE_STATE", OP_MFX_VC1_PRED_PIPE_STATE, F_LEN_VAR, 2660be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2661be1da707SZhi Wang 2662be1da707SZhi Wang {"MFX_VC1_DIRECTMODE_STATE", OP_MFX_VC1_DIRECTMODE_STATE, F_LEN_VAR, 2663be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2664be1da707SZhi Wang 2665be1da707SZhi Wang {"MFD_VC1_SHORT_PIC_STATE", OP_MFD_VC1_SHORT_PIC_STATE, F_LEN_VAR, 2666be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2667be1da707SZhi Wang 2668be1da707SZhi Wang {"MFD_VC1_LONG_PIC_STATE", OP_MFD_VC1_LONG_PIC_STATE, F_LEN_VAR, 2669be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2670be1da707SZhi Wang 2671be1da707SZhi Wang {"MFD_VC1_BSD_OBJECT", OP_MFD_VC1_BSD_OBJECT, F_LEN_VAR, 2672be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2673be1da707SZhi Wang 2674be1da707SZhi Wang {"MFC_MPEG2_SLICEGROUP_STATE", OP_MFC_MPEG2_SLICEGROUP_STATE, F_LEN_VAR, 2675be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2676be1da707SZhi Wang 2677be1da707SZhi Wang {"MFC_MPEG2_PAK_OBJECT", OP_MFC_MPEG2_PAK_OBJECT, F_LEN_VAR, 2678be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2679be1da707SZhi Wang 2680be1da707SZhi Wang {"MFX_MPEG2_PIC_STATE", OP_MFX_MPEG2_PIC_STATE, F_LEN_VAR, 2681be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2682be1da707SZhi Wang 2683be1da707SZhi Wang {"MFX_MPEG2_QM_STATE", OP_MFX_MPEG2_QM_STATE, F_LEN_VAR, 2684be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2685be1da707SZhi Wang 2686be1da707SZhi Wang {"MFD_MPEG2_BSD_OBJECT", OP_MFD_MPEG2_BSD_OBJECT, F_LEN_VAR, 2687be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2688be1da707SZhi Wang 2689be1da707SZhi Wang {"MFX_2_6_0_0", OP_MFX_2_6_0_0, F_LEN_VAR, R_VCS, D_ALL, 2690be1da707SZhi Wang 0, 16, NULL}, 2691be1da707SZhi Wang 2692be1da707SZhi Wang {"MFX_2_6_0_9", OP_MFX_2_6_0_9, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL}, 2693be1da707SZhi Wang 2694be1da707SZhi Wang {"MFX_2_6_0_8", OP_MFX_2_6_0_8, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL}, 2695be1da707SZhi Wang 2696be1da707SZhi Wang {"MFX_JPEG_PIC_STATE", OP_MFX_JPEG_PIC_STATE, F_LEN_VAR, 2697be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2698be1da707SZhi Wang 2699be1da707SZhi Wang {"MFX_JPEG_HUFF_TABLE_STATE", OP_MFX_JPEG_HUFF_TABLE_STATE, F_LEN_VAR, 2700be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2701be1da707SZhi Wang 2702be1da707SZhi Wang {"MFD_JPEG_BSD_OBJECT", OP_MFD_JPEG_BSD_OBJECT, F_LEN_VAR, 2703be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2704be1da707SZhi Wang 2705be1da707SZhi Wang {"VEBOX_STATE", OP_VEB_STATE, F_LEN_VAR, R_VECS, D_ALL, 0, 12, NULL}, 2706be1da707SZhi Wang 2707be1da707SZhi Wang {"VEBOX_SURFACE_STATE", OP_VEB_SURFACE_STATE, F_LEN_VAR, R_VECS, D_ALL, 2708be1da707SZhi Wang 0, 12, NULL}, 2709be1da707SZhi Wang 2710be1da707SZhi Wang {"VEB_DI_IECP", OP_VEB_DNDI_IECP_STATE, F_LEN_VAR, R_VECS, D_BDW_PLUS, 27113035e8cdSGao, Fred 0, 12, NULL}, 2712be1da707SZhi Wang }; 2713be1da707SZhi Wang 2714be1da707SZhi Wang static void add_cmd_entry(struct intel_gvt *gvt, struct cmd_entry *e) 2715be1da707SZhi Wang { 2716be1da707SZhi Wang hash_add(gvt->cmd_table, &e->hlist, e->info->opcode); 2717be1da707SZhi Wang } 2718be1da707SZhi Wang 2719be1da707SZhi Wang /* call the cmd handler, and advance ip */ 2720be1da707SZhi Wang static int cmd_parser_exec(struct parser_exec_state *s) 2721be1da707SZhi Wang { 2722ffc19776SChangbin Du struct intel_vgpu *vgpu = s->vgpu; 2723b007065aSJani Nikula const struct cmd_info *info; 2724be1da707SZhi Wang u32 cmd; 2725be1da707SZhi Wang int ret = 0; 2726be1da707SZhi Wang 2727be1da707SZhi Wang cmd = cmd_val(s, 0); 2728be1da707SZhi Wang 2729db47685dSZhao Yan /* fastpath for MI_NOOP */ 2730db47685dSZhao Yan if (cmd == MI_NOOP) 2731db47685dSZhao Yan info = &cmd_info[mi_noop_index]; 2732db47685dSZhao Yan else 27338fde4107SChris Wilson info = get_cmd_info(s->vgpu->gvt, cmd, s->engine); 2734db47685dSZhao Yan 2735be1da707SZhi Wang if (info == NULL) { 27368fde4107SChris Wilson gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %s, workload=%p\n", 27378fde4107SChris Wilson cmd, get_opcode(cmd, s->engine), 27388fde4107SChris Wilson repr_addr_type(s->buf_addr_type), 27398fde4107SChris Wilson s->engine->name, s->workload); 27405c56883aSfred gao return -EBADRQC; 2741be1da707SZhi Wang } 2742be1da707SZhi Wang 2743be1da707SZhi Wang s->info = info; 2744be1da707SZhi Wang 27458fde4107SChris Wilson trace_gvt_command(vgpu->id, s->engine->id, s->ip_gma, s->ip_va, 274696bebe39SZhao Yan cmd_length(s), s->buf_type, s->buf_addr_type, 274796bebe39SZhao Yan s->workload, info->name); 2748be1da707SZhi Wang 27491e2adc0dSGao, Fred if ((info->flag & F_LEN_MASK) == F_LEN_VAR_FIXED) { 27501e2adc0dSGao, Fred ret = gvt_check_valid_cmd_length(cmd_length(s), 27511e2adc0dSGao, Fred info->valid_len); 27521e2adc0dSGao, Fred if (ret) 27531e2adc0dSGao, Fred return ret; 27541e2adc0dSGao, Fred } 27551e2adc0dSGao, Fred 2756be1da707SZhi Wang if (info->handler) { 2757be1da707SZhi Wang ret = info->handler(s); 2758be1da707SZhi Wang if (ret < 0) { 2759695fbc08STina Zhang gvt_vgpu_err("%s handler error\n", info->name); 2760be1da707SZhi Wang return ret; 2761be1da707SZhi Wang } 2762be1da707SZhi Wang } 2763be1da707SZhi Wang 2764be1da707SZhi Wang if (!(info->flag & F_IP_ADVANCE_CUSTOM)) { 2765be1da707SZhi Wang ret = cmd_advance_default(s); 2766be1da707SZhi Wang if (ret) { 2767695fbc08STina Zhang gvt_vgpu_err("%s IP advance error\n", info->name); 2768be1da707SZhi Wang return ret; 2769be1da707SZhi Wang } 2770be1da707SZhi Wang } 2771be1da707SZhi Wang return 0; 2772be1da707SZhi Wang } 2773be1da707SZhi Wang 2774be1da707SZhi Wang static inline bool gma_out_of_range(unsigned long gma, 2775be1da707SZhi Wang unsigned long gma_head, unsigned int gma_tail) 2776be1da707SZhi Wang { 2777be1da707SZhi Wang if (gma_tail >= gma_head) 2778be1da707SZhi Wang return (gma < gma_head) || (gma > gma_tail); 2779be1da707SZhi Wang else 2780be1da707SZhi Wang return (gma > gma_tail) && (gma < gma_head); 2781be1da707SZhi Wang } 2782be1da707SZhi Wang 27835c56883aSfred gao /* Keep the consistent return type, e.g EBADRQC for unknown 27845c56883aSfred gao * cmd, EFAULT for invalid address, EPERM for nonpriv. later 27855c56883aSfred gao * works as the input of VM healthy status. 27865c56883aSfred gao */ 2787be1da707SZhi Wang static int command_scan(struct parser_exec_state *s, 2788be1da707SZhi Wang unsigned long rb_head, unsigned long rb_tail, 2789be1da707SZhi Wang unsigned long rb_start, unsigned long rb_len) 2790be1da707SZhi Wang { 2791be1da707SZhi Wang 2792be1da707SZhi Wang unsigned long gma_head, gma_tail, gma_bottom; 2793be1da707SZhi Wang int ret = 0; 2794695fbc08STina Zhang struct intel_vgpu *vgpu = s->vgpu; 2795be1da707SZhi Wang 2796be1da707SZhi Wang gma_head = rb_start + rb_head; 2797be1da707SZhi Wang gma_tail = rb_start + rb_tail; 2798be1da707SZhi Wang gma_bottom = rb_start + rb_len; 2799be1da707SZhi Wang 2800be1da707SZhi Wang while (s->ip_gma != gma_tail) { 2801493f30cdSYan Zhao if (s->buf_type == RING_BUFFER_INSTRUCTION || 2802493f30cdSYan Zhao s->buf_type == RING_BUFFER_CTX) { 2803be1da707SZhi Wang if (!(s->ip_gma >= rb_start) || 2804be1da707SZhi Wang !(s->ip_gma < gma_bottom)) { 2805695fbc08STina Zhang gvt_vgpu_err("ip_gma %lx out of ring scope." 2806be1da707SZhi Wang "(base:0x%lx, bottom: 0x%lx)\n", 2807be1da707SZhi Wang s->ip_gma, rb_start, 2808be1da707SZhi Wang gma_bottom); 2809be1da707SZhi Wang parser_exec_state_dump(s); 28105c56883aSfred gao return -EFAULT; 2811be1da707SZhi Wang } 2812be1da707SZhi Wang if (gma_out_of_range(s->ip_gma, gma_head, gma_tail)) { 2813695fbc08STina Zhang gvt_vgpu_err("ip_gma %lx out of range." 2814be1da707SZhi Wang "base 0x%lx head 0x%lx tail 0x%lx\n", 2815be1da707SZhi Wang s->ip_gma, rb_start, 2816be1da707SZhi Wang rb_head, rb_tail); 2817be1da707SZhi Wang parser_exec_state_dump(s); 2818be1da707SZhi Wang break; 2819be1da707SZhi Wang } 2820be1da707SZhi Wang } 2821be1da707SZhi Wang ret = cmd_parser_exec(s); 2822be1da707SZhi Wang if (ret) { 2823695fbc08STina Zhang gvt_vgpu_err("cmd parser error\n"); 2824be1da707SZhi Wang parser_exec_state_dump(s); 2825be1da707SZhi Wang break; 2826be1da707SZhi Wang } 2827be1da707SZhi Wang } 2828be1da707SZhi Wang 2829be1da707SZhi Wang return ret; 2830be1da707SZhi Wang } 2831be1da707SZhi Wang 2832be1da707SZhi Wang static int scan_workload(struct intel_vgpu_workload *workload) 2833be1da707SZhi Wang { 2834be1da707SZhi Wang unsigned long gma_head, gma_tail, gma_bottom; 2835be1da707SZhi Wang struct parser_exec_state s; 2836be1da707SZhi Wang int ret = 0; 2837be1da707SZhi Wang 2838be1da707SZhi Wang /* ring base is page aligned */ 28399556e118SZhi Wang if (WARN_ON(!IS_ALIGNED(workload->rb_start, I915_GTT_PAGE_SIZE))) 2840be1da707SZhi Wang return -EINVAL; 2841be1da707SZhi Wang 2842be1da707SZhi Wang gma_head = workload->rb_start + workload->rb_head; 2843be1da707SZhi Wang gma_tail = workload->rb_start + workload->rb_tail; 2844be1da707SZhi Wang gma_bottom = workload->rb_start + _RING_CTL_BUF_SIZE(workload->rb_ctl); 2845be1da707SZhi Wang 2846be1da707SZhi Wang s.buf_type = RING_BUFFER_INSTRUCTION; 2847be1da707SZhi Wang s.buf_addr_type = GTT_BUFFER; 2848be1da707SZhi Wang s.vgpu = workload->vgpu; 28498fde4107SChris Wilson s.engine = workload->engine; 2850be1da707SZhi Wang s.ring_start = workload->rb_start; 2851be1da707SZhi Wang s.ring_size = _RING_CTL_BUF_SIZE(workload->rb_ctl); 2852be1da707SZhi Wang s.ring_head = gma_head; 2853be1da707SZhi Wang s.ring_tail = gma_tail; 2854be1da707SZhi Wang s.rb_va = workload->shadow_ring_buffer_va; 2855be1da707SZhi Wang s.workload = workload; 2856ef75c685Sfred gao s.is_ctx_wa = false; 2857be1da707SZhi Wang 28588fde4107SChris Wilson if (bypass_scan_mask & workload->engine->mask || gma_head == gma_tail) 2859be1da707SZhi Wang return 0; 2860be1da707SZhi Wang 2861be1da707SZhi Wang ret = ip_gma_set(&s, gma_head); 2862be1da707SZhi Wang if (ret) 2863be1da707SZhi Wang goto out; 2864be1da707SZhi Wang 2865be1da707SZhi Wang ret = command_scan(&s, workload->rb_head, workload->rb_tail, 2866be1da707SZhi Wang workload->rb_start, _RING_CTL_BUF_SIZE(workload->rb_ctl)); 2867be1da707SZhi Wang 2868be1da707SZhi Wang out: 2869be1da707SZhi Wang return ret; 2870be1da707SZhi Wang } 2871be1da707SZhi Wang 2872be1da707SZhi Wang static int scan_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx) 2873be1da707SZhi Wang { 2874be1da707SZhi Wang 2875be1da707SZhi Wang unsigned long gma_head, gma_tail, gma_bottom, ring_size, ring_tail; 2876be1da707SZhi Wang struct parser_exec_state s; 2877be1da707SZhi Wang int ret = 0; 2878c10c1255STina Zhang struct intel_vgpu_workload *workload = container_of(wa_ctx, 2879c10c1255STina Zhang struct intel_vgpu_workload, 2880c10c1255STina Zhang wa_ctx); 2881be1da707SZhi Wang 2882be1da707SZhi Wang /* ring base is page aligned */ 28839556e118SZhi Wang if (WARN_ON(!IS_ALIGNED(wa_ctx->indirect_ctx.guest_gma, 28849556e118SZhi Wang I915_GTT_PAGE_SIZE))) 2885be1da707SZhi Wang return -EINVAL; 2886be1da707SZhi Wang 28872e679d48SJani Nikula ring_tail = wa_ctx->indirect_ctx.size + 3 * sizeof(u32); 2888be1da707SZhi Wang ring_size = round_up(wa_ctx->indirect_ctx.size + CACHELINE_BYTES, 2889be1da707SZhi Wang PAGE_SIZE); 2890be1da707SZhi Wang gma_head = wa_ctx->indirect_ctx.guest_gma; 2891be1da707SZhi Wang gma_tail = wa_ctx->indirect_ctx.guest_gma + ring_tail; 2892be1da707SZhi Wang gma_bottom = wa_ctx->indirect_ctx.guest_gma + ring_size; 2893be1da707SZhi Wang 2894be1da707SZhi Wang s.buf_type = RING_BUFFER_INSTRUCTION; 2895be1da707SZhi Wang s.buf_addr_type = GTT_BUFFER; 2896c10c1255STina Zhang s.vgpu = workload->vgpu; 28978fde4107SChris Wilson s.engine = workload->engine; 2898be1da707SZhi Wang s.ring_start = wa_ctx->indirect_ctx.guest_gma; 2899be1da707SZhi Wang s.ring_size = ring_size; 2900be1da707SZhi Wang s.ring_head = gma_head; 2901be1da707SZhi Wang s.ring_tail = gma_tail; 2902be1da707SZhi Wang s.rb_va = wa_ctx->indirect_ctx.shadow_va; 2903c10c1255STina Zhang s.workload = workload; 2904ef75c685Sfred gao s.is_ctx_wa = true; 2905be1da707SZhi Wang 2906be1da707SZhi Wang ret = ip_gma_set(&s, gma_head); 2907be1da707SZhi Wang if (ret) 2908be1da707SZhi Wang goto out; 2909be1da707SZhi Wang 2910be1da707SZhi Wang ret = command_scan(&s, 0, ring_tail, 2911be1da707SZhi Wang wa_ctx->indirect_ctx.guest_gma, ring_size); 2912be1da707SZhi Wang out: 2913be1da707SZhi Wang return ret; 2914be1da707SZhi Wang } 2915be1da707SZhi Wang 2916be1da707SZhi Wang static int shadow_workload_ring_buffer(struct intel_vgpu_workload *workload) 2917be1da707SZhi Wang { 2918be1da707SZhi Wang struct intel_vgpu *vgpu = workload->vgpu; 2919325eb94aSZhi Wang struct intel_vgpu_submission *s = &vgpu->submission; 2920be1da707SZhi Wang unsigned long gma_head, gma_tail, gma_top, guest_rb_size; 29210a53bc07Sfred gao void *shadow_ring_buffer_va; 2922be1da707SZhi Wang int ret; 2923be1da707SZhi Wang 2924be1da707SZhi Wang guest_rb_size = _RING_CTL_BUF_SIZE(workload->rb_ctl); 2925be1da707SZhi Wang 2926be1da707SZhi Wang /* calculate workload ring buffer size */ 2927be1da707SZhi Wang workload->rb_len = (workload->rb_tail + guest_rb_size - 2928be1da707SZhi Wang workload->rb_head) % guest_rb_size; 2929be1da707SZhi Wang 2930be1da707SZhi Wang gma_head = workload->rb_start + workload->rb_head; 2931be1da707SZhi Wang gma_tail = workload->rb_start + workload->rb_tail; 2932be1da707SZhi Wang gma_top = workload->rb_start + guest_rb_size; 2933be1da707SZhi Wang 29348fde4107SChris Wilson if (workload->rb_len > s->ring_scan_buffer_size[workload->engine->id]) { 29358cf80a2eSZhi Wang void *p; 2936bf4097eaSZhi Wang 29370a53bc07Sfred gao /* realloc the new ring buffer if needed */ 29388fde4107SChris Wilson p = krealloc(s->ring_scan_buffer[workload->engine->id], 29398fde4107SChris Wilson workload->rb_len, GFP_KERNEL); 2940bf4097eaSZhi Wang if (!p) { 29418cf80a2eSZhi Wang gvt_vgpu_err("fail to re-alloc ring scan buffer\n"); 29420a53bc07Sfred gao return -ENOMEM; 29430a53bc07Sfred gao } 29448fde4107SChris Wilson s->ring_scan_buffer[workload->engine->id] = p; 29458fde4107SChris Wilson s->ring_scan_buffer_size[workload->engine->id] = workload->rb_len; 29460a53bc07Sfred gao } 29470a53bc07Sfred gao 29488fde4107SChris Wilson shadow_ring_buffer_va = s->ring_scan_buffer[workload->engine->id]; 2949be1da707SZhi Wang 2950be1da707SZhi Wang /* get shadow ring buffer va */ 29510a53bc07Sfred gao workload->shadow_ring_buffer_va = shadow_ring_buffer_va; 2952be1da707SZhi Wang 2953be1da707SZhi Wang /* head > tail --> copy head <-> top */ 2954be1da707SZhi Wang if (gma_head > gma_tail) { 2955be1da707SZhi Wang ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm, 29560a53bc07Sfred gao gma_head, gma_top, shadow_ring_buffer_va); 29578bcad07aSZhenyu Wang if (ret < 0) { 2958695fbc08STina Zhang gvt_vgpu_err("fail to copy guest ring buffer\n"); 2959be1da707SZhi Wang return ret; 2960be1da707SZhi Wang } 29610a53bc07Sfred gao shadow_ring_buffer_va += ret; 2962be1da707SZhi Wang gma_head = workload->rb_start; 2963be1da707SZhi Wang } 2964be1da707SZhi Wang 2965be1da707SZhi Wang /* copy head or start <-> tail */ 29660a53bc07Sfred gao ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm, gma_head, gma_tail, 29670a53bc07Sfred gao shadow_ring_buffer_va); 29688bcad07aSZhenyu Wang if (ret < 0) { 2969695fbc08STina Zhang gvt_vgpu_err("fail to copy guest ring buffer\n"); 2970be1da707SZhi Wang return ret; 2971be1da707SZhi Wang } 2972be1da707SZhi Wang return 0; 2973be1da707SZhi Wang } 2974be1da707SZhi Wang 297589ea20b9SPing Gao int intel_gvt_scan_and_shadow_ringbuffer(struct intel_vgpu_workload *workload) 2976be1da707SZhi Wang { 2977be1da707SZhi Wang int ret; 2978695fbc08STina Zhang struct intel_vgpu *vgpu = workload->vgpu; 2979be1da707SZhi Wang 2980be1da707SZhi Wang ret = shadow_workload_ring_buffer(workload); 2981be1da707SZhi Wang if (ret) { 2982695fbc08STina Zhang gvt_vgpu_err("fail to shadow workload ring_buffer\n"); 2983be1da707SZhi Wang return ret; 2984be1da707SZhi Wang } 2985be1da707SZhi Wang 2986be1da707SZhi Wang ret = scan_workload(workload); 2987be1da707SZhi Wang if (ret) { 2988695fbc08STina Zhang gvt_vgpu_err("scan workload error\n"); 2989be1da707SZhi Wang return ret; 2990be1da707SZhi Wang } 2991be1da707SZhi Wang return 0; 2992be1da707SZhi Wang } 2993be1da707SZhi Wang 2994be1da707SZhi Wang static int shadow_indirect_ctx(struct intel_shadow_wa_ctx *wa_ctx) 2995be1da707SZhi Wang { 2996be1da707SZhi Wang int ctx_size = wa_ctx->indirect_ctx.size; 2997be1da707SZhi Wang unsigned long guest_gma = wa_ctx->indirect_ctx.guest_gma; 2998c10c1255STina Zhang struct intel_vgpu_workload *workload = container_of(wa_ctx, 2999c10c1255STina Zhang struct intel_vgpu_workload, 3000c10c1255STina Zhang wa_ctx); 3001c10c1255STina Zhang struct intel_vgpu *vgpu = workload->vgpu; 3002894cf7d1SChris Wilson struct drm_i915_gem_object *obj; 3003be1da707SZhi Wang int ret = 0; 3004bcd0aedeSChris Wilson void *map; 3005be1da707SZhi Wang 30068fde4107SChris Wilson obj = i915_gem_object_create_shmem(workload->engine->i915, 3007894cf7d1SChris Wilson roundup(ctx_size + CACHELINE_BYTES, 3008894cf7d1SChris Wilson PAGE_SIZE)); 3009894cf7d1SChris Wilson if (IS_ERR(obj)) 3010894cf7d1SChris Wilson return PTR_ERR(obj); 3011be1da707SZhi Wang 3012be1da707SZhi Wang /* get the va of the shadow batch buffer */ 3013bcd0aedeSChris Wilson map = i915_gem_object_pin_map(obj, I915_MAP_WB); 3014bcd0aedeSChris Wilson if (IS_ERR(map)) { 3015695fbc08STina Zhang gvt_vgpu_err("failed to vmap shadow indirect ctx\n"); 3016bcd0aedeSChris Wilson ret = PTR_ERR(map); 3017bcd0aedeSChris Wilson goto put_obj; 3018be1da707SZhi Wang } 3019be1da707SZhi Wang 302080f0b679SMaarten Lankhorst i915_gem_object_lock(obj, NULL); 3021894cf7d1SChris Wilson ret = i915_gem_object_set_to_cpu_domain(obj, false); 30226951e589SChris Wilson i915_gem_object_unlock(obj); 3023be1da707SZhi Wang if (ret) { 3024695fbc08STina Zhang gvt_vgpu_err("failed to set shadow indirect ctx to CPU\n"); 3025be1da707SZhi Wang goto unmap_src; 3026be1da707SZhi Wang } 3027be1da707SZhi Wang 3028c10c1255STina Zhang ret = copy_gma_to_hva(workload->vgpu, 3029c10c1255STina Zhang workload->vgpu->gtt.ggtt_mm, 3030bcd0aedeSChris Wilson guest_gma, guest_gma + ctx_size, 3031bcd0aedeSChris Wilson map); 30328bcad07aSZhenyu Wang if (ret < 0) { 3033695fbc08STina Zhang gvt_vgpu_err("fail to copy guest indirect ctx\n"); 3034894cf7d1SChris Wilson goto unmap_src; 3035be1da707SZhi Wang } 3036be1da707SZhi Wang 3037894cf7d1SChris Wilson wa_ctx->indirect_ctx.obj = obj; 3038bcd0aedeSChris Wilson wa_ctx->indirect_ctx.shadow_va = map; 3039be1da707SZhi Wang return 0; 3040be1da707SZhi Wang 3041be1da707SZhi Wang unmap_src: 3042bcd0aedeSChris Wilson i915_gem_object_unpin_map(obj); 3043894cf7d1SChris Wilson put_obj: 3044ffeaf9aaSfred gao i915_gem_object_put(obj); 3045be1da707SZhi Wang return ret; 3046be1da707SZhi Wang } 3047be1da707SZhi Wang 3048be1da707SZhi Wang static int combine_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx) 3049be1da707SZhi Wang { 30502e679d48SJani Nikula u32 per_ctx_start[CACHELINE_DWORDS] = {0}; 3051be1da707SZhi Wang unsigned char *bb_start_sva; 3052be1da707SZhi Wang 30538f63fc2bSZhenyu Wang if (!wa_ctx->per_ctx.valid) 30548f63fc2bSZhenyu Wang return 0; 30558f63fc2bSZhenyu Wang 3056be1da707SZhi Wang per_ctx_start[0] = 0x18800001; 3057be1da707SZhi Wang per_ctx_start[1] = wa_ctx->per_ctx.guest_gma; 3058be1da707SZhi Wang 3059be1da707SZhi Wang bb_start_sva = (unsigned char *)wa_ctx->indirect_ctx.shadow_va + 3060be1da707SZhi Wang wa_ctx->indirect_ctx.size; 3061be1da707SZhi Wang 3062be1da707SZhi Wang memcpy(bb_start_sva, per_ctx_start, CACHELINE_BYTES); 3063be1da707SZhi Wang 3064be1da707SZhi Wang return 0; 3065be1da707SZhi Wang } 3066be1da707SZhi Wang 3067be1da707SZhi Wang int intel_gvt_scan_and_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx) 3068be1da707SZhi Wang { 3069be1da707SZhi Wang int ret; 3070c10c1255STina Zhang struct intel_vgpu_workload *workload = container_of(wa_ctx, 3071c10c1255STina Zhang struct intel_vgpu_workload, 3072c10c1255STina Zhang wa_ctx); 3073c10c1255STina Zhang struct intel_vgpu *vgpu = workload->vgpu; 3074be1da707SZhi Wang 3075be1da707SZhi Wang if (wa_ctx->indirect_ctx.size == 0) 3076be1da707SZhi Wang return 0; 3077be1da707SZhi Wang 3078be1da707SZhi Wang ret = shadow_indirect_ctx(wa_ctx); 3079be1da707SZhi Wang if (ret) { 3080695fbc08STina Zhang gvt_vgpu_err("fail to shadow indirect ctx\n"); 3081be1da707SZhi Wang return ret; 3082be1da707SZhi Wang } 3083be1da707SZhi Wang 3084be1da707SZhi Wang combine_wa_ctx(wa_ctx); 3085be1da707SZhi Wang 3086be1da707SZhi Wang ret = scan_wa_ctx(wa_ctx); 3087be1da707SZhi Wang if (ret) { 3088695fbc08STina Zhang gvt_vgpu_err("scan wa ctx error\n"); 3089be1da707SZhi Wang return ret; 3090be1da707SZhi Wang } 3091be1da707SZhi Wang 3092be1da707SZhi Wang return 0; 3093be1da707SZhi Wang } 3094be1da707SZhi Wang 3095493f30cdSYan Zhao /* generate dummy contexts by sending empty requests to HW, and let 3096493f30cdSYan Zhao * the HW to fill Engine Contexts. This dummy contexts are used for 3097493f30cdSYan Zhao * initialization purpose (update reg whitelist), so referred to as 3098493f30cdSYan Zhao * init context here 3099493f30cdSYan Zhao */ 3100493f30cdSYan Zhao void intel_gvt_update_reg_whitelist(struct intel_vgpu *vgpu) 3101493f30cdSYan Zhao { 310297ea6565SChris Wilson const unsigned long start = LRC_STATE_PN * PAGE_SIZE; 3103493f30cdSYan Zhao struct intel_gvt *gvt = vgpu->gvt; 3104493f30cdSYan Zhao struct intel_engine_cs *engine; 3105493f30cdSYan Zhao enum intel_engine_id id; 3106493f30cdSYan Zhao 3107493f30cdSYan Zhao if (gvt->is_reg_whitelist_updated) 3108493f30cdSYan Zhao return; 3109493f30cdSYan Zhao 3110493f30cdSYan Zhao /* scan init ctx to update cmd accessible list */ 311197ea6565SChris Wilson for_each_engine(engine, gvt->gt, id) { 3112493f30cdSYan Zhao struct parser_exec_state s; 311397ea6565SChris Wilson void *vaddr; 311497ea6565SChris Wilson int ret; 3115493f30cdSYan Zhao 311697ea6565SChris Wilson if (!engine->default_state) 311797ea6565SChris Wilson continue; 3118493f30cdSYan Zhao 311997ea6565SChris Wilson vaddr = shmem_pin_map(engine->default_state); 3120493f30cdSYan Zhao if (IS_ERR(vaddr)) { 312197ea6565SChris Wilson gvt_err("failed to map %s->default state, err:%zd\n", 312297ea6565SChris Wilson engine->name, PTR_ERR(vaddr)); 312397ea6565SChris Wilson return; 3124493f30cdSYan Zhao } 3125493f30cdSYan Zhao 3126493f30cdSYan Zhao s.buf_type = RING_BUFFER_CTX; 3127493f30cdSYan Zhao s.buf_addr_type = GTT_BUFFER; 3128493f30cdSYan Zhao s.vgpu = vgpu; 3129493f30cdSYan Zhao s.engine = engine; 3130493f30cdSYan Zhao s.ring_start = 0; 313197ea6565SChris Wilson s.ring_size = engine->context_size - start; 3132493f30cdSYan Zhao s.ring_head = 0; 313397ea6565SChris Wilson s.ring_tail = s.ring_size; 3134493f30cdSYan Zhao s.rb_va = vaddr + start; 3135493f30cdSYan Zhao s.workload = NULL; 3136493f30cdSYan Zhao s.is_ctx_wa = false; 3137493f30cdSYan Zhao s.is_init_ctx = true; 3138493f30cdSYan Zhao 3139493f30cdSYan Zhao /* skipping the first RING_CTX_SIZE(0x50) dwords */ 3140493f30cdSYan Zhao ret = ip_gma_set(&s, RING_CTX_SIZE); 314197ea6565SChris Wilson if (ret == 0) { 314297ea6565SChris Wilson ret = command_scan(&s, 0, s.ring_size, 0, s.ring_size); 3143493f30cdSYan Zhao if (ret) 3144493f30cdSYan Zhao gvt_err("Scan init ctx error\n"); 3145493f30cdSYan Zhao } 3146493f30cdSYan Zhao 314797ea6565SChris Wilson shmem_unpin_map(engine->default_state, vaddr); 314897ea6565SChris Wilson if (ret) 314997ea6565SChris Wilson return; 315097ea6565SChris Wilson } 315197ea6565SChris Wilson 3152493f30cdSYan Zhao gvt->is_reg_whitelist_updated = true; 3153493f30cdSYan Zhao } 3154493f30cdSYan Zhao 31553c4f2120SYan Zhao int intel_gvt_scan_engine_context(struct intel_vgpu_workload *workload) 31563c4f2120SYan Zhao { 31573c4f2120SYan Zhao struct intel_vgpu *vgpu = workload->vgpu; 31583c4f2120SYan Zhao unsigned long gma_head, gma_tail, gma_start, ctx_size; 31593c4f2120SYan Zhao struct parser_exec_state s; 31603c4f2120SYan Zhao int ring_id = workload->engine->id; 31613c4f2120SYan Zhao struct intel_context *ce = vgpu->submission.shadow[ring_id]; 31623c4f2120SYan Zhao int ret; 31633c4f2120SYan Zhao 31643c4f2120SYan Zhao GEM_BUG_ON(atomic_read(&ce->pin_count) < 0); 31653c4f2120SYan Zhao 31663c4f2120SYan Zhao ctx_size = workload->engine->context_size - PAGE_SIZE; 31673c4f2120SYan Zhao 31683c4f2120SYan Zhao /* Only ring contxt is loaded to HW for inhibit context, no need to 31693c4f2120SYan Zhao * scan engine context 31703c4f2120SYan Zhao */ 31713c4f2120SYan Zhao if (is_inhibit_context(ce)) 31723c4f2120SYan Zhao return 0; 31733c4f2120SYan Zhao 31743c4f2120SYan Zhao gma_start = i915_ggtt_offset(ce->state) + LRC_STATE_PN*PAGE_SIZE; 31753c4f2120SYan Zhao gma_head = 0; 31763c4f2120SYan Zhao gma_tail = ctx_size; 31773c4f2120SYan Zhao 31783c4f2120SYan Zhao s.buf_type = RING_BUFFER_CTX; 31793c4f2120SYan Zhao s.buf_addr_type = GTT_BUFFER; 31803c4f2120SYan Zhao s.vgpu = workload->vgpu; 31813c4f2120SYan Zhao s.engine = workload->engine; 31823c4f2120SYan Zhao s.ring_start = gma_start; 31833c4f2120SYan Zhao s.ring_size = ctx_size; 31843c4f2120SYan Zhao s.ring_head = gma_start + gma_head; 31853c4f2120SYan Zhao s.ring_tail = gma_start + gma_tail; 31863c4f2120SYan Zhao s.rb_va = ce->lrc_reg_state; 31873c4f2120SYan Zhao s.workload = workload; 31883c4f2120SYan Zhao s.is_ctx_wa = false; 31893c4f2120SYan Zhao s.is_init_ctx = false; 31903c4f2120SYan Zhao 31913c4f2120SYan Zhao /* don't scan the first RING_CTX_SIZE(0x50) dwords, as it's ring 31923c4f2120SYan Zhao * context 31933c4f2120SYan Zhao */ 31943c4f2120SYan Zhao ret = ip_gma_set(&s, gma_start + gma_head + RING_CTX_SIZE); 31953c4f2120SYan Zhao if (ret) 31963c4f2120SYan Zhao goto out; 31973c4f2120SYan Zhao 31983c4f2120SYan Zhao ret = command_scan(&s, gma_head, gma_tail, 31993c4f2120SYan Zhao gma_start, ctx_size); 32003c4f2120SYan Zhao out: 32013c4f2120SYan Zhao if (ret) 32023c4f2120SYan Zhao gvt_vgpu_err("scan shadow ctx error\n"); 32033c4f2120SYan Zhao 32043c4f2120SYan Zhao return ret; 32053c4f2120SYan Zhao } 32063c4f2120SYan Zhao 3207be1da707SZhi Wang static int init_cmd_table(struct intel_gvt *gvt) 3208be1da707SZhi Wang { 32098fde4107SChris Wilson unsigned int gen_type = intel_gvt_get_device_type(gvt); 3210be1da707SZhi Wang int i; 3211be1da707SZhi Wang 3212be1da707SZhi Wang for (i = 0; i < ARRAY_SIZE(cmd_info); i++) { 32138fde4107SChris Wilson struct cmd_entry *e; 32148fde4107SChris Wilson 3215be1da707SZhi Wang if (!(cmd_info[i].devices & gen_type)) 3216be1da707SZhi Wang continue; 3217be1da707SZhi Wang 3218be1da707SZhi Wang e = kzalloc(sizeof(*e), GFP_KERNEL); 3219be1da707SZhi Wang if (!e) 3220be1da707SZhi Wang return -ENOMEM; 3221be1da707SZhi Wang 3222be1da707SZhi Wang e->info = &cmd_info[i]; 3223db47685dSZhao Yan if (cmd_info[i].opcode == OP_MI_NOOP) 3224db47685dSZhao Yan mi_noop_index = i; 3225be1da707SZhi Wang 3226be1da707SZhi Wang INIT_HLIST_NODE(&e->hlist); 3227be1da707SZhi Wang add_cmd_entry(gvt, e); 3228be1da707SZhi Wang gvt_dbg_cmd("add %-30s op %04x flag %x devs %02x rings %02x\n", 3229be1da707SZhi Wang e->info->name, e->info->opcode, e->info->flag, 3230be1da707SZhi Wang e->info->devices, e->info->rings); 3231be1da707SZhi Wang } 32328fde4107SChris Wilson 3233be1da707SZhi Wang return 0; 3234be1da707SZhi Wang } 3235be1da707SZhi Wang 3236be1da707SZhi Wang static void clean_cmd_table(struct intel_gvt *gvt) 3237be1da707SZhi Wang { 3238be1da707SZhi Wang struct hlist_node *tmp; 3239be1da707SZhi Wang struct cmd_entry *e; 3240be1da707SZhi Wang int i; 3241be1da707SZhi Wang 3242be1da707SZhi Wang hash_for_each_safe(gvt->cmd_table, i, tmp, e, hlist) 3243be1da707SZhi Wang kfree(e); 3244be1da707SZhi Wang 3245be1da707SZhi Wang hash_init(gvt->cmd_table); 3246be1da707SZhi Wang } 3247be1da707SZhi Wang 3248be1da707SZhi Wang void intel_gvt_clean_cmd_parser(struct intel_gvt *gvt) 3249be1da707SZhi Wang { 3250be1da707SZhi Wang clean_cmd_table(gvt); 3251be1da707SZhi Wang } 3252be1da707SZhi Wang 3253be1da707SZhi Wang int intel_gvt_init_cmd_parser(struct intel_gvt *gvt) 3254be1da707SZhi Wang { 3255be1da707SZhi Wang int ret; 3256be1da707SZhi Wang 3257be1da707SZhi Wang ret = init_cmd_table(gvt); 3258be1da707SZhi Wang if (ret) { 3259be1da707SZhi Wang intel_gvt_clean_cmd_parser(gvt); 3260be1da707SZhi Wang return ret; 3261be1da707SZhi Wang } 3262be1da707SZhi Wang return 0; 3263be1da707SZhi Wang } 3264