1be1da707SZhi Wang /* 2be1da707SZhi Wang * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3be1da707SZhi Wang * 4be1da707SZhi Wang * Permission is hereby granted, free of charge, to any person obtaining a 5be1da707SZhi Wang * copy of this software and associated documentation files (the "Software"), 6be1da707SZhi Wang * to deal in the Software without restriction, including without limitation 7be1da707SZhi Wang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8be1da707SZhi Wang * and/or sell copies of the Software, and to permit persons to whom the 9be1da707SZhi Wang * Software is furnished to do so, subject to the following conditions: 10be1da707SZhi Wang * 11be1da707SZhi Wang * The above copyright notice and this permission notice (including the next 12be1da707SZhi Wang * paragraph) shall be included in all copies or substantial portions of the 13be1da707SZhi Wang * Software. 14be1da707SZhi Wang * 15be1da707SZhi Wang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16be1da707SZhi Wang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17be1da707SZhi Wang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18be1da707SZhi Wang * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19be1da707SZhi Wang * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20be1da707SZhi Wang * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21be1da707SZhi Wang * SOFTWARE. 22be1da707SZhi Wang * 23be1da707SZhi Wang * Authors: 24be1da707SZhi Wang * Ke Yu 25be1da707SZhi Wang * Kevin Tian <kevin.tian@intel.com> 26be1da707SZhi Wang * Zhiyuan Lv <zhiyuan.lv@intel.com> 27be1da707SZhi Wang * 28be1da707SZhi Wang * Contributors: 29be1da707SZhi Wang * Min He <min.he@intel.com> 30be1da707SZhi Wang * Ping Gao <ping.a.gao@intel.com> 31be1da707SZhi Wang * Tina Zhang <tina.zhang@intel.com> 32be1da707SZhi Wang * Yulei Zhang <yulei.zhang@intel.com> 33be1da707SZhi Wang * Zhi Wang <zhi.a.wang@intel.com> 34be1da707SZhi Wang * 35be1da707SZhi Wang */ 36be1da707SZhi Wang 37be1da707SZhi Wang #include <linux/slab.h> 38be1da707SZhi Wang #include "i915_drv.h" 39be1da707SZhi Wang #include "trace.h" 40be1da707SZhi Wang 41be1da707SZhi Wang #define INVALID_OP (~0U) 42be1da707SZhi Wang 43be1da707SZhi Wang #define OP_LEN_MI 9 44be1da707SZhi Wang #define OP_LEN_2D 10 45be1da707SZhi Wang #define OP_LEN_3D_MEDIA 16 46be1da707SZhi Wang #define OP_LEN_MFX_VC 16 47be1da707SZhi Wang #define OP_LEN_VEBOX 16 48be1da707SZhi Wang 49be1da707SZhi Wang #define CMD_TYPE(cmd) (((cmd) >> 29) & 7) 50be1da707SZhi Wang 51be1da707SZhi Wang struct sub_op_bits { 52be1da707SZhi Wang int hi; 53be1da707SZhi Wang int low; 54be1da707SZhi Wang }; 55be1da707SZhi Wang struct decode_info { 56be1da707SZhi Wang char *name; 57be1da707SZhi Wang int op_len; 58be1da707SZhi Wang int nr_sub_op; 59be1da707SZhi Wang struct sub_op_bits *sub_op; 60be1da707SZhi Wang }; 61be1da707SZhi Wang 62be1da707SZhi Wang #define MAX_CMD_BUDGET 0x7fffffff 63be1da707SZhi Wang #define MI_WAIT_FOR_PLANE_C_FLIP_PENDING (1<<15) 64be1da707SZhi Wang #define MI_WAIT_FOR_PLANE_B_FLIP_PENDING (1<<9) 65be1da707SZhi Wang #define MI_WAIT_FOR_PLANE_A_FLIP_PENDING (1<<1) 66be1da707SZhi Wang 67be1da707SZhi Wang #define MI_WAIT_FOR_SPRITE_C_FLIP_PENDING (1<<20) 68be1da707SZhi Wang #define MI_WAIT_FOR_SPRITE_B_FLIP_PENDING (1<<10) 69be1da707SZhi Wang #define MI_WAIT_FOR_SPRITE_A_FLIP_PENDING (1<<2) 70be1da707SZhi Wang 71be1da707SZhi Wang /* Render Command Map */ 72be1da707SZhi Wang 73be1da707SZhi Wang /* MI_* command Opcode (28:23) */ 74be1da707SZhi Wang #define OP_MI_NOOP 0x0 75be1da707SZhi Wang #define OP_MI_SET_PREDICATE 0x1 /* HSW+ */ 76be1da707SZhi Wang #define OP_MI_USER_INTERRUPT 0x2 77be1da707SZhi Wang #define OP_MI_WAIT_FOR_EVENT 0x3 78be1da707SZhi Wang #define OP_MI_FLUSH 0x4 79be1da707SZhi Wang #define OP_MI_ARB_CHECK 0x5 80be1da707SZhi Wang #define OP_MI_RS_CONTROL 0x6 /* HSW+ */ 81be1da707SZhi Wang #define OP_MI_REPORT_HEAD 0x7 82be1da707SZhi Wang #define OP_MI_ARB_ON_OFF 0x8 83be1da707SZhi Wang #define OP_MI_URB_ATOMIC_ALLOC 0x9 /* HSW+ */ 84be1da707SZhi Wang #define OP_MI_BATCH_BUFFER_END 0xA 85be1da707SZhi Wang #define OP_MI_SUSPEND_FLUSH 0xB 86be1da707SZhi Wang #define OP_MI_PREDICATE 0xC /* IVB+ */ 87be1da707SZhi Wang #define OP_MI_TOPOLOGY_FILTER 0xD /* IVB+ */ 88be1da707SZhi Wang #define OP_MI_SET_APPID 0xE /* IVB+ */ 89be1da707SZhi Wang #define OP_MI_RS_CONTEXT 0xF /* HSW+ */ 90be1da707SZhi Wang #define OP_MI_LOAD_SCAN_LINES_INCL 0x12 /* HSW+ */ 91be1da707SZhi Wang #define OP_MI_DISPLAY_FLIP 0x14 92be1da707SZhi Wang #define OP_MI_SEMAPHORE_MBOX 0x16 93be1da707SZhi Wang #define OP_MI_SET_CONTEXT 0x18 94be1da707SZhi Wang #define OP_MI_MATH 0x1A 95be1da707SZhi Wang #define OP_MI_URB_CLEAR 0x19 96be1da707SZhi Wang #define OP_MI_SEMAPHORE_SIGNAL 0x1B /* BDW+ */ 97be1da707SZhi Wang #define OP_MI_SEMAPHORE_WAIT 0x1C /* BDW+ */ 98be1da707SZhi Wang 99be1da707SZhi Wang #define OP_MI_STORE_DATA_IMM 0x20 100be1da707SZhi Wang #define OP_MI_STORE_DATA_INDEX 0x21 101be1da707SZhi Wang #define OP_MI_LOAD_REGISTER_IMM 0x22 102be1da707SZhi Wang #define OP_MI_UPDATE_GTT 0x23 103be1da707SZhi Wang #define OP_MI_STORE_REGISTER_MEM 0x24 104be1da707SZhi Wang #define OP_MI_FLUSH_DW 0x26 105be1da707SZhi Wang #define OP_MI_CLFLUSH 0x27 106be1da707SZhi Wang #define OP_MI_REPORT_PERF_COUNT 0x28 107be1da707SZhi Wang #define OP_MI_LOAD_REGISTER_MEM 0x29 /* HSW+ */ 108be1da707SZhi Wang #define OP_MI_LOAD_REGISTER_REG 0x2A /* HSW+ */ 109be1da707SZhi Wang #define OP_MI_RS_STORE_DATA_IMM 0x2B /* HSW+ */ 110be1da707SZhi Wang #define OP_MI_LOAD_URB_MEM 0x2C /* HSW+ */ 111be1da707SZhi Wang #define OP_MI_STORE_URM_MEM 0x2D /* HSW+ */ 112be1da707SZhi Wang #define OP_MI_2E 0x2E /* BDW+ */ 113be1da707SZhi Wang #define OP_MI_2F 0x2F /* BDW+ */ 114be1da707SZhi Wang #define OP_MI_BATCH_BUFFER_START 0x31 115be1da707SZhi Wang 116be1da707SZhi Wang /* Bit definition for dword 0 */ 117be1da707SZhi Wang #define _CMDBIT_BB_START_IN_PPGTT (1UL << 8) 118be1da707SZhi Wang 119be1da707SZhi Wang #define OP_MI_CONDITIONAL_BATCH_BUFFER_END 0x36 120be1da707SZhi Wang 121be1da707SZhi Wang #define BATCH_BUFFER_ADDR_MASK ((1UL << 32) - (1U << 2)) 122be1da707SZhi Wang #define BATCH_BUFFER_ADDR_HIGH_MASK ((1UL << 16) - (1U)) 123be1da707SZhi Wang #define BATCH_BUFFER_ADR_SPACE_BIT(x) (((x) >> 8) & 1U) 124be1da707SZhi Wang #define BATCH_BUFFER_2ND_LEVEL_BIT(x) ((x) >> 22 & 1U) 125be1da707SZhi Wang 126be1da707SZhi Wang /* 2D command: Opcode (28:22) */ 127be1da707SZhi Wang #define OP_2D(x) ((2<<7) | x) 128be1da707SZhi Wang 129be1da707SZhi Wang #define OP_XY_SETUP_BLT OP_2D(0x1) 130be1da707SZhi Wang #define OP_XY_SETUP_CLIP_BLT OP_2D(0x3) 131be1da707SZhi Wang #define OP_XY_SETUP_MONO_PATTERN_SL_BLT OP_2D(0x11) 132be1da707SZhi Wang #define OP_XY_PIXEL_BLT OP_2D(0x24) 133be1da707SZhi Wang #define OP_XY_SCANLINES_BLT OP_2D(0x25) 134be1da707SZhi Wang #define OP_XY_TEXT_BLT OP_2D(0x26) 135be1da707SZhi Wang #define OP_XY_TEXT_IMMEDIATE_BLT OP_2D(0x31) 136be1da707SZhi Wang #define OP_XY_COLOR_BLT OP_2D(0x50) 137be1da707SZhi Wang #define OP_XY_PAT_BLT OP_2D(0x51) 138be1da707SZhi Wang #define OP_XY_MONO_PAT_BLT OP_2D(0x52) 139be1da707SZhi Wang #define OP_XY_SRC_COPY_BLT OP_2D(0x53) 140be1da707SZhi Wang #define OP_XY_MONO_SRC_COPY_BLT OP_2D(0x54) 141be1da707SZhi Wang #define OP_XY_FULL_BLT OP_2D(0x55) 142be1da707SZhi Wang #define OP_XY_FULL_MONO_SRC_BLT OP_2D(0x56) 143be1da707SZhi Wang #define OP_XY_FULL_MONO_PATTERN_BLT OP_2D(0x57) 144be1da707SZhi Wang #define OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT OP_2D(0x58) 145be1da707SZhi Wang #define OP_XY_MONO_PAT_FIXED_BLT OP_2D(0x59) 146be1da707SZhi Wang #define OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT OP_2D(0x71) 147be1da707SZhi Wang #define OP_XY_PAT_BLT_IMMEDIATE OP_2D(0x72) 148be1da707SZhi Wang #define OP_XY_SRC_COPY_CHROMA_BLT OP_2D(0x73) 149be1da707SZhi Wang #define OP_XY_FULL_IMMEDIATE_PATTERN_BLT OP_2D(0x74) 150be1da707SZhi Wang #define OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT OP_2D(0x75) 151be1da707SZhi Wang #define OP_XY_PAT_CHROMA_BLT OP_2D(0x76) 152be1da707SZhi Wang #define OP_XY_PAT_CHROMA_BLT_IMMEDIATE OP_2D(0x77) 153be1da707SZhi Wang 154be1da707SZhi Wang /* 3D/Media Command: Pipeline Type(28:27) Opcode(26:24) Sub Opcode(23:16) */ 155be1da707SZhi Wang #define OP_3D_MEDIA(sub_type, opcode, sub_opcode) \ 156be1da707SZhi Wang ((3 << 13) | ((sub_type) << 11) | ((opcode) << 8) | (sub_opcode)) 157be1da707SZhi Wang 158be1da707SZhi Wang #define OP_STATE_PREFETCH OP_3D_MEDIA(0x0, 0x0, 0x03) 159be1da707SZhi Wang 160be1da707SZhi Wang #define OP_STATE_BASE_ADDRESS OP_3D_MEDIA(0x0, 0x1, 0x01) 161be1da707SZhi Wang #define OP_STATE_SIP OP_3D_MEDIA(0x0, 0x1, 0x02) 162be1da707SZhi Wang #define OP_3D_MEDIA_0_1_4 OP_3D_MEDIA(0x0, 0x1, 0x04) 163be1da707SZhi Wang 164be1da707SZhi Wang #define OP_3DSTATE_VF_STATISTICS_GM45 OP_3D_MEDIA(0x1, 0x0, 0x0B) 165be1da707SZhi Wang 166be1da707SZhi Wang #define OP_PIPELINE_SELECT OP_3D_MEDIA(0x1, 0x1, 0x04) 167be1da707SZhi Wang 168be1da707SZhi Wang #define OP_MEDIA_VFE_STATE OP_3D_MEDIA(0x2, 0x0, 0x0) 169be1da707SZhi Wang #define OP_MEDIA_CURBE_LOAD OP_3D_MEDIA(0x2, 0x0, 0x1) 170be1da707SZhi Wang #define OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD OP_3D_MEDIA(0x2, 0x0, 0x2) 171be1da707SZhi Wang #define OP_MEDIA_GATEWAY_STATE OP_3D_MEDIA(0x2, 0x0, 0x3) 172be1da707SZhi Wang #define OP_MEDIA_STATE_FLUSH OP_3D_MEDIA(0x2, 0x0, 0x4) 173be1da707SZhi Wang 174be1da707SZhi Wang #define OP_MEDIA_OBJECT OP_3D_MEDIA(0x2, 0x1, 0x0) 175be1da707SZhi Wang #define OP_MEDIA_OBJECT_PRT OP_3D_MEDIA(0x2, 0x1, 0x2) 176be1da707SZhi Wang #define OP_MEDIA_OBJECT_WALKER OP_3D_MEDIA(0x2, 0x1, 0x3) 177be1da707SZhi Wang #define OP_GPGPU_WALKER OP_3D_MEDIA(0x2, 0x1, 0x5) 178be1da707SZhi Wang 179be1da707SZhi Wang #define OP_3DSTATE_CLEAR_PARAMS OP_3D_MEDIA(0x3, 0x0, 0x04) /* IVB+ */ 180be1da707SZhi Wang #define OP_3DSTATE_DEPTH_BUFFER OP_3D_MEDIA(0x3, 0x0, 0x05) /* IVB+ */ 181be1da707SZhi Wang #define OP_3DSTATE_STENCIL_BUFFER OP_3D_MEDIA(0x3, 0x0, 0x06) /* IVB+ */ 182be1da707SZhi Wang #define OP_3DSTATE_HIER_DEPTH_BUFFER OP_3D_MEDIA(0x3, 0x0, 0x07) /* IVB+ */ 183be1da707SZhi Wang #define OP_3DSTATE_VERTEX_BUFFERS OP_3D_MEDIA(0x3, 0x0, 0x08) 184be1da707SZhi Wang #define OP_3DSTATE_VERTEX_ELEMENTS OP_3D_MEDIA(0x3, 0x0, 0x09) 185be1da707SZhi Wang #define OP_3DSTATE_INDEX_BUFFER OP_3D_MEDIA(0x3, 0x0, 0x0A) 186be1da707SZhi Wang #define OP_3DSTATE_VF_STATISTICS OP_3D_MEDIA(0x3, 0x0, 0x0B) 187be1da707SZhi Wang #define OP_3DSTATE_VF OP_3D_MEDIA(0x3, 0x0, 0x0C) /* HSW+ */ 188be1da707SZhi Wang #define OP_3DSTATE_CC_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x0E) 189be1da707SZhi Wang #define OP_3DSTATE_SCISSOR_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x0F) 190be1da707SZhi Wang #define OP_3DSTATE_VS OP_3D_MEDIA(0x3, 0x0, 0x10) 191be1da707SZhi Wang #define OP_3DSTATE_GS OP_3D_MEDIA(0x3, 0x0, 0x11) 192be1da707SZhi Wang #define OP_3DSTATE_CLIP OP_3D_MEDIA(0x3, 0x0, 0x12) 193be1da707SZhi Wang #define OP_3DSTATE_SF OP_3D_MEDIA(0x3, 0x0, 0x13) 194be1da707SZhi Wang #define OP_3DSTATE_WM OP_3D_MEDIA(0x3, 0x0, 0x14) 195be1da707SZhi Wang #define OP_3DSTATE_CONSTANT_VS OP_3D_MEDIA(0x3, 0x0, 0x15) 196be1da707SZhi Wang #define OP_3DSTATE_CONSTANT_GS OP_3D_MEDIA(0x3, 0x0, 0x16) 197be1da707SZhi Wang #define OP_3DSTATE_CONSTANT_PS OP_3D_MEDIA(0x3, 0x0, 0x17) 198be1da707SZhi Wang #define OP_3DSTATE_SAMPLE_MASK OP_3D_MEDIA(0x3, 0x0, 0x18) 199be1da707SZhi Wang #define OP_3DSTATE_CONSTANT_HS OP_3D_MEDIA(0x3, 0x0, 0x19) /* IVB+ */ 200be1da707SZhi Wang #define OP_3DSTATE_CONSTANT_DS OP_3D_MEDIA(0x3, 0x0, 0x1A) /* IVB+ */ 201be1da707SZhi Wang #define OP_3DSTATE_HS OP_3D_MEDIA(0x3, 0x0, 0x1B) /* IVB+ */ 202be1da707SZhi Wang #define OP_3DSTATE_TE OP_3D_MEDIA(0x3, 0x0, 0x1C) /* IVB+ */ 203be1da707SZhi Wang #define OP_3DSTATE_DS OP_3D_MEDIA(0x3, 0x0, 0x1D) /* IVB+ */ 204be1da707SZhi Wang #define OP_3DSTATE_STREAMOUT OP_3D_MEDIA(0x3, 0x0, 0x1E) /* IVB+ */ 205be1da707SZhi Wang #define OP_3DSTATE_SBE OP_3D_MEDIA(0x3, 0x0, 0x1F) /* IVB+ */ 206be1da707SZhi Wang #define OP_3DSTATE_PS OP_3D_MEDIA(0x3, 0x0, 0x20) /* IVB+ */ 207be1da707SZhi Wang #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP OP_3D_MEDIA(0x3, 0x0, 0x21) /* IVB+ */ 208be1da707SZhi Wang #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC OP_3D_MEDIA(0x3, 0x0, 0x23) /* IVB+ */ 209be1da707SZhi Wang #define OP_3DSTATE_BLEND_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x24) /* IVB+ */ 210be1da707SZhi Wang #define OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x25) /* IVB+ */ 211be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_POINTERS_VS OP_3D_MEDIA(0x3, 0x0, 0x26) /* IVB+ */ 212be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_POINTERS_HS OP_3D_MEDIA(0x3, 0x0, 0x27) /* IVB+ */ 213be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_POINTERS_DS OP_3D_MEDIA(0x3, 0x0, 0x28) /* IVB+ */ 214be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_POINTERS_GS OP_3D_MEDIA(0x3, 0x0, 0x29) /* IVB+ */ 215be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_POINTERS_PS OP_3D_MEDIA(0x3, 0x0, 0x2A) /* IVB+ */ 216be1da707SZhi Wang #define OP_3DSTATE_SAMPLER_STATE_POINTERS_VS OP_3D_MEDIA(0x3, 0x0, 0x2B) /* IVB+ */ 217be1da707SZhi Wang #define OP_3DSTATE_SAMPLER_STATE_POINTERS_HS OP_3D_MEDIA(0x3, 0x0, 0x2C) /* IVB+ */ 218be1da707SZhi Wang #define OP_3DSTATE_SAMPLER_STATE_POINTERS_DS OP_3D_MEDIA(0x3, 0x0, 0x2D) /* IVB+ */ 219be1da707SZhi Wang #define OP_3DSTATE_SAMPLER_STATE_POINTERS_GS OP_3D_MEDIA(0x3, 0x0, 0x2E) /* IVB+ */ 220be1da707SZhi Wang #define OP_3DSTATE_SAMPLER_STATE_POINTERS_PS OP_3D_MEDIA(0x3, 0x0, 0x2F) /* IVB+ */ 221be1da707SZhi Wang #define OP_3DSTATE_URB_VS OP_3D_MEDIA(0x3, 0x0, 0x30) /* IVB+ */ 222be1da707SZhi Wang #define OP_3DSTATE_URB_HS OP_3D_MEDIA(0x3, 0x0, 0x31) /* IVB+ */ 223be1da707SZhi Wang #define OP_3DSTATE_URB_DS OP_3D_MEDIA(0x3, 0x0, 0x32) /* IVB+ */ 224be1da707SZhi Wang #define OP_3DSTATE_URB_GS OP_3D_MEDIA(0x3, 0x0, 0x33) /* IVB+ */ 225be1da707SZhi Wang #define OP_3DSTATE_GATHER_CONSTANT_VS OP_3D_MEDIA(0x3, 0x0, 0x34) /* HSW+ */ 226be1da707SZhi Wang #define OP_3DSTATE_GATHER_CONSTANT_GS OP_3D_MEDIA(0x3, 0x0, 0x35) /* HSW+ */ 227be1da707SZhi Wang #define OP_3DSTATE_GATHER_CONSTANT_HS OP_3D_MEDIA(0x3, 0x0, 0x36) /* HSW+ */ 228be1da707SZhi Wang #define OP_3DSTATE_GATHER_CONSTANT_DS OP_3D_MEDIA(0x3, 0x0, 0x37) /* HSW+ */ 229be1da707SZhi Wang #define OP_3DSTATE_GATHER_CONSTANT_PS OP_3D_MEDIA(0x3, 0x0, 0x38) /* HSW+ */ 230be1da707SZhi Wang #define OP_3DSTATE_DX9_CONSTANTF_VS OP_3D_MEDIA(0x3, 0x0, 0x39) /* HSW+ */ 231be1da707SZhi Wang #define OP_3DSTATE_DX9_CONSTANTF_PS OP_3D_MEDIA(0x3, 0x0, 0x3A) /* HSW+ */ 232be1da707SZhi Wang #define OP_3DSTATE_DX9_CONSTANTI_VS OP_3D_MEDIA(0x3, 0x0, 0x3B) /* HSW+ */ 233be1da707SZhi Wang #define OP_3DSTATE_DX9_CONSTANTI_PS OP_3D_MEDIA(0x3, 0x0, 0x3C) /* HSW+ */ 234be1da707SZhi Wang #define OP_3DSTATE_DX9_CONSTANTB_VS OP_3D_MEDIA(0x3, 0x0, 0x3D) /* HSW+ */ 235be1da707SZhi Wang #define OP_3DSTATE_DX9_CONSTANTB_PS OP_3D_MEDIA(0x3, 0x0, 0x3E) /* HSW+ */ 236be1da707SZhi Wang #define OP_3DSTATE_DX9_LOCAL_VALID_VS OP_3D_MEDIA(0x3, 0x0, 0x3F) /* HSW+ */ 237be1da707SZhi Wang #define OP_3DSTATE_DX9_LOCAL_VALID_PS OP_3D_MEDIA(0x3, 0x0, 0x40) /* HSW+ */ 238be1da707SZhi Wang #define OP_3DSTATE_DX9_GENERATE_ACTIVE_VS OP_3D_MEDIA(0x3, 0x0, 0x41) /* HSW+ */ 239be1da707SZhi Wang #define OP_3DSTATE_DX9_GENERATE_ACTIVE_PS OP_3D_MEDIA(0x3, 0x0, 0x42) /* HSW+ */ 240be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_EDIT_VS OP_3D_MEDIA(0x3, 0x0, 0x43) /* HSW+ */ 241be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_EDIT_GS OP_3D_MEDIA(0x3, 0x0, 0x44) /* HSW+ */ 242be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_EDIT_HS OP_3D_MEDIA(0x3, 0x0, 0x45) /* HSW+ */ 243be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_EDIT_DS OP_3D_MEDIA(0x3, 0x0, 0x46) /* HSW+ */ 244be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_EDIT_PS OP_3D_MEDIA(0x3, 0x0, 0x47) /* HSW+ */ 245be1da707SZhi Wang 246be1da707SZhi Wang #define OP_3DSTATE_VF_INSTANCING OP_3D_MEDIA(0x3, 0x0, 0x49) /* BDW+ */ 247be1da707SZhi Wang #define OP_3DSTATE_VF_SGVS OP_3D_MEDIA(0x3, 0x0, 0x4A) /* BDW+ */ 248be1da707SZhi Wang #define OP_3DSTATE_VF_TOPOLOGY OP_3D_MEDIA(0x3, 0x0, 0x4B) /* BDW+ */ 249be1da707SZhi Wang #define OP_3DSTATE_WM_CHROMAKEY OP_3D_MEDIA(0x3, 0x0, 0x4C) /* BDW+ */ 250be1da707SZhi Wang #define OP_3DSTATE_PS_BLEND OP_3D_MEDIA(0x3, 0x0, 0x4D) /* BDW+ */ 251be1da707SZhi Wang #define OP_3DSTATE_WM_DEPTH_STENCIL OP_3D_MEDIA(0x3, 0x0, 0x4E) /* BDW+ */ 252be1da707SZhi Wang #define OP_3DSTATE_PS_EXTRA OP_3D_MEDIA(0x3, 0x0, 0x4F) /* BDW+ */ 253be1da707SZhi Wang #define OP_3DSTATE_RASTER OP_3D_MEDIA(0x3, 0x0, 0x50) /* BDW+ */ 254be1da707SZhi Wang #define OP_3DSTATE_SBE_SWIZ OP_3D_MEDIA(0x3, 0x0, 0x51) /* BDW+ */ 255be1da707SZhi Wang #define OP_3DSTATE_WM_HZ_OP OP_3D_MEDIA(0x3, 0x0, 0x52) /* BDW+ */ 256be1da707SZhi Wang #define OP_3DSTATE_COMPONENT_PACKING OP_3D_MEDIA(0x3, 0x0, 0x55) /* SKL+ */ 257be1da707SZhi Wang 258be1da707SZhi Wang #define OP_3DSTATE_DRAWING_RECTANGLE OP_3D_MEDIA(0x3, 0x1, 0x00) 259be1da707SZhi Wang #define OP_3DSTATE_SAMPLER_PALETTE_LOAD0 OP_3D_MEDIA(0x3, 0x1, 0x02) 260be1da707SZhi Wang #define OP_3DSTATE_CHROMA_KEY OP_3D_MEDIA(0x3, 0x1, 0x04) 261be1da707SZhi Wang #define OP_SNB_3DSTATE_DEPTH_BUFFER OP_3D_MEDIA(0x3, 0x1, 0x05) 262be1da707SZhi Wang #define OP_3DSTATE_POLY_STIPPLE_OFFSET OP_3D_MEDIA(0x3, 0x1, 0x06) 263be1da707SZhi Wang #define OP_3DSTATE_POLY_STIPPLE_PATTERN OP_3D_MEDIA(0x3, 0x1, 0x07) 264be1da707SZhi Wang #define OP_3DSTATE_LINE_STIPPLE OP_3D_MEDIA(0x3, 0x1, 0x08) 265be1da707SZhi Wang #define OP_3DSTATE_AA_LINE_PARAMS OP_3D_MEDIA(0x3, 0x1, 0x0A) 266be1da707SZhi Wang #define OP_3DSTATE_GS_SVB_INDEX OP_3D_MEDIA(0x3, 0x1, 0x0B) 267be1da707SZhi Wang #define OP_3DSTATE_SAMPLER_PALETTE_LOAD1 OP_3D_MEDIA(0x3, 0x1, 0x0C) 268be1da707SZhi Wang #define OP_3DSTATE_MULTISAMPLE_BDW OP_3D_MEDIA(0x3, 0x0, 0x0D) 269be1da707SZhi Wang #define OP_SNB_3DSTATE_STENCIL_BUFFER OP_3D_MEDIA(0x3, 0x1, 0x0E) 270be1da707SZhi Wang #define OP_SNB_3DSTATE_HIER_DEPTH_BUFFER OP_3D_MEDIA(0x3, 0x1, 0x0F) 271be1da707SZhi Wang #define OP_SNB_3DSTATE_CLEAR_PARAMS OP_3D_MEDIA(0x3, 0x1, 0x10) 272be1da707SZhi Wang #define OP_3DSTATE_MONOFILTER_SIZE OP_3D_MEDIA(0x3, 0x1, 0x11) 273be1da707SZhi Wang #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS OP_3D_MEDIA(0x3, 0x1, 0x12) /* IVB+ */ 274be1da707SZhi Wang #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS OP_3D_MEDIA(0x3, 0x1, 0x13) /* IVB+ */ 275be1da707SZhi Wang #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS OP_3D_MEDIA(0x3, 0x1, 0x14) /* IVB+ */ 276be1da707SZhi Wang #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS OP_3D_MEDIA(0x3, 0x1, 0x15) /* IVB+ */ 277be1da707SZhi Wang #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS OP_3D_MEDIA(0x3, 0x1, 0x16) /* IVB+ */ 278be1da707SZhi Wang #define OP_3DSTATE_SO_DECL_LIST OP_3D_MEDIA(0x3, 0x1, 0x17) 279be1da707SZhi Wang #define OP_3DSTATE_SO_BUFFER OP_3D_MEDIA(0x3, 0x1, 0x18) 280be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x19) /* HSW+ */ 281be1da707SZhi Wang #define OP_3DSTATE_GATHER_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x1A) /* HSW+ */ 282be1da707SZhi Wang #define OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x1B) /* HSW+ */ 283be1da707SZhi Wang #define OP_3DSTATE_SAMPLE_PATTERN OP_3D_MEDIA(0x3, 0x1, 0x1C) 284be1da707SZhi Wang #define OP_PIPE_CONTROL OP_3D_MEDIA(0x3, 0x2, 0x00) 285be1da707SZhi Wang #define OP_3DPRIMITIVE OP_3D_MEDIA(0x3, 0x3, 0x00) 286be1da707SZhi Wang 287be1da707SZhi Wang /* VCCP Command Parser */ 288be1da707SZhi Wang 289be1da707SZhi Wang /* 290be1da707SZhi Wang * Below MFX and VBE cmd definition is from vaapi intel driver project (BSD License) 291be1da707SZhi Wang * git://anongit.freedesktop.org/vaapi/intel-driver 292be1da707SZhi Wang * src/i965_defines.h 293be1da707SZhi Wang * 294be1da707SZhi Wang */ 295be1da707SZhi Wang 296be1da707SZhi Wang #define OP_MFX(pipeline, op, sub_opa, sub_opb) \ 297be1da707SZhi Wang (3 << 13 | \ 298be1da707SZhi Wang (pipeline) << 11 | \ 299be1da707SZhi Wang (op) << 8 | \ 300be1da707SZhi Wang (sub_opa) << 5 | \ 301be1da707SZhi Wang (sub_opb)) 302be1da707SZhi Wang 303be1da707SZhi Wang #define OP_MFX_PIPE_MODE_SELECT OP_MFX(2, 0, 0, 0) /* ALL */ 304be1da707SZhi Wang #define OP_MFX_SURFACE_STATE OP_MFX(2, 0, 0, 1) /* ALL */ 305be1da707SZhi Wang #define OP_MFX_PIPE_BUF_ADDR_STATE OP_MFX(2, 0, 0, 2) /* ALL */ 306be1da707SZhi Wang #define OP_MFX_IND_OBJ_BASE_ADDR_STATE OP_MFX(2, 0, 0, 3) /* ALL */ 307be1da707SZhi Wang #define OP_MFX_BSP_BUF_BASE_ADDR_STATE OP_MFX(2, 0, 0, 4) /* ALL */ 308be1da707SZhi Wang #define OP_2_0_0_5 OP_MFX(2, 0, 0, 5) /* ALL */ 309be1da707SZhi Wang #define OP_MFX_STATE_POINTER OP_MFX(2, 0, 0, 6) /* ALL */ 310be1da707SZhi Wang #define OP_MFX_QM_STATE OP_MFX(2, 0, 0, 7) /* IVB+ */ 311be1da707SZhi Wang #define OP_MFX_FQM_STATE OP_MFX(2, 0, 0, 8) /* IVB+ */ 312be1da707SZhi Wang #define OP_MFX_PAK_INSERT_OBJECT OP_MFX(2, 0, 2, 8) /* IVB+ */ 313be1da707SZhi Wang #define OP_MFX_STITCH_OBJECT OP_MFX(2, 0, 2, 0xA) /* IVB+ */ 314be1da707SZhi Wang 315be1da707SZhi Wang #define OP_MFD_IT_OBJECT OP_MFX(2, 0, 1, 9) /* ALL */ 316be1da707SZhi Wang 317be1da707SZhi Wang #define OP_MFX_WAIT OP_MFX(1, 0, 0, 0) /* IVB+ */ 318be1da707SZhi Wang #define OP_MFX_AVC_IMG_STATE OP_MFX(2, 1, 0, 0) /* ALL */ 319be1da707SZhi Wang #define OP_MFX_AVC_QM_STATE OP_MFX(2, 1, 0, 1) /* ALL */ 320be1da707SZhi Wang #define OP_MFX_AVC_DIRECTMODE_STATE OP_MFX(2, 1, 0, 2) /* ALL */ 321be1da707SZhi Wang #define OP_MFX_AVC_SLICE_STATE OP_MFX(2, 1, 0, 3) /* ALL */ 322be1da707SZhi Wang #define OP_MFX_AVC_REF_IDX_STATE OP_MFX(2, 1, 0, 4) /* ALL */ 323be1da707SZhi Wang #define OP_MFX_AVC_WEIGHTOFFSET_STATE OP_MFX(2, 1, 0, 5) /* ALL */ 324be1da707SZhi Wang #define OP_MFD_AVC_PICID_STATE OP_MFX(2, 1, 1, 5) /* HSW+ */ 325be1da707SZhi Wang #define OP_MFD_AVC_DPB_STATE OP_MFX(2, 1, 1, 6) /* IVB+ */ 326be1da707SZhi Wang #define OP_MFD_AVC_SLICEADDR OP_MFX(2, 1, 1, 7) /* IVB+ */ 327be1da707SZhi Wang #define OP_MFD_AVC_BSD_OBJECT OP_MFX(2, 1, 1, 8) /* ALL */ 328be1da707SZhi Wang #define OP_MFC_AVC_PAK_OBJECT OP_MFX(2, 1, 2, 9) /* ALL */ 329be1da707SZhi Wang 330be1da707SZhi Wang #define OP_MFX_VC1_PRED_PIPE_STATE OP_MFX(2, 2, 0, 1) /* ALL */ 331be1da707SZhi Wang #define OP_MFX_VC1_DIRECTMODE_STATE OP_MFX(2, 2, 0, 2) /* ALL */ 332be1da707SZhi Wang #define OP_MFD_VC1_SHORT_PIC_STATE OP_MFX(2, 2, 1, 0) /* IVB+ */ 333be1da707SZhi Wang #define OP_MFD_VC1_LONG_PIC_STATE OP_MFX(2, 2, 1, 1) /* IVB+ */ 334be1da707SZhi Wang #define OP_MFD_VC1_BSD_OBJECT OP_MFX(2, 2, 1, 8) /* ALL */ 335be1da707SZhi Wang 336be1da707SZhi Wang #define OP_MFX_MPEG2_PIC_STATE OP_MFX(2, 3, 0, 0) /* ALL */ 337be1da707SZhi Wang #define OP_MFX_MPEG2_QM_STATE OP_MFX(2, 3, 0, 1) /* ALL */ 338be1da707SZhi Wang #define OP_MFD_MPEG2_BSD_OBJECT OP_MFX(2, 3, 1, 8) /* ALL */ 339be1da707SZhi Wang #define OP_MFC_MPEG2_SLICEGROUP_STATE OP_MFX(2, 3, 2, 3) /* ALL */ 340be1da707SZhi Wang #define OP_MFC_MPEG2_PAK_OBJECT OP_MFX(2, 3, 2, 9) /* ALL */ 341be1da707SZhi Wang 342be1da707SZhi Wang #define OP_MFX_2_6_0_0 OP_MFX(2, 6, 0, 0) /* IVB+ */ 343be1da707SZhi Wang #define OP_MFX_2_6_0_8 OP_MFX(2, 6, 0, 8) /* IVB+ */ 344be1da707SZhi Wang #define OP_MFX_2_6_0_9 OP_MFX(2, 6, 0, 9) /* IVB+ */ 345be1da707SZhi Wang 346be1da707SZhi Wang #define OP_MFX_JPEG_PIC_STATE OP_MFX(2, 7, 0, 0) 347be1da707SZhi Wang #define OP_MFX_JPEG_HUFF_TABLE_STATE OP_MFX(2, 7, 0, 2) 348be1da707SZhi Wang #define OP_MFD_JPEG_BSD_OBJECT OP_MFX(2, 7, 1, 8) 349be1da707SZhi Wang 350be1da707SZhi Wang #define OP_VEB(pipeline, op, sub_opa, sub_opb) \ 351be1da707SZhi Wang (3 << 13 | \ 352be1da707SZhi Wang (pipeline) << 11 | \ 353be1da707SZhi Wang (op) << 8 | \ 354be1da707SZhi Wang (sub_opa) << 5 | \ 355be1da707SZhi Wang (sub_opb)) 356be1da707SZhi Wang 357be1da707SZhi Wang #define OP_VEB_SURFACE_STATE OP_VEB(2, 4, 0, 0) 358be1da707SZhi Wang #define OP_VEB_STATE OP_VEB(2, 4, 0, 2) 359be1da707SZhi Wang #define OP_VEB_DNDI_IECP_STATE OP_VEB(2, 4, 0, 3) 360be1da707SZhi Wang 361be1da707SZhi Wang struct parser_exec_state; 362be1da707SZhi Wang 363be1da707SZhi Wang typedef int (*parser_cmd_handler)(struct parser_exec_state *s); 364be1da707SZhi Wang 365be1da707SZhi Wang #define GVT_CMD_HASH_BITS 7 366be1da707SZhi Wang 367be1da707SZhi Wang /* which DWords need address fix */ 368be1da707SZhi Wang #define ADDR_FIX_1(x1) (1 << (x1)) 369be1da707SZhi Wang #define ADDR_FIX_2(x1, x2) (ADDR_FIX_1(x1) | ADDR_FIX_1(x2)) 370be1da707SZhi Wang #define ADDR_FIX_3(x1, x2, x3) (ADDR_FIX_1(x1) | ADDR_FIX_2(x2, x3)) 371be1da707SZhi Wang #define ADDR_FIX_4(x1, x2, x3, x4) (ADDR_FIX_1(x1) | ADDR_FIX_3(x2, x3, x4)) 372be1da707SZhi Wang #define ADDR_FIX_5(x1, x2, x3, x4, x5) (ADDR_FIX_1(x1) | ADDR_FIX_4(x2, x3, x4, x5)) 373be1da707SZhi Wang 374be1da707SZhi Wang struct cmd_info { 375be1da707SZhi Wang char *name; 376be1da707SZhi Wang u32 opcode; 377be1da707SZhi Wang 378be1da707SZhi Wang #define F_LEN_MASK (1U<<0) 379be1da707SZhi Wang #define F_LEN_CONST 1U 380be1da707SZhi Wang #define F_LEN_VAR 0U 381be1da707SZhi Wang 382be1da707SZhi Wang /* 383be1da707SZhi Wang * command has its own ip advance logic 384be1da707SZhi Wang * e.g. MI_BATCH_START, MI_BATCH_END 385be1da707SZhi Wang */ 386be1da707SZhi Wang #define F_IP_ADVANCE_CUSTOM (1<<1) 387be1da707SZhi Wang 388be1da707SZhi Wang #define F_POST_HANDLE (1<<2) 389be1da707SZhi Wang u32 flag; 390be1da707SZhi Wang 391be1da707SZhi Wang #define R_RCS (1 << RCS) 392be1da707SZhi Wang #define R_VCS1 (1 << VCS) 393be1da707SZhi Wang #define R_VCS2 (1 << VCS2) 394be1da707SZhi Wang #define R_VCS (R_VCS1 | R_VCS2) 395be1da707SZhi Wang #define R_BCS (1 << BCS) 396be1da707SZhi Wang #define R_VECS (1 << VECS) 397be1da707SZhi Wang #define R_ALL (R_RCS | R_VCS | R_BCS | R_VECS) 398be1da707SZhi Wang /* rings that support this cmd: BLT/RCS/VCS/VECS */ 399be1da707SZhi Wang uint16_t rings; 400be1da707SZhi Wang 401be1da707SZhi Wang /* devices that support this cmd: SNB/IVB/HSW/... */ 402be1da707SZhi Wang uint16_t devices; 403be1da707SZhi Wang 404be1da707SZhi Wang /* which DWords are address that need fix up. 405be1da707SZhi Wang * bit 0 means a 32-bit non address operand in command 406be1da707SZhi Wang * bit 1 means address operand, which could be 32-bit 407be1da707SZhi Wang * or 64-bit depending on different architectures.( 408be1da707SZhi Wang * defined by "gmadr_bytes_in_cmd" in intel_gvt. 409be1da707SZhi Wang * No matter the address length, each address only takes 410be1da707SZhi Wang * one bit in the bitmap. 411be1da707SZhi Wang */ 412be1da707SZhi Wang uint16_t addr_bitmap; 413be1da707SZhi Wang 414be1da707SZhi Wang /* flag == F_LEN_CONST : command length 415be1da707SZhi Wang * flag == F_LEN_VAR : length bias bits 416be1da707SZhi Wang * Note: length is in DWord 417be1da707SZhi Wang */ 418be1da707SZhi Wang uint8_t len; 419be1da707SZhi Wang 420be1da707SZhi Wang parser_cmd_handler handler; 421be1da707SZhi Wang }; 422be1da707SZhi Wang 423be1da707SZhi Wang struct cmd_entry { 424be1da707SZhi Wang struct hlist_node hlist; 425be1da707SZhi Wang struct cmd_info *info; 426be1da707SZhi Wang }; 427be1da707SZhi Wang 428be1da707SZhi Wang enum { 429be1da707SZhi Wang RING_BUFFER_INSTRUCTION, 430be1da707SZhi Wang BATCH_BUFFER_INSTRUCTION, 431be1da707SZhi Wang BATCH_BUFFER_2ND_LEVEL, 432be1da707SZhi Wang }; 433be1da707SZhi Wang 434be1da707SZhi Wang enum { 435be1da707SZhi Wang GTT_BUFFER, 436be1da707SZhi Wang PPGTT_BUFFER 437be1da707SZhi Wang }; 438be1da707SZhi Wang 439be1da707SZhi Wang struct parser_exec_state { 440be1da707SZhi Wang struct intel_vgpu *vgpu; 441be1da707SZhi Wang int ring_id; 442be1da707SZhi Wang 443be1da707SZhi Wang int buf_type; 444be1da707SZhi Wang 445be1da707SZhi Wang /* batch buffer address type */ 446be1da707SZhi Wang int buf_addr_type; 447be1da707SZhi Wang 448be1da707SZhi Wang /* graphics memory address of ring buffer start */ 449be1da707SZhi Wang unsigned long ring_start; 450be1da707SZhi Wang unsigned long ring_size; 451be1da707SZhi Wang unsigned long ring_head; 452be1da707SZhi Wang unsigned long ring_tail; 453be1da707SZhi Wang 454be1da707SZhi Wang /* instruction graphics memory address */ 455be1da707SZhi Wang unsigned long ip_gma; 456be1da707SZhi Wang 457be1da707SZhi Wang /* mapped va of the instr_gma */ 458be1da707SZhi Wang void *ip_va; 459be1da707SZhi Wang void *rb_va; 460be1da707SZhi Wang 461be1da707SZhi Wang void *ret_bb_va; 462be1da707SZhi Wang /* next instruction when return from batch buffer to ring buffer */ 463be1da707SZhi Wang unsigned long ret_ip_gma_ring; 464be1da707SZhi Wang 465be1da707SZhi Wang /* next instruction when return from 2nd batch buffer to batch buffer */ 466be1da707SZhi Wang unsigned long ret_ip_gma_bb; 467be1da707SZhi Wang 468be1da707SZhi Wang /* batch buffer address type (GTT or PPGTT) 469be1da707SZhi Wang * used when ret from 2nd level batch buffer 470be1da707SZhi Wang */ 471be1da707SZhi Wang int saved_buf_addr_type; 472be1da707SZhi Wang 473be1da707SZhi Wang struct cmd_info *info; 474be1da707SZhi Wang 475be1da707SZhi Wang struct intel_vgpu_workload *workload; 476be1da707SZhi Wang }; 477be1da707SZhi Wang 478be1da707SZhi Wang #define gmadr_dw_number(s) \ 479be1da707SZhi Wang (s->vgpu->gvt->device_info.gmadr_bytes_in_cmd >> 2) 480be1da707SZhi Wang 481be1da707SZhi Wang unsigned long bypass_scan_mask = 0; 482be1da707SZhi Wang bool bypass_batch_buffer_scan = true; 483be1da707SZhi Wang 484be1da707SZhi Wang /* ring ALL, type = 0 */ 485be1da707SZhi Wang static struct sub_op_bits sub_op_mi[] = { 486be1da707SZhi Wang {31, 29}, 487be1da707SZhi Wang {28, 23}, 488be1da707SZhi Wang }; 489be1da707SZhi Wang 490be1da707SZhi Wang static struct decode_info decode_info_mi = { 491be1da707SZhi Wang "MI", 492be1da707SZhi Wang OP_LEN_MI, 493be1da707SZhi Wang ARRAY_SIZE(sub_op_mi), 494be1da707SZhi Wang sub_op_mi, 495be1da707SZhi Wang }; 496be1da707SZhi Wang 497be1da707SZhi Wang /* ring RCS, command type 2 */ 498be1da707SZhi Wang static struct sub_op_bits sub_op_2d[] = { 499be1da707SZhi Wang {31, 29}, 500be1da707SZhi Wang {28, 22}, 501be1da707SZhi Wang }; 502be1da707SZhi Wang 503be1da707SZhi Wang static struct decode_info decode_info_2d = { 504be1da707SZhi Wang "2D", 505be1da707SZhi Wang OP_LEN_2D, 506be1da707SZhi Wang ARRAY_SIZE(sub_op_2d), 507be1da707SZhi Wang sub_op_2d, 508be1da707SZhi Wang }; 509be1da707SZhi Wang 510be1da707SZhi Wang /* ring RCS, command type 3 */ 511be1da707SZhi Wang static struct sub_op_bits sub_op_3d_media[] = { 512be1da707SZhi Wang {31, 29}, 513be1da707SZhi Wang {28, 27}, 514be1da707SZhi Wang {26, 24}, 515be1da707SZhi Wang {23, 16}, 516be1da707SZhi Wang }; 517be1da707SZhi Wang 518be1da707SZhi Wang static struct decode_info decode_info_3d_media = { 519be1da707SZhi Wang "3D_Media", 520be1da707SZhi Wang OP_LEN_3D_MEDIA, 521be1da707SZhi Wang ARRAY_SIZE(sub_op_3d_media), 522be1da707SZhi Wang sub_op_3d_media, 523be1da707SZhi Wang }; 524be1da707SZhi Wang 525be1da707SZhi Wang /* ring VCS, command type 3 */ 526be1da707SZhi Wang static struct sub_op_bits sub_op_mfx_vc[] = { 527be1da707SZhi Wang {31, 29}, 528be1da707SZhi Wang {28, 27}, 529be1da707SZhi Wang {26, 24}, 530be1da707SZhi Wang {23, 21}, 531be1da707SZhi Wang {20, 16}, 532be1da707SZhi Wang }; 533be1da707SZhi Wang 534be1da707SZhi Wang static struct decode_info decode_info_mfx_vc = { 535be1da707SZhi Wang "MFX_VC", 536be1da707SZhi Wang OP_LEN_MFX_VC, 537be1da707SZhi Wang ARRAY_SIZE(sub_op_mfx_vc), 538be1da707SZhi Wang sub_op_mfx_vc, 539be1da707SZhi Wang }; 540be1da707SZhi Wang 541be1da707SZhi Wang /* ring VECS, command type 3 */ 542be1da707SZhi Wang static struct sub_op_bits sub_op_vebox[] = { 543be1da707SZhi Wang {31, 29}, 544be1da707SZhi Wang {28, 27}, 545be1da707SZhi Wang {26, 24}, 546be1da707SZhi Wang {23, 21}, 547be1da707SZhi Wang {20, 16}, 548be1da707SZhi Wang }; 549be1da707SZhi Wang 550be1da707SZhi Wang static struct decode_info decode_info_vebox = { 551be1da707SZhi Wang "VEBOX", 552be1da707SZhi Wang OP_LEN_VEBOX, 553be1da707SZhi Wang ARRAY_SIZE(sub_op_vebox), 554be1da707SZhi Wang sub_op_vebox, 555be1da707SZhi Wang }; 556be1da707SZhi Wang 557be1da707SZhi Wang static struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = { 558be1da707SZhi Wang [RCS] = { 559be1da707SZhi Wang &decode_info_mi, 560be1da707SZhi Wang NULL, 561be1da707SZhi Wang NULL, 562be1da707SZhi Wang &decode_info_3d_media, 563be1da707SZhi Wang NULL, 564be1da707SZhi Wang NULL, 565be1da707SZhi Wang NULL, 566be1da707SZhi Wang NULL, 567be1da707SZhi Wang }, 568be1da707SZhi Wang 569be1da707SZhi Wang [VCS] = { 570be1da707SZhi Wang &decode_info_mi, 571be1da707SZhi Wang NULL, 572be1da707SZhi Wang NULL, 573be1da707SZhi Wang &decode_info_mfx_vc, 574be1da707SZhi Wang NULL, 575be1da707SZhi Wang NULL, 576be1da707SZhi Wang NULL, 577be1da707SZhi Wang NULL, 578be1da707SZhi Wang }, 579be1da707SZhi Wang 580be1da707SZhi Wang [BCS] = { 581be1da707SZhi Wang &decode_info_mi, 582be1da707SZhi Wang NULL, 583be1da707SZhi Wang &decode_info_2d, 584be1da707SZhi Wang NULL, 585be1da707SZhi Wang NULL, 586be1da707SZhi Wang NULL, 587be1da707SZhi Wang NULL, 588be1da707SZhi Wang NULL, 589be1da707SZhi Wang }, 590be1da707SZhi Wang 591be1da707SZhi Wang [VECS] = { 592be1da707SZhi Wang &decode_info_mi, 593be1da707SZhi Wang NULL, 594be1da707SZhi Wang NULL, 595be1da707SZhi Wang &decode_info_vebox, 596be1da707SZhi Wang NULL, 597be1da707SZhi Wang NULL, 598be1da707SZhi Wang NULL, 599be1da707SZhi Wang NULL, 600be1da707SZhi Wang }, 601be1da707SZhi Wang 602be1da707SZhi Wang [VCS2] = { 603be1da707SZhi Wang &decode_info_mi, 604be1da707SZhi Wang NULL, 605be1da707SZhi Wang NULL, 606be1da707SZhi Wang &decode_info_mfx_vc, 607be1da707SZhi Wang NULL, 608be1da707SZhi Wang NULL, 609be1da707SZhi Wang NULL, 610be1da707SZhi Wang NULL, 611be1da707SZhi Wang }, 612be1da707SZhi Wang }; 613be1da707SZhi Wang 614be1da707SZhi Wang static inline u32 get_opcode(u32 cmd, int ring_id) 615be1da707SZhi Wang { 616be1da707SZhi Wang struct decode_info *d_info; 617be1da707SZhi Wang 618be1da707SZhi Wang if (ring_id >= I915_NUM_ENGINES) 619be1da707SZhi Wang return INVALID_OP; 620be1da707SZhi Wang 621be1da707SZhi Wang d_info = ring_decode_info[ring_id][CMD_TYPE(cmd)]; 622be1da707SZhi Wang if (d_info == NULL) 623be1da707SZhi Wang return INVALID_OP; 624be1da707SZhi Wang 625be1da707SZhi Wang return cmd >> (32 - d_info->op_len); 626be1da707SZhi Wang } 627be1da707SZhi Wang 628be1da707SZhi Wang static inline struct cmd_info *find_cmd_entry(struct intel_gvt *gvt, 629be1da707SZhi Wang unsigned int opcode, int ring_id) 630be1da707SZhi Wang { 631be1da707SZhi Wang struct cmd_entry *e; 632be1da707SZhi Wang 633be1da707SZhi Wang hash_for_each_possible(gvt->cmd_table, e, hlist, opcode) { 634be1da707SZhi Wang if ((opcode == e->info->opcode) && 635be1da707SZhi Wang (e->info->rings & (1 << ring_id))) 636be1da707SZhi Wang return e->info; 637be1da707SZhi Wang } 638be1da707SZhi Wang return NULL; 639be1da707SZhi Wang } 640be1da707SZhi Wang 641be1da707SZhi Wang static inline struct cmd_info *get_cmd_info(struct intel_gvt *gvt, 642be1da707SZhi Wang u32 cmd, int ring_id) 643be1da707SZhi Wang { 644be1da707SZhi Wang u32 opcode; 645be1da707SZhi Wang 646be1da707SZhi Wang opcode = get_opcode(cmd, ring_id); 647be1da707SZhi Wang if (opcode == INVALID_OP) 648be1da707SZhi Wang return NULL; 649be1da707SZhi Wang 650be1da707SZhi Wang return find_cmd_entry(gvt, opcode, ring_id); 651be1da707SZhi Wang } 652be1da707SZhi Wang 653be1da707SZhi Wang static inline u32 sub_op_val(u32 cmd, u32 hi, u32 low) 654be1da707SZhi Wang { 655be1da707SZhi Wang return (cmd >> low) & ((1U << (hi - low + 1)) - 1); 656be1da707SZhi Wang } 657be1da707SZhi Wang 658be1da707SZhi Wang static inline void print_opcode(u32 cmd, int ring_id) 659be1da707SZhi Wang { 660be1da707SZhi Wang struct decode_info *d_info; 661be1da707SZhi Wang int i; 662be1da707SZhi Wang 663be1da707SZhi Wang if (ring_id >= I915_NUM_ENGINES) 664be1da707SZhi Wang return; 665be1da707SZhi Wang 666be1da707SZhi Wang d_info = ring_decode_info[ring_id][CMD_TYPE(cmd)]; 667be1da707SZhi Wang if (d_info == NULL) 668be1da707SZhi Wang return; 669be1da707SZhi Wang 670be1da707SZhi Wang gvt_err("opcode=0x%x %s sub_ops:", 671be1da707SZhi Wang cmd >> (32 - d_info->op_len), d_info->name); 672be1da707SZhi Wang 673be1da707SZhi Wang for (i = 0; i < d_info->nr_sub_op; i++) 674be1da707SZhi Wang pr_err("0x%x ", sub_op_val(cmd, d_info->sub_op[i].hi, 675be1da707SZhi Wang d_info->sub_op[i].low)); 676be1da707SZhi Wang 677be1da707SZhi Wang pr_err("\n"); 678be1da707SZhi Wang } 679be1da707SZhi Wang 680be1da707SZhi Wang static inline u32 *cmd_ptr(struct parser_exec_state *s, int index) 681be1da707SZhi Wang { 682be1da707SZhi Wang return s->ip_va + (index << 2); 683be1da707SZhi Wang } 684be1da707SZhi Wang 685be1da707SZhi Wang static inline u32 cmd_val(struct parser_exec_state *s, int index) 686be1da707SZhi Wang { 687be1da707SZhi Wang return *cmd_ptr(s, index); 688be1da707SZhi Wang } 689be1da707SZhi Wang 690be1da707SZhi Wang static void parser_exec_state_dump(struct parser_exec_state *s) 691be1da707SZhi Wang { 692be1da707SZhi Wang int cnt = 0; 693be1da707SZhi Wang int i; 694be1da707SZhi Wang 695be1da707SZhi Wang gvt_err(" vgpu%d RING%d: ring_start(%08lx) ring_end(%08lx)" 696be1da707SZhi Wang " ring_head(%08lx) ring_tail(%08lx)\n", s->vgpu->id, 697be1da707SZhi Wang s->ring_id, s->ring_start, s->ring_start + s->ring_size, 698be1da707SZhi Wang s->ring_head, s->ring_tail); 699be1da707SZhi Wang 700be1da707SZhi Wang gvt_err(" %s %s ip_gma(%08lx) ", 701be1da707SZhi Wang s->buf_type == RING_BUFFER_INSTRUCTION ? 702be1da707SZhi Wang "RING_BUFFER" : "BATCH_BUFFER", 703be1da707SZhi Wang s->buf_addr_type == GTT_BUFFER ? 704be1da707SZhi Wang "GTT" : "PPGTT", s->ip_gma); 705be1da707SZhi Wang 706be1da707SZhi Wang if (s->ip_va == NULL) { 707be1da707SZhi Wang gvt_err(" ip_va(NULL)"); 708be1da707SZhi Wang return; 709be1da707SZhi Wang } 710be1da707SZhi Wang 711be1da707SZhi Wang gvt_err(" ip_va=%p: %08x %08x %08x %08x\n", 712be1da707SZhi Wang s->ip_va, cmd_val(s, 0), cmd_val(s, 1), 713be1da707SZhi Wang cmd_val(s, 2), cmd_val(s, 3)); 714be1da707SZhi Wang 715be1da707SZhi Wang print_opcode(cmd_val(s, 0), s->ring_id); 716be1da707SZhi Wang 717be1da707SZhi Wang /* print the whole page to trace */ 718be1da707SZhi Wang pr_err(" ip_va=%p: %08x %08x %08x %08x\n", 719be1da707SZhi Wang s->ip_va, cmd_val(s, 0), cmd_val(s, 1), 720be1da707SZhi Wang cmd_val(s, 2), cmd_val(s, 3)); 721be1da707SZhi Wang 722be1da707SZhi Wang s->ip_va = (u32 *)((((u64)s->ip_va) >> 12) << 12); 723be1da707SZhi Wang 724be1da707SZhi Wang while (cnt < 1024) { 725be1da707SZhi Wang pr_err("ip_va=%p: ", s->ip_va); 726be1da707SZhi Wang for (i = 0; i < 8; i++) 727be1da707SZhi Wang pr_err("%08x ", cmd_val(s, i)); 728be1da707SZhi Wang pr_err("\n"); 729be1da707SZhi Wang 730be1da707SZhi Wang s->ip_va += 8 * sizeof(u32); 731be1da707SZhi Wang cnt += 8; 732be1da707SZhi Wang } 733be1da707SZhi Wang } 734be1da707SZhi Wang 735be1da707SZhi Wang static inline void update_ip_va(struct parser_exec_state *s) 736be1da707SZhi Wang { 737be1da707SZhi Wang unsigned long len = 0; 738be1da707SZhi Wang 739be1da707SZhi Wang if (WARN_ON(s->ring_head == s->ring_tail)) 740be1da707SZhi Wang return; 741be1da707SZhi Wang 742be1da707SZhi Wang if (s->buf_type == RING_BUFFER_INSTRUCTION) { 743be1da707SZhi Wang unsigned long ring_top = s->ring_start + s->ring_size; 744be1da707SZhi Wang 745be1da707SZhi Wang if (s->ring_head > s->ring_tail) { 746be1da707SZhi Wang if (s->ip_gma >= s->ring_head && s->ip_gma < ring_top) 747be1da707SZhi Wang len = (s->ip_gma - s->ring_head); 748be1da707SZhi Wang else if (s->ip_gma >= s->ring_start && 749be1da707SZhi Wang s->ip_gma <= s->ring_tail) 750be1da707SZhi Wang len = (ring_top - s->ring_head) + 751be1da707SZhi Wang (s->ip_gma - s->ring_start); 752be1da707SZhi Wang } else 753be1da707SZhi Wang len = (s->ip_gma - s->ring_head); 754be1da707SZhi Wang 755be1da707SZhi Wang s->ip_va = s->rb_va + len; 756be1da707SZhi Wang } else {/* shadow batch buffer */ 757be1da707SZhi Wang s->ip_va = s->ret_bb_va; 758be1da707SZhi Wang } 759be1da707SZhi Wang } 760be1da707SZhi Wang 761be1da707SZhi Wang static inline int ip_gma_set(struct parser_exec_state *s, 762be1da707SZhi Wang unsigned long ip_gma) 763be1da707SZhi Wang { 764be1da707SZhi Wang WARN_ON(!IS_ALIGNED(ip_gma, 4)); 765be1da707SZhi Wang 766be1da707SZhi Wang s->ip_gma = ip_gma; 767be1da707SZhi Wang update_ip_va(s); 768be1da707SZhi Wang return 0; 769be1da707SZhi Wang } 770be1da707SZhi Wang 771be1da707SZhi Wang static inline int ip_gma_advance(struct parser_exec_state *s, 772be1da707SZhi Wang unsigned int dw_len) 773be1da707SZhi Wang { 774be1da707SZhi Wang s->ip_gma += (dw_len << 2); 775be1da707SZhi Wang 776be1da707SZhi Wang if (s->buf_type == RING_BUFFER_INSTRUCTION) { 777be1da707SZhi Wang if (s->ip_gma >= s->ring_start + s->ring_size) 778be1da707SZhi Wang s->ip_gma -= s->ring_size; 779be1da707SZhi Wang update_ip_va(s); 780be1da707SZhi Wang } else { 781be1da707SZhi Wang s->ip_va += (dw_len << 2); 782be1da707SZhi Wang } 783be1da707SZhi Wang 784be1da707SZhi Wang return 0; 785be1da707SZhi Wang } 786be1da707SZhi Wang 787be1da707SZhi Wang static inline int get_cmd_length(struct cmd_info *info, u32 cmd) 788be1da707SZhi Wang { 789be1da707SZhi Wang if ((info->flag & F_LEN_MASK) == F_LEN_CONST) 790be1da707SZhi Wang return info->len; 791be1da707SZhi Wang else 792be1da707SZhi Wang return (cmd & ((1U << info->len) - 1)) + 2; 793be1da707SZhi Wang return 0; 794be1da707SZhi Wang } 795be1da707SZhi Wang 796be1da707SZhi Wang static inline int cmd_length(struct parser_exec_state *s) 797be1da707SZhi Wang { 798be1da707SZhi Wang return get_cmd_length(s->info, cmd_val(s, 0)); 799be1da707SZhi Wang } 800be1da707SZhi Wang 801be1da707SZhi Wang /* do not remove this, some platform may need clflush here */ 802be1da707SZhi Wang #define patch_value(s, addr, val) do { \ 803be1da707SZhi Wang *addr = val; \ 804be1da707SZhi Wang } while (0) 805be1da707SZhi Wang 806be1da707SZhi Wang static bool is_shadowed_mmio(unsigned int offset) 807be1da707SZhi Wang { 808be1da707SZhi Wang bool ret = false; 809be1da707SZhi Wang 810be1da707SZhi Wang if ((offset == 0x2168) || /*BB current head register UDW */ 811be1da707SZhi Wang (offset == 0x2140) || /*BB current header register */ 812be1da707SZhi Wang (offset == 0x211c) || /*second BB header register UDW */ 813be1da707SZhi Wang (offset == 0x2114)) { /*second BB header register UDW */ 814be1da707SZhi Wang ret = true; 815be1da707SZhi Wang } 816be1da707SZhi Wang return ret; 817be1da707SZhi Wang } 818be1da707SZhi Wang 819be1da707SZhi Wang static int cmd_reg_handler(struct parser_exec_state *s, 820be1da707SZhi Wang unsigned int offset, unsigned int index, char *cmd) 821be1da707SZhi Wang { 822be1da707SZhi Wang struct intel_vgpu *vgpu = s->vgpu; 823be1da707SZhi Wang struct intel_gvt *gvt = vgpu->gvt; 824be1da707SZhi Wang 825be1da707SZhi Wang if (offset + 4 > gvt->device_info.mmio_size) { 826be1da707SZhi Wang gvt_err("%s access to (%x) outside of MMIO range\n", 827be1da707SZhi Wang cmd, offset); 828be1da707SZhi Wang return -EINVAL; 829be1da707SZhi Wang } 830be1da707SZhi Wang 831be1da707SZhi Wang if (!intel_gvt_mmio_is_cmd_access(gvt, offset)) { 832be1da707SZhi Wang gvt_err("vgpu%d: %s access to non-render register (%x)\n", 833be1da707SZhi Wang s->vgpu->id, cmd, offset); 834be1da707SZhi Wang return 0; 835be1da707SZhi Wang } 836be1da707SZhi Wang 837be1da707SZhi Wang if (is_shadowed_mmio(offset)) { 838be1da707SZhi Wang gvt_err("vgpu%d: found access of shadowed MMIO %x\n", 839be1da707SZhi Wang s->vgpu->id, offset); 840be1da707SZhi Wang return 0; 841be1da707SZhi Wang } 842be1da707SZhi Wang 843be1da707SZhi Wang if (offset == i915_mmio_reg_offset(DERRMR) || 844be1da707SZhi Wang offset == i915_mmio_reg_offset(FORCEWAKE_MT)) { 845be1da707SZhi Wang /* Writing to HW VGT_PVINFO_PAGE offset will be discarded */ 846be1da707SZhi Wang patch_value(s, cmd_ptr(s, index), VGT_PVINFO_PAGE); 847be1da707SZhi Wang } 848be1da707SZhi Wang 849be1da707SZhi Wang /* TODO: Update the global mask if this MMIO is a masked-MMIO */ 850be1da707SZhi Wang intel_gvt_mmio_set_cmd_accessed(gvt, offset); 851be1da707SZhi Wang return 0; 852be1da707SZhi Wang } 853be1da707SZhi Wang 854be1da707SZhi Wang #define cmd_reg(s, i) \ 855be1da707SZhi Wang (cmd_val(s, i) & GENMASK(22, 2)) 856be1da707SZhi Wang 857be1da707SZhi Wang #define cmd_reg_inhibit(s, i) \ 858be1da707SZhi Wang (cmd_val(s, i) & GENMASK(22, 18)) 859be1da707SZhi Wang 860be1da707SZhi Wang #define cmd_gma(s, i) \ 861be1da707SZhi Wang (cmd_val(s, i) & GENMASK(31, 2)) 862be1da707SZhi Wang 863be1da707SZhi Wang #define cmd_gma_hi(s, i) \ 864be1da707SZhi Wang (cmd_val(s, i) & GENMASK(15, 0)) 865be1da707SZhi Wang 866be1da707SZhi Wang static int cmd_handler_lri(struct parser_exec_state *s) 867be1da707SZhi Wang { 868be1da707SZhi Wang int i, ret = 0; 869be1da707SZhi Wang int cmd_len = cmd_length(s); 870be1da707SZhi Wang struct intel_gvt *gvt = s->vgpu->gvt; 871be1da707SZhi Wang 872be1da707SZhi Wang for (i = 1; i < cmd_len; i += 2) { 873be1da707SZhi Wang if (IS_BROADWELL(gvt->dev_priv) && 874be1da707SZhi Wang (s->ring_id != RCS)) { 875be1da707SZhi Wang if (s->ring_id == BCS && 876be1da707SZhi Wang cmd_reg(s, i) == 877be1da707SZhi Wang i915_mmio_reg_offset(DERRMR)) 878be1da707SZhi Wang ret |= 0; 879be1da707SZhi Wang else 880be1da707SZhi Wang ret |= (cmd_reg_inhibit(s, i)) ? -EINVAL : 0; 881be1da707SZhi Wang } 882be1da707SZhi Wang if (ret) 883be1da707SZhi Wang break; 884be1da707SZhi Wang ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lri"); 885be1da707SZhi Wang } 886be1da707SZhi Wang return ret; 887be1da707SZhi Wang } 888be1da707SZhi Wang 889be1da707SZhi Wang static int cmd_handler_lrr(struct parser_exec_state *s) 890be1da707SZhi Wang { 891be1da707SZhi Wang int i, ret = 0; 892be1da707SZhi Wang int cmd_len = cmd_length(s); 893be1da707SZhi Wang 894be1da707SZhi Wang for (i = 1; i < cmd_len; i += 2) { 895be1da707SZhi Wang if (IS_BROADWELL(s->vgpu->gvt->dev_priv)) 896be1da707SZhi Wang ret |= ((cmd_reg_inhibit(s, i) || 897be1da707SZhi Wang (cmd_reg_inhibit(s, i + 1)))) ? 898be1da707SZhi Wang -EINVAL : 0; 899be1da707SZhi Wang if (ret) 900be1da707SZhi Wang break; 901be1da707SZhi Wang ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrr-src"); 902be1da707SZhi Wang ret |= cmd_reg_handler(s, cmd_reg(s, i + 1), i, "lrr-dst"); 903be1da707SZhi Wang } 904be1da707SZhi Wang return ret; 905be1da707SZhi Wang } 906be1da707SZhi Wang 907be1da707SZhi Wang static inline int cmd_address_audit(struct parser_exec_state *s, 908be1da707SZhi Wang unsigned long guest_gma, int op_size, bool index_mode); 909be1da707SZhi Wang 910be1da707SZhi Wang static int cmd_handler_lrm(struct parser_exec_state *s) 911be1da707SZhi Wang { 912be1da707SZhi Wang struct intel_gvt *gvt = s->vgpu->gvt; 913be1da707SZhi Wang int gmadr_bytes = gvt->device_info.gmadr_bytes_in_cmd; 914be1da707SZhi Wang unsigned long gma; 915be1da707SZhi Wang int i, ret = 0; 916be1da707SZhi Wang int cmd_len = cmd_length(s); 917be1da707SZhi Wang 918be1da707SZhi Wang for (i = 1; i < cmd_len;) { 919be1da707SZhi Wang if (IS_BROADWELL(gvt->dev_priv)) 920be1da707SZhi Wang ret |= (cmd_reg_inhibit(s, i)) ? -EINVAL : 0; 921be1da707SZhi Wang if (ret) 922be1da707SZhi Wang break; 923be1da707SZhi Wang ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrm"); 924be1da707SZhi Wang if (cmd_val(s, 0) & (1 << 22)) { 925be1da707SZhi Wang gma = cmd_gma(s, i + 1); 926be1da707SZhi Wang if (gmadr_bytes == 8) 927be1da707SZhi Wang gma |= (cmd_gma_hi(s, i + 2)) << 32; 928be1da707SZhi Wang ret |= cmd_address_audit(s, gma, sizeof(u32), false); 929be1da707SZhi Wang } 930be1da707SZhi Wang i += gmadr_dw_number(s) + 1; 931be1da707SZhi Wang } 932be1da707SZhi Wang return ret; 933be1da707SZhi Wang } 934be1da707SZhi Wang 935be1da707SZhi Wang static int cmd_handler_srm(struct parser_exec_state *s) 936be1da707SZhi Wang { 937be1da707SZhi Wang int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd; 938be1da707SZhi Wang unsigned long gma; 939be1da707SZhi Wang int i, ret = 0; 940be1da707SZhi Wang int cmd_len = cmd_length(s); 941be1da707SZhi Wang 942be1da707SZhi Wang for (i = 1; i < cmd_len;) { 943be1da707SZhi Wang ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "srm"); 944be1da707SZhi Wang if (cmd_val(s, 0) & (1 << 22)) { 945be1da707SZhi Wang gma = cmd_gma(s, i + 1); 946be1da707SZhi Wang if (gmadr_bytes == 8) 947be1da707SZhi Wang gma |= (cmd_gma_hi(s, i + 2)) << 32; 948be1da707SZhi Wang ret |= cmd_address_audit(s, gma, sizeof(u32), false); 949be1da707SZhi Wang } 950be1da707SZhi Wang i += gmadr_dw_number(s) + 1; 951be1da707SZhi Wang } 952be1da707SZhi Wang return ret; 953be1da707SZhi Wang } 954be1da707SZhi Wang 955be1da707SZhi Wang struct cmd_interrupt_event { 956be1da707SZhi Wang int pipe_control_notify; 957be1da707SZhi Wang int mi_flush_dw; 958be1da707SZhi Wang int mi_user_interrupt; 959be1da707SZhi Wang }; 960be1da707SZhi Wang 961be1da707SZhi Wang struct cmd_interrupt_event cmd_interrupt_events[] = { 962be1da707SZhi Wang [RCS] = { 963be1da707SZhi Wang .pipe_control_notify = RCS_PIPE_CONTROL, 964be1da707SZhi Wang .mi_flush_dw = INTEL_GVT_EVENT_RESERVED, 965be1da707SZhi Wang .mi_user_interrupt = RCS_MI_USER_INTERRUPT, 966be1da707SZhi Wang }, 967be1da707SZhi Wang [BCS] = { 968be1da707SZhi Wang .pipe_control_notify = INTEL_GVT_EVENT_RESERVED, 969be1da707SZhi Wang .mi_flush_dw = BCS_MI_FLUSH_DW, 970be1da707SZhi Wang .mi_user_interrupt = BCS_MI_USER_INTERRUPT, 971be1da707SZhi Wang }, 972be1da707SZhi Wang [VCS] = { 973be1da707SZhi Wang .pipe_control_notify = INTEL_GVT_EVENT_RESERVED, 974be1da707SZhi Wang .mi_flush_dw = VCS_MI_FLUSH_DW, 975be1da707SZhi Wang .mi_user_interrupt = VCS_MI_USER_INTERRUPT, 976be1da707SZhi Wang }, 977be1da707SZhi Wang [VCS2] = { 978be1da707SZhi Wang .pipe_control_notify = INTEL_GVT_EVENT_RESERVED, 979be1da707SZhi Wang .mi_flush_dw = VCS2_MI_FLUSH_DW, 980be1da707SZhi Wang .mi_user_interrupt = VCS2_MI_USER_INTERRUPT, 981be1da707SZhi Wang }, 982be1da707SZhi Wang [VECS] = { 983be1da707SZhi Wang .pipe_control_notify = INTEL_GVT_EVENT_RESERVED, 984be1da707SZhi Wang .mi_flush_dw = VECS_MI_FLUSH_DW, 985be1da707SZhi Wang .mi_user_interrupt = VECS_MI_USER_INTERRUPT, 986be1da707SZhi Wang }, 987be1da707SZhi Wang }; 988be1da707SZhi Wang 989be1da707SZhi Wang static int cmd_handler_pipe_control(struct parser_exec_state *s) 990be1da707SZhi Wang { 991be1da707SZhi Wang int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd; 992be1da707SZhi Wang unsigned long gma; 993be1da707SZhi Wang bool index_mode = false; 994be1da707SZhi Wang unsigned int post_sync; 995be1da707SZhi Wang int ret = 0; 996be1da707SZhi Wang 997be1da707SZhi Wang post_sync = (cmd_val(s, 1) & PIPE_CONTROL_POST_SYNC_OP_MASK) >> 14; 998be1da707SZhi Wang 999be1da707SZhi Wang /* LRI post sync */ 1000be1da707SZhi Wang if (cmd_val(s, 1) & PIPE_CONTROL_MMIO_WRITE) 1001be1da707SZhi Wang ret = cmd_reg_handler(s, cmd_reg(s, 2), 1, "pipe_ctrl"); 1002be1da707SZhi Wang /* post sync */ 1003be1da707SZhi Wang else if (post_sync) { 1004be1da707SZhi Wang if (post_sync == 2) 1005be1da707SZhi Wang ret = cmd_reg_handler(s, 0x2350, 1, "pipe_ctrl"); 1006be1da707SZhi Wang else if (post_sync == 3) 1007be1da707SZhi Wang ret = cmd_reg_handler(s, 0x2358, 1, "pipe_ctrl"); 1008be1da707SZhi Wang else if (post_sync == 1) { 1009be1da707SZhi Wang /* check ggtt*/ 1010be1da707SZhi Wang if ((cmd_val(s, 2) & (1 << 2))) { 1011be1da707SZhi Wang gma = cmd_val(s, 2) & GENMASK(31, 3); 1012be1da707SZhi Wang if (gmadr_bytes == 8) 1013be1da707SZhi Wang gma |= (cmd_gma_hi(s, 3)) << 32; 1014be1da707SZhi Wang /* Store Data Index */ 1015be1da707SZhi Wang if (cmd_val(s, 1) & (1 << 21)) 1016be1da707SZhi Wang index_mode = true; 1017be1da707SZhi Wang ret |= cmd_address_audit(s, gma, sizeof(u64), 1018be1da707SZhi Wang index_mode); 1019be1da707SZhi Wang } 1020be1da707SZhi Wang } 1021be1da707SZhi Wang } 1022be1da707SZhi Wang 1023be1da707SZhi Wang if (ret) 1024be1da707SZhi Wang return ret; 1025be1da707SZhi Wang 1026be1da707SZhi Wang if (cmd_val(s, 1) & PIPE_CONTROL_NOTIFY) 1027be1da707SZhi Wang set_bit(cmd_interrupt_events[s->ring_id].pipe_control_notify, 1028be1da707SZhi Wang s->workload->pending_events); 1029be1da707SZhi Wang return 0; 1030be1da707SZhi Wang } 1031be1da707SZhi Wang 1032be1da707SZhi Wang static int cmd_handler_mi_user_interrupt(struct parser_exec_state *s) 1033be1da707SZhi Wang { 1034be1da707SZhi Wang set_bit(cmd_interrupt_events[s->ring_id].mi_user_interrupt, 1035be1da707SZhi Wang s->workload->pending_events); 1036be1da707SZhi Wang return 0; 1037be1da707SZhi Wang } 1038be1da707SZhi Wang 1039be1da707SZhi Wang static int cmd_advance_default(struct parser_exec_state *s) 1040be1da707SZhi Wang { 1041be1da707SZhi Wang return ip_gma_advance(s, cmd_length(s)); 1042be1da707SZhi Wang } 1043be1da707SZhi Wang 1044be1da707SZhi Wang static int cmd_handler_mi_batch_buffer_end(struct parser_exec_state *s) 1045be1da707SZhi Wang { 1046be1da707SZhi Wang int ret; 1047be1da707SZhi Wang 1048be1da707SZhi Wang if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) { 1049be1da707SZhi Wang s->buf_type = BATCH_BUFFER_INSTRUCTION; 1050be1da707SZhi Wang ret = ip_gma_set(s, s->ret_ip_gma_bb); 1051be1da707SZhi Wang s->buf_addr_type = s->saved_buf_addr_type; 1052be1da707SZhi Wang } else { 1053be1da707SZhi Wang s->buf_type = RING_BUFFER_INSTRUCTION; 1054be1da707SZhi Wang s->buf_addr_type = GTT_BUFFER; 1055be1da707SZhi Wang if (s->ret_ip_gma_ring >= s->ring_start + s->ring_size) 1056be1da707SZhi Wang s->ret_ip_gma_ring -= s->ring_size; 1057be1da707SZhi Wang ret = ip_gma_set(s, s->ret_ip_gma_ring); 1058be1da707SZhi Wang } 1059be1da707SZhi Wang return ret; 1060be1da707SZhi Wang } 1061be1da707SZhi Wang 1062be1da707SZhi Wang struct mi_display_flip_command_info { 1063be1da707SZhi Wang int pipe; 1064be1da707SZhi Wang int plane; 1065be1da707SZhi Wang int event; 1066be1da707SZhi Wang i915_reg_t stride_reg; 1067be1da707SZhi Wang i915_reg_t ctrl_reg; 1068be1da707SZhi Wang i915_reg_t surf_reg; 1069be1da707SZhi Wang u64 stride_val; 1070be1da707SZhi Wang u64 tile_val; 1071be1da707SZhi Wang u64 surf_val; 1072be1da707SZhi Wang bool async_flip; 1073be1da707SZhi Wang }; 1074be1da707SZhi Wang 1075be1da707SZhi Wang struct plane_code_mapping { 1076be1da707SZhi Wang int pipe; 1077be1da707SZhi Wang int plane; 1078be1da707SZhi Wang int event; 1079be1da707SZhi Wang }; 1080be1da707SZhi Wang 1081be1da707SZhi Wang static int gen8_decode_mi_display_flip(struct parser_exec_state *s, 1082be1da707SZhi Wang struct mi_display_flip_command_info *info) 1083be1da707SZhi Wang { 1084be1da707SZhi Wang struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv; 1085be1da707SZhi Wang struct plane_code_mapping gen8_plane_code[] = { 1086be1da707SZhi Wang [0] = {PIPE_A, PLANE_A, PRIMARY_A_FLIP_DONE}, 1087be1da707SZhi Wang [1] = {PIPE_B, PLANE_A, PRIMARY_B_FLIP_DONE}, 1088be1da707SZhi Wang [2] = {PIPE_A, PLANE_B, SPRITE_A_FLIP_DONE}, 1089be1da707SZhi Wang [3] = {PIPE_B, PLANE_B, SPRITE_B_FLIP_DONE}, 1090be1da707SZhi Wang [4] = {PIPE_C, PLANE_A, PRIMARY_C_FLIP_DONE}, 1091be1da707SZhi Wang [5] = {PIPE_C, PLANE_B, SPRITE_C_FLIP_DONE}, 1092be1da707SZhi Wang }; 1093be1da707SZhi Wang u32 dword0, dword1, dword2; 1094be1da707SZhi Wang u32 v; 1095be1da707SZhi Wang 1096be1da707SZhi Wang dword0 = cmd_val(s, 0); 1097be1da707SZhi Wang dword1 = cmd_val(s, 1); 1098be1da707SZhi Wang dword2 = cmd_val(s, 2); 1099be1da707SZhi Wang 1100be1da707SZhi Wang v = (dword0 & GENMASK(21, 19)) >> 19; 1101be1da707SZhi Wang if (WARN_ON(v >= ARRAY_SIZE(gen8_plane_code))) 1102be1da707SZhi Wang return -EINVAL; 1103be1da707SZhi Wang 1104be1da707SZhi Wang info->pipe = gen8_plane_code[v].pipe; 1105be1da707SZhi Wang info->plane = gen8_plane_code[v].plane; 1106be1da707SZhi Wang info->event = gen8_plane_code[v].event; 1107be1da707SZhi Wang info->stride_val = (dword1 & GENMASK(15, 6)) >> 6; 1108be1da707SZhi Wang info->tile_val = (dword1 & 0x1); 1109be1da707SZhi Wang info->surf_val = (dword2 & GENMASK(31, 12)) >> 12; 1110be1da707SZhi Wang info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1); 1111be1da707SZhi Wang 1112be1da707SZhi Wang if (info->plane == PLANE_A) { 1113be1da707SZhi Wang info->ctrl_reg = DSPCNTR(info->pipe); 1114be1da707SZhi Wang info->stride_reg = DSPSTRIDE(info->pipe); 1115be1da707SZhi Wang info->surf_reg = DSPSURF(info->pipe); 1116be1da707SZhi Wang } else if (info->plane == PLANE_B) { 1117be1da707SZhi Wang info->ctrl_reg = SPRCTL(info->pipe); 1118be1da707SZhi Wang info->stride_reg = SPRSTRIDE(info->pipe); 1119be1da707SZhi Wang info->surf_reg = SPRSURF(info->pipe); 1120be1da707SZhi Wang } else { 1121be1da707SZhi Wang WARN_ON(1); 1122be1da707SZhi Wang return -EINVAL; 1123be1da707SZhi Wang } 1124be1da707SZhi Wang return 0; 1125be1da707SZhi Wang } 1126be1da707SZhi Wang 1127be1da707SZhi Wang static int skl_decode_mi_display_flip(struct parser_exec_state *s, 1128be1da707SZhi Wang struct mi_display_flip_command_info *info) 1129be1da707SZhi Wang { 1130be1da707SZhi Wang struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv; 1131be1da707SZhi Wang u32 dword0 = cmd_val(s, 0); 1132be1da707SZhi Wang u32 dword1 = cmd_val(s, 1); 1133be1da707SZhi Wang u32 dword2 = cmd_val(s, 2); 1134be1da707SZhi Wang u32 plane = (dword0 & GENMASK(12, 8)) >> 8; 1135be1da707SZhi Wang 1136be1da707SZhi Wang switch (plane) { 1137be1da707SZhi Wang case MI_DISPLAY_FLIP_SKL_PLANE_1_A: 1138be1da707SZhi Wang info->pipe = PIPE_A; 1139be1da707SZhi Wang info->event = PRIMARY_A_FLIP_DONE; 1140be1da707SZhi Wang break; 1141be1da707SZhi Wang case MI_DISPLAY_FLIP_SKL_PLANE_1_B: 1142be1da707SZhi Wang info->pipe = PIPE_B; 1143be1da707SZhi Wang info->event = PRIMARY_B_FLIP_DONE; 1144be1da707SZhi Wang break; 1145be1da707SZhi Wang case MI_DISPLAY_FLIP_SKL_PLANE_1_C: 1146be1da707SZhi Wang info->pipe = PIPE_B; 1147be1da707SZhi Wang info->event = PRIMARY_C_FLIP_DONE; 1148be1da707SZhi Wang break; 1149be1da707SZhi Wang default: 1150be1da707SZhi Wang gvt_err("unknown plane code %d\n", plane); 1151be1da707SZhi Wang return -EINVAL; 1152be1da707SZhi Wang } 1153be1da707SZhi Wang 1154be1da707SZhi Wang info->pipe = PRIMARY_PLANE; 1155be1da707SZhi Wang info->stride_val = (dword1 & GENMASK(15, 6)) >> 6; 1156be1da707SZhi Wang info->tile_val = (dword1 & GENMASK(2, 0)); 1157be1da707SZhi Wang info->surf_val = (dword2 & GENMASK(31, 12)) >> 12; 1158be1da707SZhi Wang info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1); 1159be1da707SZhi Wang 1160be1da707SZhi Wang info->ctrl_reg = DSPCNTR(info->pipe); 1161be1da707SZhi Wang info->stride_reg = DSPSTRIDE(info->pipe); 1162be1da707SZhi Wang info->surf_reg = DSPSURF(info->pipe); 1163be1da707SZhi Wang 1164be1da707SZhi Wang return 0; 1165be1da707SZhi Wang } 1166be1da707SZhi Wang 1167be1da707SZhi Wang static int gen8_check_mi_display_flip(struct parser_exec_state *s, 1168be1da707SZhi Wang struct mi_display_flip_command_info *info) 1169be1da707SZhi Wang { 1170be1da707SZhi Wang struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv; 1171be1da707SZhi Wang u32 stride, tile; 1172be1da707SZhi Wang 1173be1da707SZhi Wang if (!info->async_flip) 1174be1da707SZhi Wang return 0; 1175be1da707SZhi Wang 1176be1da707SZhi Wang if (IS_SKYLAKE(dev_priv)) { 1177be1da707SZhi Wang stride = vgpu_vreg(s->vgpu, info->stride_reg) & GENMASK(9, 0); 1178be1da707SZhi Wang tile = (vgpu_vreg(s->vgpu, info->ctrl_reg) & 1179be1da707SZhi Wang GENMASK(12, 10)) >> 10; 1180be1da707SZhi Wang } else { 1181be1da707SZhi Wang stride = (vgpu_vreg(s->vgpu, info->stride_reg) & 1182be1da707SZhi Wang GENMASK(15, 6)) >> 6; 1183be1da707SZhi Wang tile = (vgpu_vreg(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10; 1184be1da707SZhi Wang } 1185be1da707SZhi Wang 1186be1da707SZhi Wang if (stride != info->stride_val) 1187be1da707SZhi Wang gvt_dbg_cmd("cannot change stride during async flip\n"); 1188be1da707SZhi Wang 1189be1da707SZhi Wang if (tile != info->tile_val) 1190be1da707SZhi Wang gvt_dbg_cmd("cannot change tile during async flip\n"); 1191be1da707SZhi Wang 1192be1da707SZhi Wang return 0; 1193be1da707SZhi Wang } 1194be1da707SZhi Wang 1195be1da707SZhi Wang static int gen8_update_plane_mmio_from_mi_display_flip( 1196be1da707SZhi Wang struct parser_exec_state *s, 1197be1da707SZhi Wang struct mi_display_flip_command_info *info) 1198be1da707SZhi Wang { 1199be1da707SZhi Wang struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv; 1200be1da707SZhi Wang struct intel_vgpu *vgpu = s->vgpu; 1201be1da707SZhi Wang 1202be1da707SZhi Wang #define write_bits(reg, e, s, v) do { \ 1203be1da707SZhi Wang vgpu_vreg(vgpu, reg) &= ~GENMASK(e, s); \ 1204be1da707SZhi Wang vgpu_vreg(vgpu, reg) |= (v << s); \ 1205be1da707SZhi Wang } while (0) 1206be1da707SZhi Wang 1207be1da707SZhi Wang write_bits(info->surf_reg, 31, 12, info->surf_val); 1208be1da707SZhi Wang if (IS_SKYLAKE(dev_priv)) 1209be1da707SZhi Wang write_bits(info->stride_reg, 9, 0, info->stride_val); 1210be1da707SZhi Wang else 1211be1da707SZhi Wang write_bits(info->stride_reg, 15, 6, info->stride_val); 1212be1da707SZhi Wang write_bits(info->ctrl_reg, IS_SKYLAKE(dev_priv) ? 12 : 10, 1213be1da707SZhi Wang 10, info->tile_val); 1214be1da707SZhi Wang 1215be1da707SZhi Wang #undef write_bits 1216be1da707SZhi Wang 1217be1da707SZhi Wang vgpu_vreg(vgpu, PIPE_FRMCOUNT_G4X(info->pipe))++; 1218be1da707SZhi Wang intel_vgpu_trigger_virtual_event(vgpu, info->event); 1219be1da707SZhi Wang return 0; 1220be1da707SZhi Wang } 1221be1da707SZhi Wang 1222be1da707SZhi Wang static int decode_mi_display_flip(struct parser_exec_state *s, 1223be1da707SZhi Wang struct mi_display_flip_command_info *info) 1224be1da707SZhi Wang { 1225be1da707SZhi Wang struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv; 1226be1da707SZhi Wang 1227be1da707SZhi Wang if (IS_BROADWELL(dev_priv)) 1228be1da707SZhi Wang return gen8_decode_mi_display_flip(s, info); 1229be1da707SZhi Wang if (IS_SKYLAKE(dev_priv)) 1230be1da707SZhi Wang return skl_decode_mi_display_flip(s, info); 1231be1da707SZhi Wang 1232be1da707SZhi Wang return -ENODEV; 1233be1da707SZhi Wang } 1234be1da707SZhi Wang 1235be1da707SZhi Wang static int check_mi_display_flip(struct parser_exec_state *s, 1236be1da707SZhi Wang struct mi_display_flip_command_info *info) 1237be1da707SZhi Wang { 1238be1da707SZhi Wang struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv; 1239be1da707SZhi Wang 1240be1da707SZhi Wang if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv)) 1241be1da707SZhi Wang return gen8_check_mi_display_flip(s, info); 1242be1da707SZhi Wang return -ENODEV; 1243be1da707SZhi Wang } 1244be1da707SZhi Wang 1245be1da707SZhi Wang static int update_plane_mmio_from_mi_display_flip( 1246be1da707SZhi Wang struct parser_exec_state *s, 1247be1da707SZhi Wang struct mi_display_flip_command_info *info) 1248be1da707SZhi Wang { 1249be1da707SZhi Wang struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv; 1250be1da707SZhi Wang 1251be1da707SZhi Wang if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv)) 1252be1da707SZhi Wang return gen8_update_plane_mmio_from_mi_display_flip(s, info); 1253be1da707SZhi Wang return -ENODEV; 1254be1da707SZhi Wang } 1255be1da707SZhi Wang 1256be1da707SZhi Wang static int cmd_handler_mi_display_flip(struct parser_exec_state *s) 1257be1da707SZhi Wang { 1258be1da707SZhi Wang struct mi_display_flip_command_info info; 1259be1da707SZhi Wang int ret; 1260be1da707SZhi Wang int i; 1261be1da707SZhi Wang int len = cmd_length(s); 1262be1da707SZhi Wang 1263be1da707SZhi Wang ret = decode_mi_display_flip(s, &info); 1264be1da707SZhi Wang if (ret) { 1265be1da707SZhi Wang gvt_err("fail to decode MI display flip command\n"); 1266be1da707SZhi Wang return ret; 1267be1da707SZhi Wang } 1268be1da707SZhi Wang 1269be1da707SZhi Wang ret = check_mi_display_flip(s, &info); 1270be1da707SZhi Wang if (ret) { 1271be1da707SZhi Wang gvt_err("invalid MI display flip command\n"); 1272be1da707SZhi Wang return ret; 1273be1da707SZhi Wang } 1274be1da707SZhi Wang 1275be1da707SZhi Wang ret = update_plane_mmio_from_mi_display_flip(s, &info); 1276be1da707SZhi Wang if (ret) { 1277be1da707SZhi Wang gvt_err("fail to update plane mmio\n"); 1278be1da707SZhi Wang return ret; 1279be1da707SZhi Wang } 1280be1da707SZhi Wang 1281be1da707SZhi Wang for (i = 0; i < len; i++) 1282be1da707SZhi Wang patch_value(s, cmd_ptr(s, i), MI_NOOP); 1283be1da707SZhi Wang return 0; 1284be1da707SZhi Wang } 1285be1da707SZhi Wang 1286be1da707SZhi Wang static bool is_wait_for_flip_pending(u32 cmd) 1287be1da707SZhi Wang { 1288be1da707SZhi Wang return cmd & (MI_WAIT_FOR_PLANE_A_FLIP_PENDING | 1289be1da707SZhi Wang MI_WAIT_FOR_PLANE_B_FLIP_PENDING | 1290be1da707SZhi Wang MI_WAIT_FOR_PLANE_C_FLIP_PENDING | 1291be1da707SZhi Wang MI_WAIT_FOR_SPRITE_A_FLIP_PENDING | 1292be1da707SZhi Wang MI_WAIT_FOR_SPRITE_B_FLIP_PENDING | 1293be1da707SZhi Wang MI_WAIT_FOR_SPRITE_C_FLIP_PENDING); 1294be1da707SZhi Wang } 1295be1da707SZhi Wang 1296be1da707SZhi Wang static int cmd_handler_mi_wait_for_event(struct parser_exec_state *s) 1297be1da707SZhi Wang { 1298be1da707SZhi Wang u32 cmd = cmd_val(s, 0); 1299be1da707SZhi Wang 1300be1da707SZhi Wang if (!is_wait_for_flip_pending(cmd)) 1301be1da707SZhi Wang return 0; 1302be1da707SZhi Wang 1303be1da707SZhi Wang patch_value(s, cmd_ptr(s, 0), MI_NOOP); 1304be1da707SZhi Wang return 0; 1305be1da707SZhi Wang } 1306be1da707SZhi Wang 1307be1da707SZhi Wang static unsigned long get_gma_bb_from_cmd(struct parser_exec_state *s, int index) 1308be1da707SZhi Wang { 1309be1da707SZhi Wang unsigned long addr; 1310be1da707SZhi Wang unsigned long gma_high, gma_low; 1311be1da707SZhi Wang int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd; 1312be1da707SZhi Wang 1313be1da707SZhi Wang if (WARN_ON(gmadr_bytes != 4 && gmadr_bytes != 8)) 1314be1da707SZhi Wang return INTEL_GVT_INVALID_ADDR; 1315be1da707SZhi Wang 1316be1da707SZhi Wang gma_low = cmd_val(s, index) & BATCH_BUFFER_ADDR_MASK; 1317be1da707SZhi Wang if (gmadr_bytes == 4) { 1318be1da707SZhi Wang addr = gma_low; 1319be1da707SZhi Wang } else { 1320be1da707SZhi Wang gma_high = cmd_val(s, index + 1) & BATCH_BUFFER_ADDR_HIGH_MASK; 1321be1da707SZhi Wang addr = (((unsigned long)gma_high) << 32) | gma_low; 1322be1da707SZhi Wang } 1323be1da707SZhi Wang return addr; 1324be1da707SZhi Wang } 1325be1da707SZhi Wang 1326be1da707SZhi Wang static inline int cmd_address_audit(struct parser_exec_state *s, 1327be1da707SZhi Wang unsigned long guest_gma, int op_size, bool index_mode) 1328be1da707SZhi Wang { 1329be1da707SZhi Wang struct intel_vgpu *vgpu = s->vgpu; 1330be1da707SZhi Wang u32 max_surface_size = vgpu->gvt->device_info.max_surface_size; 1331be1da707SZhi Wang int i; 1332be1da707SZhi Wang int ret; 1333be1da707SZhi Wang 1334be1da707SZhi Wang if (op_size > max_surface_size) { 1335be1da707SZhi Wang gvt_err("command address audit fail name %s\n", s->info->name); 1336be1da707SZhi Wang return -EINVAL; 1337be1da707SZhi Wang } 1338be1da707SZhi Wang 1339be1da707SZhi Wang if (index_mode) { 1340be1da707SZhi Wang if (guest_gma >= GTT_PAGE_SIZE / sizeof(u64)) { 1341be1da707SZhi Wang ret = -EINVAL; 1342be1da707SZhi Wang goto err; 1343be1da707SZhi Wang } 1344be1da707SZhi Wang } else if ((!vgpu_gmadr_is_valid(s->vgpu, guest_gma)) || 1345be1da707SZhi Wang (!vgpu_gmadr_is_valid(s->vgpu, 1346be1da707SZhi Wang guest_gma + op_size - 1))) { 1347be1da707SZhi Wang ret = -EINVAL; 1348be1da707SZhi Wang goto err; 1349be1da707SZhi Wang } 1350be1da707SZhi Wang return 0; 1351be1da707SZhi Wang err: 1352be1da707SZhi Wang gvt_err("cmd_parser: Malicious %s detected, addr=0x%lx, len=%d!\n", 1353be1da707SZhi Wang s->info->name, guest_gma, op_size); 1354be1da707SZhi Wang 1355be1da707SZhi Wang pr_err("cmd dump: "); 1356be1da707SZhi Wang for (i = 0; i < cmd_length(s); i++) { 1357be1da707SZhi Wang if (!(i % 4)) 1358be1da707SZhi Wang pr_err("\n%08x ", cmd_val(s, i)); 1359be1da707SZhi Wang else 1360be1da707SZhi Wang pr_err("%08x ", cmd_val(s, i)); 1361be1da707SZhi Wang } 1362be1da707SZhi Wang pr_err("\nvgpu%d: aperture 0x%llx - 0x%llx, hidden 0x%llx - 0x%llx\n", 1363be1da707SZhi Wang vgpu->id, 1364be1da707SZhi Wang vgpu_aperture_gmadr_base(vgpu), 1365be1da707SZhi Wang vgpu_aperture_gmadr_end(vgpu), 1366be1da707SZhi Wang vgpu_hidden_gmadr_base(vgpu), 1367be1da707SZhi Wang vgpu_hidden_gmadr_end(vgpu)); 1368be1da707SZhi Wang return ret; 1369be1da707SZhi Wang } 1370be1da707SZhi Wang 1371be1da707SZhi Wang static int cmd_handler_mi_store_data_imm(struct parser_exec_state *s) 1372be1da707SZhi Wang { 1373be1da707SZhi Wang int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd; 1374be1da707SZhi Wang int op_size = (cmd_length(s) - 3) * sizeof(u32); 1375be1da707SZhi Wang int core_id = (cmd_val(s, 2) & (1 << 0)) ? 1 : 0; 1376be1da707SZhi Wang unsigned long gma, gma_low, gma_high; 1377be1da707SZhi Wang int ret = 0; 1378be1da707SZhi Wang 1379be1da707SZhi Wang /* check ppggt */ 1380be1da707SZhi Wang if (!(cmd_val(s, 0) & (1 << 22))) 1381be1da707SZhi Wang return 0; 1382be1da707SZhi Wang 1383be1da707SZhi Wang gma = cmd_val(s, 2) & GENMASK(31, 2); 1384be1da707SZhi Wang 1385be1da707SZhi Wang if (gmadr_bytes == 8) { 1386be1da707SZhi Wang gma_low = cmd_val(s, 1) & GENMASK(31, 2); 1387be1da707SZhi Wang gma_high = cmd_val(s, 2) & GENMASK(15, 0); 1388be1da707SZhi Wang gma = (gma_high << 32) | gma_low; 1389be1da707SZhi Wang core_id = (cmd_val(s, 1) & (1 << 0)) ? 1 : 0; 1390be1da707SZhi Wang } 1391be1da707SZhi Wang ret = cmd_address_audit(s, gma + op_size * core_id, op_size, false); 1392be1da707SZhi Wang return ret; 1393be1da707SZhi Wang } 1394be1da707SZhi Wang 1395be1da707SZhi Wang static inline int unexpected_cmd(struct parser_exec_state *s) 1396be1da707SZhi Wang { 1397be1da707SZhi Wang gvt_err("vgpu%d: Unexpected %s in command buffer!\n", 1398be1da707SZhi Wang s->vgpu->id, s->info->name); 1399be1da707SZhi Wang return -EINVAL; 1400be1da707SZhi Wang } 1401be1da707SZhi Wang 1402be1da707SZhi Wang static int cmd_handler_mi_semaphore_wait(struct parser_exec_state *s) 1403be1da707SZhi Wang { 1404be1da707SZhi Wang return unexpected_cmd(s); 1405be1da707SZhi Wang } 1406be1da707SZhi Wang 1407be1da707SZhi Wang static int cmd_handler_mi_report_perf_count(struct parser_exec_state *s) 1408be1da707SZhi Wang { 1409be1da707SZhi Wang return unexpected_cmd(s); 1410be1da707SZhi Wang } 1411be1da707SZhi Wang 1412be1da707SZhi Wang static int cmd_handler_mi_op_2e(struct parser_exec_state *s) 1413be1da707SZhi Wang { 1414be1da707SZhi Wang return unexpected_cmd(s); 1415be1da707SZhi Wang } 1416be1da707SZhi Wang 1417be1da707SZhi Wang static int cmd_handler_mi_op_2f(struct parser_exec_state *s) 1418be1da707SZhi Wang { 1419be1da707SZhi Wang int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd; 1420be1da707SZhi Wang int op_size = ((1 << (cmd_val(s, 0) & GENMASK(20, 19) >> 19)) * 1421be1da707SZhi Wang sizeof(u32)); 1422be1da707SZhi Wang unsigned long gma, gma_high; 1423be1da707SZhi Wang int ret = 0; 1424be1da707SZhi Wang 1425be1da707SZhi Wang if (!(cmd_val(s, 0) & (1 << 22))) 1426be1da707SZhi Wang return ret; 1427be1da707SZhi Wang 1428be1da707SZhi Wang gma = cmd_val(s, 1) & GENMASK(31, 2); 1429be1da707SZhi Wang if (gmadr_bytes == 8) { 1430be1da707SZhi Wang gma_high = cmd_val(s, 2) & GENMASK(15, 0); 1431be1da707SZhi Wang gma = (gma_high << 32) | gma; 1432be1da707SZhi Wang } 1433be1da707SZhi Wang ret = cmd_address_audit(s, gma, op_size, false); 1434be1da707SZhi Wang return ret; 1435be1da707SZhi Wang } 1436be1da707SZhi Wang 1437be1da707SZhi Wang static int cmd_handler_mi_store_data_index(struct parser_exec_state *s) 1438be1da707SZhi Wang { 1439be1da707SZhi Wang return unexpected_cmd(s); 1440be1da707SZhi Wang } 1441be1da707SZhi Wang 1442be1da707SZhi Wang static int cmd_handler_mi_clflush(struct parser_exec_state *s) 1443be1da707SZhi Wang { 1444be1da707SZhi Wang return unexpected_cmd(s); 1445be1da707SZhi Wang } 1446be1da707SZhi Wang 1447be1da707SZhi Wang static int cmd_handler_mi_conditional_batch_buffer_end( 1448be1da707SZhi Wang struct parser_exec_state *s) 1449be1da707SZhi Wang { 1450be1da707SZhi Wang return unexpected_cmd(s); 1451be1da707SZhi Wang } 1452be1da707SZhi Wang 1453be1da707SZhi Wang static int cmd_handler_mi_update_gtt(struct parser_exec_state *s) 1454be1da707SZhi Wang { 1455be1da707SZhi Wang return unexpected_cmd(s); 1456be1da707SZhi Wang } 1457be1da707SZhi Wang 1458be1da707SZhi Wang static int cmd_handler_mi_flush_dw(struct parser_exec_state *s) 1459be1da707SZhi Wang { 1460be1da707SZhi Wang int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd; 1461be1da707SZhi Wang unsigned long gma; 1462be1da707SZhi Wang bool index_mode = false; 1463be1da707SZhi Wang int ret = 0; 1464be1da707SZhi Wang 1465be1da707SZhi Wang /* Check post-sync and ppgtt bit */ 1466be1da707SZhi Wang if (((cmd_val(s, 0) >> 14) & 0x3) && (cmd_val(s, 1) & (1 << 2))) { 1467be1da707SZhi Wang gma = cmd_val(s, 1) & GENMASK(31, 3); 1468be1da707SZhi Wang if (gmadr_bytes == 8) 1469be1da707SZhi Wang gma |= (cmd_val(s, 2) & GENMASK(15, 0)) << 32; 1470be1da707SZhi Wang /* Store Data Index */ 1471be1da707SZhi Wang if (cmd_val(s, 0) & (1 << 21)) 1472be1da707SZhi Wang index_mode = true; 1473be1da707SZhi Wang ret = cmd_address_audit(s, gma, sizeof(u64), index_mode); 1474be1da707SZhi Wang } 1475be1da707SZhi Wang /* Check notify bit */ 1476be1da707SZhi Wang if ((cmd_val(s, 0) & (1 << 8))) 1477be1da707SZhi Wang set_bit(cmd_interrupt_events[s->ring_id].mi_flush_dw, 1478be1da707SZhi Wang s->workload->pending_events); 1479be1da707SZhi Wang return ret; 1480be1da707SZhi Wang } 1481be1da707SZhi Wang 1482be1da707SZhi Wang static void addr_type_update_snb(struct parser_exec_state *s) 1483be1da707SZhi Wang { 1484be1da707SZhi Wang if ((s->buf_type == RING_BUFFER_INSTRUCTION) && 1485be1da707SZhi Wang (BATCH_BUFFER_ADR_SPACE_BIT(cmd_val(s, 0)) == 1)) { 1486be1da707SZhi Wang s->buf_addr_type = PPGTT_BUFFER; 1487be1da707SZhi Wang } 1488be1da707SZhi Wang } 1489be1da707SZhi Wang 1490be1da707SZhi Wang 1491be1da707SZhi Wang static int copy_gma_to_hva(struct intel_vgpu *vgpu, struct intel_vgpu_mm *mm, 1492be1da707SZhi Wang unsigned long gma, unsigned long end_gma, void *va) 1493be1da707SZhi Wang { 1494be1da707SZhi Wang unsigned long copy_len, offset; 1495be1da707SZhi Wang unsigned long len = 0; 1496be1da707SZhi Wang unsigned long gpa; 1497be1da707SZhi Wang 1498be1da707SZhi Wang while (gma != end_gma) { 1499be1da707SZhi Wang gpa = intel_vgpu_gma_to_gpa(mm, gma); 1500be1da707SZhi Wang if (gpa == INTEL_GVT_INVALID_ADDR) { 1501be1da707SZhi Wang gvt_err("invalid gma address: %lx\n", gma); 1502be1da707SZhi Wang return -EFAULT; 1503be1da707SZhi Wang } 1504be1da707SZhi Wang 1505be1da707SZhi Wang offset = gma & (GTT_PAGE_SIZE - 1); 1506be1da707SZhi Wang 1507be1da707SZhi Wang copy_len = (end_gma - gma) >= (GTT_PAGE_SIZE - offset) ? 1508be1da707SZhi Wang GTT_PAGE_SIZE - offset : end_gma - gma; 1509be1da707SZhi Wang 1510be1da707SZhi Wang intel_gvt_hypervisor_read_gpa(vgpu, gpa, va + len, copy_len); 1511be1da707SZhi Wang 1512be1da707SZhi Wang len += copy_len; 1513be1da707SZhi Wang gma += copy_len; 1514be1da707SZhi Wang } 1515be1da707SZhi Wang return 0; 1516be1da707SZhi Wang } 1517be1da707SZhi Wang 1518be1da707SZhi Wang 1519be1da707SZhi Wang /* 1520be1da707SZhi Wang * Check whether a batch buffer needs to be scanned. Currently 1521be1da707SZhi Wang * the only criteria is based on privilege. 1522be1da707SZhi Wang */ 1523be1da707SZhi Wang static int batch_buffer_needs_scan(struct parser_exec_state *s) 1524be1da707SZhi Wang { 1525be1da707SZhi Wang struct intel_gvt *gvt = s->vgpu->gvt; 1526be1da707SZhi Wang 1527be1da707SZhi Wang if (bypass_batch_buffer_scan) 1528be1da707SZhi Wang return 0; 1529be1da707SZhi Wang 1530be1da707SZhi Wang if (IS_BROADWELL(gvt->dev_priv) || IS_SKYLAKE(gvt->dev_priv)) { 1531be1da707SZhi Wang /* BDW decides privilege based on address space */ 1532be1da707SZhi Wang if (cmd_val(s, 0) & (1 << 8)) 1533be1da707SZhi Wang return 0; 1534be1da707SZhi Wang } 1535be1da707SZhi Wang return 1; 1536be1da707SZhi Wang } 1537be1da707SZhi Wang 1538be1da707SZhi Wang static uint32_t find_bb_size(struct parser_exec_state *s) 1539be1da707SZhi Wang { 1540be1da707SZhi Wang unsigned long gma = 0; 1541be1da707SZhi Wang struct cmd_info *info; 1542be1da707SZhi Wang uint32_t bb_size = 0; 1543be1da707SZhi Wang uint32_t cmd_len = 0; 1544be1da707SZhi Wang bool met_bb_end = false; 1545be1da707SZhi Wang u32 cmd; 1546be1da707SZhi Wang 1547be1da707SZhi Wang /* get the start gm address of the batch buffer */ 1548be1da707SZhi Wang gma = get_gma_bb_from_cmd(s, 1); 1549be1da707SZhi Wang cmd = cmd_val(s, 0); 1550be1da707SZhi Wang 1551be1da707SZhi Wang info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id); 1552be1da707SZhi Wang if (info == NULL) { 1553be1da707SZhi Wang gvt_err("unknown cmd 0x%x, opcode=0x%x\n", 1554be1da707SZhi Wang cmd, get_opcode(cmd, s->ring_id)); 1555be1da707SZhi Wang return -EINVAL; 1556be1da707SZhi Wang } 1557be1da707SZhi Wang do { 1558be1da707SZhi Wang copy_gma_to_hva(s->vgpu, s->vgpu->gtt.ggtt_mm, 1559be1da707SZhi Wang gma, gma + 4, &cmd); 1560be1da707SZhi Wang info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id); 1561be1da707SZhi Wang if (info == NULL) { 1562be1da707SZhi Wang gvt_err("unknown cmd 0x%x, opcode=0x%x\n", 1563be1da707SZhi Wang cmd, get_opcode(cmd, s->ring_id)); 1564be1da707SZhi Wang return -EINVAL; 1565be1da707SZhi Wang } 1566be1da707SZhi Wang 1567be1da707SZhi Wang if (info->opcode == OP_MI_BATCH_BUFFER_END) { 1568be1da707SZhi Wang met_bb_end = true; 1569be1da707SZhi Wang } else if (info->opcode == OP_MI_BATCH_BUFFER_START) { 1570be1da707SZhi Wang if (BATCH_BUFFER_2ND_LEVEL_BIT(cmd) == 0) { 1571be1da707SZhi Wang /* chained batch buffer */ 1572be1da707SZhi Wang met_bb_end = true; 1573be1da707SZhi Wang } 1574be1da707SZhi Wang } 1575be1da707SZhi Wang cmd_len = get_cmd_length(info, cmd) << 2; 1576be1da707SZhi Wang bb_size += cmd_len; 1577be1da707SZhi Wang gma += cmd_len; 1578be1da707SZhi Wang 1579be1da707SZhi Wang } while (!met_bb_end); 1580be1da707SZhi Wang 1581be1da707SZhi Wang return bb_size; 1582be1da707SZhi Wang } 1583be1da707SZhi Wang 1584be1da707SZhi Wang static u32 *vmap_batch(struct drm_i915_gem_object *obj, 1585be1da707SZhi Wang unsigned int start, unsigned int len) 1586be1da707SZhi Wang { 1587be1da707SZhi Wang int i; 1588be1da707SZhi Wang void *addr = NULL; 1589be1da707SZhi Wang struct sg_page_iter sg_iter; 1590be1da707SZhi Wang int first_page = start >> PAGE_SHIFT; 1591be1da707SZhi Wang int last_page = (len + start + 4095) >> PAGE_SHIFT; 1592be1da707SZhi Wang int npages = last_page - first_page; 1593be1da707SZhi Wang struct page **pages; 1594be1da707SZhi Wang 1595be1da707SZhi Wang pages = drm_malloc_ab(npages, sizeof(*pages)); 1596be1da707SZhi Wang if (pages == NULL) { 1597be1da707SZhi Wang DRM_DEBUG_DRIVER("Failed to get space for pages\n"); 1598be1da707SZhi Wang goto finish; 1599be1da707SZhi Wang } 1600be1da707SZhi Wang 1601be1da707SZhi Wang i = 0; 1602be1da707SZhi Wang for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 1603be1da707SZhi Wang first_page) { 1604be1da707SZhi Wang pages[i++] = sg_page_iter_page(&sg_iter); 1605be1da707SZhi Wang if (i == npages) 1606be1da707SZhi Wang break; 1607be1da707SZhi Wang } 1608be1da707SZhi Wang 1609be1da707SZhi Wang addr = vmap(pages, i, 0, PAGE_KERNEL); 1610be1da707SZhi Wang if (addr == NULL) { 1611be1da707SZhi Wang DRM_DEBUG_DRIVER("Failed to vmap pages\n"); 1612be1da707SZhi Wang goto finish; 1613be1da707SZhi Wang } 1614be1da707SZhi Wang 1615be1da707SZhi Wang finish: 1616be1da707SZhi Wang if (pages) 1617be1da707SZhi Wang drm_free_large(pages); 1618be1da707SZhi Wang return (u32 *)addr; 1619be1da707SZhi Wang } 1620be1da707SZhi Wang 1621be1da707SZhi Wang 1622be1da707SZhi Wang static int perform_bb_shadow(struct parser_exec_state *s) 1623be1da707SZhi Wang { 1624be1da707SZhi Wang struct intel_shadow_bb_entry *entry_obj; 1625be1da707SZhi Wang unsigned long gma = 0; 1626be1da707SZhi Wang uint32_t bb_size; 1627be1da707SZhi Wang void *dst = NULL; 1628be1da707SZhi Wang int ret = 0; 1629be1da707SZhi Wang 1630be1da707SZhi Wang /* get the start gm address of the batch buffer */ 1631be1da707SZhi Wang gma = get_gma_bb_from_cmd(s, 1); 1632be1da707SZhi Wang 1633be1da707SZhi Wang /* get the size of the batch buffer */ 1634be1da707SZhi Wang bb_size = find_bb_size(s); 1635be1da707SZhi Wang 1636be1da707SZhi Wang /* allocate shadow batch buffer */ 1637be1da707SZhi Wang entry_obj = kmalloc(sizeof(*entry_obj), GFP_KERNEL); 1638be1da707SZhi Wang if (entry_obj == NULL) 1639be1da707SZhi Wang return -ENOMEM; 1640be1da707SZhi Wang 1641be1da707SZhi Wang entry_obj->obj = i915_gem_object_create(&(s->vgpu->gvt->dev_priv->drm), 1642be1da707SZhi Wang round_up(bb_size, PAGE_SIZE)); 1643be1da707SZhi Wang if (entry_obj->obj == NULL) 1644be1da707SZhi Wang return -ENOMEM; 1645be1da707SZhi Wang entry_obj->len = bb_size; 1646be1da707SZhi Wang INIT_LIST_HEAD(&entry_obj->list); 1647be1da707SZhi Wang 1648be1da707SZhi Wang ret = i915_gem_object_get_pages(entry_obj->obj); 1649be1da707SZhi Wang if (ret) 1650be1da707SZhi Wang return ret; 1651be1da707SZhi Wang 1652be1da707SZhi Wang i915_gem_object_pin_pages(entry_obj->obj); 1653be1da707SZhi Wang 1654be1da707SZhi Wang /* get the va of the shadow batch buffer */ 1655be1da707SZhi Wang dst = (void *)vmap_batch(entry_obj->obj, 0, bb_size); 1656be1da707SZhi Wang if (!dst) { 1657be1da707SZhi Wang gvt_err("failed to vmap shadow batch\n"); 1658be1da707SZhi Wang ret = -ENOMEM; 1659be1da707SZhi Wang goto unpin_src; 1660be1da707SZhi Wang } 1661be1da707SZhi Wang 1662be1da707SZhi Wang ret = i915_gem_object_set_to_cpu_domain(entry_obj->obj, false); 1663be1da707SZhi Wang if (ret) { 1664be1da707SZhi Wang gvt_err("failed to set shadow batch to CPU\n"); 1665be1da707SZhi Wang goto unmap_src; 1666be1da707SZhi Wang } 1667be1da707SZhi Wang 1668be1da707SZhi Wang entry_obj->va = dst; 1669be1da707SZhi Wang entry_obj->bb_start_cmd_va = s->ip_va; 1670be1da707SZhi Wang 1671be1da707SZhi Wang /* copy batch buffer to shadow batch buffer*/ 1672be1da707SZhi Wang ret = copy_gma_to_hva(s->vgpu, s->vgpu->gtt.ggtt_mm, 1673be1da707SZhi Wang gma, gma + bb_size, dst); 1674be1da707SZhi Wang if (ret) { 1675be1da707SZhi Wang gvt_err("fail to copy guest ring buffer\n"); 1676be1da707SZhi Wang return ret; 1677be1da707SZhi Wang } 1678be1da707SZhi Wang 1679be1da707SZhi Wang list_add(&entry_obj->list, &s->workload->shadow_bb); 1680be1da707SZhi Wang /* 1681be1da707SZhi Wang * ip_va saves the virtual address of the shadow batch buffer, while 1682be1da707SZhi Wang * ip_gma saves the graphics address of the original batch buffer. 1683be1da707SZhi Wang * As the shadow batch buffer is just a copy from the originial one, 1684be1da707SZhi Wang * it should be right to use shadow batch buffer'va and original batch 1685be1da707SZhi Wang * buffer's gma in pair. After all, we don't want to pin the shadow 1686be1da707SZhi Wang * buffer here (too early). 1687be1da707SZhi Wang */ 1688be1da707SZhi Wang s->ip_va = dst; 1689be1da707SZhi Wang s->ip_gma = gma; 1690be1da707SZhi Wang 1691be1da707SZhi Wang return 0; 1692be1da707SZhi Wang 1693be1da707SZhi Wang unmap_src: 1694be1da707SZhi Wang vunmap(dst); 1695be1da707SZhi Wang unpin_src: 1696be1da707SZhi Wang i915_gem_object_unpin_pages(entry_obj->obj); 1697be1da707SZhi Wang 1698be1da707SZhi Wang return ret; 1699be1da707SZhi Wang } 1700be1da707SZhi Wang 1701be1da707SZhi Wang static int cmd_handler_mi_batch_buffer_start(struct parser_exec_state *s) 1702be1da707SZhi Wang { 1703be1da707SZhi Wang bool second_level; 1704be1da707SZhi Wang int ret = 0; 1705be1da707SZhi Wang 1706be1da707SZhi Wang if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) { 1707be1da707SZhi Wang gvt_err("Found MI_BATCH_BUFFER_START in 2nd level BB\n"); 1708be1da707SZhi Wang return -EINVAL; 1709be1da707SZhi Wang } 1710be1da707SZhi Wang 1711be1da707SZhi Wang second_level = BATCH_BUFFER_2ND_LEVEL_BIT(cmd_val(s, 0)) == 1; 1712be1da707SZhi Wang if (second_level && (s->buf_type != BATCH_BUFFER_INSTRUCTION)) { 1713be1da707SZhi Wang gvt_err("Jumping to 2nd level BB from RB is not allowed\n"); 1714be1da707SZhi Wang return -EINVAL; 1715be1da707SZhi Wang } 1716be1da707SZhi Wang 1717be1da707SZhi Wang s->saved_buf_addr_type = s->buf_addr_type; 1718be1da707SZhi Wang addr_type_update_snb(s); 1719be1da707SZhi Wang if (s->buf_type == RING_BUFFER_INSTRUCTION) { 1720be1da707SZhi Wang s->ret_ip_gma_ring = s->ip_gma + cmd_length(s) * sizeof(u32); 1721be1da707SZhi Wang s->buf_type = BATCH_BUFFER_INSTRUCTION; 1722be1da707SZhi Wang } else if (second_level) { 1723be1da707SZhi Wang s->buf_type = BATCH_BUFFER_2ND_LEVEL; 1724be1da707SZhi Wang s->ret_ip_gma_bb = s->ip_gma + cmd_length(s) * sizeof(u32); 1725be1da707SZhi Wang s->ret_bb_va = s->ip_va + cmd_length(s) * sizeof(u32); 1726be1da707SZhi Wang } 1727be1da707SZhi Wang 1728be1da707SZhi Wang if (batch_buffer_needs_scan(s)) { 1729be1da707SZhi Wang ret = perform_bb_shadow(s); 1730be1da707SZhi Wang if (ret < 0) 1731be1da707SZhi Wang gvt_err("invalid shadow batch buffer\n"); 1732be1da707SZhi Wang } else { 1733be1da707SZhi Wang /* emulate a batch buffer end to do return right */ 1734be1da707SZhi Wang ret = cmd_handler_mi_batch_buffer_end(s); 1735be1da707SZhi Wang if (ret < 0) 1736be1da707SZhi Wang return ret; 1737be1da707SZhi Wang } 1738be1da707SZhi Wang 1739be1da707SZhi Wang return ret; 1740be1da707SZhi Wang } 1741be1da707SZhi Wang 1742be1da707SZhi Wang static struct cmd_info cmd_info[] = { 1743be1da707SZhi Wang {"MI_NOOP", OP_MI_NOOP, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL}, 1744be1da707SZhi Wang 1745be1da707SZhi Wang {"MI_SET_PREDICATE", OP_MI_SET_PREDICATE, F_LEN_CONST, R_ALL, D_ALL, 1746be1da707SZhi Wang 0, 1, NULL}, 1747be1da707SZhi Wang 1748be1da707SZhi Wang {"MI_USER_INTERRUPT", OP_MI_USER_INTERRUPT, F_LEN_CONST, R_ALL, D_ALL, 1749be1da707SZhi Wang 0, 1, cmd_handler_mi_user_interrupt}, 1750be1da707SZhi Wang 1751be1da707SZhi Wang {"MI_WAIT_FOR_EVENT", OP_MI_WAIT_FOR_EVENT, F_LEN_CONST, R_RCS | R_BCS, 1752be1da707SZhi Wang D_ALL, 0, 1, cmd_handler_mi_wait_for_event}, 1753be1da707SZhi Wang 1754be1da707SZhi Wang {"MI_FLUSH", OP_MI_FLUSH, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL}, 1755be1da707SZhi Wang 1756be1da707SZhi Wang {"MI_ARB_CHECK", OP_MI_ARB_CHECK, F_LEN_CONST, R_ALL, D_ALL, 0, 1, 1757be1da707SZhi Wang NULL}, 1758be1da707SZhi Wang 1759be1da707SZhi Wang {"MI_RS_CONTROL", OP_MI_RS_CONTROL, F_LEN_CONST, R_RCS, D_ALL, 0, 1, 1760be1da707SZhi Wang NULL}, 1761be1da707SZhi Wang 1762be1da707SZhi Wang {"MI_REPORT_HEAD", OP_MI_REPORT_HEAD, F_LEN_CONST, R_ALL, D_ALL, 0, 1, 1763be1da707SZhi Wang NULL}, 1764be1da707SZhi Wang 1765be1da707SZhi Wang {"MI_ARB_ON_OFF", OP_MI_ARB_ON_OFF, F_LEN_CONST, R_ALL, D_ALL, 0, 1, 1766be1da707SZhi Wang NULL}, 1767be1da707SZhi Wang 1768be1da707SZhi Wang {"MI_URB_ATOMIC_ALLOC", OP_MI_URB_ATOMIC_ALLOC, F_LEN_CONST, R_RCS, 1769be1da707SZhi Wang D_ALL, 0, 1, NULL}, 1770be1da707SZhi Wang 1771be1da707SZhi Wang {"MI_BATCH_BUFFER_END", OP_MI_BATCH_BUFFER_END, 1772be1da707SZhi Wang F_IP_ADVANCE_CUSTOM | F_LEN_CONST, R_ALL, D_ALL, 0, 1, 1773be1da707SZhi Wang cmd_handler_mi_batch_buffer_end}, 1774be1da707SZhi Wang 1775be1da707SZhi Wang {"MI_SUSPEND_FLUSH", OP_MI_SUSPEND_FLUSH, F_LEN_CONST, R_ALL, D_ALL, 1776be1da707SZhi Wang 0, 1, NULL}, 1777be1da707SZhi Wang 1778be1da707SZhi Wang {"MI_PREDICATE", OP_MI_PREDICATE, F_LEN_CONST, R_RCS, D_ALL, 0, 1, 1779be1da707SZhi Wang NULL}, 1780be1da707SZhi Wang 1781be1da707SZhi Wang {"MI_TOPOLOGY_FILTER", OP_MI_TOPOLOGY_FILTER, F_LEN_CONST, R_ALL, 1782be1da707SZhi Wang D_ALL, 0, 1, NULL}, 1783be1da707SZhi Wang 1784be1da707SZhi Wang {"MI_SET_APPID", OP_MI_SET_APPID, F_LEN_CONST, R_ALL, D_ALL, 0, 1, 1785be1da707SZhi Wang NULL}, 1786be1da707SZhi Wang 1787be1da707SZhi Wang {"MI_RS_CONTEXT", OP_MI_RS_CONTEXT, F_LEN_CONST, R_RCS, D_ALL, 0, 1, 1788be1da707SZhi Wang NULL}, 1789be1da707SZhi Wang 1790be1da707SZhi Wang {"MI_DISPLAY_FLIP", OP_MI_DISPLAY_FLIP, F_LEN_VAR | F_POST_HANDLE, 1791be1da707SZhi Wang R_RCS | R_BCS, D_ALL, 0, 8, cmd_handler_mi_display_flip}, 1792be1da707SZhi Wang 1793be1da707SZhi Wang {"MI_SEMAPHORE_MBOX", OP_MI_SEMAPHORE_MBOX, F_LEN_VAR, R_ALL, D_ALL, 1794be1da707SZhi Wang 0, 8, NULL}, 1795be1da707SZhi Wang 1796be1da707SZhi Wang {"MI_MATH", OP_MI_MATH, F_LEN_VAR, R_ALL, D_ALL, 0, 8, NULL}, 1797be1da707SZhi Wang 1798be1da707SZhi Wang {"MI_URB_CLEAR", OP_MI_URB_CLEAR, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 1799be1da707SZhi Wang 1800be1da707SZhi Wang {"ME_SEMAPHORE_SIGNAL", OP_MI_SEMAPHORE_SIGNAL, F_LEN_VAR, R_ALL, 1801be1da707SZhi Wang D_BDW_PLUS, 0, 8, NULL}, 1802be1da707SZhi Wang 1803be1da707SZhi Wang {"ME_SEMAPHORE_WAIT", OP_MI_SEMAPHORE_WAIT, F_LEN_VAR, R_ALL, D_BDW_PLUS, 1804be1da707SZhi Wang ADDR_FIX_1(2), 8, cmd_handler_mi_semaphore_wait}, 1805be1da707SZhi Wang 1806be1da707SZhi Wang {"MI_STORE_DATA_IMM", OP_MI_STORE_DATA_IMM, F_LEN_VAR, R_ALL, D_BDW_PLUS, 1807be1da707SZhi Wang ADDR_FIX_1(1), 10, cmd_handler_mi_store_data_imm}, 1808be1da707SZhi Wang 1809be1da707SZhi Wang {"MI_STORE_DATA_INDEX", OP_MI_STORE_DATA_INDEX, F_LEN_VAR, R_ALL, D_ALL, 1810be1da707SZhi Wang 0, 8, cmd_handler_mi_store_data_index}, 1811be1da707SZhi Wang 1812be1da707SZhi Wang {"MI_LOAD_REGISTER_IMM", OP_MI_LOAD_REGISTER_IMM, F_LEN_VAR, R_ALL, 1813be1da707SZhi Wang D_ALL, 0, 8, cmd_handler_lri}, 1814be1da707SZhi Wang 1815be1da707SZhi Wang {"MI_UPDATE_GTT", OP_MI_UPDATE_GTT, F_LEN_VAR, R_ALL, D_BDW_PLUS, 0, 10, 1816be1da707SZhi Wang cmd_handler_mi_update_gtt}, 1817be1da707SZhi Wang 1818be1da707SZhi Wang {"MI_STORE_REGISTER_MEM", OP_MI_STORE_REGISTER_MEM, F_LEN_VAR, R_ALL, 1819be1da707SZhi Wang D_ALL, ADDR_FIX_1(2), 8, cmd_handler_srm}, 1820be1da707SZhi Wang 1821be1da707SZhi Wang {"MI_FLUSH_DW", OP_MI_FLUSH_DW, F_LEN_VAR, R_ALL, D_ALL, 0, 6, 1822be1da707SZhi Wang cmd_handler_mi_flush_dw}, 1823be1da707SZhi Wang 1824be1da707SZhi Wang {"MI_CLFLUSH", OP_MI_CLFLUSH, F_LEN_VAR, R_ALL, D_ALL, ADDR_FIX_1(1), 1825be1da707SZhi Wang 10, cmd_handler_mi_clflush}, 1826be1da707SZhi Wang 1827be1da707SZhi Wang {"MI_REPORT_PERF_COUNT", OP_MI_REPORT_PERF_COUNT, F_LEN_VAR, R_ALL, 1828be1da707SZhi Wang D_ALL, ADDR_FIX_1(1), 6, cmd_handler_mi_report_perf_count}, 1829be1da707SZhi Wang 1830be1da707SZhi Wang {"MI_LOAD_REGISTER_MEM", OP_MI_LOAD_REGISTER_MEM, F_LEN_VAR, R_ALL, 1831be1da707SZhi Wang D_ALL, ADDR_FIX_1(2), 8, cmd_handler_lrm}, 1832be1da707SZhi Wang 1833be1da707SZhi Wang {"MI_LOAD_REGISTER_REG", OP_MI_LOAD_REGISTER_REG, F_LEN_VAR, R_ALL, 1834be1da707SZhi Wang D_ALL, 0, 8, cmd_handler_lrr}, 1835be1da707SZhi Wang 1836be1da707SZhi Wang {"MI_RS_STORE_DATA_IMM", OP_MI_RS_STORE_DATA_IMM, F_LEN_VAR, R_RCS, 1837be1da707SZhi Wang D_ALL, 0, 8, NULL}, 1838be1da707SZhi Wang 1839be1da707SZhi Wang {"MI_LOAD_URB_MEM", OP_MI_LOAD_URB_MEM, F_LEN_VAR, R_RCS, D_ALL, 1840be1da707SZhi Wang ADDR_FIX_1(2), 8, NULL}, 1841be1da707SZhi Wang 1842be1da707SZhi Wang {"MI_STORE_URM_MEM", OP_MI_STORE_URM_MEM, F_LEN_VAR, R_RCS, D_ALL, 1843be1da707SZhi Wang ADDR_FIX_1(2), 8, NULL}, 1844be1da707SZhi Wang 1845be1da707SZhi Wang {"MI_OP_2E", OP_MI_2E, F_LEN_VAR, R_ALL, D_BDW_PLUS, ADDR_FIX_2(1, 2), 1846be1da707SZhi Wang 8, cmd_handler_mi_op_2e}, 1847be1da707SZhi Wang 1848be1da707SZhi Wang {"MI_OP_2F", OP_MI_2F, F_LEN_VAR, R_ALL, D_BDW_PLUS, ADDR_FIX_1(1), 1849be1da707SZhi Wang 8, cmd_handler_mi_op_2f}, 1850be1da707SZhi Wang 1851be1da707SZhi Wang {"MI_BATCH_BUFFER_START", OP_MI_BATCH_BUFFER_START, 1852be1da707SZhi Wang F_IP_ADVANCE_CUSTOM, R_ALL, D_ALL, 0, 8, 1853be1da707SZhi Wang cmd_handler_mi_batch_buffer_start}, 1854be1da707SZhi Wang 1855be1da707SZhi Wang {"MI_CONDITIONAL_BATCH_BUFFER_END", OP_MI_CONDITIONAL_BATCH_BUFFER_END, 1856be1da707SZhi Wang F_LEN_VAR, R_ALL, D_ALL, ADDR_FIX_1(2), 8, 1857be1da707SZhi Wang cmd_handler_mi_conditional_batch_buffer_end}, 1858be1da707SZhi Wang 1859be1da707SZhi Wang {"MI_LOAD_SCAN_LINES_INCL", OP_MI_LOAD_SCAN_LINES_INCL, F_LEN_CONST, 1860be1da707SZhi Wang R_RCS | R_BCS, D_ALL, 0, 2, NULL}, 1861be1da707SZhi Wang 1862be1da707SZhi Wang {"XY_SETUP_BLT", OP_XY_SETUP_BLT, F_LEN_VAR, R_BCS, D_ALL, 1863be1da707SZhi Wang ADDR_FIX_2(4, 7), 8, NULL}, 1864be1da707SZhi Wang 1865be1da707SZhi Wang {"XY_SETUP_CLIP_BLT", OP_XY_SETUP_CLIP_BLT, F_LEN_VAR, R_BCS, D_ALL, 1866be1da707SZhi Wang 0, 8, NULL}, 1867be1da707SZhi Wang 1868be1da707SZhi Wang {"XY_SETUP_MONO_PATTERN_SL_BLT", OP_XY_SETUP_MONO_PATTERN_SL_BLT, 1869be1da707SZhi Wang F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL}, 1870be1da707SZhi Wang 1871be1da707SZhi Wang {"XY_PIXEL_BLT", OP_XY_PIXEL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL}, 1872be1da707SZhi Wang 1873be1da707SZhi Wang {"XY_SCANLINES_BLT", OP_XY_SCANLINES_BLT, F_LEN_VAR, R_BCS, D_ALL, 1874be1da707SZhi Wang 0, 8, NULL}, 1875be1da707SZhi Wang 1876be1da707SZhi Wang {"XY_TEXT_BLT", OP_XY_TEXT_BLT, F_LEN_VAR, R_BCS, D_ALL, 1877be1da707SZhi Wang ADDR_FIX_1(3), 8, NULL}, 1878be1da707SZhi Wang 1879be1da707SZhi Wang {"XY_TEXT_IMMEDIATE_BLT", OP_XY_TEXT_IMMEDIATE_BLT, F_LEN_VAR, R_BCS, 1880be1da707SZhi Wang D_ALL, 0, 8, NULL}, 1881be1da707SZhi Wang 1882be1da707SZhi Wang {"XY_COLOR_BLT", OP_XY_COLOR_BLT, F_LEN_VAR, R_BCS, D_ALL, 1883be1da707SZhi Wang ADDR_FIX_1(4), 8, NULL}, 1884be1da707SZhi Wang 1885be1da707SZhi Wang {"XY_PAT_BLT", OP_XY_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL, 1886be1da707SZhi Wang ADDR_FIX_2(4, 5), 8, NULL}, 1887be1da707SZhi Wang 1888be1da707SZhi Wang {"XY_MONO_PAT_BLT", OP_XY_MONO_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL, 1889be1da707SZhi Wang ADDR_FIX_1(4), 8, NULL}, 1890be1da707SZhi Wang 1891be1da707SZhi Wang {"XY_SRC_COPY_BLT", OP_XY_SRC_COPY_BLT, F_LEN_VAR, R_BCS, D_ALL, 1892be1da707SZhi Wang ADDR_FIX_2(4, 7), 8, NULL}, 1893be1da707SZhi Wang 1894be1da707SZhi Wang {"XY_MONO_SRC_COPY_BLT", OP_XY_MONO_SRC_COPY_BLT, F_LEN_VAR, R_BCS, 1895be1da707SZhi Wang D_ALL, ADDR_FIX_2(4, 5), 8, NULL}, 1896be1da707SZhi Wang 1897be1da707SZhi Wang {"XY_FULL_BLT", OP_XY_FULL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL}, 1898be1da707SZhi Wang 1899be1da707SZhi Wang {"XY_FULL_MONO_SRC_BLT", OP_XY_FULL_MONO_SRC_BLT, F_LEN_VAR, R_BCS, 1900be1da707SZhi Wang D_ALL, ADDR_FIX_3(4, 5, 8), 8, NULL}, 1901be1da707SZhi Wang 1902be1da707SZhi Wang {"XY_FULL_MONO_PATTERN_BLT", OP_XY_FULL_MONO_PATTERN_BLT, F_LEN_VAR, 1903be1da707SZhi Wang R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL}, 1904be1da707SZhi Wang 1905be1da707SZhi Wang {"XY_FULL_MONO_PATTERN_MONO_SRC_BLT", 1906be1da707SZhi Wang OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT, 1907be1da707SZhi Wang F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL}, 1908be1da707SZhi Wang 1909be1da707SZhi Wang {"XY_MONO_PAT_FIXED_BLT", OP_XY_MONO_PAT_FIXED_BLT, F_LEN_VAR, R_BCS, 1910be1da707SZhi Wang D_ALL, ADDR_FIX_1(4), 8, NULL}, 1911be1da707SZhi Wang 1912be1da707SZhi Wang {"XY_MONO_SRC_COPY_IMMEDIATE_BLT", OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT, 1913be1da707SZhi Wang F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL}, 1914be1da707SZhi Wang 1915be1da707SZhi Wang {"XY_PAT_BLT_IMMEDIATE", OP_XY_PAT_BLT_IMMEDIATE, F_LEN_VAR, R_BCS, 1916be1da707SZhi Wang D_ALL, ADDR_FIX_1(4), 8, NULL}, 1917be1da707SZhi Wang 1918be1da707SZhi Wang {"XY_SRC_COPY_CHROMA_BLT", OP_XY_SRC_COPY_CHROMA_BLT, F_LEN_VAR, R_BCS, 1919be1da707SZhi Wang D_ALL, ADDR_FIX_2(4, 7), 8, NULL}, 1920be1da707SZhi Wang 1921be1da707SZhi Wang {"XY_FULL_IMMEDIATE_PATTERN_BLT", OP_XY_FULL_IMMEDIATE_PATTERN_BLT, 1922be1da707SZhi Wang F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL}, 1923be1da707SZhi Wang 1924be1da707SZhi Wang {"XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT", 1925be1da707SZhi Wang OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT, 1926be1da707SZhi Wang F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL}, 1927be1da707SZhi Wang 1928be1da707SZhi Wang {"XY_PAT_CHROMA_BLT", OP_XY_PAT_CHROMA_BLT, F_LEN_VAR, R_BCS, D_ALL, 1929be1da707SZhi Wang ADDR_FIX_2(4, 5), 8, NULL}, 1930be1da707SZhi Wang 1931be1da707SZhi Wang {"XY_PAT_CHROMA_BLT_IMMEDIATE", OP_XY_PAT_CHROMA_BLT_IMMEDIATE, 1932be1da707SZhi Wang F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL}, 1933be1da707SZhi Wang 1934be1da707SZhi Wang {"3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP", 1935be1da707SZhi Wang OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP, 1936be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 1937be1da707SZhi Wang 1938be1da707SZhi Wang {"3DSTATE_VIEWPORT_STATE_POINTERS_CC", 1939be1da707SZhi Wang OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC, 1940be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 1941be1da707SZhi Wang 1942be1da707SZhi Wang {"3DSTATE_BLEND_STATE_POINTERS", 1943be1da707SZhi Wang OP_3DSTATE_BLEND_STATE_POINTERS, 1944be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 1945be1da707SZhi Wang 1946be1da707SZhi Wang {"3DSTATE_DEPTH_STENCIL_STATE_POINTERS", 1947be1da707SZhi Wang OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS, 1948be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 1949be1da707SZhi Wang 1950be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_POINTERS_VS", 1951be1da707SZhi Wang OP_3DSTATE_BINDING_TABLE_POINTERS_VS, 1952be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 1953be1da707SZhi Wang 1954be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_POINTERS_HS", 1955be1da707SZhi Wang OP_3DSTATE_BINDING_TABLE_POINTERS_HS, 1956be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 1957be1da707SZhi Wang 1958be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_POINTERS_DS", 1959be1da707SZhi Wang OP_3DSTATE_BINDING_TABLE_POINTERS_DS, 1960be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 1961be1da707SZhi Wang 1962be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_POINTERS_GS", 1963be1da707SZhi Wang OP_3DSTATE_BINDING_TABLE_POINTERS_GS, 1964be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 1965be1da707SZhi Wang 1966be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_POINTERS_PS", 1967be1da707SZhi Wang OP_3DSTATE_BINDING_TABLE_POINTERS_PS, 1968be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 1969be1da707SZhi Wang 1970be1da707SZhi Wang {"3DSTATE_SAMPLER_STATE_POINTERS_VS", 1971be1da707SZhi Wang OP_3DSTATE_SAMPLER_STATE_POINTERS_VS, 1972be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 1973be1da707SZhi Wang 1974be1da707SZhi Wang {"3DSTATE_SAMPLER_STATE_POINTERS_HS", 1975be1da707SZhi Wang OP_3DSTATE_SAMPLER_STATE_POINTERS_HS, 1976be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 1977be1da707SZhi Wang 1978be1da707SZhi Wang {"3DSTATE_SAMPLER_STATE_POINTERS_DS", 1979be1da707SZhi Wang OP_3DSTATE_SAMPLER_STATE_POINTERS_DS, 1980be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 1981be1da707SZhi Wang 1982be1da707SZhi Wang {"3DSTATE_SAMPLER_STATE_POINTERS_GS", 1983be1da707SZhi Wang OP_3DSTATE_SAMPLER_STATE_POINTERS_GS, 1984be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 1985be1da707SZhi Wang 1986be1da707SZhi Wang {"3DSTATE_SAMPLER_STATE_POINTERS_PS", 1987be1da707SZhi Wang OP_3DSTATE_SAMPLER_STATE_POINTERS_PS, 1988be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 1989be1da707SZhi Wang 1990be1da707SZhi Wang {"3DSTATE_URB_VS", OP_3DSTATE_URB_VS, F_LEN_VAR, R_RCS, D_ALL, 1991be1da707SZhi Wang 0, 8, NULL}, 1992be1da707SZhi Wang 1993be1da707SZhi Wang {"3DSTATE_URB_HS", OP_3DSTATE_URB_HS, F_LEN_VAR, R_RCS, D_ALL, 1994be1da707SZhi Wang 0, 8, NULL}, 1995be1da707SZhi Wang 1996be1da707SZhi Wang {"3DSTATE_URB_DS", OP_3DSTATE_URB_DS, F_LEN_VAR, R_RCS, D_ALL, 1997be1da707SZhi Wang 0, 8, NULL}, 1998be1da707SZhi Wang 1999be1da707SZhi Wang {"3DSTATE_URB_GS", OP_3DSTATE_URB_GS, F_LEN_VAR, R_RCS, D_ALL, 2000be1da707SZhi Wang 0, 8, NULL}, 2001be1da707SZhi Wang 2002be1da707SZhi Wang {"3DSTATE_GATHER_CONSTANT_VS", OP_3DSTATE_GATHER_CONSTANT_VS, 2003be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2004be1da707SZhi Wang 2005be1da707SZhi Wang {"3DSTATE_GATHER_CONSTANT_GS", OP_3DSTATE_GATHER_CONSTANT_GS, 2006be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2007be1da707SZhi Wang 2008be1da707SZhi Wang {"3DSTATE_GATHER_CONSTANT_HS", OP_3DSTATE_GATHER_CONSTANT_HS, 2009be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2010be1da707SZhi Wang 2011be1da707SZhi Wang {"3DSTATE_GATHER_CONSTANT_DS", OP_3DSTATE_GATHER_CONSTANT_DS, 2012be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2013be1da707SZhi Wang 2014be1da707SZhi Wang {"3DSTATE_GATHER_CONSTANT_PS", OP_3DSTATE_GATHER_CONSTANT_PS, 2015be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2016be1da707SZhi Wang 2017be1da707SZhi Wang {"3DSTATE_DX9_CONSTANTF_VS", OP_3DSTATE_DX9_CONSTANTF_VS, 2018be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL}, 2019be1da707SZhi Wang 2020be1da707SZhi Wang {"3DSTATE_DX9_CONSTANTF_PS", OP_3DSTATE_DX9_CONSTANTF_PS, 2021be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL}, 2022be1da707SZhi Wang 2023be1da707SZhi Wang {"3DSTATE_DX9_CONSTANTI_VS", OP_3DSTATE_DX9_CONSTANTI_VS, 2024be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2025be1da707SZhi Wang 2026be1da707SZhi Wang {"3DSTATE_DX9_CONSTANTI_PS", OP_3DSTATE_DX9_CONSTANTI_PS, 2027be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2028be1da707SZhi Wang 2029be1da707SZhi Wang {"3DSTATE_DX9_CONSTANTB_VS", OP_3DSTATE_DX9_CONSTANTB_VS, 2030be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2031be1da707SZhi Wang 2032be1da707SZhi Wang {"3DSTATE_DX9_CONSTANTB_PS", OP_3DSTATE_DX9_CONSTANTB_PS, 2033be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2034be1da707SZhi Wang 2035be1da707SZhi Wang {"3DSTATE_DX9_LOCAL_VALID_VS", OP_3DSTATE_DX9_LOCAL_VALID_VS, 2036be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2037be1da707SZhi Wang 2038be1da707SZhi Wang {"3DSTATE_DX9_LOCAL_VALID_PS", OP_3DSTATE_DX9_LOCAL_VALID_PS, 2039be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2040be1da707SZhi Wang 2041be1da707SZhi Wang {"3DSTATE_DX9_GENERATE_ACTIVE_VS", OP_3DSTATE_DX9_GENERATE_ACTIVE_VS, 2042be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2043be1da707SZhi Wang 2044be1da707SZhi Wang {"3DSTATE_DX9_GENERATE_ACTIVE_PS", OP_3DSTATE_DX9_GENERATE_ACTIVE_PS, 2045be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2046be1da707SZhi Wang 2047be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_EDIT_VS", OP_3DSTATE_BINDING_TABLE_EDIT_VS, 2048be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL}, 2049be1da707SZhi Wang 2050be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_EDIT_GS", OP_3DSTATE_BINDING_TABLE_EDIT_GS, 2051be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL}, 2052be1da707SZhi Wang 2053be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_EDIT_HS", OP_3DSTATE_BINDING_TABLE_EDIT_HS, 2054be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL}, 2055be1da707SZhi Wang 2056be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_EDIT_DS", OP_3DSTATE_BINDING_TABLE_EDIT_DS, 2057be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL}, 2058be1da707SZhi Wang 2059be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_EDIT_PS", OP_3DSTATE_BINDING_TABLE_EDIT_PS, 2060be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL}, 2061be1da707SZhi Wang 2062be1da707SZhi Wang {"3DSTATE_VF_INSTANCING", OP_3DSTATE_VF_INSTANCING, F_LEN_VAR, R_RCS, 2063be1da707SZhi Wang D_BDW_PLUS, 0, 8, NULL}, 2064be1da707SZhi Wang 2065be1da707SZhi Wang {"3DSTATE_VF_SGVS", OP_3DSTATE_VF_SGVS, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8, 2066be1da707SZhi Wang NULL}, 2067be1da707SZhi Wang 2068be1da707SZhi Wang {"3DSTATE_VF_TOPOLOGY", OP_3DSTATE_VF_TOPOLOGY, F_LEN_VAR, R_RCS, 2069be1da707SZhi Wang D_BDW_PLUS, 0, 8, NULL}, 2070be1da707SZhi Wang 2071be1da707SZhi Wang {"3DSTATE_WM_CHROMAKEY", OP_3DSTATE_WM_CHROMAKEY, F_LEN_VAR, R_RCS, 2072be1da707SZhi Wang D_BDW_PLUS, 0, 8, NULL}, 2073be1da707SZhi Wang 2074be1da707SZhi Wang {"3DSTATE_PS_BLEND", OP_3DSTATE_PS_BLEND, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 2075be1da707SZhi Wang 8, NULL}, 2076be1da707SZhi Wang 2077be1da707SZhi Wang {"3DSTATE_WM_DEPTH_STENCIL", OP_3DSTATE_WM_DEPTH_STENCIL, F_LEN_VAR, 2078be1da707SZhi Wang R_RCS, D_BDW_PLUS, 0, 8, NULL}, 2079be1da707SZhi Wang 2080be1da707SZhi Wang {"3DSTATE_PS_EXTRA", OP_3DSTATE_PS_EXTRA, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 2081be1da707SZhi Wang 8, NULL}, 2082be1da707SZhi Wang 2083be1da707SZhi Wang {"3DSTATE_RASTER", OP_3DSTATE_RASTER, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8, 2084be1da707SZhi Wang NULL}, 2085be1da707SZhi Wang 2086be1da707SZhi Wang {"3DSTATE_SBE_SWIZ", OP_3DSTATE_SBE_SWIZ, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8, 2087be1da707SZhi Wang NULL}, 2088be1da707SZhi Wang 2089be1da707SZhi Wang {"3DSTATE_WM_HZ_OP", OP_3DSTATE_WM_HZ_OP, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8, 2090be1da707SZhi Wang NULL}, 2091be1da707SZhi Wang 2092be1da707SZhi Wang {"3DSTATE_VERTEX_BUFFERS", OP_3DSTATE_VERTEX_BUFFERS, F_LEN_VAR, R_RCS, 2093be1da707SZhi Wang D_BDW_PLUS, 0, 8, NULL}, 2094be1da707SZhi Wang 2095be1da707SZhi Wang {"3DSTATE_VERTEX_ELEMENTS", OP_3DSTATE_VERTEX_ELEMENTS, F_LEN_VAR, 2096be1da707SZhi Wang R_RCS, D_ALL, 0, 8, NULL}, 2097be1da707SZhi Wang 2098be1da707SZhi Wang {"3DSTATE_INDEX_BUFFER", OP_3DSTATE_INDEX_BUFFER, F_LEN_VAR, R_RCS, 2099be1da707SZhi Wang D_BDW_PLUS, ADDR_FIX_1(2), 8, NULL}, 2100be1da707SZhi Wang 2101be1da707SZhi Wang {"3DSTATE_VF_STATISTICS", OP_3DSTATE_VF_STATISTICS, F_LEN_CONST, 2102be1da707SZhi Wang R_RCS, D_ALL, 0, 1, NULL}, 2103be1da707SZhi Wang 2104be1da707SZhi Wang {"3DSTATE_VF", OP_3DSTATE_VF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2105be1da707SZhi Wang 2106be1da707SZhi Wang {"3DSTATE_CC_STATE_POINTERS", OP_3DSTATE_CC_STATE_POINTERS, F_LEN_VAR, 2107be1da707SZhi Wang R_RCS, D_ALL, 0, 8, NULL}, 2108be1da707SZhi Wang 2109be1da707SZhi Wang {"3DSTATE_SCISSOR_STATE_POINTERS", OP_3DSTATE_SCISSOR_STATE_POINTERS, 2110be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2111be1da707SZhi Wang 2112be1da707SZhi Wang {"3DSTATE_GS", OP_3DSTATE_GS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2113be1da707SZhi Wang 2114be1da707SZhi Wang {"3DSTATE_CLIP", OP_3DSTATE_CLIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2115be1da707SZhi Wang 2116be1da707SZhi Wang {"3DSTATE_WM", OP_3DSTATE_WM, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2117be1da707SZhi Wang 2118be1da707SZhi Wang {"3DSTATE_CONSTANT_GS", OP_3DSTATE_CONSTANT_GS, F_LEN_VAR, R_RCS, 2119be1da707SZhi Wang D_BDW_PLUS, 0, 8, NULL}, 2120be1da707SZhi Wang 2121be1da707SZhi Wang {"3DSTATE_CONSTANT_PS", OP_3DSTATE_CONSTANT_PS, F_LEN_VAR, R_RCS, 2122be1da707SZhi Wang D_BDW_PLUS, 0, 8, NULL}, 2123be1da707SZhi Wang 2124be1da707SZhi Wang {"3DSTATE_SAMPLE_MASK", OP_3DSTATE_SAMPLE_MASK, F_LEN_VAR, R_RCS, 2125be1da707SZhi Wang D_ALL, 0, 8, NULL}, 2126be1da707SZhi Wang 2127be1da707SZhi Wang {"3DSTATE_CONSTANT_HS", OP_3DSTATE_CONSTANT_HS, F_LEN_VAR, R_RCS, 2128be1da707SZhi Wang D_BDW_PLUS, 0, 8, NULL}, 2129be1da707SZhi Wang 2130be1da707SZhi Wang {"3DSTATE_CONSTANT_DS", OP_3DSTATE_CONSTANT_DS, F_LEN_VAR, R_RCS, 2131be1da707SZhi Wang D_BDW_PLUS, 0, 8, NULL}, 2132be1da707SZhi Wang 2133be1da707SZhi Wang {"3DSTATE_HS", OP_3DSTATE_HS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2134be1da707SZhi Wang 2135be1da707SZhi Wang {"3DSTATE_TE", OP_3DSTATE_TE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2136be1da707SZhi Wang 2137be1da707SZhi Wang {"3DSTATE_DS", OP_3DSTATE_DS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2138be1da707SZhi Wang 2139be1da707SZhi Wang {"3DSTATE_STREAMOUT", OP_3DSTATE_STREAMOUT, F_LEN_VAR, R_RCS, 2140be1da707SZhi Wang D_ALL, 0, 8, NULL}, 2141be1da707SZhi Wang 2142be1da707SZhi Wang {"3DSTATE_SBE", OP_3DSTATE_SBE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2143be1da707SZhi Wang 2144be1da707SZhi Wang {"3DSTATE_PS", OP_3DSTATE_PS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2145be1da707SZhi Wang 2146be1da707SZhi Wang {"3DSTATE_DRAWING_RECTANGLE", OP_3DSTATE_DRAWING_RECTANGLE, F_LEN_VAR, 2147be1da707SZhi Wang R_RCS, D_ALL, 0, 8, NULL}, 2148be1da707SZhi Wang 2149be1da707SZhi Wang {"3DSTATE_SAMPLER_PALETTE_LOAD0", OP_3DSTATE_SAMPLER_PALETTE_LOAD0, 2150be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2151be1da707SZhi Wang 2152be1da707SZhi Wang {"3DSTATE_CHROMA_KEY", OP_3DSTATE_CHROMA_KEY, F_LEN_VAR, R_RCS, D_ALL, 2153be1da707SZhi Wang 0, 8, NULL}, 2154be1da707SZhi Wang 2155be1da707SZhi Wang {"3DSTATE_DEPTH_BUFFER", OP_3DSTATE_DEPTH_BUFFER, F_LEN_VAR, R_RCS, 2156be1da707SZhi Wang D_ALL, ADDR_FIX_1(2), 8, NULL}, 2157be1da707SZhi Wang 2158be1da707SZhi Wang {"3DSTATE_POLY_STIPPLE_OFFSET", OP_3DSTATE_POLY_STIPPLE_OFFSET, 2159be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2160be1da707SZhi Wang 2161be1da707SZhi Wang {"3DSTATE_POLY_STIPPLE_PATTERN", OP_3DSTATE_POLY_STIPPLE_PATTERN, 2162be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2163be1da707SZhi Wang 2164be1da707SZhi Wang {"3DSTATE_LINE_STIPPLE", OP_3DSTATE_LINE_STIPPLE, F_LEN_VAR, R_RCS, 2165be1da707SZhi Wang D_ALL, 0, 8, NULL}, 2166be1da707SZhi Wang 2167be1da707SZhi Wang {"3DSTATE_AA_LINE_PARAMS", OP_3DSTATE_AA_LINE_PARAMS, F_LEN_VAR, R_RCS, 2168be1da707SZhi Wang D_ALL, 0, 8, NULL}, 2169be1da707SZhi Wang 2170be1da707SZhi Wang {"3DSTATE_GS_SVB_INDEX", OP_3DSTATE_GS_SVB_INDEX, F_LEN_VAR, R_RCS, 2171be1da707SZhi Wang D_ALL, 0, 8, NULL}, 2172be1da707SZhi Wang 2173be1da707SZhi Wang {"3DSTATE_SAMPLER_PALETTE_LOAD1", OP_3DSTATE_SAMPLER_PALETTE_LOAD1, 2174be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2175be1da707SZhi Wang 2176be1da707SZhi Wang {"3DSTATE_MULTISAMPLE", OP_3DSTATE_MULTISAMPLE_BDW, F_LEN_VAR, R_RCS, 2177be1da707SZhi Wang D_BDW_PLUS, 0, 8, NULL}, 2178be1da707SZhi Wang 2179be1da707SZhi Wang {"3DSTATE_STENCIL_BUFFER", OP_3DSTATE_STENCIL_BUFFER, F_LEN_VAR, R_RCS, 2180be1da707SZhi Wang D_ALL, ADDR_FIX_1(2), 8, NULL}, 2181be1da707SZhi Wang 2182be1da707SZhi Wang {"3DSTATE_HIER_DEPTH_BUFFER", OP_3DSTATE_HIER_DEPTH_BUFFER, F_LEN_VAR, 2183be1da707SZhi Wang R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL}, 2184be1da707SZhi Wang 2185be1da707SZhi Wang {"3DSTATE_CLEAR_PARAMS", OP_3DSTATE_CLEAR_PARAMS, F_LEN_VAR, 2186be1da707SZhi Wang R_RCS, D_ALL, 0, 8, NULL}, 2187be1da707SZhi Wang 2188be1da707SZhi Wang {"3DSTATE_PUSH_CONSTANT_ALLOC_VS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS, 2189be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2190be1da707SZhi Wang 2191be1da707SZhi Wang {"3DSTATE_PUSH_CONSTANT_ALLOC_HS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS, 2192be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2193be1da707SZhi Wang 2194be1da707SZhi Wang {"3DSTATE_PUSH_CONSTANT_ALLOC_DS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS, 2195be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2196be1da707SZhi Wang 2197be1da707SZhi Wang {"3DSTATE_PUSH_CONSTANT_ALLOC_GS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS, 2198be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2199be1da707SZhi Wang 2200be1da707SZhi Wang {"3DSTATE_PUSH_CONSTANT_ALLOC_PS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS, 2201be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2202be1da707SZhi Wang 2203be1da707SZhi Wang {"3DSTATE_MONOFILTER_SIZE", OP_3DSTATE_MONOFILTER_SIZE, F_LEN_VAR, 2204be1da707SZhi Wang R_RCS, D_ALL, 0, 8, NULL}, 2205be1da707SZhi Wang 2206be1da707SZhi Wang {"3DSTATE_SO_DECL_LIST", OP_3DSTATE_SO_DECL_LIST, F_LEN_VAR, R_RCS, 2207be1da707SZhi Wang D_ALL, 0, 9, NULL}, 2208be1da707SZhi Wang 2209be1da707SZhi Wang {"3DSTATE_SO_BUFFER", OP_3DSTATE_SO_BUFFER, F_LEN_VAR, R_RCS, D_BDW_PLUS, 2210be1da707SZhi Wang ADDR_FIX_2(2, 4), 8, NULL}, 2211be1da707SZhi Wang 2212be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_POOL_ALLOC", 2213be1da707SZhi Wang OP_3DSTATE_BINDING_TABLE_POOL_ALLOC, 2214be1da707SZhi Wang F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL}, 2215be1da707SZhi Wang 2216be1da707SZhi Wang {"3DSTATE_GATHER_POOL_ALLOC", OP_3DSTATE_GATHER_POOL_ALLOC, 2217be1da707SZhi Wang F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL}, 2218be1da707SZhi Wang 2219be1da707SZhi Wang {"3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC", 2220be1da707SZhi Wang OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC, 2221be1da707SZhi Wang F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL}, 2222be1da707SZhi Wang 2223be1da707SZhi Wang {"3DSTATE_SAMPLE_PATTERN", OP_3DSTATE_SAMPLE_PATTERN, F_LEN_VAR, R_RCS, 2224be1da707SZhi Wang D_BDW_PLUS, 0, 8, NULL}, 2225be1da707SZhi Wang 2226be1da707SZhi Wang {"PIPE_CONTROL", OP_PIPE_CONTROL, F_LEN_VAR, R_RCS, D_ALL, 2227be1da707SZhi Wang ADDR_FIX_1(2), 8, cmd_handler_pipe_control}, 2228be1da707SZhi Wang 2229be1da707SZhi Wang {"3DPRIMITIVE", OP_3DPRIMITIVE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2230be1da707SZhi Wang 2231be1da707SZhi Wang {"PIPELINE_SELECT", OP_PIPELINE_SELECT, F_LEN_CONST, R_RCS, D_ALL, 0, 2232be1da707SZhi Wang 1, NULL}, 2233be1da707SZhi Wang 2234be1da707SZhi Wang {"STATE_PREFETCH", OP_STATE_PREFETCH, F_LEN_VAR, R_RCS, D_ALL, 2235be1da707SZhi Wang ADDR_FIX_1(1), 8, NULL}, 2236be1da707SZhi Wang 2237be1da707SZhi Wang {"STATE_SIP", OP_STATE_SIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2238be1da707SZhi Wang 2239be1da707SZhi Wang {"STATE_BASE_ADDRESS", OP_STATE_BASE_ADDRESS, F_LEN_VAR, R_RCS, D_BDW_PLUS, 2240be1da707SZhi Wang ADDR_FIX_5(1, 3, 4, 5, 6), 8, NULL}, 2241be1da707SZhi Wang 2242be1da707SZhi Wang {"OP_3D_MEDIA_0_1_4", OP_3D_MEDIA_0_1_4, F_LEN_VAR, R_RCS, D_ALL, 2243be1da707SZhi Wang ADDR_FIX_1(1), 8, NULL}, 2244be1da707SZhi Wang 2245be1da707SZhi Wang {"3DSTATE_VS", OP_3DSTATE_VS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2246be1da707SZhi Wang 2247be1da707SZhi Wang {"3DSTATE_SF", OP_3DSTATE_SF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2248be1da707SZhi Wang 2249be1da707SZhi Wang {"3DSTATE_CONSTANT_VS", OP_3DSTATE_CONSTANT_VS, F_LEN_VAR, R_RCS, D_BDW_PLUS, 2250be1da707SZhi Wang 0, 8, NULL}, 2251be1da707SZhi Wang 2252be1da707SZhi Wang {"3DSTATE_COMPONENT_PACKING", OP_3DSTATE_COMPONENT_PACKING, F_LEN_VAR, R_RCS, 2253be1da707SZhi Wang D_SKL_PLUS, 0, 8, NULL}, 2254be1da707SZhi Wang 2255be1da707SZhi Wang {"MEDIA_INTERFACE_DESCRIPTOR_LOAD", OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD, 2256be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL}, 2257be1da707SZhi Wang 2258be1da707SZhi Wang {"MEDIA_GATEWAY_STATE", OP_MEDIA_GATEWAY_STATE, F_LEN_VAR, R_RCS, D_ALL, 2259be1da707SZhi Wang 0, 16, NULL}, 2260be1da707SZhi Wang 2261be1da707SZhi Wang {"MEDIA_STATE_FLUSH", OP_MEDIA_STATE_FLUSH, F_LEN_VAR, R_RCS, D_ALL, 2262be1da707SZhi Wang 0, 16, NULL}, 2263be1da707SZhi Wang 2264be1da707SZhi Wang {"MEDIA_OBJECT", OP_MEDIA_OBJECT, F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL}, 2265be1da707SZhi Wang 2266be1da707SZhi Wang {"MEDIA_CURBE_LOAD", OP_MEDIA_CURBE_LOAD, F_LEN_VAR, R_RCS, D_ALL, 2267be1da707SZhi Wang 0, 16, NULL}, 2268be1da707SZhi Wang 2269be1da707SZhi Wang {"MEDIA_OBJECT_PRT", OP_MEDIA_OBJECT_PRT, F_LEN_VAR, R_RCS, D_ALL, 2270be1da707SZhi Wang 0, 16, NULL}, 2271be1da707SZhi Wang 2272be1da707SZhi Wang {"MEDIA_OBJECT_WALKER", OP_MEDIA_OBJECT_WALKER, F_LEN_VAR, R_RCS, D_ALL, 2273be1da707SZhi Wang 0, 16, NULL}, 2274be1da707SZhi Wang 2275be1da707SZhi Wang {"GPGPU_WALKER", OP_GPGPU_WALKER, F_LEN_VAR, R_RCS, D_ALL, 2276be1da707SZhi Wang 0, 8, NULL}, 2277be1da707SZhi Wang 2278be1da707SZhi Wang {"MEDIA_VFE_STATE", OP_MEDIA_VFE_STATE, F_LEN_VAR, R_RCS, D_ALL, 0, 16, 2279be1da707SZhi Wang NULL}, 2280be1da707SZhi Wang 2281be1da707SZhi Wang {"3DSTATE_VF_STATISTICS_GM45", OP_3DSTATE_VF_STATISTICS_GM45, 2282be1da707SZhi Wang F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL}, 2283be1da707SZhi Wang 2284be1da707SZhi Wang {"MFX_PIPE_MODE_SELECT", OP_MFX_PIPE_MODE_SELECT, F_LEN_VAR, 2285be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2286be1da707SZhi Wang 2287be1da707SZhi Wang {"MFX_SURFACE_STATE", OP_MFX_SURFACE_STATE, F_LEN_VAR, 2288be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2289be1da707SZhi Wang 2290be1da707SZhi Wang {"MFX_PIPE_BUF_ADDR_STATE", OP_MFX_PIPE_BUF_ADDR_STATE, F_LEN_VAR, 2291be1da707SZhi Wang R_VCS, D_BDW_PLUS, 0, 12, NULL}, 2292be1da707SZhi Wang 2293be1da707SZhi Wang {"MFX_IND_OBJ_BASE_ADDR_STATE", OP_MFX_IND_OBJ_BASE_ADDR_STATE, 2294be1da707SZhi Wang F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL}, 2295be1da707SZhi Wang 2296be1da707SZhi Wang {"MFX_BSP_BUF_BASE_ADDR_STATE", OP_MFX_BSP_BUF_BASE_ADDR_STATE, 2297be1da707SZhi Wang F_LEN_VAR, R_VCS, D_BDW_PLUS, ADDR_FIX_3(1, 3, 5), 12, NULL}, 2298be1da707SZhi Wang 2299be1da707SZhi Wang {"OP_2_0_0_5", OP_2_0_0_5, F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL}, 2300be1da707SZhi Wang 2301be1da707SZhi Wang {"MFX_STATE_POINTER", OP_MFX_STATE_POINTER, F_LEN_VAR, 2302be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2303be1da707SZhi Wang 2304be1da707SZhi Wang {"MFX_QM_STATE", OP_MFX_QM_STATE, F_LEN_VAR, 2305be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2306be1da707SZhi Wang 2307be1da707SZhi Wang {"MFX_FQM_STATE", OP_MFX_FQM_STATE, F_LEN_VAR, 2308be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2309be1da707SZhi Wang 2310be1da707SZhi Wang {"MFX_PAK_INSERT_OBJECT", OP_MFX_PAK_INSERT_OBJECT, F_LEN_VAR, 2311be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2312be1da707SZhi Wang 2313be1da707SZhi Wang {"MFX_STITCH_OBJECT", OP_MFX_STITCH_OBJECT, F_LEN_VAR, 2314be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2315be1da707SZhi Wang 2316be1da707SZhi Wang {"MFD_IT_OBJECT", OP_MFD_IT_OBJECT, F_LEN_VAR, 2317be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2318be1da707SZhi Wang 2319be1da707SZhi Wang {"MFX_WAIT", OP_MFX_WAIT, F_LEN_VAR, 2320be1da707SZhi Wang R_VCS, D_ALL, 0, 6, NULL}, 2321be1da707SZhi Wang 2322be1da707SZhi Wang {"MFX_AVC_IMG_STATE", OP_MFX_AVC_IMG_STATE, F_LEN_VAR, 2323be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2324be1da707SZhi Wang 2325be1da707SZhi Wang {"MFX_AVC_QM_STATE", OP_MFX_AVC_QM_STATE, F_LEN_VAR, 2326be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2327be1da707SZhi Wang 2328be1da707SZhi Wang {"MFX_AVC_DIRECTMODE_STATE", OP_MFX_AVC_DIRECTMODE_STATE, F_LEN_VAR, 2329be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2330be1da707SZhi Wang 2331be1da707SZhi Wang {"MFX_AVC_SLICE_STATE", OP_MFX_AVC_SLICE_STATE, F_LEN_VAR, 2332be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2333be1da707SZhi Wang 2334be1da707SZhi Wang {"MFX_AVC_REF_IDX_STATE", OP_MFX_AVC_REF_IDX_STATE, F_LEN_VAR, 2335be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2336be1da707SZhi Wang 2337be1da707SZhi Wang {"MFX_AVC_WEIGHTOFFSET_STATE", OP_MFX_AVC_WEIGHTOFFSET_STATE, F_LEN_VAR, 2338be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2339be1da707SZhi Wang 2340be1da707SZhi Wang {"MFD_AVC_PICID_STATE", OP_MFD_AVC_PICID_STATE, F_LEN_VAR, 2341be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2342be1da707SZhi Wang {"MFD_AVC_DPB_STATE", OP_MFD_AVC_DPB_STATE, F_LEN_VAR, 2343be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2344be1da707SZhi Wang 2345be1da707SZhi Wang {"MFD_AVC_BSD_OBJECT", OP_MFD_AVC_BSD_OBJECT, F_LEN_VAR, 2346be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2347be1da707SZhi Wang 2348be1da707SZhi Wang {"MFD_AVC_SLICEADDR", OP_MFD_AVC_SLICEADDR, F_LEN_VAR, 2349be1da707SZhi Wang R_VCS, D_ALL, ADDR_FIX_1(2), 12, NULL}, 2350be1da707SZhi Wang 2351be1da707SZhi Wang {"MFC_AVC_PAK_OBJECT", OP_MFC_AVC_PAK_OBJECT, F_LEN_VAR, 2352be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2353be1da707SZhi Wang 2354be1da707SZhi Wang {"MFX_VC1_PRED_PIPE_STATE", OP_MFX_VC1_PRED_PIPE_STATE, F_LEN_VAR, 2355be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2356be1da707SZhi Wang 2357be1da707SZhi Wang {"MFX_VC1_DIRECTMODE_STATE", OP_MFX_VC1_DIRECTMODE_STATE, F_LEN_VAR, 2358be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2359be1da707SZhi Wang 2360be1da707SZhi Wang {"MFD_VC1_SHORT_PIC_STATE", OP_MFD_VC1_SHORT_PIC_STATE, F_LEN_VAR, 2361be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2362be1da707SZhi Wang 2363be1da707SZhi Wang {"MFD_VC1_LONG_PIC_STATE", OP_MFD_VC1_LONG_PIC_STATE, F_LEN_VAR, 2364be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2365be1da707SZhi Wang 2366be1da707SZhi Wang {"MFD_VC1_BSD_OBJECT", OP_MFD_VC1_BSD_OBJECT, F_LEN_VAR, 2367be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2368be1da707SZhi Wang 2369be1da707SZhi Wang {"MFC_MPEG2_SLICEGROUP_STATE", OP_MFC_MPEG2_SLICEGROUP_STATE, F_LEN_VAR, 2370be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2371be1da707SZhi Wang 2372be1da707SZhi Wang {"MFC_MPEG2_PAK_OBJECT", OP_MFC_MPEG2_PAK_OBJECT, F_LEN_VAR, 2373be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2374be1da707SZhi Wang 2375be1da707SZhi Wang {"MFX_MPEG2_PIC_STATE", OP_MFX_MPEG2_PIC_STATE, F_LEN_VAR, 2376be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2377be1da707SZhi Wang 2378be1da707SZhi Wang {"MFX_MPEG2_QM_STATE", OP_MFX_MPEG2_QM_STATE, F_LEN_VAR, 2379be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2380be1da707SZhi Wang 2381be1da707SZhi Wang {"MFD_MPEG2_BSD_OBJECT", OP_MFD_MPEG2_BSD_OBJECT, F_LEN_VAR, 2382be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2383be1da707SZhi Wang 2384be1da707SZhi Wang {"MFX_2_6_0_0", OP_MFX_2_6_0_0, F_LEN_VAR, R_VCS, D_ALL, 2385be1da707SZhi Wang 0, 16, NULL}, 2386be1da707SZhi Wang 2387be1da707SZhi Wang {"MFX_2_6_0_9", OP_MFX_2_6_0_9, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL}, 2388be1da707SZhi Wang 2389be1da707SZhi Wang {"MFX_2_6_0_8", OP_MFX_2_6_0_8, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL}, 2390be1da707SZhi Wang 2391be1da707SZhi Wang {"MFX_JPEG_PIC_STATE", OP_MFX_JPEG_PIC_STATE, F_LEN_VAR, 2392be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2393be1da707SZhi Wang 2394be1da707SZhi Wang {"MFX_JPEG_HUFF_TABLE_STATE", OP_MFX_JPEG_HUFF_TABLE_STATE, F_LEN_VAR, 2395be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2396be1da707SZhi Wang 2397be1da707SZhi Wang {"MFD_JPEG_BSD_OBJECT", OP_MFD_JPEG_BSD_OBJECT, F_LEN_VAR, 2398be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2399be1da707SZhi Wang 2400be1da707SZhi Wang {"VEBOX_STATE", OP_VEB_STATE, F_LEN_VAR, R_VECS, D_ALL, 0, 12, NULL}, 2401be1da707SZhi Wang 2402be1da707SZhi Wang {"VEBOX_SURFACE_STATE", OP_VEB_SURFACE_STATE, F_LEN_VAR, R_VECS, D_ALL, 2403be1da707SZhi Wang 0, 12, NULL}, 2404be1da707SZhi Wang 2405be1da707SZhi Wang {"VEB_DI_IECP", OP_VEB_DNDI_IECP_STATE, F_LEN_VAR, R_VECS, D_BDW_PLUS, 2406be1da707SZhi Wang 0, 20, NULL}, 2407be1da707SZhi Wang }; 2408be1da707SZhi Wang 2409be1da707SZhi Wang static void add_cmd_entry(struct intel_gvt *gvt, struct cmd_entry *e) 2410be1da707SZhi Wang { 2411be1da707SZhi Wang hash_add(gvt->cmd_table, &e->hlist, e->info->opcode); 2412be1da707SZhi Wang } 2413be1da707SZhi Wang 2414be1da707SZhi Wang #define GVT_MAX_CMD_LENGTH 20 /* In Dword */ 2415be1da707SZhi Wang 2416be1da707SZhi Wang static void trace_cs_command(struct parser_exec_state *s, 2417be1da707SZhi Wang cycles_t cost_pre_cmd_handler, cycles_t cost_cmd_handler) 2418be1da707SZhi Wang { 2419be1da707SZhi Wang /* This buffer is used by ftrace to store all commands copied from 2420be1da707SZhi Wang * guest gma space. Sometimes commands can cross pages, this should 2421be1da707SZhi Wang * not be handled in ftrace logic. So this is just used as a 2422be1da707SZhi Wang * 'bounce buffer' 2423be1da707SZhi Wang */ 2424be1da707SZhi Wang u32 cmd_trace_buf[GVT_MAX_CMD_LENGTH]; 2425be1da707SZhi Wang int i; 2426be1da707SZhi Wang u32 cmd_len = cmd_length(s); 2427be1da707SZhi Wang /* The chosen value of GVT_MAX_CMD_LENGTH are just based on 2428be1da707SZhi Wang * following two considerations: 2429be1da707SZhi Wang * 1) From observation, most common ring commands is not that long. 2430be1da707SZhi Wang * But there are execeptions. So it indeed makes sence to observe 2431be1da707SZhi Wang * longer commands. 2432be1da707SZhi Wang * 2) From the performance and debugging point of view, dumping all 2433be1da707SZhi Wang * contents of very commands is not necessary. 2434be1da707SZhi Wang * We mgith shrink GVT_MAX_CMD_LENGTH or remove this trace event in 2435be1da707SZhi Wang * future for performance considerations. 2436be1da707SZhi Wang */ 2437be1da707SZhi Wang if (unlikely(cmd_len > GVT_MAX_CMD_LENGTH)) { 2438be1da707SZhi Wang gvt_dbg_cmd("cmd length exceed tracing limitation!\n"); 2439be1da707SZhi Wang cmd_len = GVT_MAX_CMD_LENGTH; 2440be1da707SZhi Wang } 2441be1da707SZhi Wang 2442be1da707SZhi Wang for (i = 0; i < cmd_len; i++) 2443be1da707SZhi Wang cmd_trace_buf[i] = cmd_val(s, i); 2444be1da707SZhi Wang 2445be1da707SZhi Wang trace_gvt_command(s->vgpu->id, s->ring_id, s->ip_gma, cmd_trace_buf, 2446be1da707SZhi Wang cmd_len, s->buf_type == RING_BUFFER_INSTRUCTION, 2447be1da707SZhi Wang cost_pre_cmd_handler, cost_cmd_handler); 2448be1da707SZhi Wang } 2449be1da707SZhi Wang 2450be1da707SZhi Wang /* call the cmd handler, and advance ip */ 2451be1da707SZhi Wang static int cmd_parser_exec(struct parser_exec_state *s) 2452be1da707SZhi Wang { 2453be1da707SZhi Wang struct cmd_info *info; 2454be1da707SZhi Wang u32 cmd; 2455be1da707SZhi Wang int ret = 0; 2456be1da707SZhi Wang cycles_t t0, t1, t2; 2457be1da707SZhi Wang struct parser_exec_state s_before_advance_custom; 2458be1da707SZhi Wang 2459be1da707SZhi Wang t0 = get_cycles(); 2460be1da707SZhi Wang 2461be1da707SZhi Wang cmd = cmd_val(s, 0); 2462be1da707SZhi Wang 2463be1da707SZhi Wang info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id); 2464be1da707SZhi Wang if (info == NULL) { 2465be1da707SZhi Wang gvt_err("unknown cmd 0x%x, opcode=0x%x\n", 2466be1da707SZhi Wang cmd, get_opcode(cmd, s->ring_id)); 2467be1da707SZhi Wang return -EINVAL; 2468be1da707SZhi Wang } 2469be1da707SZhi Wang 2470be1da707SZhi Wang gvt_dbg_cmd("%s\n", info->name); 2471be1da707SZhi Wang 2472be1da707SZhi Wang s->info = info; 2473be1da707SZhi Wang 2474be1da707SZhi Wang t1 = get_cycles(); 2475be1da707SZhi Wang 2476be1da707SZhi Wang memcpy(&s_before_advance_custom, s, sizeof(struct parser_exec_state)); 2477be1da707SZhi Wang 2478be1da707SZhi Wang if (info->handler) { 2479be1da707SZhi Wang ret = info->handler(s); 2480be1da707SZhi Wang if (ret < 0) { 2481be1da707SZhi Wang gvt_err("%s handler error\n", info->name); 2482be1da707SZhi Wang return ret; 2483be1da707SZhi Wang } 2484be1da707SZhi Wang } 2485be1da707SZhi Wang t2 = get_cycles(); 2486be1da707SZhi Wang 2487be1da707SZhi Wang trace_cs_command(&s_before_advance_custom, t1 - t0, t2 - t1); 2488be1da707SZhi Wang 2489be1da707SZhi Wang if (!(info->flag & F_IP_ADVANCE_CUSTOM)) { 2490be1da707SZhi Wang ret = cmd_advance_default(s); 2491be1da707SZhi Wang if (ret) { 2492be1da707SZhi Wang gvt_err("%s IP advance error\n", info->name); 2493be1da707SZhi Wang return ret; 2494be1da707SZhi Wang } 2495be1da707SZhi Wang } 2496be1da707SZhi Wang return 0; 2497be1da707SZhi Wang } 2498be1da707SZhi Wang 2499be1da707SZhi Wang static inline bool gma_out_of_range(unsigned long gma, 2500be1da707SZhi Wang unsigned long gma_head, unsigned int gma_tail) 2501be1da707SZhi Wang { 2502be1da707SZhi Wang if (gma_tail >= gma_head) 2503be1da707SZhi Wang return (gma < gma_head) || (gma > gma_tail); 2504be1da707SZhi Wang else 2505be1da707SZhi Wang return (gma > gma_tail) && (gma < gma_head); 2506be1da707SZhi Wang } 2507be1da707SZhi Wang 2508be1da707SZhi Wang static int command_scan(struct parser_exec_state *s, 2509be1da707SZhi Wang unsigned long rb_head, unsigned long rb_tail, 2510be1da707SZhi Wang unsigned long rb_start, unsigned long rb_len) 2511be1da707SZhi Wang { 2512be1da707SZhi Wang 2513be1da707SZhi Wang unsigned long gma_head, gma_tail, gma_bottom; 2514be1da707SZhi Wang int ret = 0; 2515be1da707SZhi Wang 2516be1da707SZhi Wang gma_head = rb_start + rb_head; 2517be1da707SZhi Wang gma_tail = rb_start + rb_tail; 2518be1da707SZhi Wang gma_bottom = rb_start + rb_len; 2519be1da707SZhi Wang 2520be1da707SZhi Wang gvt_dbg_cmd("scan_start: start=%lx end=%lx\n", gma_head, gma_tail); 2521be1da707SZhi Wang 2522be1da707SZhi Wang while (s->ip_gma != gma_tail) { 2523be1da707SZhi Wang if (s->buf_type == RING_BUFFER_INSTRUCTION) { 2524be1da707SZhi Wang if (!(s->ip_gma >= rb_start) || 2525be1da707SZhi Wang !(s->ip_gma < gma_bottom)) { 2526be1da707SZhi Wang gvt_err("ip_gma %lx out of ring scope." 2527be1da707SZhi Wang "(base:0x%lx, bottom: 0x%lx)\n", 2528be1da707SZhi Wang s->ip_gma, rb_start, 2529be1da707SZhi Wang gma_bottom); 2530be1da707SZhi Wang parser_exec_state_dump(s); 2531be1da707SZhi Wang return -EINVAL; 2532be1da707SZhi Wang } 2533be1da707SZhi Wang if (gma_out_of_range(s->ip_gma, gma_head, gma_tail)) { 2534be1da707SZhi Wang gvt_err("ip_gma %lx out of range." 2535be1da707SZhi Wang "base 0x%lx head 0x%lx tail 0x%lx\n", 2536be1da707SZhi Wang s->ip_gma, rb_start, 2537be1da707SZhi Wang rb_head, rb_tail); 2538be1da707SZhi Wang parser_exec_state_dump(s); 2539be1da707SZhi Wang break; 2540be1da707SZhi Wang } 2541be1da707SZhi Wang } 2542be1da707SZhi Wang ret = cmd_parser_exec(s); 2543be1da707SZhi Wang if (ret) { 2544be1da707SZhi Wang gvt_err("cmd parser error\n"); 2545be1da707SZhi Wang parser_exec_state_dump(s); 2546be1da707SZhi Wang break; 2547be1da707SZhi Wang } 2548be1da707SZhi Wang } 2549be1da707SZhi Wang 2550be1da707SZhi Wang gvt_dbg_cmd("scan_end\n"); 2551be1da707SZhi Wang 2552be1da707SZhi Wang return ret; 2553be1da707SZhi Wang } 2554be1da707SZhi Wang 2555be1da707SZhi Wang static int scan_workload(struct intel_vgpu_workload *workload) 2556be1da707SZhi Wang { 2557be1da707SZhi Wang unsigned long gma_head, gma_tail, gma_bottom; 2558be1da707SZhi Wang struct parser_exec_state s; 2559be1da707SZhi Wang int ret = 0; 2560be1da707SZhi Wang 2561be1da707SZhi Wang /* ring base is page aligned */ 2562be1da707SZhi Wang if (WARN_ON(!IS_ALIGNED(workload->rb_start, GTT_PAGE_SIZE))) 2563be1da707SZhi Wang return -EINVAL; 2564be1da707SZhi Wang 2565be1da707SZhi Wang gma_head = workload->rb_start + workload->rb_head; 2566be1da707SZhi Wang gma_tail = workload->rb_start + workload->rb_tail; 2567be1da707SZhi Wang gma_bottom = workload->rb_start + _RING_CTL_BUF_SIZE(workload->rb_ctl); 2568be1da707SZhi Wang 2569be1da707SZhi Wang s.buf_type = RING_BUFFER_INSTRUCTION; 2570be1da707SZhi Wang s.buf_addr_type = GTT_BUFFER; 2571be1da707SZhi Wang s.vgpu = workload->vgpu; 2572be1da707SZhi Wang s.ring_id = workload->ring_id; 2573be1da707SZhi Wang s.ring_start = workload->rb_start; 2574be1da707SZhi Wang s.ring_size = _RING_CTL_BUF_SIZE(workload->rb_ctl); 2575be1da707SZhi Wang s.ring_head = gma_head; 2576be1da707SZhi Wang s.ring_tail = gma_tail; 2577be1da707SZhi Wang s.rb_va = workload->shadow_ring_buffer_va; 2578be1da707SZhi Wang s.workload = workload; 2579be1da707SZhi Wang 2580be1da707SZhi Wang if (bypass_scan_mask & (1 << workload->ring_id)) 2581be1da707SZhi Wang return 0; 2582be1da707SZhi Wang 2583be1da707SZhi Wang ret = ip_gma_set(&s, gma_head); 2584be1da707SZhi Wang if (ret) 2585be1da707SZhi Wang goto out; 2586be1da707SZhi Wang 2587be1da707SZhi Wang ret = command_scan(&s, workload->rb_head, workload->rb_tail, 2588be1da707SZhi Wang workload->rb_start, _RING_CTL_BUF_SIZE(workload->rb_ctl)); 2589be1da707SZhi Wang 2590be1da707SZhi Wang out: 2591be1da707SZhi Wang return ret; 2592be1da707SZhi Wang } 2593be1da707SZhi Wang 2594be1da707SZhi Wang static int scan_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx) 2595be1da707SZhi Wang { 2596be1da707SZhi Wang 2597be1da707SZhi Wang unsigned long gma_head, gma_tail, gma_bottom, ring_size, ring_tail; 2598be1da707SZhi Wang struct parser_exec_state s; 2599be1da707SZhi Wang int ret = 0; 2600be1da707SZhi Wang 2601be1da707SZhi Wang /* ring base is page aligned */ 2602be1da707SZhi Wang if (WARN_ON(!IS_ALIGNED(wa_ctx->indirect_ctx.guest_gma, GTT_PAGE_SIZE))) 2603be1da707SZhi Wang return -EINVAL; 2604be1da707SZhi Wang 2605be1da707SZhi Wang ring_tail = wa_ctx->indirect_ctx.size + 3 * sizeof(uint32_t); 2606be1da707SZhi Wang ring_size = round_up(wa_ctx->indirect_ctx.size + CACHELINE_BYTES, 2607be1da707SZhi Wang PAGE_SIZE); 2608be1da707SZhi Wang gma_head = wa_ctx->indirect_ctx.guest_gma; 2609be1da707SZhi Wang gma_tail = wa_ctx->indirect_ctx.guest_gma + ring_tail; 2610be1da707SZhi Wang gma_bottom = wa_ctx->indirect_ctx.guest_gma + ring_size; 2611be1da707SZhi Wang 2612be1da707SZhi Wang s.buf_type = RING_BUFFER_INSTRUCTION; 2613be1da707SZhi Wang s.buf_addr_type = GTT_BUFFER; 2614be1da707SZhi Wang s.vgpu = wa_ctx->workload->vgpu; 2615be1da707SZhi Wang s.ring_id = wa_ctx->workload->ring_id; 2616be1da707SZhi Wang s.ring_start = wa_ctx->indirect_ctx.guest_gma; 2617be1da707SZhi Wang s.ring_size = ring_size; 2618be1da707SZhi Wang s.ring_head = gma_head; 2619be1da707SZhi Wang s.ring_tail = gma_tail; 2620be1da707SZhi Wang s.rb_va = wa_ctx->indirect_ctx.shadow_va; 2621be1da707SZhi Wang s.workload = wa_ctx->workload; 2622be1da707SZhi Wang 2623be1da707SZhi Wang ret = ip_gma_set(&s, gma_head); 2624be1da707SZhi Wang if (ret) 2625be1da707SZhi Wang goto out; 2626be1da707SZhi Wang 2627be1da707SZhi Wang ret = command_scan(&s, 0, ring_tail, 2628be1da707SZhi Wang wa_ctx->indirect_ctx.guest_gma, ring_size); 2629be1da707SZhi Wang out: 2630be1da707SZhi Wang return ret; 2631be1da707SZhi Wang } 2632be1da707SZhi Wang 2633be1da707SZhi Wang static int shadow_workload_ring_buffer(struct intel_vgpu_workload *workload) 2634be1da707SZhi Wang { 2635be1da707SZhi Wang struct intel_vgpu *vgpu = workload->vgpu; 2636be1da707SZhi Wang int ring_id = workload->ring_id; 2637be1da707SZhi Wang struct i915_gem_context *shadow_ctx = vgpu->shadow_ctx; 2638be1da707SZhi Wang struct intel_ring *ring = shadow_ctx->engine[ring_id].ring; 2639be1da707SZhi Wang unsigned long gma_head, gma_tail, gma_top, guest_rb_size; 2640be1da707SZhi Wang unsigned int copy_len = 0; 2641be1da707SZhi Wang int ret; 2642be1da707SZhi Wang 2643be1da707SZhi Wang guest_rb_size = _RING_CTL_BUF_SIZE(workload->rb_ctl); 2644be1da707SZhi Wang 2645be1da707SZhi Wang /* calculate workload ring buffer size */ 2646be1da707SZhi Wang workload->rb_len = (workload->rb_tail + guest_rb_size - 2647be1da707SZhi Wang workload->rb_head) % guest_rb_size; 2648be1da707SZhi Wang 2649be1da707SZhi Wang gma_head = workload->rb_start + workload->rb_head; 2650be1da707SZhi Wang gma_tail = workload->rb_start + workload->rb_tail; 2651be1da707SZhi Wang gma_top = workload->rb_start + guest_rb_size; 2652be1da707SZhi Wang 2653be1da707SZhi Wang /* allocate shadow ring buffer */ 2654be1da707SZhi Wang ret = intel_ring_begin(workload->req, workload->rb_len / 4); 2655be1da707SZhi Wang if (ret) 2656be1da707SZhi Wang return ret; 2657be1da707SZhi Wang 2658be1da707SZhi Wang /* get shadow ring buffer va */ 2659be1da707SZhi Wang workload->shadow_ring_buffer_va = ring->vaddr + ring->tail; 2660be1da707SZhi Wang 2661be1da707SZhi Wang /* head > tail --> copy head <-> top */ 2662be1da707SZhi Wang if (gma_head > gma_tail) { 2663be1da707SZhi Wang ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm, 2664be1da707SZhi Wang gma_head, gma_top, 2665be1da707SZhi Wang workload->shadow_ring_buffer_va); 2666be1da707SZhi Wang if (ret) { 2667be1da707SZhi Wang gvt_err("fail to copy guest ring buffer\n"); 2668be1da707SZhi Wang return ret; 2669be1da707SZhi Wang } 2670be1da707SZhi Wang copy_len = gma_top - gma_head; 2671be1da707SZhi Wang gma_head = workload->rb_start; 2672be1da707SZhi Wang } 2673be1da707SZhi Wang 2674be1da707SZhi Wang /* copy head or start <-> tail */ 2675be1da707SZhi Wang ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm, 2676be1da707SZhi Wang gma_head, gma_tail, 2677be1da707SZhi Wang workload->shadow_ring_buffer_va + copy_len); 2678be1da707SZhi Wang if (ret) { 2679be1da707SZhi Wang gvt_err("fail to copy guest ring buffer\n"); 2680be1da707SZhi Wang return ret; 2681be1da707SZhi Wang } 2682be1da707SZhi Wang ring->tail += workload->rb_len; 2683be1da707SZhi Wang intel_ring_advance(ring); 2684be1da707SZhi Wang return 0; 2685be1da707SZhi Wang } 2686be1da707SZhi Wang 2687be1da707SZhi Wang int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload) 2688be1da707SZhi Wang { 2689be1da707SZhi Wang int ret; 2690be1da707SZhi Wang 2691be1da707SZhi Wang ret = shadow_workload_ring_buffer(workload); 2692be1da707SZhi Wang if (ret) { 2693be1da707SZhi Wang gvt_err("fail to shadow workload ring_buffer\n"); 2694be1da707SZhi Wang return ret; 2695be1da707SZhi Wang } 2696be1da707SZhi Wang 2697be1da707SZhi Wang ret = scan_workload(workload); 2698be1da707SZhi Wang if (ret) { 2699be1da707SZhi Wang gvt_err("scan workload error\n"); 2700be1da707SZhi Wang return ret; 2701be1da707SZhi Wang } 2702be1da707SZhi Wang return 0; 2703be1da707SZhi Wang } 2704be1da707SZhi Wang 2705be1da707SZhi Wang static int shadow_indirect_ctx(struct intel_shadow_wa_ctx *wa_ctx) 2706be1da707SZhi Wang { 2707be1da707SZhi Wang struct drm_device *dev = &wa_ctx->workload->vgpu->gvt->dev_priv->drm; 2708be1da707SZhi Wang int ctx_size = wa_ctx->indirect_ctx.size; 2709be1da707SZhi Wang unsigned long guest_gma = wa_ctx->indirect_ctx.guest_gma; 2710be1da707SZhi Wang int ret = 0; 2711be1da707SZhi Wang void *dest = NULL; 2712be1da707SZhi Wang 2713be1da707SZhi Wang wa_ctx->indirect_ctx.obj = i915_gem_object_create(dev, 2714be1da707SZhi Wang round_up(ctx_size + CACHELINE_BYTES, PAGE_SIZE)); 2715be1da707SZhi Wang if (wa_ctx->indirect_ctx.obj == NULL) 2716be1da707SZhi Wang return -ENOMEM; 2717be1da707SZhi Wang 2718be1da707SZhi Wang ret = i915_gem_object_get_pages(wa_ctx->indirect_ctx.obj); 2719be1da707SZhi Wang if (ret) 2720be1da707SZhi Wang return ret; 2721be1da707SZhi Wang 2722be1da707SZhi Wang i915_gem_object_pin_pages(wa_ctx->indirect_ctx.obj); 2723be1da707SZhi Wang 2724be1da707SZhi Wang /* get the va of the shadow batch buffer */ 2725be1da707SZhi Wang dest = (void *)vmap_batch(wa_ctx->indirect_ctx.obj, 0, 2726be1da707SZhi Wang ctx_size + CACHELINE_BYTES); 2727be1da707SZhi Wang if (!dest) { 2728be1da707SZhi Wang gvt_err("failed to vmap shadow indirect ctx\n"); 2729be1da707SZhi Wang ret = -ENOMEM; 2730be1da707SZhi Wang goto unpin_src; 2731be1da707SZhi Wang } 2732be1da707SZhi Wang 2733be1da707SZhi Wang ret = i915_gem_object_set_to_cpu_domain(wa_ctx->indirect_ctx.obj, 2734be1da707SZhi Wang false); 2735be1da707SZhi Wang if (ret) { 2736be1da707SZhi Wang gvt_err("failed to set shadow indirect ctx to CPU\n"); 2737be1da707SZhi Wang goto unmap_src; 2738be1da707SZhi Wang } 2739be1da707SZhi Wang 2740be1da707SZhi Wang wa_ctx->indirect_ctx.shadow_va = dest; 2741be1da707SZhi Wang 2742be1da707SZhi Wang memset(dest, 0, round_up(ctx_size + CACHELINE_BYTES, PAGE_SIZE)); 2743be1da707SZhi Wang 2744be1da707SZhi Wang ret = copy_gma_to_hva(wa_ctx->workload->vgpu, 2745be1da707SZhi Wang wa_ctx->workload->vgpu->gtt.ggtt_mm, 2746be1da707SZhi Wang guest_gma, guest_gma + ctx_size, dest); 2747be1da707SZhi Wang if (ret) { 2748be1da707SZhi Wang gvt_err("fail to copy guest indirect ctx\n"); 2749be1da707SZhi Wang return ret; 2750be1da707SZhi Wang } 2751be1da707SZhi Wang 2752be1da707SZhi Wang return 0; 2753be1da707SZhi Wang 2754be1da707SZhi Wang unmap_src: 2755be1da707SZhi Wang vunmap(dest); 2756be1da707SZhi Wang unpin_src: 2757be1da707SZhi Wang i915_gem_object_unpin_pages(wa_ctx->indirect_ctx.obj); 2758be1da707SZhi Wang 2759be1da707SZhi Wang return ret; 2760be1da707SZhi Wang } 2761be1da707SZhi Wang 2762be1da707SZhi Wang static int combine_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx) 2763be1da707SZhi Wang { 2764be1da707SZhi Wang uint32_t per_ctx_start[CACHELINE_DWORDS] = {0}; 2765be1da707SZhi Wang unsigned char *bb_start_sva; 2766be1da707SZhi Wang 2767be1da707SZhi Wang per_ctx_start[0] = 0x18800001; 2768be1da707SZhi Wang per_ctx_start[1] = wa_ctx->per_ctx.guest_gma; 2769be1da707SZhi Wang 2770be1da707SZhi Wang bb_start_sva = (unsigned char *)wa_ctx->indirect_ctx.shadow_va + 2771be1da707SZhi Wang wa_ctx->indirect_ctx.size; 2772be1da707SZhi Wang 2773be1da707SZhi Wang memcpy(bb_start_sva, per_ctx_start, CACHELINE_BYTES); 2774be1da707SZhi Wang 2775be1da707SZhi Wang return 0; 2776be1da707SZhi Wang } 2777be1da707SZhi Wang 2778be1da707SZhi Wang int intel_gvt_scan_and_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx) 2779be1da707SZhi Wang { 2780be1da707SZhi Wang int ret; 2781be1da707SZhi Wang 2782be1da707SZhi Wang if (wa_ctx->indirect_ctx.size == 0) 2783be1da707SZhi Wang return 0; 2784be1da707SZhi Wang 2785be1da707SZhi Wang ret = shadow_indirect_ctx(wa_ctx); 2786be1da707SZhi Wang if (ret) { 2787be1da707SZhi Wang gvt_err("fail to shadow indirect ctx\n"); 2788be1da707SZhi Wang return ret; 2789be1da707SZhi Wang } 2790be1da707SZhi Wang 2791be1da707SZhi Wang combine_wa_ctx(wa_ctx); 2792be1da707SZhi Wang 2793be1da707SZhi Wang ret = scan_wa_ctx(wa_ctx); 2794be1da707SZhi Wang if (ret) { 2795be1da707SZhi Wang gvt_err("scan wa ctx error\n"); 2796be1da707SZhi Wang return ret; 2797be1da707SZhi Wang } 2798be1da707SZhi Wang 2799be1da707SZhi Wang return 0; 2800be1da707SZhi Wang } 2801be1da707SZhi Wang 2802be1da707SZhi Wang static struct cmd_info *find_cmd_entry_any_ring(struct intel_gvt *gvt, 2803be1da707SZhi Wang unsigned int opcode, int rings) 2804be1da707SZhi Wang { 2805be1da707SZhi Wang struct cmd_info *info = NULL; 2806be1da707SZhi Wang unsigned int ring; 2807be1da707SZhi Wang 2808be1da707SZhi Wang for_each_set_bit(ring, (unsigned long *)&rings, I915_NUM_ENGINES) { 2809be1da707SZhi Wang info = find_cmd_entry(gvt, opcode, ring); 2810be1da707SZhi Wang if (info) 2811be1da707SZhi Wang break; 2812be1da707SZhi Wang } 2813be1da707SZhi Wang return info; 2814be1da707SZhi Wang } 2815be1da707SZhi Wang 2816be1da707SZhi Wang static int init_cmd_table(struct intel_gvt *gvt) 2817be1da707SZhi Wang { 2818be1da707SZhi Wang int i; 2819be1da707SZhi Wang struct cmd_entry *e; 2820be1da707SZhi Wang struct cmd_info *info; 2821be1da707SZhi Wang unsigned int gen_type; 2822be1da707SZhi Wang 2823be1da707SZhi Wang gen_type = intel_gvt_get_device_type(gvt); 2824be1da707SZhi Wang 2825be1da707SZhi Wang for (i = 0; i < ARRAY_SIZE(cmd_info); i++) { 2826be1da707SZhi Wang if (!(cmd_info[i].devices & gen_type)) 2827be1da707SZhi Wang continue; 2828be1da707SZhi Wang 2829be1da707SZhi Wang e = kzalloc(sizeof(*e), GFP_KERNEL); 2830be1da707SZhi Wang if (!e) 2831be1da707SZhi Wang return -ENOMEM; 2832be1da707SZhi Wang 2833be1da707SZhi Wang e->info = &cmd_info[i]; 2834be1da707SZhi Wang info = find_cmd_entry_any_ring(gvt, 2835be1da707SZhi Wang e->info->opcode, e->info->rings); 2836be1da707SZhi Wang if (info) { 2837be1da707SZhi Wang gvt_err("%s %s duplicated\n", e->info->name, 2838be1da707SZhi Wang info->name); 2839be1da707SZhi Wang return -EEXIST; 2840be1da707SZhi Wang } 2841be1da707SZhi Wang 2842be1da707SZhi Wang INIT_HLIST_NODE(&e->hlist); 2843be1da707SZhi Wang add_cmd_entry(gvt, e); 2844be1da707SZhi Wang gvt_dbg_cmd("add %-30s op %04x flag %x devs %02x rings %02x\n", 2845be1da707SZhi Wang e->info->name, e->info->opcode, e->info->flag, 2846be1da707SZhi Wang e->info->devices, e->info->rings); 2847be1da707SZhi Wang } 2848be1da707SZhi Wang return 0; 2849be1da707SZhi Wang } 2850be1da707SZhi Wang 2851be1da707SZhi Wang static void clean_cmd_table(struct intel_gvt *gvt) 2852be1da707SZhi Wang { 2853be1da707SZhi Wang struct hlist_node *tmp; 2854be1da707SZhi Wang struct cmd_entry *e; 2855be1da707SZhi Wang int i; 2856be1da707SZhi Wang 2857be1da707SZhi Wang hash_for_each_safe(gvt->cmd_table, i, tmp, e, hlist) 2858be1da707SZhi Wang kfree(e); 2859be1da707SZhi Wang 2860be1da707SZhi Wang hash_init(gvt->cmd_table); 2861be1da707SZhi Wang } 2862be1da707SZhi Wang 2863be1da707SZhi Wang void intel_gvt_clean_cmd_parser(struct intel_gvt *gvt) 2864be1da707SZhi Wang { 2865be1da707SZhi Wang clean_cmd_table(gvt); 2866be1da707SZhi Wang } 2867be1da707SZhi Wang 2868be1da707SZhi Wang int intel_gvt_init_cmd_parser(struct intel_gvt *gvt) 2869be1da707SZhi Wang { 2870be1da707SZhi Wang int ret; 2871be1da707SZhi Wang 2872be1da707SZhi Wang ret = init_cmd_table(gvt); 2873be1da707SZhi Wang if (ret) { 2874be1da707SZhi Wang intel_gvt_clean_cmd_parser(gvt); 2875be1da707SZhi Wang return ret; 2876be1da707SZhi Wang } 2877be1da707SZhi Wang return 0; 2878be1da707SZhi Wang } 2879