1be1da707SZhi Wang /* 2be1da707SZhi Wang * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3be1da707SZhi Wang * 4be1da707SZhi Wang * Permission is hereby granted, free of charge, to any person obtaining a 5be1da707SZhi Wang * copy of this software and associated documentation files (the "Software"), 6be1da707SZhi Wang * to deal in the Software without restriction, including without limitation 7be1da707SZhi Wang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8be1da707SZhi Wang * and/or sell copies of the Software, and to permit persons to whom the 9be1da707SZhi Wang * Software is furnished to do so, subject to the following conditions: 10be1da707SZhi Wang * 11be1da707SZhi Wang * The above copyright notice and this permission notice (including the next 12be1da707SZhi Wang * paragraph) shall be included in all copies or substantial portions of the 13be1da707SZhi Wang * Software. 14be1da707SZhi Wang * 15be1da707SZhi Wang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16be1da707SZhi Wang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17be1da707SZhi Wang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18be1da707SZhi Wang * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19be1da707SZhi Wang * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20be1da707SZhi Wang * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21be1da707SZhi Wang * SOFTWARE. 22be1da707SZhi Wang * 23be1da707SZhi Wang * Authors: 24be1da707SZhi Wang * Ke Yu 25be1da707SZhi Wang * Kevin Tian <kevin.tian@intel.com> 26be1da707SZhi Wang * Zhiyuan Lv <zhiyuan.lv@intel.com> 27be1da707SZhi Wang * 28be1da707SZhi Wang * Contributors: 29be1da707SZhi Wang * Min He <min.he@intel.com> 30be1da707SZhi Wang * Ping Gao <ping.a.gao@intel.com> 31be1da707SZhi Wang * Tina Zhang <tina.zhang@intel.com> 32be1da707SZhi Wang * Yulei Zhang <yulei.zhang@intel.com> 33be1da707SZhi Wang * Zhi Wang <zhi.a.wang@intel.com> 34be1da707SZhi Wang * 35be1da707SZhi Wang */ 36be1da707SZhi Wang 37be1da707SZhi Wang #include <linux/slab.h> 382871ea85SChris Wilson 39be1da707SZhi Wang #include "i915_drv.h" 402871ea85SChris Wilson #include "gt/intel_ring.h" 41feddf6e8SZhenyu Wang #include "gvt.h" 42feddf6e8SZhenyu Wang #include "i915_pvinfo.h" 43be1da707SZhi Wang #include "trace.h" 44be1da707SZhi Wang 45be1da707SZhi Wang #define INVALID_OP (~0U) 46be1da707SZhi Wang 47be1da707SZhi Wang #define OP_LEN_MI 9 48be1da707SZhi Wang #define OP_LEN_2D 10 49be1da707SZhi Wang #define OP_LEN_3D_MEDIA 16 50be1da707SZhi Wang #define OP_LEN_MFX_VC 16 51be1da707SZhi Wang #define OP_LEN_VEBOX 16 52be1da707SZhi Wang 53be1da707SZhi Wang #define CMD_TYPE(cmd) (((cmd) >> 29) & 7) 54be1da707SZhi Wang 55be1da707SZhi Wang struct sub_op_bits { 56be1da707SZhi Wang int hi; 57be1da707SZhi Wang int low; 58be1da707SZhi Wang }; 59be1da707SZhi Wang struct decode_info { 60ed8cce30SJani Nikula const char *name; 61be1da707SZhi Wang int op_len; 62be1da707SZhi Wang int nr_sub_op; 63ed8cce30SJani Nikula const struct sub_op_bits *sub_op; 64be1da707SZhi Wang }; 65be1da707SZhi Wang 66be1da707SZhi Wang #define MAX_CMD_BUDGET 0x7fffffff 67be1da707SZhi Wang #define MI_WAIT_FOR_PLANE_C_FLIP_PENDING (1<<15) 68be1da707SZhi Wang #define MI_WAIT_FOR_PLANE_B_FLIP_PENDING (1<<9) 69be1da707SZhi Wang #define MI_WAIT_FOR_PLANE_A_FLIP_PENDING (1<<1) 70be1da707SZhi Wang 71be1da707SZhi Wang #define MI_WAIT_FOR_SPRITE_C_FLIP_PENDING (1<<20) 72be1da707SZhi Wang #define MI_WAIT_FOR_SPRITE_B_FLIP_PENDING (1<<10) 73be1da707SZhi Wang #define MI_WAIT_FOR_SPRITE_A_FLIP_PENDING (1<<2) 74be1da707SZhi Wang 75be1da707SZhi Wang /* Render Command Map */ 76be1da707SZhi Wang 77be1da707SZhi Wang /* MI_* command Opcode (28:23) */ 78be1da707SZhi Wang #define OP_MI_NOOP 0x0 79be1da707SZhi Wang #define OP_MI_SET_PREDICATE 0x1 /* HSW+ */ 80be1da707SZhi Wang #define OP_MI_USER_INTERRUPT 0x2 81be1da707SZhi Wang #define OP_MI_WAIT_FOR_EVENT 0x3 82be1da707SZhi Wang #define OP_MI_FLUSH 0x4 83be1da707SZhi Wang #define OP_MI_ARB_CHECK 0x5 84be1da707SZhi Wang #define OP_MI_RS_CONTROL 0x6 /* HSW+ */ 85be1da707SZhi Wang #define OP_MI_REPORT_HEAD 0x7 86be1da707SZhi Wang #define OP_MI_ARB_ON_OFF 0x8 87be1da707SZhi Wang #define OP_MI_URB_ATOMIC_ALLOC 0x9 /* HSW+ */ 88be1da707SZhi Wang #define OP_MI_BATCH_BUFFER_END 0xA 89be1da707SZhi Wang #define OP_MI_SUSPEND_FLUSH 0xB 90be1da707SZhi Wang #define OP_MI_PREDICATE 0xC /* IVB+ */ 91be1da707SZhi Wang #define OP_MI_TOPOLOGY_FILTER 0xD /* IVB+ */ 92be1da707SZhi Wang #define OP_MI_SET_APPID 0xE /* IVB+ */ 93be1da707SZhi Wang #define OP_MI_RS_CONTEXT 0xF /* HSW+ */ 94be1da707SZhi Wang #define OP_MI_LOAD_SCAN_LINES_INCL 0x12 /* HSW+ */ 95be1da707SZhi Wang #define OP_MI_DISPLAY_FLIP 0x14 96be1da707SZhi Wang #define OP_MI_SEMAPHORE_MBOX 0x16 97be1da707SZhi Wang #define OP_MI_SET_CONTEXT 0x18 98be1da707SZhi Wang #define OP_MI_MATH 0x1A 99be1da707SZhi Wang #define OP_MI_URB_CLEAR 0x19 100be1da707SZhi Wang #define OP_MI_SEMAPHORE_SIGNAL 0x1B /* BDW+ */ 101be1da707SZhi Wang #define OP_MI_SEMAPHORE_WAIT 0x1C /* BDW+ */ 102be1da707SZhi Wang 103be1da707SZhi Wang #define OP_MI_STORE_DATA_IMM 0x20 104be1da707SZhi Wang #define OP_MI_STORE_DATA_INDEX 0x21 105be1da707SZhi Wang #define OP_MI_LOAD_REGISTER_IMM 0x22 106be1da707SZhi Wang #define OP_MI_UPDATE_GTT 0x23 107be1da707SZhi Wang #define OP_MI_STORE_REGISTER_MEM 0x24 108be1da707SZhi Wang #define OP_MI_FLUSH_DW 0x26 109be1da707SZhi Wang #define OP_MI_CLFLUSH 0x27 110be1da707SZhi Wang #define OP_MI_REPORT_PERF_COUNT 0x28 111be1da707SZhi Wang #define OP_MI_LOAD_REGISTER_MEM 0x29 /* HSW+ */ 112be1da707SZhi Wang #define OP_MI_LOAD_REGISTER_REG 0x2A /* HSW+ */ 113be1da707SZhi Wang #define OP_MI_RS_STORE_DATA_IMM 0x2B /* HSW+ */ 114be1da707SZhi Wang #define OP_MI_LOAD_URB_MEM 0x2C /* HSW+ */ 115be1da707SZhi Wang #define OP_MI_STORE_URM_MEM 0x2D /* HSW+ */ 116be1da707SZhi Wang #define OP_MI_2E 0x2E /* BDW+ */ 117be1da707SZhi Wang #define OP_MI_2F 0x2F /* BDW+ */ 118be1da707SZhi Wang #define OP_MI_BATCH_BUFFER_START 0x31 119be1da707SZhi Wang 120be1da707SZhi Wang /* Bit definition for dword 0 */ 121be1da707SZhi Wang #define _CMDBIT_BB_START_IN_PPGTT (1UL << 8) 122be1da707SZhi Wang 123be1da707SZhi Wang #define OP_MI_CONDITIONAL_BATCH_BUFFER_END 0x36 124be1da707SZhi Wang 125be1da707SZhi Wang #define BATCH_BUFFER_ADDR_MASK ((1UL << 32) - (1U << 2)) 126be1da707SZhi Wang #define BATCH_BUFFER_ADDR_HIGH_MASK ((1UL << 16) - (1U)) 127be1da707SZhi Wang #define BATCH_BUFFER_ADR_SPACE_BIT(x) (((x) >> 8) & 1U) 128be1da707SZhi Wang #define BATCH_BUFFER_2ND_LEVEL_BIT(x) ((x) >> 22 & 1U) 129be1da707SZhi Wang 130be1da707SZhi Wang /* 2D command: Opcode (28:22) */ 131be1da707SZhi Wang #define OP_2D(x) ((2<<7) | x) 132be1da707SZhi Wang 133be1da707SZhi Wang #define OP_XY_SETUP_BLT OP_2D(0x1) 134be1da707SZhi Wang #define OP_XY_SETUP_CLIP_BLT OP_2D(0x3) 135be1da707SZhi Wang #define OP_XY_SETUP_MONO_PATTERN_SL_BLT OP_2D(0x11) 136be1da707SZhi Wang #define OP_XY_PIXEL_BLT OP_2D(0x24) 137be1da707SZhi Wang #define OP_XY_SCANLINES_BLT OP_2D(0x25) 138be1da707SZhi Wang #define OP_XY_TEXT_BLT OP_2D(0x26) 139be1da707SZhi Wang #define OP_XY_TEXT_IMMEDIATE_BLT OP_2D(0x31) 140be1da707SZhi Wang #define OP_XY_COLOR_BLT OP_2D(0x50) 141be1da707SZhi Wang #define OP_XY_PAT_BLT OP_2D(0x51) 142be1da707SZhi Wang #define OP_XY_MONO_PAT_BLT OP_2D(0x52) 143be1da707SZhi Wang #define OP_XY_SRC_COPY_BLT OP_2D(0x53) 144be1da707SZhi Wang #define OP_XY_MONO_SRC_COPY_BLT OP_2D(0x54) 145be1da707SZhi Wang #define OP_XY_FULL_BLT OP_2D(0x55) 146be1da707SZhi Wang #define OP_XY_FULL_MONO_SRC_BLT OP_2D(0x56) 147be1da707SZhi Wang #define OP_XY_FULL_MONO_PATTERN_BLT OP_2D(0x57) 148be1da707SZhi Wang #define OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT OP_2D(0x58) 149be1da707SZhi Wang #define OP_XY_MONO_PAT_FIXED_BLT OP_2D(0x59) 150be1da707SZhi Wang #define OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT OP_2D(0x71) 151be1da707SZhi Wang #define OP_XY_PAT_BLT_IMMEDIATE OP_2D(0x72) 152be1da707SZhi Wang #define OP_XY_SRC_COPY_CHROMA_BLT OP_2D(0x73) 153be1da707SZhi Wang #define OP_XY_FULL_IMMEDIATE_PATTERN_BLT OP_2D(0x74) 154be1da707SZhi Wang #define OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT OP_2D(0x75) 155be1da707SZhi Wang #define OP_XY_PAT_CHROMA_BLT OP_2D(0x76) 156be1da707SZhi Wang #define OP_XY_PAT_CHROMA_BLT_IMMEDIATE OP_2D(0x77) 157be1da707SZhi Wang 158be1da707SZhi Wang /* 3D/Media Command: Pipeline Type(28:27) Opcode(26:24) Sub Opcode(23:16) */ 159be1da707SZhi Wang #define OP_3D_MEDIA(sub_type, opcode, sub_opcode) \ 160be1da707SZhi Wang ((3 << 13) | ((sub_type) << 11) | ((opcode) << 8) | (sub_opcode)) 161be1da707SZhi Wang 162be1da707SZhi Wang #define OP_STATE_PREFETCH OP_3D_MEDIA(0x0, 0x0, 0x03) 163be1da707SZhi Wang 164be1da707SZhi Wang #define OP_STATE_BASE_ADDRESS OP_3D_MEDIA(0x0, 0x1, 0x01) 165be1da707SZhi Wang #define OP_STATE_SIP OP_3D_MEDIA(0x0, 0x1, 0x02) 166be1da707SZhi Wang #define OP_3D_MEDIA_0_1_4 OP_3D_MEDIA(0x0, 0x1, 0x04) 167be1da707SZhi Wang 168be1da707SZhi Wang #define OP_3DSTATE_VF_STATISTICS_GM45 OP_3D_MEDIA(0x1, 0x0, 0x0B) 169be1da707SZhi Wang 170be1da707SZhi Wang #define OP_PIPELINE_SELECT OP_3D_MEDIA(0x1, 0x1, 0x04) 171be1da707SZhi Wang 172be1da707SZhi Wang #define OP_MEDIA_VFE_STATE OP_3D_MEDIA(0x2, 0x0, 0x0) 173be1da707SZhi Wang #define OP_MEDIA_CURBE_LOAD OP_3D_MEDIA(0x2, 0x0, 0x1) 174be1da707SZhi Wang #define OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD OP_3D_MEDIA(0x2, 0x0, 0x2) 175be1da707SZhi Wang #define OP_MEDIA_GATEWAY_STATE OP_3D_MEDIA(0x2, 0x0, 0x3) 176be1da707SZhi Wang #define OP_MEDIA_STATE_FLUSH OP_3D_MEDIA(0x2, 0x0, 0x4) 17702b966c1SColin Xu #define OP_MEDIA_POOL_STATE OP_3D_MEDIA(0x2, 0x0, 0x5) 178be1da707SZhi Wang 179be1da707SZhi Wang #define OP_MEDIA_OBJECT OP_3D_MEDIA(0x2, 0x1, 0x0) 180be1da707SZhi Wang #define OP_MEDIA_OBJECT_PRT OP_3D_MEDIA(0x2, 0x1, 0x2) 181be1da707SZhi Wang #define OP_MEDIA_OBJECT_WALKER OP_3D_MEDIA(0x2, 0x1, 0x3) 182be1da707SZhi Wang #define OP_GPGPU_WALKER OP_3D_MEDIA(0x2, 0x1, 0x5) 183be1da707SZhi Wang 184be1da707SZhi Wang #define OP_3DSTATE_CLEAR_PARAMS OP_3D_MEDIA(0x3, 0x0, 0x04) /* IVB+ */ 185be1da707SZhi Wang #define OP_3DSTATE_DEPTH_BUFFER OP_3D_MEDIA(0x3, 0x0, 0x05) /* IVB+ */ 186be1da707SZhi Wang #define OP_3DSTATE_STENCIL_BUFFER OP_3D_MEDIA(0x3, 0x0, 0x06) /* IVB+ */ 187be1da707SZhi Wang #define OP_3DSTATE_HIER_DEPTH_BUFFER OP_3D_MEDIA(0x3, 0x0, 0x07) /* IVB+ */ 188be1da707SZhi Wang #define OP_3DSTATE_VERTEX_BUFFERS OP_3D_MEDIA(0x3, 0x0, 0x08) 189be1da707SZhi Wang #define OP_3DSTATE_VERTEX_ELEMENTS OP_3D_MEDIA(0x3, 0x0, 0x09) 190be1da707SZhi Wang #define OP_3DSTATE_INDEX_BUFFER OP_3D_MEDIA(0x3, 0x0, 0x0A) 191be1da707SZhi Wang #define OP_3DSTATE_VF_STATISTICS OP_3D_MEDIA(0x3, 0x0, 0x0B) 192be1da707SZhi Wang #define OP_3DSTATE_VF OP_3D_MEDIA(0x3, 0x0, 0x0C) /* HSW+ */ 193be1da707SZhi Wang #define OP_3DSTATE_CC_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x0E) 194be1da707SZhi Wang #define OP_3DSTATE_SCISSOR_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x0F) 195be1da707SZhi Wang #define OP_3DSTATE_VS OP_3D_MEDIA(0x3, 0x0, 0x10) 196be1da707SZhi Wang #define OP_3DSTATE_GS OP_3D_MEDIA(0x3, 0x0, 0x11) 197be1da707SZhi Wang #define OP_3DSTATE_CLIP OP_3D_MEDIA(0x3, 0x0, 0x12) 198be1da707SZhi Wang #define OP_3DSTATE_SF OP_3D_MEDIA(0x3, 0x0, 0x13) 199be1da707SZhi Wang #define OP_3DSTATE_WM OP_3D_MEDIA(0x3, 0x0, 0x14) 200be1da707SZhi Wang #define OP_3DSTATE_CONSTANT_VS OP_3D_MEDIA(0x3, 0x0, 0x15) 201be1da707SZhi Wang #define OP_3DSTATE_CONSTANT_GS OP_3D_MEDIA(0x3, 0x0, 0x16) 202be1da707SZhi Wang #define OP_3DSTATE_CONSTANT_PS OP_3D_MEDIA(0x3, 0x0, 0x17) 203be1da707SZhi Wang #define OP_3DSTATE_SAMPLE_MASK OP_3D_MEDIA(0x3, 0x0, 0x18) 204be1da707SZhi Wang #define OP_3DSTATE_CONSTANT_HS OP_3D_MEDIA(0x3, 0x0, 0x19) /* IVB+ */ 205be1da707SZhi Wang #define OP_3DSTATE_CONSTANT_DS OP_3D_MEDIA(0x3, 0x0, 0x1A) /* IVB+ */ 206be1da707SZhi Wang #define OP_3DSTATE_HS OP_3D_MEDIA(0x3, 0x0, 0x1B) /* IVB+ */ 207be1da707SZhi Wang #define OP_3DSTATE_TE OP_3D_MEDIA(0x3, 0x0, 0x1C) /* IVB+ */ 208be1da707SZhi Wang #define OP_3DSTATE_DS OP_3D_MEDIA(0x3, 0x0, 0x1D) /* IVB+ */ 209be1da707SZhi Wang #define OP_3DSTATE_STREAMOUT OP_3D_MEDIA(0x3, 0x0, 0x1E) /* IVB+ */ 210be1da707SZhi Wang #define OP_3DSTATE_SBE OP_3D_MEDIA(0x3, 0x0, 0x1F) /* IVB+ */ 211be1da707SZhi Wang #define OP_3DSTATE_PS OP_3D_MEDIA(0x3, 0x0, 0x20) /* IVB+ */ 212be1da707SZhi Wang #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP OP_3D_MEDIA(0x3, 0x0, 0x21) /* IVB+ */ 213be1da707SZhi Wang #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC OP_3D_MEDIA(0x3, 0x0, 0x23) /* IVB+ */ 214be1da707SZhi Wang #define OP_3DSTATE_BLEND_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x24) /* IVB+ */ 215be1da707SZhi Wang #define OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x25) /* IVB+ */ 216be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_POINTERS_VS OP_3D_MEDIA(0x3, 0x0, 0x26) /* IVB+ */ 217be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_POINTERS_HS OP_3D_MEDIA(0x3, 0x0, 0x27) /* IVB+ */ 218be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_POINTERS_DS OP_3D_MEDIA(0x3, 0x0, 0x28) /* IVB+ */ 219be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_POINTERS_GS OP_3D_MEDIA(0x3, 0x0, 0x29) /* IVB+ */ 220be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_POINTERS_PS OP_3D_MEDIA(0x3, 0x0, 0x2A) /* IVB+ */ 221be1da707SZhi Wang #define OP_3DSTATE_SAMPLER_STATE_POINTERS_VS OP_3D_MEDIA(0x3, 0x0, 0x2B) /* IVB+ */ 222be1da707SZhi Wang #define OP_3DSTATE_SAMPLER_STATE_POINTERS_HS OP_3D_MEDIA(0x3, 0x0, 0x2C) /* IVB+ */ 223be1da707SZhi Wang #define OP_3DSTATE_SAMPLER_STATE_POINTERS_DS OP_3D_MEDIA(0x3, 0x0, 0x2D) /* IVB+ */ 224be1da707SZhi Wang #define OP_3DSTATE_SAMPLER_STATE_POINTERS_GS OP_3D_MEDIA(0x3, 0x0, 0x2E) /* IVB+ */ 225be1da707SZhi Wang #define OP_3DSTATE_SAMPLER_STATE_POINTERS_PS OP_3D_MEDIA(0x3, 0x0, 0x2F) /* IVB+ */ 226be1da707SZhi Wang #define OP_3DSTATE_URB_VS OP_3D_MEDIA(0x3, 0x0, 0x30) /* IVB+ */ 227be1da707SZhi Wang #define OP_3DSTATE_URB_HS OP_3D_MEDIA(0x3, 0x0, 0x31) /* IVB+ */ 228be1da707SZhi Wang #define OP_3DSTATE_URB_DS OP_3D_MEDIA(0x3, 0x0, 0x32) /* IVB+ */ 229be1da707SZhi Wang #define OP_3DSTATE_URB_GS OP_3D_MEDIA(0x3, 0x0, 0x33) /* IVB+ */ 230be1da707SZhi Wang #define OP_3DSTATE_GATHER_CONSTANT_VS OP_3D_MEDIA(0x3, 0x0, 0x34) /* HSW+ */ 231be1da707SZhi Wang #define OP_3DSTATE_GATHER_CONSTANT_GS OP_3D_MEDIA(0x3, 0x0, 0x35) /* HSW+ */ 232be1da707SZhi Wang #define OP_3DSTATE_GATHER_CONSTANT_HS OP_3D_MEDIA(0x3, 0x0, 0x36) /* HSW+ */ 233be1da707SZhi Wang #define OP_3DSTATE_GATHER_CONSTANT_DS OP_3D_MEDIA(0x3, 0x0, 0x37) /* HSW+ */ 234be1da707SZhi Wang #define OP_3DSTATE_GATHER_CONSTANT_PS OP_3D_MEDIA(0x3, 0x0, 0x38) /* HSW+ */ 235be1da707SZhi Wang #define OP_3DSTATE_DX9_CONSTANTF_VS OP_3D_MEDIA(0x3, 0x0, 0x39) /* HSW+ */ 236be1da707SZhi Wang #define OP_3DSTATE_DX9_CONSTANTF_PS OP_3D_MEDIA(0x3, 0x0, 0x3A) /* HSW+ */ 237be1da707SZhi Wang #define OP_3DSTATE_DX9_CONSTANTI_VS OP_3D_MEDIA(0x3, 0x0, 0x3B) /* HSW+ */ 238be1da707SZhi Wang #define OP_3DSTATE_DX9_CONSTANTI_PS OP_3D_MEDIA(0x3, 0x0, 0x3C) /* HSW+ */ 239be1da707SZhi Wang #define OP_3DSTATE_DX9_CONSTANTB_VS OP_3D_MEDIA(0x3, 0x0, 0x3D) /* HSW+ */ 240be1da707SZhi Wang #define OP_3DSTATE_DX9_CONSTANTB_PS OP_3D_MEDIA(0x3, 0x0, 0x3E) /* HSW+ */ 241be1da707SZhi Wang #define OP_3DSTATE_DX9_LOCAL_VALID_VS OP_3D_MEDIA(0x3, 0x0, 0x3F) /* HSW+ */ 242be1da707SZhi Wang #define OP_3DSTATE_DX9_LOCAL_VALID_PS OP_3D_MEDIA(0x3, 0x0, 0x40) /* HSW+ */ 243be1da707SZhi Wang #define OP_3DSTATE_DX9_GENERATE_ACTIVE_VS OP_3D_MEDIA(0x3, 0x0, 0x41) /* HSW+ */ 244be1da707SZhi Wang #define OP_3DSTATE_DX9_GENERATE_ACTIVE_PS OP_3D_MEDIA(0x3, 0x0, 0x42) /* HSW+ */ 245be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_EDIT_VS OP_3D_MEDIA(0x3, 0x0, 0x43) /* HSW+ */ 246be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_EDIT_GS OP_3D_MEDIA(0x3, 0x0, 0x44) /* HSW+ */ 247be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_EDIT_HS OP_3D_MEDIA(0x3, 0x0, 0x45) /* HSW+ */ 248be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_EDIT_DS OP_3D_MEDIA(0x3, 0x0, 0x46) /* HSW+ */ 249be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_EDIT_PS OP_3D_MEDIA(0x3, 0x0, 0x47) /* HSW+ */ 250be1da707SZhi Wang 251be1da707SZhi Wang #define OP_3DSTATE_VF_INSTANCING OP_3D_MEDIA(0x3, 0x0, 0x49) /* BDW+ */ 252be1da707SZhi Wang #define OP_3DSTATE_VF_SGVS OP_3D_MEDIA(0x3, 0x0, 0x4A) /* BDW+ */ 253be1da707SZhi Wang #define OP_3DSTATE_VF_TOPOLOGY OP_3D_MEDIA(0x3, 0x0, 0x4B) /* BDW+ */ 254be1da707SZhi Wang #define OP_3DSTATE_WM_CHROMAKEY OP_3D_MEDIA(0x3, 0x0, 0x4C) /* BDW+ */ 255be1da707SZhi Wang #define OP_3DSTATE_PS_BLEND OP_3D_MEDIA(0x3, 0x0, 0x4D) /* BDW+ */ 256be1da707SZhi Wang #define OP_3DSTATE_WM_DEPTH_STENCIL OP_3D_MEDIA(0x3, 0x0, 0x4E) /* BDW+ */ 257be1da707SZhi Wang #define OP_3DSTATE_PS_EXTRA OP_3D_MEDIA(0x3, 0x0, 0x4F) /* BDW+ */ 258be1da707SZhi Wang #define OP_3DSTATE_RASTER OP_3D_MEDIA(0x3, 0x0, 0x50) /* BDW+ */ 259be1da707SZhi Wang #define OP_3DSTATE_SBE_SWIZ OP_3D_MEDIA(0x3, 0x0, 0x51) /* BDW+ */ 260be1da707SZhi Wang #define OP_3DSTATE_WM_HZ_OP OP_3D_MEDIA(0x3, 0x0, 0x52) /* BDW+ */ 261be1da707SZhi Wang #define OP_3DSTATE_COMPONENT_PACKING OP_3D_MEDIA(0x3, 0x0, 0x55) /* SKL+ */ 262be1da707SZhi Wang 263be1da707SZhi Wang #define OP_3DSTATE_DRAWING_RECTANGLE OP_3D_MEDIA(0x3, 0x1, 0x00) 264be1da707SZhi Wang #define OP_3DSTATE_SAMPLER_PALETTE_LOAD0 OP_3D_MEDIA(0x3, 0x1, 0x02) 265be1da707SZhi Wang #define OP_3DSTATE_CHROMA_KEY OP_3D_MEDIA(0x3, 0x1, 0x04) 266be1da707SZhi Wang #define OP_SNB_3DSTATE_DEPTH_BUFFER OP_3D_MEDIA(0x3, 0x1, 0x05) 267be1da707SZhi Wang #define OP_3DSTATE_POLY_STIPPLE_OFFSET OP_3D_MEDIA(0x3, 0x1, 0x06) 268be1da707SZhi Wang #define OP_3DSTATE_POLY_STIPPLE_PATTERN OP_3D_MEDIA(0x3, 0x1, 0x07) 269be1da707SZhi Wang #define OP_3DSTATE_LINE_STIPPLE OP_3D_MEDIA(0x3, 0x1, 0x08) 270be1da707SZhi Wang #define OP_3DSTATE_AA_LINE_PARAMS OP_3D_MEDIA(0x3, 0x1, 0x0A) 271be1da707SZhi Wang #define OP_3DSTATE_GS_SVB_INDEX OP_3D_MEDIA(0x3, 0x1, 0x0B) 272be1da707SZhi Wang #define OP_3DSTATE_SAMPLER_PALETTE_LOAD1 OP_3D_MEDIA(0x3, 0x1, 0x0C) 273be1da707SZhi Wang #define OP_3DSTATE_MULTISAMPLE_BDW OP_3D_MEDIA(0x3, 0x0, 0x0D) 274be1da707SZhi Wang #define OP_SNB_3DSTATE_STENCIL_BUFFER OP_3D_MEDIA(0x3, 0x1, 0x0E) 275be1da707SZhi Wang #define OP_SNB_3DSTATE_HIER_DEPTH_BUFFER OP_3D_MEDIA(0x3, 0x1, 0x0F) 276be1da707SZhi Wang #define OP_SNB_3DSTATE_CLEAR_PARAMS OP_3D_MEDIA(0x3, 0x1, 0x10) 277be1da707SZhi Wang #define OP_3DSTATE_MONOFILTER_SIZE OP_3D_MEDIA(0x3, 0x1, 0x11) 278be1da707SZhi Wang #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS OP_3D_MEDIA(0x3, 0x1, 0x12) /* IVB+ */ 279be1da707SZhi Wang #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS OP_3D_MEDIA(0x3, 0x1, 0x13) /* IVB+ */ 280be1da707SZhi Wang #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS OP_3D_MEDIA(0x3, 0x1, 0x14) /* IVB+ */ 281be1da707SZhi Wang #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS OP_3D_MEDIA(0x3, 0x1, 0x15) /* IVB+ */ 282be1da707SZhi Wang #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS OP_3D_MEDIA(0x3, 0x1, 0x16) /* IVB+ */ 283be1da707SZhi Wang #define OP_3DSTATE_SO_DECL_LIST OP_3D_MEDIA(0x3, 0x1, 0x17) 284be1da707SZhi Wang #define OP_3DSTATE_SO_BUFFER OP_3D_MEDIA(0x3, 0x1, 0x18) 285be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x19) /* HSW+ */ 286be1da707SZhi Wang #define OP_3DSTATE_GATHER_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x1A) /* HSW+ */ 287be1da707SZhi Wang #define OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x1B) /* HSW+ */ 288be1da707SZhi Wang #define OP_3DSTATE_SAMPLE_PATTERN OP_3D_MEDIA(0x3, 0x1, 0x1C) 289be1da707SZhi Wang #define OP_PIPE_CONTROL OP_3D_MEDIA(0x3, 0x2, 0x00) 290be1da707SZhi Wang #define OP_3DPRIMITIVE OP_3D_MEDIA(0x3, 0x3, 0x00) 291be1da707SZhi Wang 292be1da707SZhi Wang /* VCCP Command Parser */ 293be1da707SZhi Wang 294be1da707SZhi Wang /* 295be1da707SZhi Wang * Below MFX and VBE cmd definition is from vaapi intel driver project (BSD License) 296be1da707SZhi Wang * git://anongit.freedesktop.org/vaapi/intel-driver 297be1da707SZhi Wang * src/i965_defines.h 298be1da707SZhi Wang * 299be1da707SZhi Wang */ 300be1da707SZhi Wang 301be1da707SZhi Wang #define OP_MFX(pipeline, op, sub_opa, sub_opb) \ 302be1da707SZhi Wang (3 << 13 | \ 303be1da707SZhi Wang (pipeline) << 11 | \ 304be1da707SZhi Wang (op) << 8 | \ 305be1da707SZhi Wang (sub_opa) << 5 | \ 306be1da707SZhi Wang (sub_opb)) 307be1da707SZhi Wang 308be1da707SZhi Wang #define OP_MFX_PIPE_MODE_SELECT OP_MFX(2, 0, 0, 0) /* ALL */ 309be1da707SZhi Wang #define OP_MFX_SURFACE_STATE OP_MFX(2, 0, 0, 1) /* ALL */ 310be1da707SZhi Wang #define OP_MFX_PIPE_BUF_ADDR_STATE OP_MFX(2, 0, 0, 2) /* ALL */ 311be1da707SZhi Wang #define OP_MFX_IND_OBJ_BASE_ADDR_STATE OP_MFX(2, 0, 0, 3) /* ALL */ 312be1da707SZhi Wang #define OP_MFX_BSP_BUF_BASE_ADDR_STATE OP_MFX(2, 0, 0, 4) /* ALL */ 313be1da707SZhi Wang #define OP_2_0_0_5 OP_MFX(2, 0, 0, 5) /* ALL */ 314be1da707SZhi Wang #define OP_MFX_STATE_POINTER OP_MFX(2, 0, 0, 6) /* ALL */ 315be1da707SZhi Wang #define OP_MFX_QM_STATE OP_MFX(2, 0, 0, 7) /* IVB+ */ 316be1da707SZhi Wang #define OP_MFX_FQM_STATE OP_MFX(2, 0, 0, 8) /* IVB+ */ 317be1da707SZhi Wang #define OP_MFX_PAK_INSERT_OBJECT OP_MFX(2, 0, 2, 8) /* IVB+ */ 318be1da707SZhi Wang #define OP_MFX_STITCH_OBJECT OP_MFX(2, 0, 2, 0xA) /* IVB+ */ 319be1da707SZhi Wang 320be1da707SZhi Wang #define OP_MFD_IT_OBJECT OP_MFX(2, 0, 1, 9) /* ALL */ 321be1da707SZhi Wang 322be1da707SZhi Wang #define OP_MFX_WAIT OP_MFX(1, 0, 0, 0) /* IVB+ */ 323be1da707SZhi Wang #define OP_MFX_AVC_IMG_STATE OP_MFX(2, 1, 0, 0) /* ALL */ 324be1da707SZhi Wang #define OP_MFX_AVC_QM_STATE OP_MFX(2, 1, 0, 1) /* ALL */ 325be1da707SZhi Wang #define OP_MFX_AVC_DIRECTMODE_STATE OP_MFX(2, 1, 0, 2) /* ALL */ 326be1da707SZhi Wang #define OP_MFX_AVC_SLICE_STATE OP_MFX(2, 1, 0, 3) /* ALL */ 327be1da707SZhi Wang #define OP_MFX_AVC_REF_IDX_STATE OP_MFX(2, 1, 0, 4) /* ALL */ 328be1da707SZhi Wang #define OP_MFX_AVC_WEIGHTOFFSET_STATE OP_MFX(2, 1, 0, 5) /* ALL */ 329be1da707SZhi Wang #define OP_MFD_AVC_PICID_STATE OP_MFX(2, 1, 1, 5) /* HSW+ */ 330be1da707SZhi Wang #define OP_MFD_AVC_DPB_STATE OP_MFX(2, 1, 1, 6) /* IVB+ */ 331be1da707SZhi Wang #define OP_MFD_AVC_SLICEADDR OP_MFX(2, 1, 1, 7) /* IVB+ */ 332be1da707SZhi Wang #define OP_MFD_AVC_BSD_OBJECT OP_MFX(2, 1, 1, 8) /* ALL */ 333be1da707SZhi Wang #define OP_MFC_AVC_PAK_OBJECT OP_MFX(2, 1, 2, 9) /* ALL */ 334be1da707SZhi Wang 335be1da707SZhi Wang #define OP_MFX_VC1_PRED_PIPE_STATE OP_MFX(2, 2, 0, 1) /* ALL */ 336be1da707SZhi Wang #define OP_MFX_VC1_DIRECTMODE_STATE OP_MFX(2, 2, 0, 2) /* ALL */ 337be1da707SZhi Wang #define OP_MFD_VC1_SHORT_PIC_STATE OP_MFX(2, 2, 1, 0) /* IVB+ */ 338be1da707SZhi Wang #define OP_MFD_VC1_LONG_PIC_STATE OP_MFX(2, 2, 1, 1) /* IVB+ */ 339be1da707SZhi Wang #define OP_MFD_VC1_BSD_OBJECT OP_MFX(2, 2, 1, 8) /* ALL */ 340be1da707SZhi Wang 341be1da707SZhi Wang #define OP_MFX_MPEG2_PIC_STATE OP_MFX(2, 3, 0, 0) /* ALL */ 342be1da707SZhi Wang #define OP_MFX_MPEG2_QM_STATE OP_MFX(2, 3, 0, 1) /* ALL */ 343be1da707SZhi Wang #define OP_MFD_MPEG2_BSD_OBJECT OP_MFX(2, 3, 1, 8) /* ALL */ 344be1da707SZhi Wang #define OP_MFC_MPEG2_SLICEGROUP_STATE OP_MFX(2, 3, 2, 3) /* ALL */ 345be1da707SZhi Wang #define OP_MFC_MPEG2_PAK_OBJECT OP_MFX(2, 3, 2, 9) /* ALL */ 346be1da707SZhi Wang 347be1da707SZhi Wang #define OP_MFX_2_6_0_0 OP_MFX(2, 6, 0, 0) /* IVB+ */ 348be1da707SZhi Wang #define OP_MFX_2_6_0_8 OP_MFX(2, 6, 0, 8) /* IVB+ */ 349be1da707SZhi Wang #define OP_MFX_2_6_0_9 OP_MFX(2, 6, 0, 9) /* IVB+ */ 350be1da707SZhi Wang 351be1da707SZhi Wang #define OP_MFX_JPEG_PIC_STATE OP_MFX(2, 7, 0, 0) 352be1da707SZhi Wang #define OP_MFX_JPEG_HUFF_TABLE_STATE OP_MFX(2, 7, 0, 2) 353be1da707SZhi Wang #define OP_MFD_JPEG_BSD_OBJECT OP_MFX(2, 7, 1, 8) 354be1da707SZhi Wang 355be1da707SZhi Wang #define OP_VEB(pipeline, op, sub_opa, sub_opb) \ 356be1da707SZhi Wang (3 << 13 | \ 357be1da707SZhi Wang (pipeline) << 11 | \ 358be1da707SZhi Wang (op) << 8 | \ 359be1da707SZhi Wang (sub_opa) << 5 | \ 360be1da707SZhi Wang (sub_opb)) 361be1da707SZhi Wang 362be1da707SZhi Wang #define OP_VEB_SURFACE_STATE OP_VEB(2, 4, 0, 0) 363be1da707SZhi Wang #define OP_VEB_STATE OP_VEB(2, 4, 0, 2) 364be1da707SZhi Wang #define OP_VEB_DNDI_IECP_STATE OP_VEB(2, 4, 0, 3) 365be1da707SZhi Wang 366be1da707SZhi Wang struct parser_exec_state; 367be1da707SZhi Wang 368be1da707SZhi Wang typedef int (*parser_cmd_handler)(struct parser_exec_state *s); 369be1da707SZhi Wang 370be1da707SZhi Wang #define GVT_CMD_HASH_BITS 7 371be1da707SZhi Wang 372be1da707SZhi Wang /* which DWords need address fix */ 373be1da707SZhi Wang #define ADDR_FIX_1(x1) (1 << (x1)) 374be1da707SZhi Wang #define ADDR_FIX_2(x1, x2) (ADDR_FIX_1(x1) | ADDR_FIX_1(x2)) 375be1da707SZhi Wang #define ADDR_FIX_3(x1, x2, x3) (ADDR_FIX_1(x1) | ADDR_FIX_2(x2, x3)) 376be1da707SZhi Wang #define ADDR_FIX_4(x1, x2, x3, x4) (ADDR_FIX_1(x1) | ADDR_FIX_3(x2, x3, x4)) 377be1da707SZhi Wang #define ADDR_FIX_5(x1, x2, x3, x4, x5) (ADDR_FIX_1(x1) | ADDR_FIX_4(x2, x3, x4, x5)) 378be1da707SZhi Wang 37900a33be4SGao, Fred #define DWORD_FIELD(dword, end, start) \ 38000a33be4SGao, Fred FIELD_GET(GENMASK(end, start), cmd_val(s, dword)) 38100a33be4SGao, Fred 3821e2adc0dSGao, Fred #define OP_LENGTH_BIAS 2 3831e2adc0dSGao, Fred #define CMD_LEN(value) (value + OP_LENGTH_BIAS) 3841e2adc0dSGao, Fred 3851e2adc0dSGao, Fred static int gvt_check_valid_cmd_length(int len, int valid_len) 3861e2adc0dSGao, Fred { 3871e2adc0dSGao, Fred if (valid_len != len) { 3881e2adc0dSGao, Fred gvt_err("len is not valid: len=%u valid_len=%u\n", 3891e2adc0dSGao, Fred len, valid_len); 3901e2adc0dSGao, Fred return -EFAULT; 3911e2adc0dSGao, Fred } 3921e2adc0dSGao, Fred return 0; 3931e2adc0dSGao, Fred } 3941e2adc0dSGao, Fred 395be1da707SZhi Wang struct cmd_info { 396b007065aSJani Nikula const char *name; 397be1da707SZhi Wang u32 opcode; 398be1da707SZhi Wang 3994f870f1fSGao, Fred #define F_LEN_MASK 3U 400be1da707SZhi Wang #define F_LEN_CONST 1U 401be1da707SZhi Wang #define F_LEN_VAR 0U 4024f870f1fSGao, Fred /* value is const although LEN maybe variable */ 4034f870f1fSGao, Fred #define F_LEN_VAR_FIXED (1<<1) 404be1da707SZhi Wang 405be1da707SZhi Wang /* 406be1da707SZhi Wang * command has its own ip advance logic 407be1da707SZhi Wang * e.g. MI_BATCH_START, MI_BATCH_END 408be1da707SZhi Wang */ 4094f870f1fSGao, Fred #define F_IP_ADVANCE_CUSTOM (1<<2) 410be1da707SZhi Wang u32 flag; 411be1da707SZhi Wang 4128a68d464SChris Wilson #define R_RCS BIT(RCS0) 4138a68d464SChris Wilson #define R_VCS1 BIT(VCS0) 4148a68d464SChris Wilson #define R_VCS2 BIT(VCS1) 415be1da707SZhi Wang #define R_VCS (R_VCS1 | R_VCS2) 4168a68d464SChris Wilson #define R_BCS BIT(BCS0) 4178a68d464SChris Wilson #define R_VECS BIT(VECS0) 418be1da707SZhi Wang #define R_ALL (R_RCS | R_VCS | R_BCS | R_VECS) 419be1da707SZhi Wang /* rings that support this cmd: BLT/RCS/VCS/VECS */ 4202e679d48SJani Nikula u16 rings; 421be1da707SZhi Wang 422be1da707SZhi Wang /* devices that support this cmd: SNB/IVB/HSW/... */ 4232e679d48SJani Nikula u16 devices; 424be1da707SZhi Wang 425be1da707SZhi Wang /* which DWords are address that need fix up. 426be1da707SZhi Wang * bit 0 means a 32-bit non address operand in command 427be1da707SZhi Wang * bit 1 means address operand, which could be 32-bit 428be1da707SZhi Wang * or 64-bit depending on different architectures.( 429be1da707SZhi Wang * defined by "gmadr_bytes_in_cmd" in intel_gvt. 430be1da707SZhi Wang * No matter the address length, each address only takes 431be1da707SZhi Wang * one bit in the bitmap. 432be1da707SZhi Wang */ 4332e679d48SJani Nikula u16 addr_bitmap; 434be1da707SZhi Wang 435be1da707SZhi Wang /* flag == F_LEN_CONST : command length 436be1da707SZhi Wang * flag == F_LEN_VAR : length bias bits 437be1da707SZhi Wang * Note: length is in DWord 438be1da707SZhi Wang */ 4394f870f1fSGao, Fred u32 len; 440be1da707SZhi Wang 441be1da707SZhi Wang parser_cmd_handler handler; 4424f870f1fSGao, Fred 4434f870f1fSGao, Fred /* valid length in DWord */ 4444f870f1fSGao, Fred u32 valid_len; 445be1da707SZhi Wang }; 446be1da707SZhi Wang 447be1da707SZhi Wang struct cmd_entry { 448be1da707SZhi Wang struct hlist_node hlist; 449b007065aSJani Nikula const struct cmd_info *info; 450be1da707SZhi Wang }; 451be1da707SZhi Wang 452be1da707SZhi Wang enum { 453be1da707SZhi Wang RING_BUFFER_INSTRUCTION, 454be1da707SZhi Wang BATCH_BUFFER_INSTRUCTION, 455be1da707SZhi Wang BATCH_BUFFER_2ND_LEVEL, 456be1da707SZhi Wang }; 457be1da707SZhi Wang 458be1da707SZhi Wang enum { 459be1da707SZhi Wang GTT_BUFFER, 460be1da707SZhi Wang PPGTT_BUFFER 461be1da707SZhi Wang }; 462be1da707SZhi Wang 463be1da707SZhi Wang struct parser_exec_state { 464be1da707SZhi Wang struct intel_vgpu *vgpu; 465be1da707SZhi Wang int ring_id; 466be1da707SZhi Wang 467be1da707SZhi Wang int buf_type; 468be1da707SZhi Wang 469be1da707SZhi Wang /* batch buffer address type */ 470be1da707SZhi Wang int buf_addr_type; 471be1da707SZhi Wang 472be1da707SZhi Wang /* graphics memory address of ring buffer start */ 473be1da707SZhi Wang unsigned long ring_start; 474be1da707SZhi Wang unsigned long ring_size; 475be1da707SZhi Wang unsigned long ring_head; 476be1da707SZhi Wang unsigned long ring_tail; 477be1da707SZhi Wang 478be1da707SZhi Wang /* instruction graphics memory address */ 479be1da707SZhi Wang unsigned long ip_gma; 480be1da707SZhi Wang 481be1da707SZhi Wang /* mapped va of the instr_gma */ 482be1da707SZhi Wang void *ip_va; 483be1da707SZhi Wang void *rb_va; 484be1da707SZhi Wang 485be1da707SZhi Wang void *ret_bb_va; 486be1da707SZhi Wang /* next instruction when return from batch buffer to ring buffer */ 487be1da707SZhi Wang unsigned long ret_ip_gma_ring; 488be1da707SZhi Wang 489be1da707SZhi Wang /* next instruction when return from 2nd batch buffer to batch buffer */ 490be1da707SZhi Wang unsigned long ret_ip_gma_bb; 491be1da707SZhi Wang 492be1da707SZhi Wang /* batch buffer address type (GTT or PPGTT) 493be1da707SZhi Wang * used when ret from 2nd level batch buffer 494be1da707SZhi Wang */ 495be1da707SZhi Wang int saved_buf_addr_type; 496ef75c685Sfred gao bool is_ctx_wa; 497be1da707SZhi Wang 498b007065aSJani Nikula const struct cmd_info *info; 499be1da707SZhi Wang 500be1da707SZhi Wang struct intel_vgpu_workload *workload; 501be1da707SZhi Wang }; 502be1da707SZhi Wang 503be1da707SZhi Wang #define gmadr_dw_number(s) \ 504be1da707SZhi Wang (s->vgpu->gvt->device_info.gmadr_bytes_in_cmd >> 2) 505be1da707SZhi Wang 506999ccb40SDu, Changbin static unsigned long bypass_scan_mask = 0; 507be1da707SZhi Wang 508be1da707SZhi Wang /* ring ALL, type = 0 */ 509ed8cce30SJani Nikula static const struct sub_op_bits sub_op_mi[] = { 510be1da707SZhi Wang {31, 29}, 511be1da707SZhi Wang {28, 23}, 512be1da707SZhi Wang }; 513be1da707SZhi Wang 514ed8cce30SJani Nikula static const struct decode_info decode_info_mi = { 515be1da707SZhi Wang "MI", 516be1da707SZhi Wang OP_LEN_MI, 517be1da707SZhi Wang ARRAY_SIZE(sub_op_mi), 518be1da707SZhi Wang sub_op_mi, 519be1da707SZhi Wang }; 520be1da707SZhi Wang 521be1da707SZhi Wang /* ring RCS, command type 2 */ 522ed8cce30SJani Nikula static const struct sub_op_bits sub_op_2d[] = { 523be1da707SZhi Wang {31, 29}, 524be1da707SZhi Wang {28, 22}, 525be1da707SZhi Wang }; 526be1da707SZhi Wang 527ed8cce30SJani Nikula static const struct decode_info decode_info_2d = { 528be1da707SZhi Wang "2D", 529be1da707SZhi Wang OP_LEN_2D, 530be1da707SZhi Wang ARRAY_SIZE(sub_op_2d), 531be1da707SZhi Wang sub_op_2d, 532be1da707SZhi Wang }; 533be1da707SZhi Wang 534be1da707SZhi Wang /* ring RCS, command type 3 */ 535ed8cce30SJani Nikula static const struct sub_op_bits sub_op_3d_media[] = { 536be1da707SZhi Wang {31, 29}, 537be1da707SZhi Wang {28, 27}, 538be1da707SZhi Wang {26, 24}, 539be1da707SZhi Wang {23, 16}, 540be1da707SZhi Wang }; 541be1da707SZhi Wang 542ed8cce30SJani Nikula static const struct decode_info decode_info_3d_media = { 543be1da707SZhi Wang "3D_Media", 544be1da707SZhi Wang OP_LEN_3D_MEDIA, 545be1da707SZhi Wang ARRAY_SIZE(sub_op_3d_media), 546be1da707SZhi Wang sub_op_3d_media, 547be1da707SZhi Wang }; 548be1da707SZhi Wang 549be1da707SZhi Wang /* ring VCS, command type 3 */ 550ed8cce30SJani Nikula static const struct sub_op_bits sub_op_mfx_vc[] = { 551be1da707SZhi Wang {31, 29}, 552be1da707SZhi Wang {28, 27}, 553be1da707SZhi Wang {26, 24}, 554be1da707SZhi Wang {23, 21}, 555be1da707SZhi Wang {20, 16}, 556be1da707SZhi Wang }; 557be1da707SZhi Wang 558ed8cce30SJani Nikula static const struct decode_info decode_info_mfx_vc = { 559be1da707SZhi Wang "MFX_VC", 560be1da707SZhi Wang OP_LEN_MFX_VC, 561be1da707SZhi Wang ARRAY_SIZE(sub_op_mfx_vc), 562be1da707SZhi Wang sub_op_mfx_vc, 563be1da707SZhi Wang }; 564be1da707SZhi Wang 565be1da707SZhi Wang /* ring VECS, command type 3 */ 566ed8cce30SJani Nikula static const struct sub_op_bits sub_op_vebox[] = { 567be1da707SZhi Wang {31, 29}, 568be1da707SZhi Wang {28, 27}, 569be1da707SZhi Wang {26, 24}, 570be1da707SZhi Wang {23, 21}, 571be1da707SZhi Wang {20, 16}, 572be1da707SZhi Wang }; 573be1da707SZhi Wang 574ed8cce30SJani Nikula static const struct decode_info decode_info_vebox = { 575be1da707SZhi Wang "VEBOX", 576be1da707SZhi Wang OP_LEN_VEBOX, 577be1da707SZhi Wang ARRAY_SIZE(sub_op_vebox), 578be1da707SZhi Wang sub_op_vebox, 579be1da707SZhi Wang }; 580be1da707SZhi Wang 581ed8cce30SJani Nikula static const struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = { 5828a68d464SChris Wilson [RCS0] = { 583be1da707SZhi Wang &decode_info_mi, 584be1da707SZhi Wang NULL, 585be1da707SZhi Wang NULL, 586be1da707SZhi Wang &decode_info_3d_media, 587be1da707SZhi Wang NULL, 588be1da707SZhi Wang NULL, 589be1da707SZhi Wang NULL, 590be1da707SZhi Wang NULL, 591be1da707SZhi Wang }, 592be1da707SZhi Wang 5938a68d464SChris Wilson [VCS0] = { 594be1da707SZhi Wang &decode_info_mi, 595be1da707SZhi Wang NULL, 596be1da707SZhi Wang NULL, 597be1da707SZhi Wang &decode_info_mfx_vc, 598be1da707SZhi Wang NULL, 599be1da707SZhi Wang NULL, 600be1da707SZhi Wang NULL, 601be1da707SZhi Wang NULL, 602be1da707SZhi Wang }, 603be1da707SZhi Wang 6048a68d464SChris Wilson [BCS0] = { 605be1da707SZhi Wang &decode_info_mi, 606be1da707SZhi Wang NULL, 607be1da707SZhi Wang &decode_info_2d, 608be1da707SZhi Wang NULL, 609be1da707SZhi Wang NULL, 610be1da707SZhi Wang NULL, 611be1da707SZhi Wang NULL, 612be1da707SZhi Wang NULL, 613be1da707SZhi Wang }, 614be1da707SZhi Wang 6158a68d464SChris Wilson [VECS0] = { 616be1da707SZhi Wang &decode_info_mi, 617be1da707SZhi Wang NULL, 618be1da707SZhi Wang NULL, 619be1da707SZhi Wang &decode_info_vebox, 620be1da707SZhi Wang NULL, 621be1da707SZhi Wang NULL, 622be1da707SZhi Wang NULL, 623be1da707SZhi Wang NULL, 624be1da707SZhi Wang }, 625be1da707SZhi Wang 6268a68d464SChris Wilson [VCS1] = { 627be1da707SZhi Wang &decode_info_mi, 628be1da707SZhi Wang NULL, 629be1da707SZhi Wang NULL, 630be1da707SZhi Wang &decode_info_mfx_vc, 631be1da707SZhi Wang NULL, 632be1da707SZhi Wang NULL, 633be1da707SZhi Wang NULL, 634be1da707SZhi Wang NULL, 635be1da707SZhi Wang }, 636be1da707SZhi Wang }; 637be1da707SZhi Wang 638be1da707SZhi Wang static inline u32 get_opcode(u32 cmd, int ring_id) 639be1da707SZhi Wang { 640ed8cce30SJani Nikula const struct decode_info *d_info; 641be1da707SZhi Wang 642be1da707SZhi Wang d_info = ring_decode_info[ring_id][CMD_TYPE(cmd)]; 643be1da707SZhi Wang if (d_info == NULL) 644be1da707SZhi Wang return INVALID_OP; 645be1da707SZhi Wang 646be1da707SZhi Wang return cmd >> (32 - d_info->op_len); 647be1da707SZhi Wang } 648be1da707SZhi Wang 649b007065aSJani Nikula static inline const struct cmd_info *find_cmd_entry(struct intel_gvt *gvt, 650be1da707SZhi Wang unsigned int opcode, int ring_id) 651be1da707SZhi Wang { 652be1da707SZhi Wang struct cmd_entry *e; 653be1da707SZhi Wang 654be1da707SZhi Wang hash_for_each_possible(gvt->cmd_table, e, hlist, opcode) { 6558a68d464SChris Wilson if (opcode == e->info->opcode && e->info->rings & BIT(ring_id)) 656be1da707SZhi Wang return e->info; 657be1da707SZhi Wang } 658be1da707SZhi Wang return NULL; 659be1da707SZhi Wang } 660be1da707SZhi Wang 661b007065aSJani Nikula static inline const struct cmd_info *get_cmd_info(struct intel_gvt *gvt, 662be1da707SZhi Wang u32 cmd, int ring_id) 663be1da707SZhi Wang { 664be1da707SZhi Wang u32 opcode; 665be1da707SZhi Wang 666be1da707SZhi Wang opcode = get_opcode(cmd, ring_id); 667be1da707SZhi Wang if (opcode == INVALID_OP) 668be1da707SZhi Wang return NULL; 669be1da707SZhi Wang 670be1da707SZhi Wang return find_cmd_entry(gvt, opcode, ring_id); 671be1da707SZhi Wang } 672be1da707SZhi Wang 673be1da707SZhi Wang static inline u32 sub_op_val(u32 cmd, u32 hi, u32 low) 674be1da707SZhi Wang { 675be1da707SZhi Wang return (cmd >> low) & ((1U << (hi - low + 1)) - 1); 676be1da707SZhi Wang } 677be1da707SZhi Wang 678be1da707SZhi Wang static inline void print_opcode(u32 cmd, int ring_id) 679be1da707SZhi Wang { 680ed8cce30SJani Nikula const struct decode_info *d_info; 681be1da707SZhi Wang int i; 682be1da707SZhi Wang 683be1da707SZhi Wang d_info = ring_decode_info[ring_id][CMD_TYPE(cmd)]; 684be1da707SZhi Wang if (d_info == NULL) 685be1da707SZhi Wang return; 686be1da707SZhi Wang 687627c845cSTina Zhang gvt_dbg_cmd("opcode=0x%x %s sub_ops:", 688be1da707SZhi Wang cmd >> (32 - d_info->op_len), d_info->name); 689be1da707SZhi Wang 690be1da707SZhi Wang for (i = 0; i < d_info->nr_sub_op; i++) 691be1da707SZhi Wang pr_err("0x%x ", sub_op_val(cmd, d_info->sub_op[i].hi, 692be1da707SZhi Wang d_info->sub_op[i].low)); 693be1da707SZhi Wang 694be1da707SZhi Wang pr_err("\n"); 695be1da707SZhi Wang } 696be1da707SZhi Wang 697be1da707SZhi Wang static inline u32 *cmd_ptr(struct parser_exec_state *s, int index) 698be1da707SZhi Wang { 699be1da707SZhi Wang return s->ip_va + (index << 2); 700be1da707SZhi Wang } 701be1da707SZhi Wang 702be1da707SZhi Wang static inline u32 cmd_val(struct parser_exec_state *s, int index) 703be1da707SZhi Wang { 704be1da707SZhi Wang return *cmd_ptr(s, index); 705be1da707SZhi Wang } 706be1da707SZhi Wang 707be1da707SZhi Wang static void parser_exec_state_dump(struct parser_exec_state *s) 708be1da707SZhi Wang { 709be1da707SZhi Wang int cnt = 0; 710be1da707SZhi Wang int i; 711be1da707SZhi Wang 712627c845cSTina Zhang gvt_dbg_cmd(" vgpu%d RING%d: ring_start(%08lx) ring_end(%08lx)" 713be1da707SZhi Wang " ring_head(%08lx) ring_tail(%08lx)\n", s->vgpu->id, 714be1da707SZhi Wang s->ring_id, s->ring_start, s->ring_start + s->ring_size, 715be1da707SZhi Wang s->ring_head, s->ring_tail); 716be1da707SZhi Wang 717627c845cSTina Zhang gvt_dbg_cmd(" %s %s ip_gma(%08lx) ", 718be1da707SZhi Wang s->buf_type == RING_BUFFER_INSTRUCTION ? 719be1da707SZhi Wang "RING_BUFFER" : "BATCH_BUFFER", 720be1da707SZhi Wang s->buf_addr_type == GTT_BUFFER ? 721be1da707SZhi Wang "GTT" : "PPGTT", s->ip_gma); 722be1da707SZhi Wang 723be1da707SZhi Wang if (s->ip_va == NULL) { 724627c845cSTina Zhang gvt_dbg_cmd(" ip_va(NULL)"); 725be1da707SZhi Wang return; 726be1da707SZhi Wang } 727be1da707SZhi Wang 728627c845cSTina Zhang gvt_dbg_cmd(" ip_va=%p: %08x %08x %08x %08x\n", 729be1da707SZhi Wang s->ip_va, cmd_val(s, 0), cmd_val(s, 1), 730be1da707SZhi Wang cmd_val(s, 2), cmd_val(s, 3)); 731be1da707SZhi Wang 732be1da707SZhi Wang print_opcode(cmd_val(s, 0), s->ring_id); 733be1da707SZhi Wang 734be1da707SZhi Wang s->ip_va = (u32 *)((((u64)s->ip_va) >> 12) << 12); 735be1da707SZhi Wang 736be1da707SZhi Wang while (cnt < 1024) { 737e4aeba69SChangbin Du gvt_dbg_cmd("ip_va=%p: ", s->ip_va); 738be1da707SZhi Wang for (i = 0; i < 8; i++) 739e4aeba69SChangbin Du gvt_dbg_cmd("%08x ", cmd_val(s, i)); 740e4aeba69SChangbin Du gvt_dbg_cmd("\n"); 741be1da707SZhi Wang 742be1da707SZhi Wang s->ip_va += 8 * sizeof(u32); 743be1da707SZhi Wang cnt += 8; 744be1da707SZhi Wang } 745be1da707SZhi Wang } 746be1da707SZhi Wang 747be1da707SZhi Wang static inline void update_ip_va(struct parser_exec_state *s) 748be1da707SZhi Wang { 749be1da707SZhi Wang unsigned long len = 0; 750be1da707SZhi Wang 751be1da707SZhi Wang if (WARN_ON(s->ring_head == s->ring_tail)) 752be1da707SZhi Wang return; 753be1da707SZhi Wang 754be1da707SZhi Wang if (s->buf_type == RING_BUFFER_INSTRUCTION) { 755be1da707SZhi Wang unsigned long ring_top = s->ring_start + s->ring_size; 756be1da707SZhi Wang 757be1da707SZhi Wang if (s->ring_head > s->ring_tail) { 758be1da707SZhi Wang if (s->ip_gma >= s->ring_head && s->ip_gma < ring_top) 759be1da707SZhi Wang len = (s->ip_gma - s->ring_head); 760be1da707SZhi Wang else if (s->ip_gma >= s->ring_start && 761be1da707SZhi Wang s->ip_gma <= s->ring_tail) 762be1da707SZhi Wang len = (ring_top - s->ring_head) + 763be1da707SZhi Wang (s->ip_gma - s->ring_start); 764be1da707SZhi Wang } else 765be1da707SZhi Wang len = (s->ip_gma - s->ring_head); 766be1da707SZhi Wang 767be1da707SZhi Wang s->ip_va = s->rb_va + len; 768be1da707SZhi Wang } else {/* shadow batch buffer */ 769be1da707SZhi Wang s->ip_va = s->ret_bb_va; 770be1da707SZhi Wang } 771be1da707SZhi Wang } 772be1da707SZhi Wang 773be1da707SZhi Wang static inline int ip_gma_set(struct parser_exec_state *s, 774be1da707SZhi Wang unsigned long ip_gma) 775be1da707SZhi Wang { 776be1da707SZhi Wang WARN_ON(!IS_ALIGNED(ip_gma, 4)); 777be1da707SZhi Wang 778be1da707SZhi Wang s->ip_gma = ip_gma; 779be1da707SZhi Wang update_ip_va(s); 780be1da707SZhi Wang return 0; 781be1da707SZhi Wang } 782be1da707SZhi Wang 783be1da707SZhi Wang static inline int ip_gma_advance(struct parser_exec_state *s, 784be1da707SZhi Wang unsigned int dw_len) 785be1da707SZhi Wang { 786be1da707SZhi Wang s->ip_gma += (dw_len << 2); 787be1da707SZhi Wang 788be1da707SZhi Wang if (s->buf_type == RING_BUFFER_INSTRUCTION) { 789be1da707SZhi Wang if (s->ip_gma >= s->ring_start + s->ring_size) 790be1da707SZhi Wang s->ip_gma -= s->ring_size; 791be1da707SZhi Wang update_ip_va(s); 792be1da707SZhi Wang } else { 793be1da707SZhi Wang s->ip_va += (dw_len << 2); 794be1da707SZhi Wang } 795be1da707SZhi Wang 796be1da707SZhi Wang return 0; 797be1da707SZhi Wang } 798be1da707SZhi Wang 799b007065aSJani Nikula static inline int get_cmd_length(const struct cmd_info *info, u32 cmd) 800be1da707SZhi Wang { 801be1da707SZhi Wang if ((info->flag & F_LEN_MASK) == F_LEN_CONST) 802be1da707SZhi Wang return info->len; 803be1da707SZhi Wang else 804be1da707SZhi Wang return (cmd & ((1U << info->len) - 1)) + 2; 805be1da707SZhi Wang return 0; 806be1da707SZhi Wang } 807be1da707SZhi Wang 808be1da707SZhi Wang static inline int cmd_length(struct parser_exec_state *s) 809be1da707SZhi Wang { 810be1da707SZhi Wang return get_cmd_length(s->info, cmd_val(s, 0)); 811be1da707SZhi Wang } 812be1da707SZhi Wang 813be1da707SZhi Wang /* do not remove this, some platform may need clflush here */ 814be1da707SZhi Wang #define patch_value(s, addr, val) do { \ 815be1da707SZhi Wang *addr = val; \ 816be1da707SZhi Wang } while (0) 817be1da707SZhi Wang 818be1da707SZhi Wang static bool is_shadowed_mmio(unsigned int offset) 819be1da707SZhi Wang { 820be1da707SZhi Wang bool ret = false; 821be1da707SZhi Wang 822be1da707SZhi Wang if ((offset == 0x2168) || /*BB current head register UDW */ 823be1da707SZhi Wang (offset == 0x2140) || /*BB current header register */ 824be1da707SZhi Wang (offset == 0x211c) || /*second BB header register UDW */ 825be1da707SZhi Wang (offset == 0x2114)) { /*second BB header register UDW */ 826be1da707SZhi Wang ret = true; 827be1da707SZhi Wang } 828be1da707SZhi Wang return ret; 829be1da707SZhi Wang } 830be1da707SZhi Wang 8314938ca90SZhao Yan static inline bool is_force_nonpriv_mmio(unsigned int offset) 8324938ca90SZhao Yan { 8334938ca90SZhao Yan return (offset >= 0x24d0 && offset < 0x2500); 8344938ca90SZhao Yan } 8354938ca90SZhao Yan 8364938ca90SZhao Yan static int force_nonpriv_reg_handler(struct parser_exec_state *s, 837cb8ba171SZhao Yan unsigned int offset, unsigned int index, char *cmd) 8384938ca90SZhao Yan { 8394938ca90SZhao Yan struct intel_gvt *gvt = s->vgpu->gvt; 840cb8ba171SZhao Yan unsigned int data; 8413d8b9e25SZhao Yan u32 ring_base; 8423d8b9e25SZhao Yan u32 nopid; 8433d8b9e25SZhao Yan struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv; 8444938ca90SZhao Yan 845cb8ba171SZhao Yan if (!strcmp(cmd, "lri")) 846cb8ba171SZhao Yan data = cmd_val(s, index + 1); 847cb8ba171SZhao Yan else { 848cb8ba171SZhao Yan gvt_err("Unexpected forcenonpriv 0x%x write from cmd %s\n", 849cb8ba171SZhao Yan offset, cmd); 850cb8ba171SZhao Yan return -EINVAL; 851cb8ba171SZhao Yan } 852cb8ba171SZhao Yan 8533d8b9e25SZhao Yan ring_base = dev_priv->engine[s->ring_id]->mmio_base; 8543d8b9e25SZhao Yan nopid = i915_mmio_reg_offset(RING_NOPID(ring_base)); 8553d8b9e25SZhao Yan 8563d8b9e25SZhao Yan if (!intel_gvt_in_force_nonpriv_whitelist(gvt, data) && 8573d8b9e25SZhao Yan data != nopid) { 8584938ca90SZhao Yan gvt_err("Unexpected forcenonpriv 0x%x LRI write, value=0x%x\n", 8594938ca90SZhao Yan offset, data); 8600438a105SZhao Yan patch_value(s, cmd_ptr(s, index), nopid); 8610438a105SZhao Yan return 0; 8624938ca90SZhao Yan } 8634938ca90SZhao Yan return 0; 8644938ca90SZhao Yan } 8654938ca90SZhao Yan 866f402f2d6SWeinan Li static inline bool is_mocs_mmio(unsigned int offset) 867f402f2d6SWeinan Li { 868f402f2d6SWeinan Li return ((offset >= 0xc800) && (offset <= 0xcff8)) || 869f402f2d6SWeinan Li ((offset >= 0xb020) && (offset <= 0xb0a0)); 870f402f2d6SWeinan Li } 871f402f2d6SWeinan Li 872f402f2d6SWeinan Li static int mocs_cmd_reg_handler(struct parser_exec_state *s, 873f402f2d6SWeinan Li unsigned int offset, unsigned int index) 874f402f2d6SWeinan Li { 875f402f2d6SWeinan Li if (!is_mocs_mmio(offset)) 876f402f2d6SWeinan Li return -EINVAL; 877f402f2d6SWeinan Li vgpu_vreg(s->vgpu, offset) = cmd_val(s, index + 1); 878f402f2d6SWeinan Li return 0; 879f402f2d6SWeinan Li } 880f402f2d6SWeinan Li 881be1da707SZhi Wang static int cmd_reg_handler(struct parser_exec_state *s, 882be1da707SZhi Wang unsigned int offset, unsigned int index, char *cmd) 883be1da707SZhi Wang { 884be1da707SZhi Wang struct intel_vgpu *vgpu = s->vgpu; 885be1da707SZhi Wang struct intel_gvt *gvt = vgpu->gvt; 8866cef21a1SHang Yuan u32 ctx_sr_ctl; 887be1da707SZhi Wang 888be1da707SZhi Wang if (offset + 4 > gvt->device_info.mmio_size) { 889695fbc08STina Zhang gvt_vgpu_err("%s access to (%x) outside of MMIO range\n", 890be1da707SZhi Wang cmd, offset); 8915c56883aSfred gao return -EFAULT; 892be1da707SZhi Wang } 893be1da707SZhi Wang 894be1da707SZhi Wang if (!intel_gvt_mmio_is_cmd_access(gvt, offset)) { 895695fbc08STina Zhang gvt_vgpu_err("%s access to non-render register (%x)\n", 896695fbc08STina Zhang cmd, offset); 8978d458ea0SZhao Yan return -EBADRQC; 898be1da707SZhi Wang } 899be1da707SZhi Wang 900be1da707SZhi Wang if (is_shadowed_mmio(offset)) { 901695fbc08STina Zhang gvt_vgpu_err("found access of shadowed MMIO %x\n", offset); 902be1da707SZhi Wang return 0; 903be1da707SZhi Wang } 904be1da707SZhi Wang 905f402f2d6SWeinan Li if (is_mocs_mmio(offset) && 906f402f2d6SWeinan Li mocs_cmd_reg_handler(s, offset, index)) 907f402f2d6SWeinan Li return -EINVAL; 908f402f2d6SWeinan Li 9094938ca90SZhao Yan if (is_force_nonpriv_mmio(offset) && 910cb8ba171SZhao Yan force_nonpriv_reg_handler(s, offset, index, cmd)) 9115c56883aSfred gao return -EPERM; 9124938ca90SZhao Yan 913be1da707SZhi Wang if (offset == i915_mmio_reg_offset(DERRMR) || 914be1da707SZhi Wang offset == i915_mmio_reg_offset(FORCEWAKE_MT)) { 915be1da707SZhi Wang /* Writing to HW VGT_PVINFO_PAGE offset will be discarded */ 916be1da707SZhi Wang patch_value(s, cmd_ptr(s, index), VGT_PVINFO_PAGE); 917be1da707SZhi Wang } 918be1da707SZhi Wang 9196cef21a1SHang Yuan /* TODO 920df2ea3c2SYan Zhao * In order to let workload with inhibit context to generate 921df2ea3c2SYan Zhao * correct image data into memory, vregs values will be loaded to 922df2ea3c2SYan Zhao * hw via LRIs in the workload with inhibit context. But as 923df2ea3c2SYan Zhao * indirect context is loaded prior to LRIs in workload, we don't 924df2ea3c2SYan Zhao * want reg values specified in indirect context overwritten by 925df2ea3c2SYan Zhao * LRIs in workloads. So, when scanning an indirect context, we 926df2ea3c2SYan Zhao * update reg values in it into vregs, so LRIs in workload with 927df2ea3c2SYan Zhao * inhibit context will restore with correct values 9286cef21a1SHang Yuan */ 929df2ea3c2SYan Zhao if (IS_GEN(gvt->dev_priv, 9) && 9306cef21a1SHang Yuan intel_gvt_mmio_is_in_ctx(gvt, offset) && 9316cef21a1SHang Yuan !strncmp(cmd, "lri", 3)) { 9326cef21a1SHang Yuan intel_gvt_hypervisor_read_gpa(s->vgpu, 9336cef21a1SHang Yuan s->workload->ring_context_gpa + 12, &ctx_sr_ctl, 4); 9346cef21a1SHang Yuan /* check inhibit context */ 9356cef21a1SHang Yuan if (ctx_sr_ctl & 1) { 9366cef21a1SHang Yuan u32 data = cmd_val(s, index + 1); 9376cef21a1SHang Yuan 9386cef21a1SHang Yuan if (intel_gvt_mmio_has_mode_mask(s->vgpu->gvt, offset)) 9396cef21a1SHang Yuan intel_vgpu_mask_mmio_write(vgpu, 9406cef21a1SHang Yuan offset, &data, 4); 9416cef21a1SHang Yuan else 9426cef21a1SHang Yuan vgpu_vreg(vgpu, offset) = data; 9436cef21a1SHang Yuan } 9446cef21a1SHang Yuan } 9456cef21a1SHang Yuan 946be1da707SZhi Wang /* TODO: Update the global mask if this MMIO is a masked-MMIO */ 947be1da707SZhi Wang intel_gvt_mmio_set_cmd_accessed(gvt, offset); 948be1da707SZhi Wang return 0; 949be1da707SZhi Wang } 950be1da707SZhi Wang 951be1da707SZhi Wang #define cmd_reg(s, i) \ 952be1da707SZhi Wang (cmd_val(s, i) & GENMASK(22, 2)) 953be1da707SZhi Wang 954be1da707SZhi Wang #define cmd_reg_inhibit(s, i) \ 955be1da707SZhi Wang (cmd_val(s, i) & GENMASK(22, 18)) 956be1da707SZhi Wang 957be1da707SZhi Wang #define cmd_gma(s, i) \ 958be1da707SZhi Wang (cmd_val(s, i) & GENMASK(31, 2)) 959be1da707SZhi Wang 960be1da707SZhi Wang #define cmd_gma_hi(s, i) \ 961be1da707SZhi Wang (cmd_val(s, i) & GENMASK(15, 0)) 962be1da707SZhi Wang 963be1da707SZhi Wang static int cmd_handler_lri(struct parser_exec_state *s) 964be1da707SZhi Wang { 965be1da707SZhi Wang int i, ret = 0; 966be1da707SZhi Wang int cmd_len = cmd_length(s); 967be1da707SZhi Wang struct intel_gvt *gvt = s->vgpu->gvt; 96800a33be4SGao, Fred u32 valid_len = CMD_LEN(1); 96900a33be4SGao, Fred 97000a33be4SGao, Fred /* 97100a33be4SGao, Fred * Official intel docs are somewhat sloppy , check the definition of 97200a33be4SGao, Fred * MI_LOAD_REGISTER_IMM. 97300a33be4SGao, Fred */ 97400a33be4SGao, Fred #define MAX_VALID_LEN 127 97500a33be4SGao, Fred if ((cmd_len < valid_len) || (cmd_len > MAX_VALID_LEN)) { 97600a33be4SGao, Fred gvt_err("len is not valid: len=%u valid_len=%u\n", 97700a33be4SGao, Fred cmd_len, valid_len); 97800a33be4SGao, Fred return -EFAULT; 97900a33be4SGao, Fred } 980be1da707SZhi Wang 981be1da707SZhi Wang for (i = 1; i < cmd_len; i += 2) { 9828a68d464SChris Wilson if (IS_BROADWELL(gvt->dev_priv) && s->ring_id != RCS0) { 9838a68d464SChris Wilson if (s->ring_id == BCS0 && 9848a68d464SChris Wilson cmd_reg(s, i) == i915_mmio_reg_offset(DERRMR)) 985be1da707SZhi Wang ret |= 0; 986be1da707SZhi Wang else 9878a68d464SChris Wilson ret |= cmd_reg_inhibit(s, i) ? -EBADRQC : 0; 988be1da707SZhi Wang } 989be1da707SZhi Wang if (ret) 990be1da707SZhi Wang break; 991be1da707SZhi Wang ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lri"); 9925c56883aSfred gao if (ret) 9935c56883aSfred gao break; 994be1da707SZhi Wang } 995be1da707SZhi Wang return ret; 996be1da707SZhi Wang } 997be1da707SZhi Wang 998be1da707SZhi Wang static int cmd_handler_lrr(struct parser_exec_state *s) 999be1da707SZhi Wang { 1000be1da707SZhi Wang int i, ret = 0; 1001be1da707SZhi Wang int cmd_len = cmd_length(s); 1002be1da707SZhi Wang 1003be1da707SZhi Wang for (i = 1; i < cmd_len; i += 2) { 1004be1da707SZhi Wang if (IS_BROADWELL(s->vgpu->gvt->dev_priv)) 1005be1da707SZhi Wang ret |= ((cmd_reg_inhibit(s, i) || 1006be1da707SZhi Wang (cmd_reg_inhibit(s, i + 1)))) ? 10075c56883aSfred gao -EBADRQC : 0; 1008be1da707SZhi Wang if (ret) 1009be1da707SZhi Wang break; 1010be1da707SZhi Wang ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrr-src"); 10115c56883aSfred gao if (ret) 10125c56883aSfred gao break; 1013be1da707SZhi Wang ret |= cmd_reg_handler(s, cmd_reg(s, i + 1), i, "lrr-dst"); 10145c56883aSfred gao if (ret) 10155c56883aSfred gao break; 1016be1da707SZhi Wang } 1017be1da707SZhi Wang return ret; 1018be1da707SZhi Wang } 1019be1da707SZhi Wang 1020be1da707SZhi Wang static inline int cmd_address_audit(struct parser_exec_state *s, 1021be1da707SZhi Wang unsigned long guest_gma, int op_size, bool index_mode); 1022be1da707SZhi Wang 1023be1da707SZhi Wang static int cmd_handler_lrm(struct parser_exec_state *s) 1024be1da707SZhi Wang { 1025be1da707SZhi Wang struct intel_gvt *gvt = s->vgpu->gvt; 1026be1da707SZhi Wang int gmadr_bytes = gvt->device_info.gmadr_bytes_in_cmd; 1027be1da707SZhi Wang unsigned long gma; 1028be1da707SZhi Wang int i, ret = 0; 1029be1da707SZhi Wang int cmd_len = cmd_length(s); 1030be1da707SZhi Wang 1031be1da707SZhi Wang for (i = 1; i < cmd_len;) { 1032be1da707SZhi Wang if (IS_BROADWELL(gvt->dev_priv)) 10335c56883aSfred gao ret |= (cmd_reg_inhibit(s, i)) ? -EBADRQC : 0; 1034be1da707SZhi Wang if (ret) 1035be1da707SZhi Wang break; 1036be1da707SZhi Wang ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrm"); 10375c56883aSfred gao if (ret) 10385c56883aSfred gao break; 1039be1da707SZhi Wang if (cmd_val(s, 0) & (1 << 22)) { 1040be1da707SZhi Wang gma = cmd_gma(s, i + 1); 1041be1da707SZhi Wang if (gmadr_bytes == 8) 1042be1da707SZhi Wang gma |= (cmd_gma_hi(s, i + 2)) << 32; 1043be1da707SZhi Wang ret |= cmd_address_audit(s, gma, sizeof(u32), false); 10445c56883aSfred gao if (ret) 10455c56883aSfred gao break; 1046be1da707SZhi Wang } 1047be1da707SZhi Wang i += gmadr_dw_number(s) + 1; 1048be1da707SZhi Wang } 1049be1da707SZhi Wang return ret; 1050be1da707SZhi Wang } 1051be1da707SZhi Wang 1052be1da707SZhi Wang static int cmd_handler_srm(struct parser_exec_state *s) 1053be1da707SZhi Wang { 1054be1da707SZhi Wang int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd; 1055be1da707SZhi Wang unsigned long gma; 1056be1da707SZhi Wang int i, ret = 0; 1057be1da707SZhi Wang int cmd_len = cmd_length(s); 1058be1da707SZhi Wang 1059be1da707SZhi Wang for (i = 1; i < cmd_len;) { 1060be1da707SZhi Wang ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "srm"); 10615c56883aSfred gao if (ret) 10625c56883aSfred gao break; 1063be1da707SZhi Wang if (cmd_val(s, 0) & (1 << 22)) { 1064be1da707SZhi Wang gma = cmd_gma(s, i + 1); 1065be1da707SZhi Wang if (gmadr_bytes == 8) 1066be1da707SZhi Wang gma |= (cmd_gma_hi(s, i + 2)) << 32; 1067be1da707SZhi Wang ret |= cmd_address_audit(s, gma, sizeof(u32), false); 10685c56883aSfred gao if (ret) 10695c56883aSfred gao break; 1070be1da707SZhi Wang } 1071be1da707SZhi Wang i += gmadr_dw_number(s) + 1; 1072be1da707SZhi Wang } 1073be1da707SZhi Wang return ret; 1074be1da707SZhi Wang } 1075be1da707SZhi Wang 1076be1da707SZhi Wang struct cmd_interrupt_event { 1077be1da707SZhi Wang int pipe_control_notify; 1078be1da707SZhi Wang int mi_flush_dw; 1079be1da707SZhi Wang int mi_user_interrupt; 1080be1da707SZhi Wang }; 1081be1da707SZhi Wang 1082999ccb40SDu, Changbin static struct cmd_interrupt_event cmd_interrupt_events[] = { 10838a68d464SChris Wilson [RCS0] = { 1084be1da707SZhi Wang .pipe_control_notify = RCS_PIPE_CONTROL, 1085be1da707SZhi Wang .mi_flush_dw = INTEL_GVT_EVENT_RESERVED, 1086be1da707SZhi Wang .mi_user_interrupt = RCS_MI_USER_INTERRUPT, 1087be1da707SZhi Wang }, 10888a68d464SChris Wilson [BCS0] = { 1089be1da707SZhi Wang .pipe_control_notify = INTEL_GVT_EVENT_RESERVED, 1090be1da707SZhi Wang .mi_flush_dw = BCS_MI_FLUSH_DW, 1091be1da707SZhi Wang .mi_user_interrupt = BCS_MI_USER_INTERRUPT, 1092be1da707SZhi Wang }, 10938a68d464SChris Wilson [VCS0] = { 1094be1da707SZhi Wang .pipe_control_notify = INTEL_GVT_EVENT_RESERVED, 1095be1da707SZhi Wang .mi_flush_dw = VCS_MI_FLUSH_DW, 1096be1da707SZhi Wang .mi_user_interrupt = VCS_MI_USER_INTERRUPT, 1097be1da707SZhi Wang }, 10988a68d464SChris Wilson [VCS1] = { 1099be1da707SZhi Wang .pipe_control_notify = INTEL_GVT_EVENT_RESERVED, 1100be1da707SZhi Wang .mi_flush_dw = VCS2_MI_FLUSH_DW, 1101be1da707SZhi Wang .mi_user_interrupt = VCS2_MI_USER_INTERRUPT, 1102be1da707SZhi Wang }, 11038a68d464SChris Wilson [VECS0] = { 1104be1da707SZhi Wang .pipe_control_notify = INTEL_GVT_EVENT_RESERVED, 1105be1da707SZhi Wang .mi_flush_dw = VECS_MI_FLUSH_DW, 1106be1da707SZhi Wang .mi_user_interrupt = VECS_MI_USER_INTERRUPT, 1107be1da707SZhi Wang }, 1108be1da707SZhi Wang }; 1109be1da707SZhi Wang 1110be1da707SZhi Wang static int cmd_handler_pipe_control(struct parser_exec_state *s) 1111be1da707SZhi Wang { 1112be1da707SZhi Wang int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd; 1113be1da707SZhi Wang unsigned long gma; 1114be1da707SZhi Wang bool index_mode = false; 1115be1da707SZhi Wang unsigned int post_sync; 1116be1da707SZhi Wang int ret = 0; 1117ac071578SXiaolin Zhang u32 hws_pga, val; 1118be1da707SZhi Wang 1119be1da707SZhi Wang post_sync = (cmd_val(s, 1) & PIPE_CONTROL_POST_SYNC_OP_MASK) >> 14; 1120be1da707SZhi Wang 1121be1da707SZhi Wang /* LRI post sync */ 1122be1da707SZhi Wang if (cmd_val(s, 1) & PIPE_CONTROL_MMIO_WRITE) 1123be1da707SZhi Wang ret = cmd_reg_handler(s, cmd_reg(s, 2), 1, "pipe_ctrl"); 1124be1da707SZhi Wang /* post sync */ 1125be1da707SZhi Wang else if (post_sync) { 1126be1da707SZhi Wang if (post_sync == 2) 1127be1da707SZhi Wang ret = cmd_reg_handler(s, 0x2350, 1, "pipe_ctrl"); 1128be1da707SZhi Wang else if (post_sync == 3) 1129be1da707SZhi Wang ret = cmd_reg_handler(s, 0x2358, 1, "pipe_ctrl"); 1130be1da707SZhi Wang else if (post_sync == 1) { 1131be1da707SZhi Wang /* check ggtt*/ 11323f765a34SYulei Zhang if ((cmd_val(s, 1) & PIPE_CONTROL_GLOBAL_GTT_IVB)) { 1133be1da707SZhi Wang gma = cmd_val(s, 2) & GENMASK(31, 3); 1134be1da707SZhi Wang if (gmadr_bytes == 8) 1135be1da707SZhi Wang gma |= (cmd_gma_hi(s, 3)) << 32; 1136be1da707SZhi Wang /* Store Data Index */ 1137be1da707SZhi Wang if (cmd_val(s, 1) & (1 << 21)) 1138be1da707SZhi Wang index_mode = true; 1139be1da707SZhi Wang ret |= cmd_address_audit(s, gma, sizeof(u64), 1140be1da707SZhi Wang index_mode); 1141ac071578SXiaolin Zhang if (ret) 1142ac071578SXiaolin Zhang return ret; 1143ac071578SXiaolin Zhang if (index_mode) { 1144ac071578SXiaolin Zhang hws_pga = s->vgpu->hws_pga[s->ring_id]; 1145ac071578SXiaolin Zhang gma = hws_pga + gma; 1146ac071578SXiaolin Zhang patch_value(s, cmd_ptr(s, 2), gma); 1147ac071578SXiaolin Zhang val = cmd_val(s, 1) & (~(1 << 21)); 1148ac071578SXiaolin Zhang patch_value(s, cmd_ptr(s, 1), val); 1149ac071578SXiaolin Zhang } 1150be1da707SZhi Wang } 1151be1da707SZhi Wang } 1152be1da707SZhi Wang } 1153be1da707SZhi Wang 1154be1da707SZhi Wang if (ret) 1155be1da707SZhi Wang return ret; 1156be1da707SZhi Wang 1157be1da707SZhi Wang if (cmd_val(s, 1) & PIPE_CONTROL_NOTIFY) 1158be1da707SZhi Wang set_bit(cmd_interrupt_events[s->ring_id].pipe_control_notify, 1159be1da707SZhi Wang s->workload->pending_events); 1160be1da707SZhi Wang return 0; 1161be1da707SZhi Wang } 1162be1da707SZhi Wang 1163be1da707SZhi Wang static int cmd_handler_mi_user_interrupt(struct parser_exec_state *s) 1164be1da707SZhi Wang { 1165be1da707SZhi Wang set_bit(cmd_interrupt_events[s->ring_id].mi_user_interrupt, 1166be1da707SZhi Wang s->workload->pending_events); 11675da795b0SZhipeng Gong patch_value(s, cmd_ptr(s, 0), MI_NOOP); 1168be1da707SZhi Wang return 0; 1169be1da707SZhi Wang } 1170be1da707SZhi Wang 1171be1da707SZhi Wang static int cmd_advance_default(struct parser_exec_state *s) 1172be1da707SZhi Wang { 1173be1da707SZhi Wang return ip_gma_advance(s, cmd_length(s)); 1174be1da707SZhi Wang } 1175be1da707SZhi Wang 1176be1da707SZhi Wang static int cmd_handler_mi_batch_buffer_end(struct parser_exec_state *s) 1177be1da707SZhi Wang { 1178be1da707SZhi Wang int ret; 1179be1da707SZhi Wang 1180be1da707SZhi Wang if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) { 1181be1da707SZhi Wang s->buf_type = BATCH_BUFFER_INSTRUCTION; 1182be1da707SZhi Wang ret = ip_gma_set(s, s->ret_ip_gma_bb); 1183be1da707SZhi Wang s->buf_addr_type = s->saved_buf_addr_type; 1184be1da707SZhi Wang } else { 1185be1da707SZhi Wang s->buf_type = RING_BUFFER_INSTRUCTION; 1186be1da707SZhi Wang s->buf_addr_type = GTT_BUFFER; 1187be1da707SZhi Wang if (s->ret_ip_gma_ring >= s->ring_start + s->ring_size) 1188be1da707SZhi Wang s->ret_ip_gma_ring -= s->ring_size; 1189be1da707SZhi Wang ret = ip_gma_set(s, s->ret_ip_gma_ring); 1190be1da707SZhi Wang } 1191be1da707SZhi Wang return ret; 1192be1da707SZhi Wang } 1193be1da707SZhi Wang 1194be1da707SZhi Wang struct mi_display_flip_command_info { 1195be1da707SZhi Wang int pipe; 1196be1da707SZhi Wang int plane; 1197be1da707SZhi Wang int event; 1198be1da707SZhi Wang i915_reg_t stride_reg; 1199be1da707SZhi Wang i915_reg_t ctrl_reg; 1200be1da707SZhi Wang i915_reg_t surf_reg; 1201be1da707SZhi Wang u64 stride_val; 1202be1da707SZhi Wang u64 tile_val; 1203be1da707SZhi Wang u64 surf_val; 1204be1da707SZhi Wang bool async_flip; 1205be1da707SZhi Wang }; 1206be1da707SZhi Wang 1207be1da707SZhi Wang struct plane_code_mapping { 1208be1da707SZhi Wang int pipe; 1209be1da707SZhi Wang int plane; 1210be1da707SZhi Wang int event; 1211be1da707SZhi Wang }; 1212be1da707SZhi Wang 1213be1da707SZhi Wang static int gen8_decode_mi_display_flip(struct parser_exec_state *s, 1214be1da707SZhi Wang struct mi_display_flip_command_info *info) 1215be1da707SZhi Wang { 1216be1da707SZhi Wang struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv; 1217be1da707SZhi Wang struct plane_code_mapping gen8_plane_code[] = { 1218be1da707SZhi Wang [0] = {PIPE_A, PLANE_A, PRIMARY_A_FLIP_DONE}, 1219be1da707SZhi Wang [1] = {PIPE_B, PLANE_A, PRIMARY_B_FLIP_DONE}, 1220be1da707SZhi Wang [2] = {PIPE_A, PLANE_B, SPRITE_A_FLIP_DONE}, 1221be1da707SZhi Wang [3] = {PIPE_B, PLANE_B, SPRITE_B_FLIP_DONE}, 1222be1da707SZhi Wang [4] = {PIPE_C, PLANE_A, PRIMARY_C_FLIP_DONE}, 1223be1da707SZhi Wang [5] = {PIPE_C, PLANE_B, SPRITE_C_FLIP_DONE}, 1224be1da707SZhi Wang }; 1225be1da707SZhi Wang u32 dword0, dword1, dword2; 1226be1da707SZhi Wang u32 v; 1227be1da707SZhi Wang 1228be1da707SZhi Wang dword0 = cmd_val(s, 0); 1229be1da707SZhi Wang dword1 = cmd_val(s, 1); 1230be1da707SZhi Wang dword2 = cmd_val(s, 2); 1231be1da707SZhi Wang 1232be1da707SZhi Wang v = (dword0 & GENMASK(21, 19)) >> 19; 1233be1da707SZhi Wang if (WARN_ON(v >= ARRAY_SIZE(gen8_plane_code))) 12345c56883aSfred gao return -EBADRQC; 1235be1da707SZhi Wang 1236be1da707SZhi Wang info->pipe = gen8_plane_code[v].pipe; 1237be1da707SZhi Wang info->plane = gen8_plane_code[v].plane; 1238be1da707SZhi Wang info->event = gen8_plane_code[v].event; 1239be1da707SZhi Wang info->stride_val = (dword1 & GENMASK(15, 6)) >> 6; 1240be1da707SZhi Wang info->tile_val = (dword1 & 0x1); 1241be1da707SZhi Wang info->surf_val = (dword2 & GENMASK(31, 12)) >> 12; 1242be1da707SZhi Wang info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1); 1243be1da707SZhi Wang 1244be1da707SZhi Wang if (info->plane == PLANE_A) { 1245be1da707SZhi Wang info->ctrl_reg = DSPCNTR(info->pipe); 1246be1da707SZhi Wang info->stride_reg = DSPSTRIDE(info->pipe); 1247be1da707SZhi Wang info->surf_reg = DSPSURF(info->pipe); 1248be1da707SZhi Wang } else if (info->plane == PLANE_B) { 1249be1da707SZhi Wang info->ctrl_reg = SPRCTL(info->pipe); 1250be1da707SZhi Wang info->stride_reg = SPRSTRIDE(info->pipe); 1251be1da707SZhi Wang info->surf_reg = SPRSURF(info->pipe); 1252be1da707SZhi Wang } else { 1253be1da707SZhi Wang WARN_ON(1); 12545c56883aSfred gao return -EBADRQC; 1255be1da707SZhi Wang } 1256be1da707SZhi Wang return 0; 1257be1da707SZhi Wang } 1258be1da707SZhi Wang 1259be1da707SZhi Wang static int skl_decode_mi_display_flip(struct parser_exec_state *s, 1260be1da707SZhi Wang struct mi_display_flip_command_info *info) 1261be1da707SZhi Wang { 1262be1da707SZhi Wang struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv; 1263695fbc08STina Zhang struct intel_vgpu *vgpu = s->vgpu; 1264be1da707SZhi Wang u32 dword0 = cmd_val(s, 0); 1265be1da707SZhi Wang u32 dword1 = cmd_val(s, 1); 1266be1da707SZhi Wang u32 dword2 = cmd_val(s, 2); 1267be1da707SZhi Wang u32 plane = (dword0 & GENMASK(12, 8)) >> 8; 1268be1da707SZhi Wang 12696e27d514SXu Han info->plane = PRIMARY_PLANE; 12706e27d514SXu Han 1271be1da707SZhi Wang switch (plane) { 1272be1da707SZhi Wang case MI_DISPLAY_FLIP_SKL_PLANE_1_A: 1273be1da707SZhi Wang info->pipe = PIPE_A; 1274be1da707SZhi Wang info->event = PRIMARY_A_FLIP_DONE; 1275be1da707SZhi Wang break; 1276be1da707SZhi Wang case MI_DISPLAY_FLIP_SKL_PLANE_1_B: 1277be1da707SZhi Wang info->pipe = PIPE_B; 1278be1da707SZhi Wang info->event = PRIMARY_B_FLIP_DONE; 1279be1da707SZhi Wang break; 1280be1da707SZhi Wang case MI_DISPLAY_FLIP_SKL_PLANE_1_C: 128164fafcf5SMin He info->pipe = PIPE_C; 1282be1da707SZhi Wang info->event = PRIMARY_C_FLIP_DONE; 1283be1da707SZhi Wang break; 12846e27d514SXu Han 12856e27d514SXu Han case MI_DISPLAY_FLIP_SKL_PLANE_2_A: 12866e27d514SXu Han info->pipe = PIPE_A; 12876e27d514SXu Han info->event = SPRITE_A_FLIP_DONE; 12886e27d514SXu Han info->plane = SPRITE_PLANE; 12896e27d514SXu Han break; 12906e27d514SXu Han case MI_DISPLAY_FLIP_SKL_PLANE_2_B: 12916e27d514SXu Han info->pipe = PIPE_B; 12926e27d514SXu Han info->event = SPRITE_B_FLIP_DONE; 12936e27d514SXu Han info->plane = SPRITE_PLANE; 12946e27d514SXu Han break; 12956e27d514SXu Han case MI_DISPLAY_FLIP_SKL_PLANE_2_C: 12966e27d514SXu Han info->pipe = PIPE_C; 12976e27d514SXu Han info->event = SPRITE_C_FLIP_DONE; 12986e27d514SXu Han info->plane = SPRITE_PLANE; 12996e27d514SXu Han break; 13006e27d514SXu Han 1301be1da707SZhi Wang default: 1302695fbc08STina Zhang gvt_vgpu_err("unknown plane code %d\n", plane); 13035c56883aSfred gao return -EBADRQC; 1304be1da707SZhi Wang } 1305be1da707SZhi Wang 1306be1da707SZhi Wang info->stride_val = (dword1 & GENMASK(15, 6)) >> 6; 1307be1da707SZhi Wang info->tile_val = (dword1 & GENMASK(2, 0)); 1308be1da707SZhi Wang info->surf_val = (dword2 & GENMASK(31, 12)) >> 12; 1309be1da707SZhi Wang info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1); 1310be1da707SZhi Wang 1311be1da707SZhi Wang info->ctrl_reg = DSPCNTR(info->pipe); 1312be1da707SZhi Wang info->stride_reg = DSPSTRIDE(info->pipe); 1313be1da707SZhi Wang info->surf_reg = DSPSURF(info->pipe); 1314be1da707SZhi Wang 1315be1da707SZhi Wang return 0; 1316be1da707SZhi Wang } 1317be1da707SZhi Wang 1318be1da707SZhi Wang static int gen8_check_mi_display_flip(struct parser_exec_state *s, 1319be1da707SZhi Wang struct mi_display_flip_command_info *info) 1320be1da707SZhi Wang { 1321be1da707SZhi Wang struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv; 1322be1da707SZhi Wang u32 stride, tile; 1323be1da707SZhi Wang 1324be1da707SZhi Wang if (!info->async_flip) 1325be1da707SZhi Wang return 0; 1326be1da707SZhi Wang 1327c3b5a843Sfred gao if (INTEL_GEN(dev_priv) >= 9) { 132890551a12SZhenyu Wang stride = vgpu_vreg_t(s->vgpu, info->stride_reg) & GENMASK(9, 0); 132990551a12SZhenyu Wang tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & 1330be1da707SZhi Wang GENMASK(12, 10)) >> 10; 1331be1da707SZhi Wang } else { 133290551a12SZhenyu Wang stride = (vgpu_vreg_t(s->vgpu, info->stride_reg) & 1333be1da707SZhi Wang GENMASK(15, 6)) >> 6; 133490551a12SZhenyu Wang tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10; 1335be1da707SZhi Wang } 1336be1da707SZhi Wang 1337be1da707SZhi Wang if (stride != info->stride_val) 1338be1da707SZhi Wang gvt_dbg_cmd("cannot change stride during async flip\n"); 1339be1da707SZhi Wang 1340be1da707SZhi Wang if (tile != info->tile_val) 1341be1da707SZhi Wang gvt_dbg_cmd("cannot change tile during async flip\n"); 1342be1da707SZhi Wang 1343be1da707SZhi Wang return 0; 1344be1da707SZhi Wang } 1345be1da707SZhi Wang 1346be1da707SZhi Wang static int gen8_update_plane_mmio_from_mi_display_flip( 1347be1da707SZhi Wang struct parser_exec_state *s, 1348be1da707SZhi Wang struct mi_display_flip_command_info *info) 1349be1da707SZhi Wang { 1350be1da707SZhi Wang struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv; 1351be1da707SZhi Wang struct intel_vgpu *vgpu = s->vgpu; 1352be1da707SZhi Wang 135390551a12SZhenyu Wang set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12), 135499c79fd4SDu, Changbin info->surf_val << 12); 1355c3b5a843Sfred gao if (INTEL_GEN(dev_priv) >= 9) { 135690551a12SZhenyu Wang set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(9, 0), 135799c79fd4SDu, Changbin info->stride_val); 135890551a12SZhenyu Wang set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10), 135999c79fd4SDu, Changbin info->tile_val << 10); 136099c79fd4SDu, Changbin } else { 136190551a12SZhenyu Wang set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(15, 6), 136299c79fd4SDu, Changbin info->stride_val << 6); 136390551a12SZhenyu Wang set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(10, 10), 136499c79fd4SDu, Changbin info->tile_val << 10); 136599c79fd4SDu, Changbin } 1366be1da707SZhi Wang 1367d39af942SColin Xu if (info->plane == PLANE_PRIMARY) 1368d39af942SColin Xu vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(info->pipe))++; 1369d39af942SColin Xu 1370d39af942SColin Xu if (info->async_flip) 1371be1da707SZhi Wang intel_vgpu_trigger_virtual_event(vgpu, info->event); 1372d39af942SColin Xu else 1373d39af942SColin Xu set_bit(info->event, vgpu->irq.flip_done_event[info->pipe]); 1374d39af942SColin Xu 1375be1da707SZhi Wang return 0; 1376be1da707SZhi Wang } 1377be1da707SZhi Wang 1378be1da707SZhi Wang static int decode_mi_display_flip(struct parser_exec_state *s, 1379be1da707SZhi Wang struct mi_display_flip_command_info *info) 1380be1da707SZhi Wang { 1381be1da707SZhi Wang struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv; 1382be1da707SZhi Wang 1383be1da707SZhi Wang if (IS_BROADWELL(dev_priv)) 1384be1da707SZhi Wang return gen8_decode_mi_display_flip(s, info); 1385c3b5a843Sfred gao if (INTEL_GEN(dev_priv) >= 9) 1386be1da707SZhi Wang return skl_decode_mi_display_flip(s, info); 1387be1da707SZhi Wang 1388be1da707SZhi Wang return -ENODEV; 1389be1da707SZhi Wang } 1390be1da707SZhi Wang 1391be1da707SZhi Wang static int check_mi_display_flip(struct parser_exec_state *s, 1392be1da707SZhi Wang struct mi_display_flip_command_info *info) 1393be1da707SZhi Wang { 1394be1da707SZhi Wang return gen8_check_mi_display_flip(s, info); 1395be1da707SZhi Wang } 1396be1da707SZhi Wang 1397be1da707SZhi Wang static int update_plane_mmio_from_mi_display_flip( 1398be1da707SZhi Wang struct parser_exec_state *s, 1399be1da707SZhi Wang struct mi_display_flip_command_info *info) 1400be1da707SZhi Wang { 1401be1da707SZhi Wang return gen8_update_plane_mmio_from_mi_display_flip(s, info); 1402be1da707SZhi Wang } 1403be1da707SZhi Wang 1404be1da707SZhi Wang static int cmd_handler_mi_display_flip(struct parser_exec_state *s) 1405be1da707SZhi Wang { 1406be1da707SZhi Wang struct mi_display_flip_command_info info; 1407695fbc08STina Zhang struct intel_vgpu *vgpu = s->vgpu; 1408be1da707SZhi Wang int ret; 1409be1da707SZhi Wang int i; 1410be1da707SZhi Wang int len = cmd_length(s); 141100a33be4SGao, Fred u32 valid_len = CMD_LEN(1); 141200a33be4SGao, Fred 141300a33be4SGao, Fred /* Flip Type == Stereo 3D Flip */ 141400a33be4SGao, Fred if (DWORD_FIELD(2, 1, 0) == 2) 141500a33be4SGao, Fred valid_len++; 141600a33be4SGao, Fred ret = gvt_check_valid_cmd_length(cmd_length(s), 141700a33be4SGao, Fred valid_len); 141800a33be4SGao, Fred if (ret) 141900a33be4SGao, Fred return ret; 1420be1da707SZhi Wang 1421be1da707SZhi Wang ret = decode_mi_display_flip(s, &info); 1422be1da707SZhi Wang if (ret) { 1423695fbc08STina Zhang gvt_vgpu_err("fail to decode MI display flip command\n"); 1424be1da707SZhi Wang return ret; 1425be1da707SZhi Wang } 1426be1da707SZhi Wang 1427be1da707SZhi Wang ret = check_mi_display_flip(s, &info); 1428be1da707SZhi Wang if (ret) { 1429695fbc08STina Zhang gvt_vgpu_err("invalid MI display flip command\n"); 1430be1da707SZhi Wang return ret; 1431be1da707SZhi Wang } 1432be1da707SZhi Wang 1433be1da707SZhi Wang ret = update_plane_mmio_from_mi_display_flip(s, &info); 1434be1da707SZhi Wang if (ret) { 1435695fbc08STina Zhang gvt_vgpu_err("fail to update plane mmio\n"); 1436be1da707SZhi Wang return ret; 1437be1da707SZhi Wang } 1438be1da707SZhi Wang 1439be1da707SZhi Wang for (i = 0; i < len; i++) 1440be1da707SZhi Wang patch_value(s, cmd_ptr(s, i), MI_NOOP); 1441be1da707SZhi Wang return 0; 1442be1da707SZhi Wang } 1443be1da707SZhi Wang 1444be1da707SZhi Wang static bool is_wait_for_flip_pending(u32 cmd) 1445be1da707SZhi Wang { 1446be1da707SZhi Wang return cmd & (MI_WAIT_FOR_PLANE_A_FLIP_PENDING | 1447be1da707SZhi Wang MI_WAIT_FOR_PLANE_B_FLIP_PENDING | 1448be1da707SZhi Wang MI_WAIT_FOR_PLANE_C_FLIP_PENDING | 1449be1da707SZhi Wang MI_WAIT_FOR_SPRITE_A_FLIP_PENDING | 1450be1da707SZhi Wang MI_WAIT_FOR_SPRITE_B_FLIP_PENDING | 1451be1da707SZhi Wang MI_WAIT_FOR_SPRITE_C_FLIP_PENDING); 1452be1da707SZhi Wang } 1453be1da707SZhi Wang 1454be1da707SZhi Wang static int cmd_handler_mi_wait_for_event(struct parser_exec_state *s) 1455be1da707SZhi Wang { 1456be1da707SZhi Wang u32 cmd = cmd_val(s, 0); 1457be1da707SZhi Wang 1458be1da707SZhi Wang if (!is_wait_for_flip_pending(cmd)) 1459be1da707SZhi Wang return 0; 1460be1da707SZhi Wang 1461be1da707SZhi Wang patch_value(s, cmd_ptr(s, 0), MI_NOOP); 1462be1da707SZhi Wang return 0; 1463be1da707SZhi Wang } 1464be1da707SZhi Wang 1465be1da707SZhi Wang static unsigned long get_gma_bb_from_cmd(struct parser_exec_state *s, int index) 1466be1da707SZhi Wang { 1467be1da707SZhi Wang unsigned long addr; 1468be1da707SZhi Wang unsigned long gma_high, gma_low; 14695c56883aSfred gao struct intel_vgpu *vgpu = s->vgpu; 14705c56883aSfred gao int gmadr_bytes = vgpu->gvt->device_info.gmadr_bytes_in_cmd; 1471be1da707SZhi Wang 14725c56883aSfred gao if (WARN_ON(gmadr_bytes != 4 && gmadr_bytes != 8)) { 14735c56883aSfred gao gvt_vgpu_err("invalid gma bytes %d\n", gmadr_bytes); 1474be1da707SZhi Wang return INTEL_GVT_INVALID_ADDR; 14755c56883aSfred gao } 1476be1da707SZhi Wang 1477be1da707SZhi Wang gma_low = cmd_val(s, index) & BATCH_BUFFER_ADDR_MASK; 1478be1da707SZhi Wang if (gmadr_bytes == 4) { 1479be1da707SZhi Wang addr = gma_low; 1480be1da707SZhi Wang } else { 1481be1da707SZhi Wang gma_high = cmd_val(s, index + 1) & BATCH_BUFFER_ADDR_HIGH_MASK; 1482be1da707SZhi Wang addr = (((unsigned long)gma_high) << 32) | gma_low; 1483be1da707SZhi Wang } 1484be1da707SZhi Wang return addr; 1485be1da707SZhi Wang } 1486be1da707SZhi Wang 1487be1da707SZhi Wang static inline int cmd_address_audit(struct parser_exec_state *s, 1488be1da707SZhi Wang unsigned long guest_gma, int op_size, bool index_mode) 1489be1da707SZhi Wang { 1490be1da707SZhi Wang struct intel_vgpu *vgpu = s->vgpu; 1491be1da707SZhi Wang u32 max_surface_size = vgpu->gvt->device_info.max_surface_size; 1492be1da707SZhi Wang int i; 1493be1da707SZhi Wang int ret; 1494be1da707SZhi Wang 1495be1da707SZhi Wang if (op_size > max_surface_size) { 1496695fbc08STina Zhang gvt_vgpu_err("command address audit fail name %s\n", 1497695fbc08STina Zhang s->info->name); 14985c56883aSfred gao return -EFAULT; 1499be1da707SZhi Wang } 1500be1da707SZhi Wang 1501be1da707SZhi Wang if (index_mode) { 150213bcb80bSZhenyu Wang if (guest_gma >= I915_GTT_PAGE_SIZE) { 15035c56883aSfred gao ret = -EFAULT; 1504be1da707SZhi Wang goto err; 1505be1da707SZhi Wang } 150664d8bb83SPing Gao } else if (!intel_gvt_ggtt_validate_range(vgpu, guest_gma, op_size)) { 15075c56883aSfred gao ret = -EFAULT; 1508be1da707SZhi Wang goto err; 1509be1da707SZhi Wang } 151064d8bb83SPing Gao 1511be1da707SZhi Wang return 0; 151264d8bb83SPing Gao 1513be1da707SZhi Wang err: 1514695fbc08STina Zhang gvt_vgpu_err("cmd_parser: Malicious %s detected, addr=0x%lx, len=%d!\n", 1515be1da707SZhi Wang s->info->name, guest_gma, op_size); 1516be1da707SZhi Wang 1517be1da707SZhi Wang pr_err("cmd dump: "); 1518be1da707SZhi Wang for (i = 0; i < cmd_length(s); i++) { 1519be1da707SZhi Wang if (!(i % 4)) 1520be1da707SZhi Wang pr_err("\n%08x ", cmd_val(s, i)); 1521be1da707SZhi Wang else 1522be1da707SZhi Wang pr_err("%08x ", cmd_val(s, i)); 1523be1da707SZhi Wang } 1524be1da707SZhi Wang pr_err("\nvgpu%d: aperture 0x%llx - 0x%llx, hidden 0x%llx - 0x%llx\n", 1525be1da707SZhi Wang vgpu->id, 1526be1da707SZhi Wang vgpu_aperture_gmadr_base(vgpu), 1527be1da707SZhi Wang vgpu_aperture_gmadr_end(vgpu), 1528be1da707SZhi Wang vgpu_hidden_gmadr_base(vgpu), 1529be1da707SZhi Wang vgpu_hidden_gmadr_end(vgpu)); 1530be1da707SZhi Wang return ret; 1531be1da707SZhi Wang } 1532be1da707SZhi Wang 1533be1da707SZhi Wang static int cmd_handler_mi_store_data_imm(struct parser_exec_state *s) 1534be1da707SZhi Wang { 1535be1da707SZhi Wang int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd; 1536be1da707SZhi Wang int op_size = (cmd_length(s) - 3) * sizeof(u32); 1537be1da707SZhi Wang int core_id = (cmd_val(s, 2) & (1 << 0)) ? 1 : 0; 1538be1da707SZhi Wang unsigned long gma, gma_low, gma_high; 153900a33be4SGao, Fred u32 valid_len = CMD_LEN(2); 1540be1da707SZhi Wang int ret = 0; 1541be1da707SZhi Wang 1542be1da707SZhi Wang /* check ppggt */ 1543be1da707SZhi Wang if (!(cmd_val(s, 0) & (1 << 22))) 1544be1da707SZhi Wang return 0; 1545be1da707SZhi Wang 154600a33be4SGao, Fred /* check if QWORD */ 154700a33be4SGao, Fred if (DWORD_FIELD(0, 21, 21)) 154800a33be4SGao, Fred valid_len++; 154900a33be4SGao, Fred ret = gvt_check_valid_cmd_length(cmd_length(s), 155000a33be4SGao, Fred valid_len); 155100a33be4SGao, Fred if (ret) 155200a33be4SGao, Fred return ret; 155300a33be4SGao, Fred 1554be1da707SZhi Wang gma = cmd_val(s, 2) & GENMASK(31, 2); 1555be1da707SZhi Wang 1556be1da707SZhi Wang if (gmadr_bytes == 8) { 1557be1da707SZhi Wang gma_low = cmd_val(s, 1) & GENMASK(31, 2); 1558be1da707SZhi Wang gma_high = cmd_val(s, 2) & GENMASK(15, 0); 1559be1da707SZhi Wang gma = (gma_high << 32) | gma_low; 1560be1da707SZhi Wang core_id = (cmd_val(s, 1) & (1 << 0)) ? 1 : 0; 1561be1da707SZhi Wang } 1562be1da707SZhi Wang ret = cmd_address_audit(s, gma + op_size * core_id, op_size, false); 1563be1da707SZhi Wang return ret; 1564be1da707SZhi Wang } 1565be1da707SZhi Wang 1566be1da707SZhi Wang static inline int unexpected_cmd(struct parser_exec_state *s) 1567be1da707SZhi Wang { 1568695fbc08STina Zhang struct intel_vgpu *vgpu = s->vgpu; 1569695fbc08STina Zhang 1570695fbc08STina Zhang gvt_vgpu_err("Unexpected %s in command buffer!\n", s->info->name); 1571695fbc08STina Zhang 15725c56883aSfred gao return -EBADRQC; 1573be1da707SZhi Wang } 1574be1da707SZhi Wang 1575be1da707SZhi Wang static int cmd_handler_mi_semaphore_wait(struct parser_exec_state *s) 1576be1da707SZhi Wang { 1577be1da707SZhi Wang return unexpected_cmd(s); 1578be1da707SZhi Wang } 1579be1da707SZhi Wang 1580be1da707SZhi Wang static int cmd_handler_mi_report_perf_count(struct parser_exec_state *s) 1581be1da707SZhi Wang { 1582be1da707SZhi Wang return unexpected_cmd(s); 1583be1da707SZhi Wang } 1584be1da707SZhi Wang 1585be1da707SZhi Wang static int cmd_handler_mi_op_2e(struct parser_exec_state *s) 1586be1da707SZhi Wang { 1587be1da707SZhi Wang return unexpected_cmd(s); 1588be1da707SZhi Wang } 1589be1da707SZhi Wang 1590be1da707SZhi Wang static int cmd_handler_mi_op_2f(struct parser_exec_state *s) 1591be1da707SZhi Wang { 1592be1da707SZhi Wang int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd; 1593173bcc60SZhenyu Wang int op_size = (1 << ((cmd_val(s, 0) & GENMASK(20, 19)) >> 19)) * 1594173bcc60SZhenyu Wang sizeof(u32); 1595be1da707SZhi Wang unsigned long gma, gma_high; 159600a33be4SGao, Fred u32 valid_len = CMD_LEN(1); 1597be1da707SZhi Wang int ret = 0; 1598be1da707SZhi Wang 1599be1da707SZhi Wang if (!(cmd_val(s, 0) & (1 << 22))) 1600be1da707SZhi Wang return ret; 1601be1da707SZhi Wang 160200a33be4SGao, Fred /* check if QWORD */ 160300a33be4SGao, Fred if (DWORD_FIELD(0, 20, 19) == 1) 160400a33be4SGao, Fred valid_len += 8; 160500a33be4SGao, Fred ret = gvt_check_valid_cmd_length(cmd_length(s), 160600a33be4SGao, Fred valid_len); 160700a33be4SGao, Fred if (ret) 160800a33be4SGao, Fred return ret; 160900a33be4SGao, Fred 1610be1da707SZhi Wang gma = cmd_val(s, 1) & GENMASK(31, 2); 1611be1da707SZhi Wang if (gmadr_bytes == 8) { 1612be1da707SZhi Wang gma_high = cmd_val(s, 2) & GENMASK(15, 0); 1613be1da707SZhi Wang gma = (gma_high << 32) | gma; 1614be1da707SZhi Wang } 1615be1da707SZhi Wang ret = cmd_address_audit(s, gma, op_size, false); 1616be1da707SZhi Wang return ret; 1617be1da707SZhi Wang } 1618be1da707SZhi Wang 1619be1da707SZhi Wang static int cmd_handler_mi_store_data_index(struct parser_exec_state *s) 1620be1da707SZhi Wang { 1621be1da707SZhi Wang return unexpected_cmd(s); 1622be1da707SZhi Wang } 1623be1da707SZhi Wang 1624be1da707SZhi Wang static int cmd_handler_mi_clflush(struct parser_exec_state *s) 1625be1da707SZhi Wang { 1626be1da707SZhi Wang return unexpected_cmd(s); 1627be1da707SZhi Wang } 1628be1da707SZhi Wang 1629be1da707SZhi Wang static int cmd_handler_mi_conditional_batch_buffer_end( 1630be1da707SZhi Wang struct parser_exec_state *s) 1631be1da707SZhi Wang { 1632be1da707SZhi Wang return unexpected_cmd(s); 1633be1da707SZhi Wang } 1634be1da707SZhi Wang 1635be1da707SZhi Wang static int cmd_handler_mi_update_gtt(struct parser_exec_state *s) 1636be1da707SZhi Wang { 1637be1da707SZhi Wang return unexpected_cmd(s); 1638be1da707SZhi Wang } 1639be1da707SZhi Wang 1640be1da707SZhi Wang static int cmd_handler_mi_flush_dw(struct parser_exec_state *s) 1641be1da707SZhi Wang { 1642be1da707SZhi Wang int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd; 1643be1da707SZhi Wang unsigned long gma; 1644be1da707SZhi Wang bool index_mode = false; 1645be1da707SZhi Wang int ret = 0; 1646ac071578SXiaolin Zhang u32 hws_pga, val; 164700a33be4SGao, Fred u32 valid_len = CMD_LEN(2); 164800a33be4SGao, Fred 164900a33be4SGao, Fred ret = gvt_check_valid_cmd_length(cmd_length(s), 165000a33be4SGao, Fred valid_len); 165100a33be4SGao, Fred if (ret) { 165200a33be4SGao, Fred /* Check again for Qword */ 165300a33be4SGao, Fred ret = gvt_check_valid_cmd_length(cmd_length(s), 165400a33be4SGao, Fred ++valid_len); 165500a33be4SGao, Fred return ret; 165600a33be4SGao, Fred } 1657be1da707SZhi Wang 1658be1da707SZhi Wang /* Check post-sync and ppgtt bit */ 1659be1da707SZhi Wang if (((cmd_val(s, 0) >> 14) & 0x3) && (cmd_val(s, 1) & (1 << 2))) { 1660be1da707SZhi Wang gma = cmd_val(s, 1) & GENMASK(31, 3); 1661be1da707SZhi Wang if (gmadr_bytes == 8) 1662be1da707SZhi Wang gma |= (cmd_val(s, 2) & GENMASK(15, 0)) << 32; 1663be1da707SZhi Wang /* Store Data Index */ 1664be1da707SZhi Wang if (cmd_val(s, 0) & (1 << 21)) 1665be1da707SZhi Wang index_mode = true; 1666be1da707SZhi Wang ret = cmd_address_audit(s, gma, sizeof(u64), index_mode); 1667ac071578SXiaolin Zhang if (ret) 1668ac071578SXiaolin Zhang return ret; 1669ac071578SXiaolin Zhang if (index_mode) { 1670ac071578SXiaolin Zhang hws_pga = s->vgpu->hws_pga[s->ring_id]; 1671ac071578SXiaolin Zhang gma = hws_pga + gma; 1672ac071578SXiaolin Zhang patch_value(s, cmd_ptr(s, 1), gma); 1673ac071578SXiaolin Zhang val = cmd_val(s, 0) & (~(1 << 21)); 1674ac071578SXiaolin Zhang patch_value(s, cmd_ptr(s, 0), val); 1675ac071578SXiaolin Zhang } 1676be1da707SZhi Wang } 1677be1da707SZhi Wang /* Check notify bit */ 1678be1da707SZhi Wang if ((cmd_val(s, 0) & (1 << 8))) 1679be1da707SZhi Wang set_bit(cmd_interrupt_events[s->ring_id].mi_flush_dw, 1680be1da707SZhi Wang s->workload->pending_events); 1681be1da707SZhi Wang return ret; 1682be1da707SZhi Wang } 1683be1da707SZhi Wang 1684be1da707SZhi Wang static void addr_type_update_snb(struct parser_exec_state *s) 1685be1da707SZhi Wang { 1686be1da707SZhi Wang if ((s->buf_type == RING_BUFFER_INSTRUCTION) && 1687be1da707SZhi Wang (BATCH_BUFFER_ADR_SPACE_BIT(cmd_val(s, 0)) == 1)) { 1688be1da707SZhi Wang s->buf_addr_type = PPGTT_BUFFER; 1689be1da707SZhi Wang } 1690be1da707SZhi Wang } 1691be1da707SZhi Wang 1692be1da707SZhi Wang 1693be1da707SZhi Wang static int copy_gma_to_hva(struct intel_vgpu *vgpu, struct intel_vgpu_mm *mm, 1694be1da707SZhi Wang unsigned long gma, unsigned long end_gma, void *va) 1695be1da707SZhi Wang { 1696be1da707SZhi Wang unsigned long copy_len, offset; 1697be1da707SZhi Wang unsigned long len = 0; 1698be1da707SZhi Wang unsigned long gpa; 1699be1da707SZhi Wang 1700be1da707SZhi Wang while (gma != end_gma) { 1701be1da707SZhi Wang gpa = intel_vgpu_gma_to_gpa(mm, gma); 1702be1da707SZhi Wang if (gpa == INTEL_GVT_INVALID_ADDR) { 1703695fbc08STina Zhang gvt_vgpu_err("invalid gma address: %lx\n", gma); 1704be1da707SZhi Wang return -EFAULT; 1705be1da707SZhi Wang } 1706be1da707SZhi Wang 17079556e118SZhi Wang offset = gma & (I915_GTT_PAGE_SIZE - 1); 1708be1da707SZhi Wang 17099556e118SZhi Wang copy_len = (end_gma - gma) >= (I915_GTT_PAGE_SIZE - offset) ? 17109556e118SZhi Wang I915_GTT_PAGE_SIZE - offset : end_gma - gma; 1711be1da707SZhi Wang 1712be1da707SZhi Wang intel_gvt_hypervisor_read_gpa(vgpu, gpa, va + len, copy_len); 1713be1da707SZhi Wang 1714be1da707SZhi Wang len += copy_len; 1715be1da707SZhi Wang gma += copy_len; 1716be1da707SZhi Wang } 171773dec95eSTvrtko Ursulin return len; 1718be1da707SZhi Wang } 1719be1da707SZhi Wang 1720be1da707SZhi Wang 1721be1da707SZhi Wang /* 1722be1da707SZhi Wang * Check whether a batch buffer needs to be scanned. Currently 1723be1da707SZhi Wang * the only criteria is based on privilege. 1724be1da707SZhi Wang */ 1725be1da707SZhi Wang static int batch_buffer_needs_scan(struct parser_exec_state *s) 1726be1da707SZhi Wang { 1727f093f182SColin Xu /* Decide privilege based on address space */ 172896bebe39SZhao Yan if (cmd_val(s, 0) & (1 << 8) && 172996bebe39SZhao Yan !(s->vgpu->scan_nonprivbb & (1 << s->ring_id))) 1730be1da707SZhi Wang return 0; 1731be1da707SZhi Wang return 1; 1732be1da707SZhi Wang } 1733be1da707SZhi Wang 1734220b65d8STina Zhang static int find_bb_size(struct parser_exec_state *s, 1735220b65d8STina Zhang unsigned long *bb_size, 1736220b65d8STina Zhang unsigned long *bb_end_cmd_offset) 1737be1da707SZhi Wang { 1738be1da707SZhi Wang unsigned long gma = 0; 1739b007065aSJani Nikula const struct cmd_info *info; 17402e679d48SJani Nikula u32 cmd_len = 0; 174158facf8cSZhi Wang bool bb_end = false; 1742695fbc08STina Zhang struct intel_vgpu *vgpu = s->vgpu; 1743be1da707SZhi Wang u32 cmd; 174496bebe39SZhao Yan struct intel_vgpu_mm *mm = (s->buf_addr_type == GTT_BUFFER) ? 174596bebe39SZhao Yan s->vgpu->gtt.ggtt_mm : s->workload->shadow_mm; 1746be1da707SZhi Wang 174758facf8cSZhi Wang *bb_size = 0; 1748220b65d8STina Zhang *bb_end_cmd_offset = 0; 174958facf8cSZhi Wang 1750be1da707SZhi Wang /* get the start gm address of the batch buffer */ 1751be1da707SZhi Wang gma = get_gma_bb_from_cmd(s, 1); 17525c56883aSfred gao if (gma == INTEL_GVT_INVALID_ADDR) 17535c56883aSfred gao return -EFAULT; 17545c56883aSfred gao 1755be1da707SZhi Wang cmd = cmd_val(s, 0); 1756be1da707SZhi Wang info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id); 1757be1da707SZhi Wang if (info == NULL) { 175896bebe39SZhao Yan gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %d, workload=%p\n", 175996bebe39SZhao Yan cmd, get_opcode(cmd, s->ring_id), 176096bebe39SZhao Yan (s->buf_addr_type == PPGTT_BUFFER) ? 176196bebe39SZhao Yan "ppgtt" : "ggtt", s->ring_id, s->workload); 17625c56883aSfred gao return -EBADRQC; 1763be1da707SZhi Wang } 1764be1da707SZhi Wang do { 176596bebe39SZhao Yan if (copy_gma_to_hva(s->vgpu, mm, 17665c56883aSfred gao gma, gma + 4, &cmd) < 0) 17675c56883aSfred gao return -EFAULT; 1768be1da707SZhi Wang info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id); 1769be1da707SZhi Wang if (info == NULL) { 177096bebe39SZhao Yan gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %d, workload=%p\n", 177196bebe39SZhao Yan cmd, get_opcode(cmd, s->ring_id), 177296bebe39SZhao Yan (s->buf_addr_type == PPGTT_BUFFER) ? 177396bebe39SZhao Yan "ppgtt" : "ggtt", s->ring_id, s->workload); 17745c56883aSfred gao return -EBADRQC; 1775be1da707SZhi Wang } 1776be1da707SZhi Wang 1777be1da707SZhi Wang if (info->opcode == OP_MI_BATCH_BUFFER_END) { 177858facf8cSZhi Wang bb_end = true; 1779be1da707SZhi Wang } else if (info->opcode == OP_MI_BATCH_BUFFER_START) { 178058facf8cSZhi Wang if (BATCH_BUFFER_2ND_LEVEL_BIT(cmd) == 0) 1781be1da707SZhi Wang /* chained batch buffer */ 178258facf8cSZhi Wang bb_end = true; 1783be1da707SZhi Wang } 1784220b65d8STina Zhang 1785220b65d8STina Zhang if (bb_end) 1786220b65d8STina Zhang *bb_end_cmd_offset = *bb_size; 1787220b65d8STina Zhang 1788be1da707SZhi Wang cmd_len = get_cmd_length(info, cmd) << 2; 178958facf8cSZhi Wang *bb_size += cmd_len; 1790be1da707SZhi Wang gma += cmd_len; 179158facf8cSZhi Wang } while (!bb_end); 1792be1da707SZhi Wang 179358facf8cSZhi Wang return 0; 1794be1da707SZhi Wang } 1795be1da707SZhi Wang 1796220b65d8STina Zhang static int audit_bb_end(struct parser_exec_state *s, void *va) 1797220b65d8STina Zhang { 1798220b65d8STina Zhang struct intel_vgpu *vgpu = s->vgpu; 1799220b65d8STina Zhang u32 cmd = *(u32 *)va; 1800220b65d8STina Zhang const struct cmd_info *info; 1801220b65d8STina Zhang 1802220b65d8STina Zhang info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id); 1803220b65d8STina Zhang if (info == NULL) { 1804220b65d8STina Zhang gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %d, workload=%p\n", 1805220b65d8STina Zhang cmd, get_opcode(cmd, s->ring_id), 1806220b65d8STina Zhang (s->buf_addr_type == PPGTT_BUFFER) ? 1807220b65d8STina Zhang "ppgtt" : "ggtt", s->ring_id, s->workload); 1808220b65d8STina Zhang return -EBADRQC; 1809220b65d8STina Zhang } 1810220b65d8STina Zhang 1811220b65d8STina Zhang if ((info->opcode == OP_MI_BATCH_BUFFER_END) || 1812220b65d8STina Zhang ((info->opcode == OP_MI_BATCH_BUFFER_START) && 1813220b65d8STina Zhang (BATCH_BUFFER_2ND_LEVEL_BIT(cmd) == 0))) 1814220b65d8STina Zhang return 0; 1815220b65d8STina Zhang 1816220b65d8STina Zhang return -EBADRQC; 1817220b65d8STina Zhang } 1818220b65d8STina Zhang 1819be1da707SZhi Wang static int perform_bb_shadow(struct parser_exec_state *s) 1820be1da707SZhi Wang { 1821695fbc08STina Zhang struct intel_vgpu *vgpu = s->vgpu; 1822f52c380aSZhi Wang struct intel_vgpu_shadow_bb *bb; 1823be1da707SZhi Wang unsigned long gma = 0; 182458facf8cSZhi Wang unsigned long bb_size; 1825220b65d8STina Zhang unsigned long bb_end_cmd_offset; 1826be1da707SZhi Wang int ret = 0; 182796bebe39SZhao Yan struct intel_vgpu_mm *mm = (s->buf_addr_type == GTT_BUFFER) ? 182896bebe39SZhao Yan s->vgpu->gtt.ggtt_mm : s->workload->shadow_mm; 18298475355fSChris Wilson unsigned long start_offset = 0; 1830be1da707SZhi Wang 1831be1da707SZhi Wang /* get the start gm address of the batch buffer */ 1832be1da707SZhi Wang gma = get_gma_bb_from_cmd(s, 1); 18335c56883aSfred gao if (gma == INTEL_GVT_INVALID_ADDR) 18345c56883aSfred gao return -EFAULT; 1835be1da707SZhi Wang 1836220b65d8STina Zhang ret = find_bb_size(s, &bb_size, &bb_end_cmd_offset); 183758facf8cSZhi Wang if (ret) 183858facf8cSZhi Wang return ret; 1839be1da707SZhi Wang 1840f52c380aSZhi Wang bb = kzalloc(sizeof(*bb), GFP_KERNEL); 1841f52c380aSZhi Wang if (!bb) 1842be1da707SZhi Wang return -ENOMEM; 1843be1da707SZhi Wang 184496bebe39SZhao Yan bb->ppgtt = (s->buf_addr_type == GTT_BUFFER) ? false : true; 184596bebe39SZhao Yan 18468475355fSChris Wilson /* the start_offset stores the batch buffer's start gma's 184796bebe39SZhao Yan * offset relative to page boundary. so for non-privileged batch 184896bebe39SZhao Yan * buffer, the shadowed gem object holds exactly the same page 184996bebe39SZhao Yan * layout as original gem object. This is for the convience of 185096bebe39SZhao Yan * replacing the whole non-privilged batch buffer page to this 185196bebe39SZhao Yan * shadowed one in PPGTT at the same gma address. (this replacing 185296bebe39SZhao Yan * action is not implemented yet now, but may be necessary in 185396bebe39SZhao Yan * future). 185496bebe39SZhao Yan * for prileged batch buffer, we just change start gma address to 185596bebe39SZhao Yan * that of shadowed page. 185696bebe39SZhao Yan */ 185796bebe39SZhao Yan if (bb->ppgtt) 18588475355fSChris Wilson start_offset = gma & ~I915_GTT_PAGE_MASK; 185996bebe39SZhao Yan 18608475355fSChris Wilson bb->obj = i915_gem_object_create_shmem(s->vgpu->gvt->dev_priv, 18618475355fSChris Wilson round_up(bb_size + start_offset, 18628475355fSChris Wilson PAGE_SIZE)); 1863f52c380aSZhi Wang if (IS_ERR(bb->obj)) { 1864f52c380aSZhi Wang ret = PTR_ERR(bb->obj); 1865f52c380aSZhi Wang goto err_free_bb; 1866be1da707SZhi Wang } 1867be1da707SZhi Wang 1868f0e4a063SChris Wilson ret = i915_gem_object_prepare_write(bb->obj, &bb->clflush); 1869f52c380aSZhi Wang if (ret) 1870f52c380aSZhi Wang goto err_free_obj; 1871f52c380aSZhi Wang 1872f52c380aSZhi Wang bb->va = i915_gem_object_pin_map(bb->obj, I915_MAP_WB); 1873f52c380aSZhi Wang if (IS_ERR(bb->va)) { 1874f52c380aSZhi Wang ret = PTR_ERR(bb->va); 1875f52c380aSZhi Wang goto err_finish_shmem_access; 1876be1da707SZhi Wang } 1877be1da707SZhi Wang 1878f52c380aSZhi Wang if (bb->clflush & CLFLUSH_BEFORE) { 1879f52c380aSZhi Wang drm_clflush_virt_range(bb->va, bb->obj->base.size); 1880f52c380aSZhi Wang bb->clflush &= ~CLFLUSH_BEFORE; 1881f52c380aSZhi Wang } 1882be1da707SZhi Wang 188396bebe39SZhao Yan ret = copy_gma_to_hva(s->vgpu, mm, 1884a2861504SChris Wilson gma, gma + bb_size, 18858475355fSChris Wilson bb->va + start_offset); 18868bcad07aSZhenyu Wang if (ret < 0) { 1887695fbc08STina Zhang gvt_vgpu_err("fail to copy guest ring buffer\n"); 1888f52c380aSZhi Wang ret = -EFAULT; 1889f52c380aSZhi Wang goto err_unmap; 1890be1da707SZhi Wang } 1891be1da707SZhi Wang 1892220b65d8STina Zhang ret = audit_bb_end(s, bb->va + start_offset + bb_end_cmd_offset); 1893220b65d8STina Zhang if (ret) 1894220b65d8STina Zhang goto err_unmap; 1895220b65d8STina Zhang 1896f52c380aSZhi Wang INIT_LIST_HEAD(&bb->list); 1897f52c380aSZhi Wang list_add(&bb->list, &s->workload->shadow_bb); 1898f52c380aSZhi Wang 1899f52c380aSZhi Wang bb->accessing = true; 1900f52c380aSZhi Wang bb->bb_start_cmd_va = s->ip_va; 1901f52c380aSZhi Wang 1902ef75c685Sfred gao if ((s->buf_type == BATCH_BUFFER_INSTRUCTION) && (!s->is_ctx_wa)) 1903ef75c685Sfred gao bb->bb_offset = s->ip_va - s->rb_va; 1904ef75c685Sfred gao else 1905ef75c685Sfred gao bb->bb_offset = 0; 1906ef75c685Sfred gao 1907be1da707SZhi Wang /* 1908be1da707SZhi Wang * ip_va saves the virtual address of the shadow batch buffer, while 1909be1da707SZhi Wang * ip_gma saves the graphics address of the original batch buffer. 1910be1da707SZhi Wang * As the shadow batch buffer is just a copy from the originial one, 1911be1da707SZhi Wang * it should be right to use shadow batch buffer'va and original batch 1912be1da707SZhi Wang * buffer's gma in pair. After all, we don't want to pin the shadow 1913be1da707SZhi Wang * buffer here (too early). 1914be1da707SZhi Wang */ 19158475355fSChris Wilson s->ip_va = bb->va + start_offset; 1916be1da707SZhi Wang s->ip_gma = gma; 1917be1da707SZhi Wang return 0; 1918f52c380aSZhi Wang err_unmap: 1919f52c380aSZhi Wang i915_gem_object_unpin_map(bb->obj); 1920f52c380aSZhi Wang err_finish_shmem_access: 1921f0e4a063SChris Wilson i915_gem_object_finish_access(bb->obj); 1922f52c380aSZhi Wang err_free_obj: 1923f52c380aSZhi Wang i915_gem_object_put(bb->obj); 1924f52c380aSZhi Wang err_free_bb: 1925f52c380aSZhi Wang kfree(bb); 1926be1da707SZhi Wang return ret; 1927be1da707SZhi Wang } 1928be1da707SZhi Wang 1929be1da707SZhi Wang static int cmd_handler_mi_batch_buffer_start(struct parser_exec_state *s) 1930be1da707SZhi Wang { 1931be1da707SZhi Wang bool second_level; 1932be1da707SZhi Wang int ret = 0; 1933695fbc08STina Zhang struct intel_vgpu *vgpu = s->vgpu; 1934be1da707SZhi Wang 1935be1da707SZhi Wang if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) { 1936695fbc08STina Zhang gvt_vgpu_err("Found MI_BATCH_BUFFER_START in 2nd level BB\n"); 19375c56883aSfred gao return -EFAULT; 1938be1da707SZhi Wang } 1939be1da707SZhi Wang 1940be1da707SZhi Wang second_level = BATCH_BUFFER_2ND_LEVEL_BIT(cmd_val(s, 0)) == 1; 1941be1da707SZhi Wang if (second_level && (s->buf_type != BATCH_BUFFER_INSTRUCTION)) { 1942695fbc08STina Zhang gvt_vgpu_err("Jumping to 2nd level BB from RB is not allowed\n"); 19435c56883aSfred gao return -EFAULT; 1944be1da707SZhi Wang } 1945be1da707SZhi Wang 1946be1da707SZhi Wang s->saved_buf_addr_type = s->buf_addr_type; 1947be1da707SZhi Wang addr_type_update_snb(s); 1948be1da707SZhi Wang if (s->buf_type == RING_BUFFER_INSTRUCTION) { 1949be1da707SZhi Wang s->ret_ip_gma_ring = s->ip_gma + cmd_length(s) * sizeof(u32); 1950be1da707SZhi Wang s->buf_type = BATCH_BUFFER_INSTRUCTION; 1951be1da707SZhi Wang } else if (second_level) { 1952be1da707SZhi Wang s->buf_type = BATCH_BUFFER_2ND_LEVEL; 1953be1da707SZhi Wang s->ret_ip_gma_bb = s->ip_gma + cmd_length(s) * sizeof(u32); 1954be1da707SZhi Wang s->ret_bb_va = s->ip_va + cmd_length(s) * sizeof(u32); 1955be1da707SZhi Wang } 1956be1da707SZhi Wang 1957be1da707SZhi Wang if (batch_buffer_needs_scan(s)) { 1958be1da707SZhi Wang ret = perform_bb_shadow(s); 1959be1da707SZhi Wang if (ret < 0) 1960695fbc08STina Zhang gvt_vgpu_err("invalid shadow batch buffer\n"); 1961be1da707SZhi Wang } else { 1962be1da707SZhi Wang /* emulate a batch buffer end to do return right */ 1963be1da707SZhi Wang ret = cmd_handler_mi_batch_buffer_end(s); 1964be1da707SZhi Wang if (ret < 0) 1965be1da707SZhi Wang return ret; 1966be1da707SZhi Wang } 1967be1da707SZhi Wang return ret; 1968be1da707SZhi Wang } 1969be1da707SZhi Wang 1970db47685dSZhao Yan static int mi_noop_index; 1971db47685dSZhao Yan 1972b007065aSJani Nikula static const struct cmd_info cmd_info[] = { 1973be1da707SZhi Wang {"MI_NOOP", OP_MI_NOOP, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL}, 1974be1da707SZhi Wang 1975be1da707SZhi Wang {"MI_SET_PREDICATE", OP_MI_SET_PREDICATE, F_LEN_CONST, R_ALL, D_ALL, 1976be1da707SZhi Wang 0, 1, NULL}, 1977be1da707SZhi Wang 1978be1da707SZhi Wang {"MI_USER_INTERRUPT", OP_MI_USER_INTERRUPT, F_LEN_CONST, R_ALL, D_ALL, 1979be1da707SZhi Wang 0, 1, cmd_handler_mi_user_interrupt}, 1980be1da707SZhi Wang 1981be1da707SZhi Wang {"MI_WAIT_FOR_EVENT", OP_MI_WAIT_FOR_EVENT, F_LEN_CONST, R_RCS | R_BCS, 1982be1da707SZhi Wang D_ALL, 0, 1, cmd_handler_mi_wait_for_event}, 1983be1da707SZhi Wang 1984be1da707SZhi Wang {"MI_FLUSH", OP_MI_FLUSH, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL}, 1985be1da707SZhi Wang 1986be1da707SZhi Wang {"MI_ARB_CHECK", OP_MI_ARB_CHECK, F_LEN_CONST, R_ALL, D_ALL, 0, 1, 1987be1da707SZhi Wang NULL}, 1988be1da707SZhi Wang 1989be1da707SZhi Wang {"MI_RS_CONTROL", OP_MI_RS_CONTROL, F_LEN_CONST, R_RCS, D_ALL, 0, 1, 1990be1da707SZhi Wang NULL}, 1991be1da707SZhi Wang 1992be1da707SZhi Wang {"MI_REPORT_HEAD", OP_MI_REPORT_HEAD, F_LEN_CONST, R_ALL, D_ALL, 0, 1, 1993be1da707SZhi Wang NULL}, 1994be1da707SZhi Wang 1995be1da707SZhi Wang {"MI_ARB_ON_OFF", OP_MI_ARB_ON_OFF, F_LEN_CONST, R_ALL, D_ALL, 0, 1, 1996be1da707SZhi Wang NULL}, 1997be1da707SZhi Wang 1998be1da707SZhi Wang {"MI_URB_ATOMIC_ALLOC", OP_MI_URB_ATOMIC_ALLOC, F_LEN_CONST, R_RCS, 1999be1da707SZhi Wang D_ALL, 0, 1, NULL}, 2000be1da707SZhi Wang 2001be1da707SZhi Wang {"MI_BATCH_BUFFER_END", OP_MI_BATCH_BUFFER_END, 2002be1da707SZhi Wang F_IP_ADVANCE_CUSTOM | F_LEN_CONST, R_ALL, D_ALL, 0, 1, 2003be1da707SZhi Wang cmd_handler_mi_batch_buffer_end}, 2004be1da707SZhi Wang 2005be1da707SZhi Wang {"MI_SUSPEND_FLUSH", OP_MI_SUSPEND_FLUSH, F_LEN_CONST, R_ALL, D_ALL, 2006be1da707SZhi Wang 0, 1, NULL}, 2007be1da707SZhi Wang 2008be1da707SZhi Wang {"MI_PREDICATE", OP_MI_PREDICATE, F_LEN_CONST, R_RCS, D_ALL, 0, 1, 2009be1da707SZhi Wang NULL}, 2010be1da707SZhi Wang 2011be1da707SZhi Wang {"MI_TOPOLOGY_FILTER", OP_MI_TOPOLOGY_FILTER, F_LEN_CONST, R_ALL, 2012be1da707SZhi Wang D_ALL, 0, 1, NULL}, 2013be1da707SZhi Wang 2014be1da707SZhi Wang {"MI_SET_APPID", OP_MI_SET_APPID, F_LEN_CONST, R_ALL, D_ALL, 0, 1, 2015be1da707SZhi Wang NULL}, 2016be1da707SZhi Wang 2017be1da707SZhi Wang {"MI_RS_CONTEXT", OP_MI_RS_CONTEXT, F_LEN_CONST, R_RCS, D_ALL, 0, 1, 2018be1da707SZhi Wang NULL}, 2019be1da707SZhi Wang 20204f870f1fSGao, Fred {"MI_DISPLAY_FLIP", OP_MI_DISPLAY_FLIP, F_LEN_VAR, 2021be1da707SZhi Wang R_RCS | R_BCS, D_ALL, 0, 8, cmd_handler_mi_display_flip}, 2022be1da707SZhi Wang 20231e2adc0dSGao, Fred {"MI_SEMAPHORE_MBOX", OP_MI_SEMAPHORE_MBOX, F_LEN_VAR | F_LEN_VAR_FIXED, 20241e2adc0dSGao, Fred R_ALL, D_ALL, 0, 8, NULL, CMD_LEN(1)}, 2025be1da707SZhi Wang 2026be1da707SZhi Wang {"MI_MATH", OP_MI_MATH, F_LEN_VAR, R_ALL, D_ALL, 0, 8, NULL}, 2027be1da707SZhi Wang 20281e2adc0dSGao, Fred {"MI_URB_CLEAR", OP_MI_URB_CLEAR, F_LEN_VAR | F_LEN_VAR_FIXED, R_RCS, 20291e2adc0dSGao, Fred D_ALL, 0, 8, NULL, CMD_LEN(0)}, 2030be1da707SZhi Wang 20311e2adc0dSGao, Fred {"MI_SEMAPHORE_SIGNAL", OP_MI_SEMAPHORE_SIGNAL, 20321e2adc0dSGao, Fred F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_BDW_PLUS, 0, 8, 20331e2adc0dSGao, Fred NULL, CMD_LEN(0)}, 2034be1da707SZhi Wang 20351e2adc0dSGao, Fred {"MI_SEMAPHORE_WAIT", OP_MI_SEMAPHORE_WAIT, 20361e2adc0dSGao, Fred F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_BDW_PLUS, ADDR_FIX_1(2), 20371e2adc0dSGao, Fred 8, cmd_handler_mi_semaphore_wait, CMD_LEN(2)}, 2038be1da707SZhi Wang 2039be1da707SZhi Wang {"MI_STORE_DATA_IMM", OP_MI_STORE_DATA_IMM, F_LEN_VAR, R_ALL, D_BDW_PLUS, 2040be1da707SZhi Wang ADDR_FIX_1(1), 10, cmd_handler_mi_store_data_imm}, 2041be1da707SZhi Wang 2042be1da707SZhi Wang {"MI_STORE_DATA_INDEX", OP_MI_STORE_DATA_INDEX, F_LEN_VAR, R_ALL, D_ALL, 2043be1da707SZhi Wang 0, 8, cmd_handler_mi_store_data_index}, 2044be1da707SZhi Wang 2045be1da707SZhi Wang {"MI_LOAD_REGISTER_IMM", OP_MI_LOAD_REGISTER_IMM, F_LEN_VAR, R_ALL, 2046be1da707SZhi Wang D_ALL, 0, 8, cmd_handler_lri}, 2047be1da707SZhi Wang 2048be1da707SZhi Wang {"MI_UPDATE_GTT", OP_MI_UPDATE_GTT, F_LEN_VAR, R_ALL, D_BDW_PLUS, 0, 10, 2049be1da707SZhi Wang cmd_handler_mi_update_gtt}, 2050be1da707SZhi Wang 20511e2adc0dSGao, Fred {"MI_STORE_REGISTER_MEM", OP_MI_STORE_REGISTER_MEM, 20521e2adc0dSGao, Fred F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(2), 8, 20531e2adc0dSGao, Fred cmd_handler_srm, CMD_LEN(2)}, 2054be1da707SZhi Wang 2055be1da707SZhi Wang {"MI_FLUSH_DW", OP_MI_FLUSH_DW, F_LEN_VAR, R_ALL, D_ALL, 0, 6, 2056be1da707SZhi Wang cmd_handler_mi_flush_dw}, 2057be1da707SZhi Wang 2058be1da707SZhi Wang {"MI_CLFLUSH", OP_MI_CLFLUSH, F_LEN_VAR, R_ALL, D_ALL, ADDR_FIX_1(1), 2059be1da707SZhi Wang 10, cmd_handler_mi_clflush}, 2060be1da707SZhi Wang 20611e2adc0dSGao, Fred {"MI_REPORT_PERF_COUNT", OP_MI_REPORT_PERF_COUNT, 20621e2adc0dSGao, Fred F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(1), 6, 20631e2adc0dSGao, Fred cmd_handler_mi_report_perf_count, CMD_LEN(2)}, 2064be1da707SZhi Wang 20651e2adc0dSGao, Fred {"MI_LOAD_REGISTER_MEM", OP_MI_LOAD_REGISTER_MEM, 20661e2adc0dSGao, Fred F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(2), 8, 20671e2adc0dSGao, Fred cmd_handler_lrm, CMD_LEN(2)}, 2068be1da707SZhi Wang 20691e2adc0dSGao, Fred {"MI_LOAD_REGISTER_REG", OP_MI_LOAD_REGISTER_REG, 20701e2adc0dSGao, Fred F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, 0, 8, 20711e2adc0dSGao, Fred cmd_handler_lrr, CMD_LEN(1)}, 2072be1da707SZhi Wang 20731e2adc0dSGao, Fred {"MI_RS_STORE_DATA_IMM", OP_MI_RS_STORE_DATA_IMM, 20741e2adc0dSGao, Fred F_LEN_VAR | F_LEN_VAR_FIXED, R_RCS, D_ALL, 0, 20751e2adc0dSGao, Fred 8, NULL, CMD_LEN(2)}, 2076be1da707SZhi Wang 20771e2adc0dSGao, Fred {"MI_LOAD_URB_MEM", OP_MI_LOAD_URB_MEM, F_LEN_VAR | F_LEN_VAR_FIXED, 20781e2adc0dSGao, Fred R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL, CMD_LEN(2)}, 2079be1da707SZhi Wang 2080be1da707SZhi Wang {"MI_STORE_URM_MEM", OP_MI_STORE_URM_MEM, F_LEN_VAR, R_RCS, D_ALL, 2081be1da707SZhi Wang ADDR_FIX_1(2), 8, NULL}, 2082be1da707SZhi Wang 20831e2adc0dSGao, Fred {"MI_OP_2E", OP_MI_2E, F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_BDW_PLUS, 20841e2adc0dSGao, Fred ADDR_FIX_2(1, 2), 8, cmd_handler_mi_op_2e, CMD_LEN(3)}, 2085be1da707SZhi Wang 2086be1da707SZhi Wang {"MI_OP_2F", OP_MI_2F, F_LEN_VAR, R_ALL, D_BDW_PLUS, ADDR_FIX_1(1), 2087be1da707SZhi Wang 8, cmd_handler_mi_op_2f}, 2088be1da707SZhi Wang 2089be1da707SZhi Wang {"MI_BATCH_BUFFER_START", OP_MI_BATCH_BUFFER_START, 2090be1da707SZhi Wang F_IP_ADVANCE_CUSTOM, R_ALL, D_ALL, 0, 8, 2091be1da707SZhi Wang cmd_handler_mi_batch_buffer_start}, 2092be1da707SZhi Wang 2093be1da707SZhi Wang {"MI_CONDITIONAL_BATCH_BUFFER_END", OP_MI_CONDITIONAL_BATCH_BUFFER_END, 20941e2adc0dSGao, Fred F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(2), 8, 20951e2adc0dSGao, Fred cmd_handler_mi_conditional_batch_buffer_end, CMD_LEN(2)}, 2096be1da707SZhi Wang 2097be1da707SZhi Wang {"MI_LOAD_SCAN_LINES_INCL", OP_MI_LOAD_SCAN_LINES_INCL, F_LEN_CONST, 2098be1da707SZhi Wang R_RCS | R_BCS, D_ALL, 0, 2, NULL}, 2099be1da707SZhi Wang 2100be1da707SZhi Wang {"XY_SETUP_BLT", OP_XY_SETUP_BLT, F_LEN_VAR, R_BCS, D_ALL, 2101be1da707SZhi Wang ADDR_FIX_2(4, 7), 8, NULL}, 2102be1da707SZhi Wang 2103be1da707SZhi Wang {"XY_SETUP_CLIP_BLT", OP_XY_SETUP_CLIP_BLT, F_LEN_VAR, R_BCS, D_ALL, 2104be1da707SZhi Wang 0, 8, NULL}, 2105be1da707SZhi Wang 2106be1da707SZhi Wang {"XY_SETUP_MONO_PATTERN_SL_BLT", OP_XY_SETUP_MONO_PATTERN_SL_BLT, 2107be1da707SZhi Wang F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL}, 2108be1da707SZhi Wang 2109be1da707SZhi Wang {"XY_PIXEL_BLT", OP_XY_PIXEL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL}, 2110be1da707SZhi Wang 2111be1da707SZhi Wang {"XY_SCANLINES_BLT", OP_XY_SCANLINES_BLT, F_LEN_VAR, R_BCS, D_ALL, 2112be1da707SZhi Wang 0, 8, NULL}, 2113be1da707SZhi Wang 2114be1da707SZhi Wang {"XY_TEXT_BLT", OP_XY_TEXT_BLT, F_LEN_VAR, R_BCS, D_ALL, 2115be1da707SZhi Wang ADDR_FIX_1(3), 8, NULL}, 2116be1da707SZhi Wang 2117be1da707SZhi Wang {"XY_TEXT_IMMEDIATE_BLT", OP_XY_TEXT_IMMEDIATE_BLT, F_LEN_VAR, R_BCS, 2118be1da707SZhi Wang D_ALL, 0, 8, NULL}, 2119be1da707SZhi Wang 2120be1da707SZhi Wang {"XY_COLOR_BLT", OP_XY_COLOR_BLT, F_LEN_VAR, R_BCS, D_ALL, 2121be1da707SZhi Wang ADDR_FIX_1(4), 8, NULL}, 2122be1da707SZhi Wang 2123be1da707SZhi Wang {"XY_PAT_BLT", OP_XY_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL, 2124be1da707SZhi Wang ADDR_FIX_2(4, 5), 8, NULL}, 2125be1da707SZhi Wang 2126be1da707SZhi Wang {"XY_MONO_PAT_BLT", OP_XY_MONO_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL, 2127be1da707SZhi Wang ADDR_FIX_1(4), 8, NULL}, 2128be1da707SZhi Wang 2129be1da707SZhi Wang {"XY_SRC_COPY_BLT", OP_XY_SRC_COPY_BLT, F_LEN_VAR, R_BCS, D_ALL, 2130be1da707SZhi Wang ADDR_FIX_2(4, 7), 8, NULL}, 2131be1da707SZhi Wang 2132be1da707SZhi Wang {"XY_MONO_SRC_COPY_BLT", OP_XY_MONO_SRC_COPY_BLT, F_LEN_VAR, R_BCS, 2133be1da707SZhi Wang D_ALL, ADDR_FIX_2(4, 5), 8, NULL}, 2134be1da707SZhi Wang 2135be1da707SZhi Wang {"XY_FULL_BLT", OP_XY_FULL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL}, 2136be1da707SZhi Wang 2137be1da707SZhi Wang {"XY_FULL_MONO_SRC_BLT", OP_XY_FULL_MONO_SRC_BLT, F_LEN_VAR, R_BCS, 2138be1da707SZhi Wang D_ALL, ADDR_FIX_3(4, 5, 8), 8, NULL}, 2139be1da707SZhi Wang 2140be1da707SZhi Wang {"XY_FULL_MONO_PATTERN_BLT", OP_XY_FULL_MONO_PATTERN_BLT, F_LEN_VAR, 2141be1da707SZhi Wang R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL}, 2142be1da707SZhi Wang 2143be1da707SZhi Wang {"XY_FULL_MONO_PATTERN_MONO_SRC_BLT", 2144be1da707SZhi Wang OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT, 2145be1da707SZhi Wang F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL}, 2146be1da707SZhi Wang 2147be1da707SZhi Wang {"XY_MONO_PAT_FIXED_BLT", OP_XY_MONO_PAT_FIXED_BLT, F_LEN_VAR, R_BCS, 2148be1da707SZhi Wang D_ALL, ADDR_FIX_1(4), 8, NULL}, 2149be1da707SZhi Wang 2150be1da707SZhi Wang {"XY_MONO_SRC_COPY_IMMEDIATE_BLT", OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT, 2151be1da707SZhi Wang F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL}, 2152be1da707SZhi Wang 2153be1da707SZhi Wang {"XY_PAT_BLT_IMMEDIATE", OP_XY_PAT_BLT_IMMEDIATE, F_LEN_VAR, R_BCS, 2154be1da707SZhi Wang D_ALL, ADDR_FIX_1(4), 8, NULL}, 2155be1da707SZhi Wang 2156be1da707SZhi Wang {"XY_SRC_COPY_CHROMA_BLT", OP_XY_SRC_COPY_CHROMA_BLT, F_LEN_VAR, R_BCS, 2157be1da707SZhi Wang D_ALL, ADDR_FIX_2(4, 7), 8, NULL}, 2158be1da707SZhi Wang 2159be1da707SZhi Wang {"XY_FULL_IMMEDIATE_PATTERN_BLT", OP_XY_FULL_IMMEDIATE_PATTERN_BLT, 2160be1da707SZhi Wang F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL}, 2161be1da707SZhi Wang 2162be1da707SZhi Wang {"XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT", 2163be1da707SZhi Wang OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT, 2164be1da707SZhi Wang F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL}, 2165be1da707SZhi Wang 2166be1da707SZhi Wang {"XY_PAT_CHROMA_BLT", OP_XY_PAT_CHROMA_BLT, F_LEN_VAR, R_BCS, D_ALL, 2167be1da707SZhi Wang ADDR_FIX_2(4, 5), 8, NULL}, 2168be1da707SZhi Wang 2169be1da707SZhi Wang {"XY_PAT_CHROMA_BLT_IMMEDIATE", OP_XY_PAT_CHROMA_BLT_IMMEDIATE, 2170be1da707SZhi Wang F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL}, 2171be1da707SZhi Wang 2172be1da707SZhi Wang {"3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP", 2173be1da707SZhi Wang OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP, 2174be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2175be1da707SZhi Wang 2176be1da707SZhi Wang {"3DSTATE_VIEWPORT_STATE_POINTERS_CC", 2177be1da707SZhi Wang OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC, 2178be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2179be1da707SZhi Wang 2180be1da707SZhi Wang {"3DSTATE_BLEND_STATE_POINTERS", 2181be1da707SZhi Wang OP_3DSTATE_BLEND_STATE_POINTERS, 2182be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2183be1da707SZhi Wang 2184be1da707SZhi Wang {"3DSTATE_DEPTH_STENCIL_STATE_POINTERS", 2185be1da707SZhi Wang OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS, 2186be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2187be1da707SZhi Wang 2188be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_POINTERS_VS", 2189be1da707SZhi Wang OP_3DSTATE_BINDING_TABLE_POINTERS_VS, 2190be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2191be1da707SZhi Wang 2192be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_POINTERS_HS", 2193be1da707SZhi Wang OP_3DSTATE_BINDING_TABLE_POINTERS_HS, 2194be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2195be1da707SZhi Wang 2196be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_POINTERS_DS", 2197be1da707SZhi Wang OP_3DSTATE_BINDING_TABLE_POINTERS_DS, 2198be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2199be1da707SZhi Wang 2200be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_POINTERS_GS", 2201be1da707SZhi Wang OP_3DSTATE_BINDING_TABLE_POINTERS_GS, 2202be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2203be1da707SZhi Wang 2204be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_POINTERS_PS", 2205be1da707SZhi Wang OP_3DSTATE_BINDING_TABLE_POINTERS_PS, 2206be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2207be1da707SZhi Wang 2208be1da707SZhi Wang {"3DSTATE_SAMPLER_STATE_POINTERS_VS", 2209be1da707SZhi Wang OP_3DSTATE_SAMPLER_STATE_POINTERS_VS, 2210be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2211be1da707SZhi Wang 2212be1da707SZhi Wang {"3DSTATE_SAMPLER_STATE_POINTERS_HS", 2213be1da707SZhi Wang OP_3DSTATE_SAMPLER_STATE_POINTERS_HS, 2214be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2215be1da707SZhi Wang 2216be1da707SZhi Wang {"3DSTATE_SAMPLER_STATE_POINTERS_DS", 2217be1da707SZhi Wang OP_3DSTATE_SAMPLER_STATE_POINTERS_DS, 2218be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2219be1da707SZhi Wang 2220be1da707SZhi Wang {"3DSTATE_SAMPLER_STATE_POINTERS_GS", 2221be1da707SZhi Wang OP_3DSTATE_SAMPLER_STATE_POINTERS_GS, 2222be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2223be1da707SZhi Wang 2224be1da707SZhi Wang {"3DSTATE_SAMPLER_STATE_POINTERS_PS", 2225be1da707SZhi Wang OP_3DSTATE_SAMPLER_STATE_POINTERS_PS, 2226be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2227be1da707SZhi Wang 2228be1da707SZhi Wang {"3DSTATE_URB_VS", OP_3DSTATE_URB_VS, F_LEN_VAR, R_RCS, D_ALL, 2229be1da707SZhi Wang 0, 8, NULL}, 2230be1da707SZhi Wang 2231be1da707SZhi Wang {"3DSTATE_URB_HS", OP_3DSTATE_URB_HS, F_LEN_VAR, R_RCS, D_ALL, 2232be1da707SZhi Wang 0, 8, NULL}, 2233be1da707SZhi Wang 2234be1da707SZhi Wang {"3DSTATE_URB_DS", OP_3DSTATE_URB_DS, F_LEN_VAR, R_RCS, D_ALL, 2235be1da707SZhi Wang 0, 8, NULL}, 2236be1da707SZhi Wang 2237be1da707SZhi Wang {"3DSTATE_URB_GS", OP_3DSTATE_URB_GS, F_LEN_VAR, R_RCS, D_ALL, 2238be1da707SZhi Wang 0, 8, NULL}, 2239be1da707SZhi Wang 2240be1da707SZhi Wang {"3DSTATE_GATHER_CONSTANT_VS", OP_3DSTATE_GATHER_CONSTANT_VS, 2241be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2242be1da707SZhi Wang 2243be1da707SZhi Wang {"3DSTATE_GATHER_CONSTANT_GS", OP_3DSTATE_GATHER_CONSTANT_GS, 2244be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2245be1da707SZhi Wang 2246be1da707SZhi Wang {"3DSTATE_GATHER_CONSTANT_HS", OP_3DSTATE_GATHER_CONSTANT_HS, 2247be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2248be1da707SZhi Wang 2249be1da707SZhi Wang {"3DSTATE_GATHER_CONSTANT_DS", OP_3DSTATE_GATHER_CONSTANT_DS, 2250be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2251be1da707SZhi Wang 2252be1da707SZhi Wang {"3DSTATE_GATHER_CONSTANT_PS", OP_3DSTATE_GATHER_CONSTANT_PS, 2253be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2254be1da707SZhi Wang 2255be1da707SZhi Wang {"3DSTATE_DX9_CONSTANTF_VS", OP_3DSTATE_DX9_CONSTANTF_VS, 2256be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL}, 2257be1da707SZhi Wang 2258be1da707SZhi Wang {"3DSTATE_DX9_CONSTANTF_PS", OP_3DSTATE_DX9_CONSTANTF_PS, 2259be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL}, 2260be1da707SZhi Wang 2261be1da707SZhi Wang {"3DSTATE_DX9_CONSTANTI_VS", OP_3DSTATE_DX9_CONSTANTI_VS, 2262be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2263be1da707SZhi Wang 2264be1da707SZhi Wang {"3DSTATE_DX9_CONSTANTI_PS", OP_3DSTATE_DX9_CONSTANTI_PS, 2265be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2266be1da707SZhi Wang 2267be1da707SZhi Wang {"3DSTATE_DX9_CONSTANTB_VS", OP_3DSTATE_DX9_CONSTANTB_VS, 2268be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2269be1da707SZhi Wang 2270be1da707SZhi Wang {"3DSTATE_DX9_CONSTANTB_PS", OP_3DSTATE_DX9_CONSTANTB_PS, 2271be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2272be1da707SZhi Wang 2273be1da707SZhi Wang {"3DSTATE_DX9_LOCAL_VALID_VS", OP_3DSTATE_DX9_LOCAL_VALID_VS, 2274be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2275be1da707SZhi Wang 2276be1da707SZhi Wang {"3DSTATE_DX9_LOCAL_VALID_PS", OP_3DSTATE_DX9_LOCAL_VALID_PS, 2277be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2278be1da707SZhi Wang 2279be1da707SZhi Wang {"3DSTATE_DX9_GENERATE_ACTIVE_VS", OP_3DSTATE_DX9_GENERATE_ACTIVE_VS, 2280be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2281be1da707SZhi Wang 2282be1da707SZhi Wang {"3DSTATE_DX9_GENERATE_ACTIVE_PS", OP_3DSTATE_DX9_GENERATE_ACTIVE_PS, 2283be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2284be1da707SZhi Wang 2285be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_EDIT_VS", OP_3DSTATE_BINDING_TABLE_EDIT_VS, 2286be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL}, 2287be1da707SZhi Wang 2288be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_EDIT_GS", OP_3DSTATE_BINDING_TABLE_EDIT_GS, 2289be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL}, 2290be1da707SZhi Wang 2291be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_EDIT_HS", OP_3DSTATE_BINDING_TABLE_EDIT_HS, 2292be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL}, 2293be1da707SZhi Wang 2294be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_EDIT_DS", OP_3DSTATE_BINDING_TABLE_EDIT_DS, 2295be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL}, 2296be1da707SZhi Wang 2297be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_EDIT_PS", OP_3DSTATE_BINDING_TABLE_EDIT_PS, 2298be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL}, 2299be1da707SZhi Wang 2300be1da707SZhi Wang {"3DSTATE_VF_INSTANCING", OP_3DSTATE_VF_INSTANCING, F_LEN_VAR, R_RCS, 2301be1da707SZhi Wang D_BDW_PLUS, 0, 8, NULL}, 2302be1da707SZhi Wang 2303be1da707SZhi Wang {"3DSTATE_VF_SGVS", OP_3DSTATE_VF_SGVS, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8, 2304be1da707SZhi Wang NULL}, 2305be1da707SZhi Wang 2306be1da707SZhi Wang {"3DSTATE_VF_TOPOLOGY", OP_3DSTATE_VF_TOPOLOGY, F_LEN_VAR, R_RCS, 2307be1da707SZhi Wang D_BDW_PLUS, 0, 8, NULL}, 2308be1da707SZhi Wang 2309be1da707SZhi Wang {"3DSTATE_WM_CHROMAKEY", OP_3DSTATE_WM_CHROMAKEY, F_LEN_VAR, R_RCS, 2310be1da707SZhi Wang D_BDW_PLUS, 0, 8, NULL}, 2311be1da707SZhi Wang 2312be1da707SZhi Wang {"3DSTATE_PS_BLEND", OP_3DSTATE_PS_BLEND, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 2313be1da707SZhi Wang 8, NULL}, 2314be1da707SZhi Wang 2315be1da707SZhi Wang {"3DSTATE_WM_DEPTH_STENCIL", OP_3DSTATE_WM_DEPTH_STENCIL, F_LEN_VAR, 2316be1da707SZhi Wang R_RCS, D_BDW_PLUS, 0, 8, NULL}, 2317be1da707SZhi Wang 2318be1da707SZhi Wang {"3DSTATE_PS_EXTRA", OP_3DSTATE_PS_EXTRA, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 2319be1da707SZhi Wang 8, NULL}, 2320be1da707SZhi Wang 2321be1da707SZhi Wang {"3DSTATE_RASTER", OP_3DSTATE_RASTER, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8, 2322be1da707SZhi Wang NULL}, 2323be1da707SZhi Wang 2324be1da707SZhi Wang {"3DSTATE_SBE_SWIZ", OP_3DSTATE_SBE_SWIZ, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8, 2325be1da707SZhi Wang NULL}, 2326be1da707SZhi Wang 2327be1da707SZhi Wang {"3DSTATE_WM_HZ_OP", OP_3DSTATE_WM_HZ_OP, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8, 2328be1da707SZhi Wang NULL}, 2329be1da707SZhi Wang 2330be1da707SZhi Wang {"3DSTATE_VERTEX_BUFFERS", OP_3DSTATE_VERTEX_BUFFERS, F_LEN_VAR, R_RCS, 2331be1da707SZhi Wang D_BDW_PLUS, 0, 8, NULL}, 2332be1da707SZhi Wang 2333be1da707SZhi Wang {"3DSTATE_VERTEX_ELEMENTS", OP_3DSTATE_VERTEX_ELEMENTS, F_LEN_VAR, 2334be1da707SZhi Wang R_RCS, D_ALL, 0, 8, NULL}, 2335be1da707SZhi Wang 2336be1da707SZhi Wang {"3DSTATE_INDEX_BUFFER", OP_3DSTATE_INDEX_BUFFER, F_LEN_VAR, R_RCS, 2337be1da707SZhi Wang D_BDW_PLUS, ADDR_FIX_1(2), 8, NULL}, 2338be1da707SZhi Wang 2339be1da707SZhi Wang {"3DSTATE_VF_STATISTICS", OP_3DSTATE_VF_STATISTICS, F_LEN_CONST, 2340be1da707SZhi Wang R_RCS, D_ALL, 0, 1, NULL}, 2341be1da707SZhi Wang 2342be1da707SZhi Wang {"3DSTATE_VF", OP_3DSTATE_VF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2343be1da707SZhi Wang 2344be1da707SZhi Wang {"3DSTATE_CC_STATE_POINTERS", OP_3DSTATE_CC_STATE_POINTERS, F_LEN_VAR, 2345be1da707SZhi Wang R_RCS, D_ALL, 0, 8, NULL}, 2346be1da707SZhi Wang 2347be1da707SZhi Wang {"3DSTATE_SCISSOR_STATE_POINTERS", OP_3DSTATE_SCISSOR_STATE_POINTERS, 2348be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2349be1da707SZhi Wang 2350be1da707SZhi Wang {"3DSTATE_GS", OP_3DSTATE_GS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2351be1da707SZhi Wang 2352be1da707SZhi Wang {"3DSTATE_CLIP", OP_3DSTATE_CLIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2353be1da707SZhi Wang 2354be1da707SZhi Wang {"3DSTATE_WM", OP_3DSTATE_WM, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2355be1da707SZhi Wang 2356be1da707SZhi Wang {"3DSTATE_CONSTANT_GS", OP_3DSTATE_CONSTANT_GS, F_LEN_VAR, R_RCS, 2357be1da707SZhi Wang D_BDW_PLUS, 0, 8, NULL}, 2358be1da707SZhi Wang 2359be1da707SZhi Wang {"3DSTATE_CONSTANT_PS", OP_3DSTATE_CONSTANT_PS, F_LEN_VAR, R_RCS, 2360be1da707SZhi Wang D_BDW_PLUS, 0, 8, NULL}, 2361be1da707SZhi Wang 2362be1da707SZhi Wang {"3DSTATE_SAMPLE_MASK", OP_3DSTATE_SAMPLE_MASK, F_LEN_VAR, R_RCS, 2363be1da707SZhi Wang D_ALL, 0, 8, NULL}, 2364be1da707SZhi Wang 2365be1da707SZhi Wang {"3DSTATE_CONSTANT_HS", OP_3DSTATE_CONSTANT_HS, F_LEN_VAR, R_RCS, 2366be1da707SZhi Wang D_BDW_PLUS, 0, 8, NULL}, 2367be1da707SZhi Wang 2368be1da707SZhi Wang {"3DSTATE_CONSTANT_DS", OP_3DSTATE_CONSTANT_DS, F_LEN_VAR, R_RCS, 2369be1da707SZhi Wang D_BDW_PLUS, 0, 8, NULL}, 2370be1da707SZhi Wang 2371be1da707SZhi Wang {"3DSTATE_HS", OP_3DSTATE_HS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2372be1da707SZhi Wang 2373be1da707SZhi Wang {"3DSTATE_TE", OP_3DSTATE_TE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2374be1da707SZhi Wang 2375be1da707SZhi Wang {"3DSTATE_DS", OP_3DSTATE_DS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2376be1da707SZhi Wang 2377be1da707SZhi Wang {"3DSTATE_STREAMOUT", OP_3DSTATE_STREAMOUT, F_LEN_VAR, R_RCS, 2378be1da707SZhi Wang D_ALL, 0, 8, NULL}, 2379be1da707SZhi Wang 2380be1da707SZhi Wang {"3DSTATE_SBE", OP_3DSTATE_SBE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2381be1da707SZhi Wang 2382be1da707SZhi Wang {"3DSTATE_PS", OP_3DSTATE_PS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2383be1da707SZhi Wang 2384be1da707SZhi Wang {"3DSTATE_DRAWING_RECTANGLE", OP_3DSTATE_DRAWING_RECTANGLE, F_LEN_VAR, 2385be1da707SZhi Wang R_RCS, D_ALL, 0, 8, NULL}, 2386be1da707SZhi Wang 2387be1da707SZhi Wang {"3DSTATE_SAMPLER_PALETTE_LOAD0", OP_3DSTATE_SAMPLER_PALETTE_LOAD0, 2388be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2389be1da707SZhi Wang 2390be1da707SZhi Wang {"3DSTATE_CHROMA_KEY", OP_3DSTATE_CHROMA_KEY, F_LEN_VAR, R_RCS, D_ALL, 2391be1da707SZhi Wang 0, 8, NULL}, 2392be1da707SZhi Wang 2393be1da707SZhi Wang {"3DSTATE_DEPTH_BUFFER", OP_3DSTATE_DEPTH_BUFFER, F_LEN_VAR, R_RCS, 2394be1da707SZhi Wang D_ALL, ADDR_FIX_1(2), 8, NULL}, 2395be1da707SZhi Wang 2396be1da707SZhi Wang {"3DSTATE_POLY_STIPPLE_OFFSET", OP_3DSTATE_POLY_STIPPLE_OFFSET, 2397be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2398be1da707SZhi Wang 2399be1da707SZhi Wang {"3DSTATE_POLY_STIPPLE_PATTERN", OP_3DSTATE_POLY_STIPPLE_PATTERN, 2400be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2401be1da707SZhi Wang 2402be1da707SZhi Wang {"3DSTATE_LINE_STIPPLE", OP_3DSTATE_LINE_STIPPLE, F_LEN_VAR, R_RCS, 2403be1da707SZhi Wang D_ALL, 0, 8, NULL}, 2404be1da707SZhi Wang 2405be1da707SZhi Wang {"3DSTATE_AA_LINE_PARAMS", OP_3DSTATE_AA_LINE_PARAMS, F_LEN_VAR, R_RCS, 2406be1da707SZhi Wang D_ALL, 0, 8, NULL}, 2407be1da707SZhi Wang 2408be1da707SZhi Wang {"3DSTATE_GS_SVB_INDEX", OP_3DSTATE_GS_SVB_INDEX, F_LEN_VAR, R_RCS, 2409be1da707SZhi Wang D_ALL, 0, 8, NULL}, 2410be1da707SZhi Wang 2411be1da707SZhi Wang {"3DSTATE_SAMPLER_PALETTE_LOAD1", OP_3DSTATE_SAMPLER_PALETTE_LOAD1, 2412be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2413be1da707SZhi Wang 2414be1da707SZhi Wang {"3DSTATE_MULTISAMPLE", OP_3DSTATE_MULTISAMPLE_BDW, F_LEN_VAR, R_RCS, 2415be1da707SZhi Wang D_BDW_PLUS, 0, 8, NULL}, 2416be1da707SZhi Wang 2417be1da707SZhi Wang {"3DSTATE_STENCIL_BUFFER", OP_3DSTATE_STENCIL_BUFFER, F_LEN_VAR, R_RCS, 2418be1da707SZhi Wang D_ALL, ADDR_FIX_1(2), 8, NULL}, 2419be1da707SZhi Wang 2420be1da707SZhi Wang {"3DSTATE_HIER_DEPTH_BUFFER", OP_3DSTATE_HIER_DEPTH_BUFFER, F_LEN_VAR, 2421be1da707SZhi Wang R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL}, 2422be1da707SZhi Wang 2423be1da707SZhi Wang {"3DSTATE_CLEAR_PARAMS", OP_3DSTATE_CLEAR_PARAMS, F_LEN_VAR, 2424be1da707SZhi Wang R_RCS, D_ALL, 0, 8, NULL}, 2425be1da707SZhi Wang 2426be1da707SZhi Wang {"3DSTATE_PUSH_CONSTANT_ALLOC_VS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS, 2427be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2428be1da707SZhi Wang 2429be1da707SZhi Wang {"3DSTATE_PUSH_CONSTANT_ALLOC_HS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS, 2430be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2431be1da707SZhi Wang 2432be1da707SZhi Wang {"3DSTATE_PUSH_CONSTANT_ALLOC_DS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS, 2433be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2434be1da707SZhi Wang 2435be1da707SZhi Wang {"3DSTATE_PUSH_CONSTANT_ALLOC_GS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS, 2436be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2437be1da707SZhi Wang 2438be1da707SZhi Wang {"3DSTATE_PUSH_CONSTANT_ALLOC_PS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS, 2439be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2440be1da707SZhi Wang 2441be1da707SZhi Wang {"3DSTATE_MONOFILTER_SIZE", OP_3DSTATE_MONOFILTER_SIZE, F_LEN_VAR, 2442be1da707SZhi Wang R_RCS, D_ALL, 0, 8, NULL}, 2443be1da707SZhi Wang 2444be1da707SZhi Wang {"3DSTATE_SO_DECL_LIST", OP_3DSTATE_SO_DECL_LIST, F_LEN_VAR, R_RCS, 2445be1da707SZhi Wang D_ALL, 0, 9, NULL}, 2446be1da707SZhi Wang 2447be1da707SZhi Wang {"3DSTATE_SO_BUFFER", OP_3DSTATE_SO_BUFFER, F_LEN_VAR, R_RCS, D_BDW_PLUS, 2448be1da707SZhi Wang ADDR_FIX_2(2, 4), 8, NULL}, 2449be1da707SZhi Wang 2450be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_POOL_ALLOC", 2451be1da707SZhi Wang OP_3DSTATE_BINDING_TABLE_POOL_ALLOC, 2452be1da707SZhi Wang F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL}, 2453be1da707SZhi Wang 2454be1da707SZhi Wang {"3DSTATE_GATHER_POOL_ALLOC", OP_3DSTATE_GATHER_POOL_ALLOC, 2455be1da707SZhi Wang F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL}, 2456be1da707SZhi Wang 2457be1da707SZhi Wang {"3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC", 2458be1da707SZhi Wang OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC, 2459be1da707SZhi Wang F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL}, 2460be1da707SZhi Wang 2461be1da707SZhi Wang {"3DSTATE_SAMPLE_PATTERN", OP_3DSTATE_SAMPLE_PATTERN, F_LEN_VAR, R_RCS, 2462be1da707SZhi Wang D_BDW_PLUS, 0, 8, NULL}, 2463be1da707SZhi Wang 2464be1da707SZhi Wang {"PIPE_CONTROL", OP_PIPE_CONTROL, F_LEN_VAR, R_RCS, D_ALL, 2465be1da707SZhi Wang ADDR_FIX_1(2), 8, cmd_handler_pipe_control}, 2466be1da707SZhi Wang 2467be1da707SZhi Wang {"3DPRIMITIVE", OP_3DPRIMITIVE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2468be1da707SZhi Wang 2469be1da707SZhi Wang {"PIPELINE_SELECT", OP_PIPELINE_SELECT, F_LEN_CONST, R_RCS, D_ALL, 0, 2470be1da707SZhi Wang 1, NULL}, 2471be1da707SZhi Wang 2472be1da707SZhi Wang {"STATE_PREFETCH", OP_STATE_PREFETCH, F_LEN_VAR, R_RCS, D_ALL, 2473be1da707SZhi Wang ADDR_FIX_1(1), 8, NULL}, 2474be1da707SZhi Wang 2475be1da707SZhi Wang {"STATE_SIP", OP_STATE_SIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2476be1da707SZhi Wang 2477be1da707SZhi Wang {"STATE_BASE_ADDRESS", OP_STATE_BASE_ADDRESS, F_LEN_VAR, R_RCS, D_BDW_PLUS, 2478be1da707SZhi Wang ADDR_FIX_5(1, 3, 4, 5, 6), 8, NULL}, 2479be1da707SZhi Wang 2480be1da707SZhi Wang {"OP_3D_MEDIA_0_1_4", OP_3D_MEDIA_0_1_4, F_LEN_VAR, R_RCS, D_ALL, 2481be1da707SZhi Wang ADDR_FIX_1(1), 8, NULL}, 2482be1da707SZhi Wang 2483be1da707SZhi Wang {"3DSTATE_VS", OP_3DSTATE_VS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2484be1da707SZhi Wang 2485be1da707SZhi Wang {"3DSTATE_SF", OP_3DSTATE_SF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, 2486be1da707SZhi Wang 2487be1da707SZhi Wang {"3DSTATE_CONSTANT_VS", OP_3DSTATE_CONSTANT_VS, F_LEN_VAR, R_RCS, D_BDW_PLUS, 2488be1da707SZhi Wang 0, 8, NULL}, 2489be1da707SZhi Wang 2490be1da707SZhi Wang {"3DSTATE_COMPONENT_PACKING", OP_3DSTATE_COMPONENT_PACKING, F_LEN_VAR, R_RCS, 2491be1da707SZhi Wang D_SKL_PLUS, 0, 8, NULL}, 2492be1da707SZhi Wang 2493be1da707SZhi Wang {"MEDIA_INTERFACE_DESCRIPTOR_LOAD", OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD, 2494be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL}, 2495be1da707SZhi Wang 2496be1da707SZhi Wang {"MEDIA_GATEWAY_STATE", OP_MEDIA_GATEWAY_STATE, F_LEN_VAR, R_RCS, D_ALL, 2497be1da707SZhi Wang 0, 16, NULL}, 2498be1da707SZhi Wang 2499be1da707SZhi Wang {"MEDIA_STATE_FLUSH", OP_MEDIA_STATE_FLUSH, F_LEN_VAR, R_RCS, D_ALL, 2500be1da707SZhi Wang 0, 16, NULL}, 2501be1da707SZhi Wang 250202b966c1SColin Xu {"MEDIA_POOL_STATE", OP_MEDIA_POOL_STATE, F_LEN_VAR, R_RCS, D_ALL, 250302b966c1SColin Xu 0, 16, NULL}, 250402b966c1SColin Xu 2505be1da707SZhi Wang {"MEDIA_OBJECT", OP_MEDIA_OBJECT, F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL}, 2506be1da707SZhi Wang 2507be1da707SZhi Wang {"MEDIA_CURBE_LOAD", OP_MEDIA_CURBE_LOAD, F_LEN_VAR, R_RCS, D_ALL, 2508be1da707SZhi Wang 0, 16, NULL}, 2509be1da707SZhi Wang 2510be1da707SZhi Wang {"MEDIA_OBJECT_PRT", OP_MEDIA_OBJECT_PRT, F_LEN_VAR, R_RCS, D_ALL, 2511be1da707SZhi Wang 0, 16, NULL}, 2512be1da707SZhi Wang 2513be1da707SZhi Wang {"MEDIA_OBJECT_WALKER", OP_MEDIA_OBJECT_WALKER, F_LEN_VAR, R_RCS, D_ALL, 2514be1da707SZhi Wang 0, 16, NULL}, 2515be1da707SZhi Wang 2516be1da707SZhi Wang {"GPGPU_WALKER", OP_GPGPU_WALKER, F_LEN_VAR, R_RCS, D_ALL, 2517be1da707SZhi Wang 0, 8, NULL}, 2518be1da707SZhi Wang 2519be1da707SZhi Wang {"MEDIA_VFE_STATE", OP_MEDIA_VFE_STATE, F_LEN_VAR, R_RCS, D_ALL, 0, 16, 2520be1da707SZhi Wang NULL}, 2521be1da707SZhi Wang 2522be1da707SZhi Wang {"3DSTATE_VF_STATISTICS_GM45", OP_3DSTATE_VF_STATISTICS_GM45, 2523be1da707SZhi Wang F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL}, 2524be1da707SZhi Wang 2525be1da707SZhi Wang {"MFX_PIPE_MODE_SELECT", OP_MFX_PIPE_MODE_SELECT, F_LEN_VAR, 2526be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2527be1da707SZhi Wang 2528be1da707SZhi Wang {"MFX_SURFACE_STATE", OP_MFX_SURFACE_STATE, F_LEN_VAR, 2529be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2530be1da707SZhi Wang 2531be1da707SZhi Wang {"MFX_PIPE_BUF_ADDR_STATE", OP_MFX_PIPE_BUF_ADDR_STATE, F_LEN_VAR, 2532be1da707SZhi Wang R_VCS, D_BDW_PLUS, 0, 12, NULL}, 2533be1da707SZhi Wang 2534be1da707SZhi Wang {"MFX_IND_OBJ_BASE_ADDR_STATE", OP_MFX_IND_OBJ_BASE_ADDR_STATE, 2535be1da707SZhi Wang F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL}, 2536be1da707SZhi Wang 2537be1da707SZhi Wang {"MFX_BSP_BUF_BASE_ADDR_STATE", OP_MFX_BSP_BUF_BASE_ADDR_STATE, 2538be1da707SZhi Wang F_LEN_VAR, R_VCS, D_BDW_PLUS, ADDR_FIX_3(1, 3, 5), 12, NULL}, 2539be1da707SZhi Wang 2540be1da707SZhi Wang {"OP_2_0_0_5", OP_2_0_0_5, F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL}, 2541be1da707SZhi Wang 2542be1da707SZhi Wang {"MFX_STATE_POINTER", OP_MFX_STATE_POINTER, F_LEN_VAR, 2543be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2544be1da707SZhi Wang 2545be1da707SZhi Wang {"MFX_QM_STATE", OP_MFX_QM_STATE, F_LEN_VAR, 2546be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2547be1da707SZhi Wang 2548be1da707SZhi Wang {"MFX_FQM_STATE", OP_MFX_FQM_STATE, F_LEN_VAR, 2549be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2550be1da707SZhi Wang 2551be1da707SZhi Wang {"MFX_PAK_INSERT_OBJECT", OP_MFX_PAK_INSERT_OBJECT, F_LEN_VAR, 2552be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2553be1da707SZhi Wang 2554be1da707SZhi Wang {"MFX_STITCH_OBJECT", OP_MFX_STITCH_OBJECT, F_LEN_VAR, 2555be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2556be1da707SZhi Wang 2557be1da707SZhi Wang {"MFD_IT_OBJECT", OP_MFD_IT_OBJECT, F_LEN_VAR, 2558be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2559be1da707SZhi Wang 2560be1da707SZhi Wang {"MFX_WAIT", OP_MFX_WAIT, F_LEN_VAR, 2561be1da707SZhi Wang R_VCS, D_ALL, 0, 6, NULL}, 2562be1da707SZhi Wang 2563be1da707SZhi Wang {"MFX_AVC_IMG_STATE", OP_MFX_AVC_IMG_STATE, F_LEN_VAR, 2564be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2565be1da707SZhi Wang 2566be1da707SZhi Wang {"MFX_AVC_QM_STATE", OP_MFX_AVC_QM_STATE, F_LEN_VAR, 2567be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2568be1da707SZhi Wang 2569be1da707SZhi Wang {"MFX_AVC_DIRECTMODE_STATE", OP_MFX_AVC_DIRECTMODE_STATE, F_LEN_VAR, 2570be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2571be1da707SZhi Wang 2572be1da707SZhi Wang {"MFX_AVC_SLICE_STATE", OP_MFX_AVC_SLICE_STATE, F_LEN_VAR, 2573be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2574be1da707SZhi Wang 2575be1da707SZhi Wang {"MFX_AVC_REF_IDX_STATE", OP_MFX_AVC_REF_IDX_STATE, F_LEN_VAR, 2576be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2577be1da707SZhi Wang 2578be1da707SZhi Wang {"MFX_AVC_WEIGHTOFFSET_STATE", OP_MFX_AVC_WEIGHTOFFSET_STATE, F_LEN_VAR, 2579be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2580be1da707SZhi Wang 2581be1da707SZhi Wang {"MFD_AVC_PICID_STATE", OP_MFD_AVC_PICID_STATE, F_LEN_VAR, 2582be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2583be1da707SZhi Wang {"MFD_AVC_DPB_STATE", OP_MFD_AVC_DPB_STATE, F_LEN_VAR, 2584be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2585be1da707SZhi Wang 2586be1da707SZhi Wang {"MFD_AVC_BSD_OBJECT", OP_MFD_AVC_BSD_OBJECT, F_LEN_VAR, 2587be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2588be1da707SZhi Wang 2589be1da707SZhi Wang {"MFD_AVC_SLICEADDR", OP_MFD_AVC_SLICEADDR, F_LEN_VAR, 2590be1da707SZhi Wang R_VCS, D_ALL, ADDR_FIX_1(2), 12, NULL}, 2591be1da707SZhi Wang 2592be1da707SZhi Wang {"MFC_AVC_PAK_OBJECT", OP_MFC_AVC_PAK_OBJECT, F_LEN_VAR, 2593be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2594be1da707SZhi Wang 2595be1da707SZhi Wang {"MFX_VC1_PRED_PIPE_STATE", OP_MFX_VC1_PRED_PIPE_STATE, F_LEN_VAR, 2596be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2597be1da707SZhi Wang 2598be1da707SZhi Wang {"MFX_VC1_DIRECTMODE_STATE", OP_MFX_VC1_DIRECTMODE_STATE, F_LEN_VAR, 2599be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2600be1da707SZhi Wang 2601be1da707SZhi Wang {"MFD_VC1_SHORT_PIC_STATE", OP_MFD_VC1_SHORT_PIC_STATE, F_LEN_VAR, 2602be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2603be1da707SZhi Wang 2604be1da707SZhi Wang {"MFD_VC1_LONG_PIC_STATE", OP_MFD_VC1_LONG_PIC_STATE, F_LEN_VAR, 2605be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2606be1da707SZhi Wang 2607be1da707SZhi Wang {"MFD_VC1_BSD_OBJECT", OP_MFD_VC1_BSD_OBJECT, F_LEN_VAR, 2608be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2609be1da707SZhi Wang 2610be1da707SZhi Wang {"MFC_MPEG2_SLICEGROUP_STATE", OP_MFC_MPEG2_SLICEGROUP_STATE, F_LEN_VAR, 2611be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2612be1da707SZhi Wang 2613be1da707SZhi Wang {"MFC_MPEG2_PAK_OBJECT", OP_MFC_MPEG2_PAK_OBJECT, F_LEN_VAR, 2614be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2615be1da707SZhi Wang 2616be1da707SZhi Wang {"MFX_MPEG2_PIC_STATE", OP_MFX_MPEG2_PIC_STATE, F_LEN_VAR, 2617be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2618be1da707SZhi Wang 2619be1da707SZhi Wang {"MFX_MPEG2_QM_STATE", OP_MFX_MPEG2_QM_STATE, F_LEN_VAR, 2620be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2621be1da707SZhi Wang 2622be1da707SZhi Wang {"MFD_MPEG2_BSD_OBJECT", OP_MFD_MPEG2_BSD_OBJECT, F_LEN_VAR, 2623be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2624be1da707SZhi Wang 2625be1da707SZhi Wang {"MFX_2_6_0_0", OP_MFX_2_6_0_0, F_LEN_VAR, R_VCS, D_ALL, 2626be1da707SZhi Wang 0, 16, NULL}, 2627be1da707SZhi Wang 2628be1da707SZhi Wang {"MFX_2_6_0_9", OP_MFX_2_6_0_9, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL}, 2629be1da707SZhi Wang 2630be1da707SZhi Wang {"MFX_2_6_0_8", OP_MFX_2_6_0_8, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL}, 2631be1da707SZhi Wang 2632be1da707SZhi Wang {"MFX_JPEG_PIC_STATE", OP_MFX_JPEG_PIC_STATE, F_LEN_VAR, 2633be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2634be1da707SZhi Wang 2635be1da707SZhi Wang {"MFX_JPEG_HUFF_TABLE_STATE", OP_MFX_JPEG_HUFF_TABLE_STATE, F_LEN_VAR, 2636be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2637be1da707SZhi Wang 2638be1da707SZhi Wang {"MFD_JPEG_BSD_OBJECT", OP_MFD_JPEG_BSD_OBJECT, F_LEN_VAR, 2639be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL}, 2640be1da707SZhi Wang 2641be1da707SZhi Wang {"VEBOX_STATE", OP_VEB_STATE, F_LEN_VAR, R_VECS, D_ALL, 0, 12, NULL}, 2642be1da707SZhi Wang 2643be1da707SZhi Wang {"VEBOX_SURFACE_STATE", OP_VEB_SURFACE_STATE, F_LEN_VAR, R_VECS, D_ALL, 2644be1da707SZhi Wang 0, 12, NULL}, 2645be1da707SZhi Wang 2646be1da707SZhi Wang {"VEB_DI_IECP", OP_VEB_DNDI_IECP_STATE, F_LEN_VAR, R_VECS, D_BDW_PLUS, 26473035e8cdSGao, Fred 0, 12, NULL}, 2648be1da707SZhi Wang }; 2649be1da707SZhi Wang 2650be1da707SZhi Wang static void add_cmd_entry(struct intel_gvt *gvt, struct cmd_entry *e) 2651be1da707SZhi Wang { 2652be1da707SZhi Wang hash_add(gvt->cmd_table, &e->hlist, e->info->opcode); 2653be1da707SZhi Wang } 2654be1da707SZhi Wang 2655be1da707SZhi Wang /* call the cmd handler, and advance ip */ 2656be1da707SZhi Wang static int cmd_parser_exec(struct parser_exec_state *s) 2657be1da707SZhi Wang { 2658ffc19776SChangbin Du struct intel_vgpu *vgpu = s->vgpu; 2659b007065aSJani Nikula const struct cmd_info *info; 2660be1da707SZhi Wang u32 cmd; 2661be1da707SZhi Wang int ret = 0; 2662be1da707SZhi Wang 2663be1da707SZhi Wang cmd = cmd_val(s, 0); 2664be1da707SZhi Wang 2665db47685dSZhao Yan /* fastpath for MI_NOOP */ 2666db47685dSZhao Yan if (cmd == MI_NOOP) 2667db47685dSZhao Yan info = &cmd_info[mi_noop_index]; 2668db47685dSZhao Yan else 2669be1da707SZhi Wang info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id); 2670db47685dSZhao Yan 2671be1da707SZhi Wang if (info == NULL) { 267296bebe39SZhao Yan gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %d, workload=%p\n", 267396bebe39SZhao Yan cmd, get_opcode(cmd, s->ring_id), 267496bebe39SZhao Yan (s->buf_addr_type == PPGTT_BUFFER) ? 267596bebe39SZhao Yan "ppgtt" : "ggtt", s->ring_id, s->workload); 26765c56883aSfred gao return -EBADRQC; 2677be1da707SZhi Wang } 2678be1da707SZhi Wang 2679be1da707SZhi Wang s->info = info; 2680be1da707SZhi Wang 2681ffc19776SChangbin Du trace_gvt_command(vgpu->id, s->ring_id, s->ip_gma, s->ip_va, 268296bebe39SZhao Yan cmd_length(s), s->buf_type, s->buf_addr_type, 268396bebe39SZhao Yan s->workload, info->name); 2684be1da707SZhi Wang 26851e2adc0dSGao, Fred if ((info->flag & F_LEN_MASK) == F_LEN_VAR_FIXED) { 26861e2adc0dSGao, Fred ret = gvt_check_valid_cmd_length(cmd_length(s), 26871e2adc0dSGao, Fred info->valid_len); 26881e2adc0dSGao, Fred if (ret) 26891e2adc0dSGao, Fred return ret; 26901e2adc0dSGao, Fred } 26911e2adc0dSGao, Fred 2692be1da707SZhi Wang if (info->handler) { 2693be1da707SZhi Wang ret = info->handler(s); 2694be1da707SZhi Wang if (ret < 0) { 2695695fbc08STina Zhang gvt_vgpu_err("%s handler error\n", info->name); 2696be1da707SZhi Wang return ret; 2697be1da707SZhi Wang } 2698be1da707SZhi Wang } 2699be1da707SZhi Wang 2700be1da707SZhi Wang if (!(info->flag & F_IP_ADVANCE_CUSTOM)) { 2701be1da707SZhi Wang ret = cmd_advance_default(s); 2702be1da707SZhi Wang if (ret) { 2703695fbc08STina Zhang gvt_vgpu_err("%s IP advance error\n", info->name); 2704be1da707SZhi Wang return ret; 2705be1da707SZhi Wang } 2706be1da707SZhi Wang } 2707be1da707SZhi Wang return 0; 2708be1da707SZhi Wang } 2709be1da707SZhi Wang 2710be1da707SZhi Wang static inline bool gma_out_of_range(unsigned long gma, 2711be1da707SZhi Wang unsigned long gma_head, unsigned int gma_tail) 2712be1da707SZhi Wang { 2713be1da707SZhi Wang if (gma_tail >= gma_head) 2714be1da707SZhi Wang return (gma < gma_head) || (gma > gma_tail); 2715be1da707SZhi Wang else 2716be1da707SZhi Wang return (gma > gma_tail) && (gma < gma_head); 2717be1da707SZhi Wang } 2718be1da707SZhi Wang 27195c56883aSfred gao /* Keep the consistent return type, e.g EBADRQC for unknown 27205c56883aSfred gao * cmd, EFAULT for invalid address, EPERM for nonpriv. later 27215c56883aSfred gao * works as the input of VM healthy status. 27225c56883aSfred gao */ 2723be1da707SZhi Wang static int command_scan(struct parser_exec_state *s, 2724be1da707SZhi Wang unsigned long rb_head, unsigned long rb_tail, 2725be1da707SZhi Wang unsigned long rb_start, unsigned long rb_len) 2726be1da707SZhi Wang { 2727be1da707SZhi Wang 2728be1da707SZhi Wang unsigned long gma_head, gma_tail, gma_bottom; 2729be1da707SZhi Wang int ret = 0; 2730695fbc08STina Zhang struct intel_vgpu *vgpu = s->vgpu; 2731be1da707SZhi Wang 2732be1da707SZhi Wang gma_head = rb_start + rb_head; 2733be1da707SZhi Wang gma_tail = rb_start + rb_tail; 2734be1da707SZhi Wang gma_bottom = rb_start + rb_len; 2735be1da707SZhi Wang 2736be1da707SZhi Wang while (s->ip_gma != gma_tail) { 2737be1da707SZhi Wang if (s->buf_type == RING_BUFFER_INSTRUCTION) { 2738be1da707SZhi Wang if (!(s->ip_gma >= rb_start) || 2739be1da707SZhi Wang !(s->ip_gma < gma_bottom)) { 2740695fbc08STina Zhang gvt_vgpu_err("ip_gma %lx out of ring scope." 2741be1da707SZhi Wang "(base:0x%lx, bottom: 0x%lx)\n", 2742be1da707SZhi Wang s->ip_gma, rb_start, 2743be1da707SZhi Wang gma_bottom); 2744be1da707SZhi Wang parser_exec_state_dump(s); 27455c56883aSfred gao return -EFAULT; 2746be1da707SZhi Wang } 2747be1da707SZhi Wang if (gma_out_of_range(s->ip_gma, gma_head, gma_tail)) { 2748695fbc08STina Zhang gvt_vgpu_err("ip_gma %lx out of range." 2749be1da707SZhi Wang "base 0x%lx head 0x%lx tail 0x%lx\n", 2750be1da707SZhi Wang s->ip_gma, rb_start, 2751be1da707SZhi Wang rb_head, rb_tail); 2752be1da707SZhi Wang parser_exec_state_dump(s); 2753be1da707SZhi Wang break; 2754be1da707SZhi Wang } 2755be1da707SZhi Wang } 2756be1da707SZhi Wang ret = cmd_parser_exec(s); 2757be1da707SZhi Wang if (ret) { 2758695fbc08STina Zhang gvt_vgpu_err("cmd parser error\n"); 2759be1da707SZhi Wang parser_exec_state_dump(s); 2760be1da707SZhi Wang break; 2761be1da707SZhi Wang } 2762be1da707SZhi Wang } 2763be1da707SZhi Wang 2764be1da707SZhi Wang return ret; 2765be1da707SZhi Wang } 2766be1da707SZhi Wang 2767be1da707SZhi Wang static int scan_workload(struct intel_vgpu_workload *workload) 2768be1da707SZhi Wang { 2769be1da707SZhi Wang unsigned long gma_head, gma_tail, gma_bottom; 2770be1da707SZhi Wang struct parser_exec_state s; 2771be1da707SZhi Wang int ret = 0; 2772be1da707SZhi Wang 2773be1da707SZhi Wang /* ring base is page aligned */ 27749556e118SZhi Wang if (WARN_ON(!IS_ALIGNED(workload->rb_start, I915_GTT_PAGE_SIZE))) 2775be1da707SZhi Wang return -EINVAL; 2776be1da707SZhi Wang 2777be1da707SZhi Wang gma_head = workload->rb_start + workload->rb_head; 2778be1da707SZhi Wang gma_tail = workload->rb_start + workload->rb_tail; 2779be1da707SZhi Wang gma_bottom = workload->rb_start + _RING_CTL_BUF_SIZE(workload->rb_ctl); 2780be1da707SZhi Wang 2781be1da707SZhi Wang s.buf_type = RING_BUFFER_INSTRUCTION; 2782be1da707SZhi Wang s.buf_addr_type = GTT_BUFFER; 2783be1da707SZhi Wang s.vgpu = workload->vgpu; 2784be1da707SZhi Wang s.ring_id = workload->ring_id; 2785be1da707SZhi Wang s.ring_start = workload->rb_start; 2786be1da707SZhi Wang s.ring_size = _RING_CTL_BUF_SIZE(workload->rb_ctl); 2787be1da707SZhi Wang s.ring_head = gma_head; 2788be1da707SZhi Wang s.ring_tail = gma_tail; 2789be1da707SZhi Wang s.rb_va = workload->shadow_ring_buffer_va; 2790be1da707SZhi Wang s.workload = workload; 2791ef75c685Sfred gao s.is_ctx_wa = false; 2792be1da707SZhi Wang 27930aaee4ccSPei Zhang if ((bypass_scan_mask & (1 << workload->ring_id)) || 27940aaee4ccSPei Zhang gma_head == gma_tail) 2795be1da707SZhi Wang return 0; 2796be1da707SZhi Wang 2797be1da707SZhi Wang ret = ip_gma_set(&s, gma_head); 2798be1da707SZhi Wang if (ret) 2799be1da707SZhi Wang goto out; 2800be1da707SZhi Wang 2801be1da707SZhi Wang ret = command_scan(&s, workload->rb_head, workload->rb_tail, 2802be1da707SZhi Wang workload->rb_start, _RING_CTL_BUF_SIZE(workload->rb_ctl)); 2803be1da707SZhi Wang 2804be1da707SZhi Wang out: 2805be1da707SZhi Wang return ret; 2806be1da707SZhi Wang } 2807be1da707SZhi Wang 2808be1da707SZhi Wang static int scan_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx) 2809be1da707SZhi Wang { 2810be1da707SZhi Wang 2811be1da707SZhi Wang unsigned long gma_head, gma_tail, gma_bottom, ring_size, ring_tail; 2812be1da707SZhi Wang struct parser_exec_state s; 2813be1da707SZhi Wang int ret = 0; 2814c10c1255STina Zhang struct intel_vgpu_workload *workload = container_of(wa_ctx, 2815c10c1255STina Zhang struct intel_vgpu_workload, 2816c10c1255STina Zhang wa_ctx); 2817be1da707SZhi Wang 2818be1da707SZhi Wang /* ring base is page aligned */ 28199556e118SZhi Wang if (WARN_ON(!IS_ALIGNED(wa_ctx->indirect_ctx.guest_gma, 28209556e118SZhi Wang I915_GTT_PAGE_SIZE))) 2821be1da707SZhi Wang return -EINVAL; 2822be1da707SZhi Wang 28232e679d48SJani Nikula ring_tail = wa_ctx->indirect_ctx.size + 3 * sizeof(u32); 2824be1da707SZhi Wang ring_size = round_up(wa_ctx->indirect_ctx.size + CACHELINE_BYTES, 2825be1da707SZhi Wang PAGE_SIZE); 2826be1da707SZhi Wang gma_head = wa_ctx->indirect_ctx.guest_gma; 2827be1da707SZhi Wang gma_tail = wa_ctx->indirect_ctx.guest_gma + ring_tail; 2828be1da707SZhi Wang gma_bottom = wa_ctx->indirect_ctx.guest_gma + ring_size; 2829be1da707SZhi Wang 2830be1da707SZhi Wang s.buf_type = RING_BUFFER_INSTRUCTION; 2831be1da707SZhi Wang s.buf_addr_type = GTT_BUFFER; 2832c10c1255STina Zhang s.vgpu = workload->vgpu; 2833c10c1255STina Zhang s.ring_id = workload->ring_id; 2834be1da707SZhi Wang s.ring_start = wa_ctx->indirect_ctx.guest_gma; 2835be1da707SZhi Wang s.ring_size = ring_size; 2836be1da707SZhi Wang s.ring_head = gma_head; 2837be1da707SZhi Wang s.ring_tail = gma_tail; 2838be1da707SZhi Wang s.rb_va = wa_ctx->indirect_ctx.shadow_va; 2839c10c1255STina Zhang s.workload = workload; 2840ef75c685Sfred gao s.is_ctx_wa = true; 2841be1da707SZhi Wang 2842be1da707SZhi Wang ret = ip_gma_set(&s, gma_head); 2843be1da707SZhi Wang if (ret) 2844be1da707SZhi Wang goto out; 2845be1da707SZhi Wang 2846be1da707SZhi Wang ret = command_scan(&s, 0, ring_tail, 2847be1da707SZhi Wang wa_ctx->indirect_ctx.guest_gma, ring_size); 2848be1da707SZhi Wang out: 2849be1da707SZhi Wang return ret; 2850be1da707SZhi Wang } 2851be1da707SZhi Wang 2852be1da707SZhi Wang static int shadow_workload_ring_buffer(struct intel_vgpu_workload *workload) 2853be1da707SZhi Wang { 2854be1da707SZhi Wang struct intel_vgpu *vgpu = workload->vgpu; 2855325eb94aSZhi Wang struct intel_vgpu_submission *s = &vgpu->submission; 2856be1da707SZhi Wang unsigned long gma_head, gma_tail, gma_top, guest_rb_size; 28570a53bc07Sfred gao void *shadow_ring_buffer_va; 28580a53bc07Sfred gao int ring_id = workload->ring_id; 2859be1da707SZhi Wang int ret; 2860be1da707SZhi Wang 2861be1da707SZhi Wang guest_rb_size = _RING_CTL_BUF_SIZE(workload->rb_ctl); 2862be1da707SZhi Wang 2863be1da707SZhi Wang /* calculate workload ring buffer size */ 2864be1da707SZhi Wang workload->rb_len = (workload->rb_tail + guest_rb_size - 2865be1da707SZhi Wang workload->rb_head) % guest_rb_size; 2866be1da707SZhi Wang 2867be1da707SZhi Wang gma_head = workload->rb_start + workload->rb_head; 2868be1da707SZhi Wang gma_tail = workload->rb_start + workload->rb_tail; 2869be1da707SZhi Wang gma_top = workload->rb_start + guest_rb_size; 2870be1da707SZhi Wang 2871325eb94aSZhi Wang if (workload->rb_len > s->ring_scan_buffer_size[ring_id]) { 28728cf80a2eSZhi Wang void *p; 2873bf4097eaSZhi Wang 28740a53bc07Sfred gao /* realloc the new ring buffer if needed */ 2875325eb94aSZhi Wang p = krealloc(s->ring_scan_buffer[ring_id], workload->rb_len, 28768cf80a2eSZhi Wang GFP_KERNEL); 2877bf4097eaSZhi Wang if (!p) { 28788cf80a2eSZhi Wang gvt_vgpu_err("fail to re-alloc ring scan buffer\n"); 28790a53bc07Sfred gao return -ENOMEM; 28800a53bc07Sfred gao } 2881325eb94aSZhi Wang s->ring_scan_buffer[ring_id] = p; 2882325eb94aSZhi Wang s->ring_scan_buffer_size[ring_id] = workload->rb_len; 28830a53bc07Sfred gao } 28840a53bc07Sfred gao 2885325eb94aSZhi Wang shadow_ring_buffer_va = s->ring_scan_buffer[ring_id]; 2886be1da707SZhi Wang 2887be1da707SZhi Wang /* get shadow ring buffer va */ 28880a53bc07Sfred gao workload->shadow_ring_buffer_va = shadow_ring_buffer_va; 2889be1da707SZhi Wang 2890be1da707SZhi Wang /* head > tail --> copy head <-> top */ 2891be1da707SZhi Wang if (gma_head > gma_tail) { 2892be1da707SZhi Wang ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm, 28930a53bc07Sfred gao gma_head, gma_top, shadow_ring_buffer_va); 28948bcad07aSZhenyu Wang if (ret < 0) { 2895695fbc08STina Zhang gvt_vgpu_err("fail to copy guest ring buffer\n"); 2896be1da707SZhi Wang return ret; 2897be1da707SZhi Wang } 28980a53bc07Sfred gao shadow_ring_buffer_va += ret; 2899be1da707SZhi Wang gma_head = workload->rb_start; 2900be1da707SZhi Wang } 2901be1da707SZhi Wang 2902be1da707SZhi Wang /* copy head or start <-> tail */ 29030a53bc07Sfred gao ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm, gma_head, gma_tail, 29040a53bc07Sfred gao shadow_ring_buffer_va); 29058bcad07aSZhenyu Wang if (ret < 0) { 2906695fbc08STina Zhang gvt_vgpu_err("fail to copy guest ring buffer\n"); 2907be1da707SZhi Wang return ret; 2908be1da707SZhi Wang } 2909be1da707SZhi Wang return 0; 2910be1da707SZhi Wang } 2911be1da707SZhi Wang 291289ea20b9SPing Gao int intel_gvt_scan_and_shadow_ringbuffer(struct intel_vgpu_workload *workload) 2913be1da707SZhi Wang { 2914be1da707SZhi Wang int ret; 2915695fbc08STina Zhang struct intel_vgpu *vgpu = workload->vgpu; 2916be1da707SZhi Wang 2917be1da707SZhi Wang ret = shadow_workload_ring_buffer(workload); 2918be1da707SZhi Wang if (ret) { 2919695fbc08STina Zhang gvt_vgpu_err("fail to shadow workload ring_buffer\n"); 2920be1da707SZhi Wang return ret; 2921be1da707SZhi Wang } 2922be1da707SZhi Wang 2923be1da707SZhi Wang ret = scan_workload(workload); 2924be1da707SZhi Wang if (ret) { 2925695fbc08STina Zhang gvt_vgpu_err("scan workload error\n"); 2926be1da707SZhi Wang return ret; 2927be1da707SZhi Wang } 2928be1da707SZhi Wang return 0; 2929be1da707SZhi Wang } 2930be1da707SZhi Wang 2931be1da707SZhi Wang static int shadow_indirect_ctx(struct intel_shadow_wa_ctx *wa_ctx) 2932be1da707SZhi Wang { 2933be1da707SZhi Wang int ctx_size = wa_ctx->indirect_ctx.size; 2934be1da707SZhi Wang unsigned long guest_gma = wa_ctx->indirect_ctx.guest_gma; 2935c10c1255STina Zhang struct intel_vgpu_workload *workload = container_of(wa_ctx, 2936c10c1255STina Zhang struct intel_vgpu_workload, 2937c10c1255STina Zhang wa_ctx); 2938c10c1255STina Zhang struct intel_vgpu *vgpu = workload->vgpu; 2939894cf7d1SChris Wilson struct drm_i915_gem_object *obj; 2940be1da707SZhi Wang int ret = 0; 2941bcd0aedeSChris Wilson void *map; 2942be1da707SZhi Wang 29438475355fSChris Wilson obj = i915_gem_object_create_shmem(workload->vgpu->gvt->dev_priv, 2944894cf7d1SChris Wilson roundup(ctx_size + CACHELINE_BYTES, 2945894cf7d1SChris Wilson PAGE_SIZE)); 2946894cf7d1SChris Wilson if (IS_ERR(obj)) 2947894cf7d1SChris Wilson return PTR_ERR(obj); 2948be1da707SZhi Wang 2949be1da707SZhi Wang /* get the va of the shadow batch buffer */ 2950bcd0aedeSChris Wilson map = i915_gem_object_pin_map(obj, I915_MAP_WB); 2951bcd0aedeSChris Wilson if (IS_ERR(map)) { 2952695fbc08STina Zhang gvt_vgpu_err("failed to vmap shadow indirect ctx\n"); 2953bcd0aedeSChris Wilson ret = PTR_ERR(map); 2954bcd0aedeSChris Wilson goto put_obj; 2955be1da707SZhi Wang } 2956be1da707SZhi Wang 29576951e589SChris Wilson i915_gem_object_lock(obj); 2958894cf7d1SChris Wilson ret = i915_gem_object_set_to_cpu_domain(obj, false); 29596951e589SChris Wilson i915_gem_object_unlock(obj); 2960be1da707SZhi Wang if (ret) { 2961695fbc08STina Zhang gvt_vgpu_err("failed to set shadow indirect ctx to CPU\n"); 2962be1da707SZhi Wang goto unmap_src; 2963be1da707SZhi Wang } 2964be1da707SZhi Wang 2965c10c1255STina Zhang ret = copy_gma_to_hva(workload->vgpu, 2966c10c1255STina Zhang workload->vgpu->gtt.ggtt_mm, 2967bcd0aedeSChris Wilson guest_gma, guest_gma + ctx_size, 2968bcd0aedeSChris Wilson map); 29698bcad07aSZhenyu Wang if (ret < 0) { 2970695fbc08STina Zhang gvt_vgpu_err("fail to copy guest indirect ctx\n"); 2971894cf7d1SChris Wilson goto unmap_src; 2972be1da707SZhi Wang } 2973be1da707SZhi Wang 2974894cf7d1SChris Wilson wa_ctx->indirect_ctx.obj = obj; 2975bcd0aedeSChris Wilson wa_ctx->indirect_ctx.shadow_va = map; 2976be1da707SZhi Wang return 0; 2977be1da707SZhi Wang 2978be1da707SZhi Wang unmap_src: 2979bcd0aedeSChris Wilson i915_gem_object_unpin_map(obj); 2980894cf7d1SChris Wilson put_obj: 2981ffeaf9aaSfred gao i915_gem_object_put(obj); 2982be1da707SZhi Wang return ret; 2983be1da707SZhi Wang } 2984be1da707SZhi Wang 2985be1da707SZhi Wang static int combine_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx) 2986be1da707SZhi Wang { 29872e679d48SJani Nikula u32 per_ctx_start[CACHELINE_DWORDS] = {0}; 2988be1da707SZhi Wang unsigned char *bb_start_sva; 2989be1da707SZhi Wang 29908f63fc2bSZhenyu Wang if (!wa_ctx->per_ctx.valid) 29918f63fc2bSZhenyu Wang return 0; 29928f63fc2bSZhenyu Wang 2993be1da707SZhi Wang per_ctx_start[0] = 0x18800001; 2994be1da707SZhi Wang per_ctx_start[1] = wa_ctx->per_ctx.guest_gma; 2995be1da707SZhi Wang 2996be1da707SZhi Wang bb_start_sva = (unsigned char *)wa_ctx->indirect_ctx.shadow_va + 2997be1da707SZhi Wang wa_ctx->indirect_ctx.size; 2998be1da707SZhi Wang 2999be1da707SZhi Wang memcpy(bb_start_sva, per_ctx_start, CACHELINE_BYTES); 3000be1da707SZhi Wang 3001be1da707SZhi Wang return 0; 3002be1da707SZhi Wang } 3003be1da707SZhi Wang 3004be1da707SZhi Wang int intel_gvt_scan_and_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx) 3005be1da707SZhi Wang { 3006be1da707SZhi Wang int ret; 3007c10c1255STina Zhang struct intel_vgpu_workload *workload = container_of(wa_ctx, 3008c10c1255STina Zhang struct intel_vgpu_workload, 3009c10c1255STina Zhang wa_ctx); 3010c10c1255STina Zhang struct intel_vgpu *vgpu = workload->vgpu; 3011be1da707SZhi Wang 3012be1da707SZhi Wang if (wa_ctx->indirect_ctx.size == 0) 3013be1da707SZhi Wang return 0; 3014be1da707SZhi Wang 3015be1da707SZhi Wang ret = shadow_indirect_ctx(wa_ctx); 3016be1da707SZhi Wang if (ret) { 3017695fbc08STina Zhang gvt_vgpu_err("fail to shadow indirect ctx\n"); 3018be1da707SZhi Wang return ret; 3019be1da707SZhi Wang } 3020be1da707SZhi Wang 3021be1da707SZhi Wang combine_wa_ctx(wa_ctx); 3022be1da707SZhi Wang 3023be1da707SZhi Wang ret = scan_wa_ctx(wa_ctx); 3024be1da707SZhi Wang if (ret) { 3025695fbc08STina Zhang gvt_vgpu_err("scan wa ctx error\n"); 3026be1da707SZhi Wang return ret; 3027be1da707SZhi Wang } 3028be1da707SZhi Wang 3029be1da707SZhi Wang return 0; 3030be1da707SZhi Wang } 3031be1da707SZhi Wang 3032b007065aSJani Nikula static const struct cmd_info *find_cmd_entry_any_ring(struct intel_gvt *gvt, 303365e74392SChangbin Du unsigned int opcode, unsigned long rings) 3034be1da707SZhi Wang { 3035b007065aSJani Nikula const struct cmd_info *info = NULL; 3036be1da707SZhi Wang unsigned int ring; 3037be1da707SZhi Wang 303865e74392SChangbin Du for_each_set_bit(ring, &rings, I915_NUM_ENGINES) { 3039be1da707SZhi Wang info = find_cmd_entry(gvt, opcode, ring); 3040be1da707SZhi Wang if (info) 3041be1da707SZhi Wang break; 3042be1da707SZhi Wang } 3043be1da707SZhi Wang return info; 3044be1da707SZhi Wang } 3045be1da707SZhi Wang 3046be1da707SZhi Wang static int init_cmd_table(struct intel_gvt *gvt) 3047be1da707SZhi Wang { 3048be1da707SZhi Wang int i; 3049be1da707SZhi Wang struct cmd_entry *e; 3050b007065aSJani Nikula const struct cmd_info *info; 3051be1da707SZhi Wang unsigned int gen_type; 3052be1da707SZhi Wang 3053be1da707SZhi Wang gen_type = intel_gvt_get_device_type(gvt); 3054be1da707SZhi Wang 3055be1da707SZhi Wang for (i = 0; i < ARRAY_SIZE(cmd_info); i++) { 3056be1da707SZhi Wang if (!(cmd_info[i].devices & gen_type)) 3057be1da707SZhi Wang continue; 3058be1da707SZhi Wang 3059be1da707SZhi Wang e = kzalloc(sizeof(*e), GFP_KERNEL); 3060be1da707SZhi Wang if (!e) 3061be1da707SZhi Wang return -ENOMEM; 3062be1da707SZhi Wang 3063be1da707SZhi Wang e->info = &cmd_info[i]; 3064be1da707SZhi Wang info = find_cmd_entry_any_ring(gvt, 3065be1da707SZhi Wang e->info->opcode, e->info->rings); 3066be1da707SZhi Wang if (info) { 3067be1da707SZhi Wang gvt_err("%s %s duplicated\n", e->info->name, 3068be1da707SZhi Wang info->name); 3069ffdf16edSColin Ian King kfree(e); 3070be1da707SZhi Wang return -EEXIST; 3071be1da707SZhi Wang } 3072db47685dSZhao Yan if (cmd_info[i].opcode == OP_MI_NOOP) 3073db47685dSZhao Yan mi_noop_index = i; 3074be1da707SZhi Wang 3075be1da707SZhi Wang INIT_HLIST_NODE(&e->hlist); 3076be1da707SZhi Wang add_cmd_entry(gvt, e); 3077be1da707SZhi Wang gvt_dbg_cmd("add %-30s op %04x flag %x devs %02x rings %02x\n", 3078be1da707SZhi Wang e->info->name, e->info->opcode, e->info->flag, 3079be1da707SZhi Wang e->info->devices, e->info->rings); 3080be1da707SZhi Wang } 3081be1da707SZhi Wang return 0; 3082be1da707SZhi Wang } 3083be1da707SZhi Wang 3084be1da707SZhi Wang static void clean_cmd_table(struct intel_gvt *gvt) 3085be1da707SZhi Wang { 3086be1da707SZhi Wang struct hlist_node *tmp; 3087be1da707SZhi Wang struct cmd_entry *e; 3088be1da707SZhi Wang int i; 3089be1da707SZhi Wang 3090be1da707SZhi Wang hash_for_each_safe(gvt->cmd_table, i, tmp, e, hlist) 3091be1da707SZhi Wang kfree(e); 3092be1da707SZhi Wang 3093be1da707SZhi Wang hash_init(gvt->cmd_table); 3094be1da707SZhi Wang } 3095be1da707SZhi Wang 3096be1da707SZhi Wang void intel_gvt_clean_cmd_parser(struct intel_gvt *gvt) 3097be1da707SZhi Wang { 3098be1da707SZhi Wang clean_cmd_table(gvt); 3099be1da707SZhi Wang } 3100be1da707SZhi Wang 3101be1da707SZhi Wang int intel_gvt_init_cmd_parser(struct intel_gvt *gvt) 3102be1da707SZhi Wang { 3103be1da707SZhi Wang int ret; 3104be1da707SZhi Wang 3105be1da707SZhi Wang ret = init_cmd_table(gvt); 3106be1da707SZhi Wang if (ret) { 3107be1da707SZhi Wang intel_gvt_clean_cmd_parser(gvt); 3108be1da707SZhi Wang return ret; 3109be1da707SZhi Wang } 3110be1da707SZhi Wang return 0; 3111be1da707SZhi Wang } 3112