1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Eddie Dong <eddie.dong@intel.com> 25 * Jike Song <jike.song@intel.com> 26 * 27 * Contributors: 28 * Zhi Wang <zhi.a.wang@intel.com> 29 * Min He <min.he@intel.com> 30 * Bing Niu <bing.niu@intel.com> 31 * 32 */ 33 34 #include "i915_drv.h" 35 #include "gvt.h" 36 37 enum { 38 INTEL_GVT_PCI_BAR_GTTMMIO = 0, 39 INTEL_GVT_PCI_BAR_APERTURE, 40 INTEL_GVT_PCI_BAR_PIO, 41 INTEL_GVT_PCI_BAR_MAX, 42 }; 43 44 /* bitmap for writable bits (RW or RW1C bits, but cannot co-exist in one 45 * byte) byte by byte in standard pci configuration space. (not the full 46 * 256 bytes.) 47 */ 48 static const u8 pci_cfg_space_rw_bmp[PCI_INTERRUPT_LINE + 4] = { 49 [PCI_COMMAND] = 0xff, 0x07, 50 [PCI_STATUS] = 0x00, 0xf9, /* the only one RW1C byte */ 51 [PCI_CACHE_LINE_SIZE] = 0xff, 52 [PCI_BASE_ADDRESS_0 ... PCI_CARDBUS_CIS - 1] = 0xff, 53 [PCI_ROM_ADDRESS] = 0x01, 0xf8, 0xff, 0xff, 54 [PCI_INTERRUPT_LINE] = 0xff, 55 }; 56 57 /** 58 * vgpu_pci_cfg_mem_write - write virtual cfg space memory 59 * 60 * Use this function to write virtual cfg space memory. 61 * For standard cfg space, only RW bits can be changed, 62 * and we emulates the RW1C behavior of PCI_STATUS register. 63 */ 64 static void vgpu_pci_cfg_mem_write(struct intel_vgpu *vgpu, unsigned int off, 65 u8 *src, unsigned int bytes) 66 { 67 u8 *cfg_base = vgpu_cfg_space(vgpu); 68 u8 mask, new, old; 69 int i = 0; 70 71 for (; i < bytes && (off + i < sizeof(pci_cfg_space_rw_bmp)); i++) { 72 mask = pci_cfg_space_rw_bmp[off + i]; 73 old = cfg_base[off + i]; 74 new = src[i] & mask; 75 76 /** 77 * The PCI_STATUS high byte has RW1C bits, here 78 * emulates clear by writing 1 for these bits. 79 * Writing a 0b to RW1C bits has no effect. 80 */ 81 if (off + i == PCI_STATUS + 1) 82 new = (~new & old) & mask; 83 84 cfg_base[off + i] = (old & ~mask) | new; 85 } 86 87 /* For other configuration space directly copy as it is. */ 88 if (i < bytes) 89 memcpy(cfg_base + off + i, src + i, bytes - i); 90 } 91 92 /** 93 * intel_vgpu_emulate_cfg_read - emulate vGPU configuration space read 94 * 95 * Returns: 96 * Zero on success, negative error code if failed. 97 */ 98 int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset, 99 void *p_data, unsigned int bytes) 100 { 101 if (WARN_ON(bytes > 4)) 102 return -EINVAL; 103 104 if (WARN_ON(offset + bytes > vgpu->gvt->device_info.cfg_space_size)) 105 return -EINVAL; 106 107 memcpy(p_data, vgpu_cfg_space(vgpu) + offset, bytes); 108 return 0; 109 } 110 111 static int map_aperture(struct intel_vgpu *vgpu, bool map) 112 { 113 phys_addr_t aperture_pa = vgpu_aperture_pa_base(vgpu); 114 unsigned long aperture_sz = vgpu_aperture_sz(vgpu); 115 u64 first_gfn; 116 u64 val; 117 int ret; 118 119 if (map == vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].tracked) 120 return 0; 121 122 if (map) { 123 vgpu->gm.aperture_va = memremap(aperture_pa, aperture_sz, 124 MEMREMAP_WC); 125 if (!vgpu->gm.aperture_va) 126 return -ENOMEM; 127 } else { 128 memunmap(vgpu->gm.aperture_va); 129 vgpu->gm.aperture_va = NULL; 130 } 131 132 val = vgpu_cfg_space(vgpu)[PCI_BASE_ADDRESS_2]; 133 if (val & PCI_BASE_ADDRESS_MEM_TYPE_64) 134 val = *(u64 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_2); 135 else 136 val = *(u32 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_2); 137 138 first_gfn = (val + vgpu_aperture_offset(vgpu)) >> PAGE_SHIFT; 139 140 ret = intel_gvt_hypervisor_map_gfn_to_mfn(vgpu, first_gfn, 141 aperture_pa >> PAGE_SHIFT, 142 aperture_sz >> PAGE_SHIFT, 143 map); 144 if (ret) { 145 memunmap(vgpu->gm.aperture_va); 146 vgpu->gm.aperture_va = NULL; 147 return ret; 148 } 149 150 vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].tracked = map; 151 return 0; 152 } 153 154 static int trap_gttmmio(struct intel_vgpu *vgpu, bool trap) 155 { 156 u64 start, end; 157 u64 val; 158 int ret; 159 160 if (trap == vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].tracked) 161 return 0; 162 163 val = vgpu_cfg_space(vgpu)[PCI_BASE_ADDRESS_0]; 164 if (val & PCI_BASE_ADDRESS_MEM_TYPE_64) 165 start = *(u64 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_0); 166 else 167 start = *(u32 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_0); 168 169 start &= ~GENMASK(3, 0); 170 end = start + vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].size - 1; 171 172 ret = intel_gvt_hypervisor_set_trap_area(vgpu, start, end, trap); 173 if (ret) 174 return ret; 175 176 vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].tracked = trap; 177 return 0; 178 } 179 180 static int emulate_pci_command_write(struct intel_vgpu *vgpu, 181 unsigned int offset, void *p_data, unsigned int bytes) 182 { 183 u8 old = vgpu_cfg_space(vgpu)[offset]; 184 u8 new = *(u8 *)p_data; 185 u8 changed = old ^ new; 186 int ret; 187 188 vgpu_pci_cfg_mem_write(vgpu, offset, p_data, bytes); 189 if (!(changed & PCI_COMMAND_MEMORY)) 190 return 0; 191 192 if (old & PCI_COMMAND_MEMORY) { 193 ret = trap_gttmmio(vgpu, false); 194 if (ret) 195 return ret; 196 ret = map_aperture(vgpu, false); 197 if (ret) 198 return ret; 199 } else { 200 ret = trap_gttmmio(vgpu, true); 201 if (ret) 202 return ret; 203 ret = map_aperture(vgpu, true); 204 if (ret) 205 return ret; 206 } 207 208 return 0; 209 } 210 211 static int emulate_pci_bar_write(struct intel_vgpu *vgpu, unsigned int offset, 212 void *p_data, unsigned int bytes) 213 { 214 u32 new = *(u32 *)(p_data); 215 bool lo = IS_ALIGNED(offset, 8); 216 u64 size; 217 int ret = 0; 218 bool mmio_enabled = 219 vgpu_cfg_space(vgpu)[PCI_COMMAND] & PCI_COMMAND_MEMORY; 220 struct intel_vgpu_pci_bar *bars = vgpu->cfg_space.bar; 221 222 /* 223 * Power-up software can determine how much address 224 * space the device requires by writing a value of 225 * all 1's to the register and then reading the value 226 * back. The device will return 0's in all don't-care 227 * address bits. 228 */ 229 if (new == 0xffffffff) { 230 switch (offset) { 231 case PCI_BASE_ADDRESS_0: 232 case PCI_BASE_ADDRESS_1: 233 size = ~(bars[INTEL_GVT_PCI_BAR_GTTMMIO].size -1); 234 intel_vgpu_write_pci_bar(vgpu, offset, 235 size >> (lo ? 0 : 32), lo); 236 /* 237 * Untrap the BAR, since guest hasn't configured a 238 * valid GPA 239 */ 240 ret = trap_gttmmio(vgpu, false); 241 break; 242 case PCI_BASE_ADDRESS_2: 243 case PCI_BASE_ADDRESS_3: 244 size = ~(bars[INTEL_GVT_PCI_BAR_APERTURE].size -1); 245 intel_vgpu_write_pci_bar(vgpu, offset, 246 size >> (lo ? 0 : 32), lo); 247 ret = map_aperture(vgpu, false); 248 break; 249 default: 250 /* Unimplemented BARs */ 251 intel_vgpu_write_pci_bar(vgpu, offset, 0x0, false); 252 } 253 } else { 254 switch (offset) { 255 case PCI_BASE_ADDRESS_0: 256 case PCI_BASE_ADDRESS_1: 257 /* 258 * Untrap the old BAR first, since guest has 259 * re-configured the BAR 260 */ 261 trap_gttmmio(vgpu, false); 262 intel_vgpu_write_pci_bar(vgpu, offset, new, lo); 263 ret = trap_gttmmio(vgpu, mmio_enabled); 264 break; 265 case PCI_BASE_ADDRESS_2: 266 case PCI_BASE_ADDRESS_3: 267 map_aperture(vgpu, false); 268 intel_vgpu_write_pci_bar(vgpu, offset, new, lo); 269 ret = map_aperture(vgpu, mmio_enabled); 270 break; 271 default: 272 intel_vgpu_write_pci_bar(vgpu, offset, new, lo); 273 } 274 } 275 return ret; 276 } 277 278 /** 279 * intel_vgpu_emulate_cfg_read - emulate vGPU configuration space write 280 * 281 * Returns: 282 * Zero on success, negative error code if failed. 283 */ 284 int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset, 285 void *p_data, unsigned int bytes) 286 { 287 int ret; 288 289 if (WARN_ON(bytes > 4)) 290 return -EINVAL; 291 292 if (WARN_ON(offset + bytes > vgpu->gvt->device_info.cfg_space_size)) 293 return -EINVAL; 294 295 /* First check if it's PCI_COMMAND */ 296 if (IS_ALIGNED(offset, 2) && offset == PCI_COMMAND) { 297 if (WARN_ON(bytes > 2)) 298 return -EINVAL; 299 return emulate_pci_command_write(vgpu, offset, p_data, bytes); 300 } 301 302 switch (rounddown(offset, 4)) { 303 case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_5: 304 if (WARN_ON(!IS_ALIGNED(offset, 4))) 305 return -EINVAL; 306 return emulate_pci_bar_write(vgpu, offset, p_data, bytes); 307 308 case INTEL_GVT_PCI_SWSCI: 309 if (WARN_ON(!IS_ALIGNED(offset, 4))) 310 return -EINVAL; 311 ret = intel_vgpu_emulate_opregion_request(vgpu, *(u32 *)p_data); 312 if (ret) 313 return ret; 314 break; 315 316 case INTEL_GVT_PCI_OPREGION: 317 if (WARN_ON(!IS_ALIGNED(offset, 4))) 318 return -EINVAL; 319 ret = intel_vgpu_init_opregion(vgpu, *(u32 *)p_data); 320 if (ret) 321 return ret; 322 323 vgpu_pci_cfg_mem_write(vgpu, offset, p_data, bytes); 324 break; 325 default: 326 vgpu_pci_cfg_mem_write(vgpu, offset, p_data, bytes); 327 break; 328 } 329 return 0; 330 } 331 332 /** 333 * intel_vgpu_init_cfg_space - init vGPU configuration space when create vGPU 334 * 335 * @vgpu: a vGPU 336 * @primary: is the vGPU presented as primary 337 * 338 */ 339 void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu, 340 bool primary) 341 { 342 struct intel_gvt *gvt = vgpu->gvt; 343 const struct intel_gvt_device_info *info = &gvt->device_info; 344 u16 *gmch_ctl; 345 346 memcpy(vgpu_cfg_space(vgpu), gvt->firmware.cfg_space, 347 info->cfg_space_size); 348 349 if (!primary) { 350 vgpu_cfg_space(vgpu)[PCI_CLASS_DEVICE] = 351 INTEL_GVT_PCI_CLASS_VGA_OTHER; 352 vgpu_cfg_space(vgpu)[PCI_CLASS_PROG] = 353 INTEL_GVT_PCI_CLASS_VGA_OTHER; 354 } 355 356 /* Show guest that there isn't any stolen memory.*/ 357 gmch_ctl = (u16 *)(vgpu_cfg_space(vgpu) + INTEL_GVT_PCI_GMCH_CONTROL); 358 *gmch_ctl &= ~(BDW_GMCH_GMS_MASK << BDW_GMCH_GMS_SHIFT); 359 360 intel_vgpu_write_pci_bar(vgpu, PCI_BASE_ADDRESS_2, 361 gvt_aperture_pa_base(gvt), true); 362 363 vgpu_cfg_space(vgpu)[PCI_COMMAND] &= ~(PCI_COMMAND_IO 364 | PCI_COMMAND_MEMORY 365 | PCI_COMMAND_MASTER); 366 /* 367 * Clear the bar upper 32bit and let guest to assign the new value 368 */ 369 memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_1, 0, 4); 370 memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_3, 0, 4); 371 memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_4, 0, 8); 372 memset(vgpu_cfg_space(vgpu) + INTEL_GVT_PCI_OPREGION, 0, 4); 373 374 vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].size = 375 pci_resource_len(gvt->dev_priv->drm.pdev, 0); 376 vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].size = 377 pci_resource_len(gvt->dev_priv->drm.pdev, 2); 378 } 379 380 /** 381 * intel_vgpu_reset_cfg_space - reset vGPU configuration space 382 * 383 * @vgpu: a vGPU 384 * 385 */ 386 void intel_vgpu_reset_cfg_space(struct intel_vgpu *vgpu) 387 { 388 u8 cmd = vgpu_cfg_space(vgpu)[PCI_COMMAND]; 389 bool primary = vgpu_cfg_space(vgpu)[PCI_CLASS_DEVICE] != 390 INTEL_GVT_PCI_CLASS_VGA_OTHER; 391 392 if (cmd & PCI_COMMAND_MEMORY) { 393 trap_gttmmio(vgpu, false); 394 map_aperture(vgpu, false); 395 } 396 397 /** 398 * Currently we only do such reset when vGPU is not 399 * owned by any VM, so we simply restore entire cfg 400 * space to default value. 401 */ 402 intel_vgpu_init_cfg_space(vgpu, primary); 403 } 404