14d60c5fdSZhi Wang /* 24d60c5fdSZhi Wang * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 34d60c5fdSZhi Wang * 44d60c5fdSZhi Wang * Permission is hereby granted, free of charge, to any person obtaining a 54d60c5fdSZhi Wang * copy of this software and associated documentation files (the "Software"), 64d60c5fdSZhi Wang * to deal in the Software without restriction, including without limitation 74d60c5fdSZhi Wang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 84d60c5fdSZhi Wang * and/or sell copies of the Software, and to permit persons to whom the 94d60c5fdSZhi Wang * Software is furnished to do so, subject to the following conditions: 104d60c5fdSZhi Wang * 114d60c5fdSZhi Wang * The above copyright notice and this permission notice (including the next 124d60c5fdSZhi Wang * paragraph) shall be included in all copies or substantial portions of the 134d60c5fdSZhi Wang * Software. 144d60c5fdSZhi Wang * 154d60c5fdSZhi Wang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 164d60c5fdSZhi Wang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 174d60c5fdSZhi Wang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 184d60c5fdSZhi Wang * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 194d60c5fdSZhi Wang * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 204d60c5fdSZhi Wang * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 214d60c5fdSZhi Wang * SOFTWARE. 224d60c5fdSZhi Wang * 234d60c5fdSZhi Wang * Authors: 244d60c5fdSZhi Wang * Eddie Dong <eddie.dong@intel.com> 254d60c5fdSZhi Wang * Jike Song <jike.song@intel.com> 264d60c5fdSZhi Wang * 274d60c5fdSZhi Wang * Contributors: 284d60c5fdSZhi Wang * Zhi Wang <zhi.a.wang@intel.com> 294d60c5fdSZhi Wang * Min He <min.he@intel.com> 304d60c5fdSZhi Wang * Bing Niu <bing.niu@intel.com> 314d60c5fdSZhi Wang * 324d60c5fdSZhi Wang */ 334d60c5fdSZhi Wang 344d60c5fdSZhi Wang #include "i915_drv.h" 35feddf6e8SZhenyu Wang #include "gvt.h" 364d60c5fdSZhi Wang 374d60c5fdSZhi Wang enum { 384d60c5fdSZhi Wang INTEL_GVT_PCI_BAR_GTTMMIO = 0, 394d60c5fdSZhi Wang INTEL_GVT_PCI_BAR_APERTURE, 404d60c5fdSZhi Wang INTEL_GVT_PCI_BAR_PIO, 414d60c5fdSZhi Wang INTEL_GVT_PCI_BAR_MAX, 424d60c5fdSZhi Wang }; 434d60c5fdSZhi Wang 44c2e04fdaSChangbin Du /* bitmap for writable bits (RW or RW1C bits, but cannot co-exist in one 45c2e04fdaSChangbin Du * byte) byte by byte in standard pci configuration space. (not the full 46c2e04fdaSChangbin Du * 256 bytes.) 47c2e04fdaSChangbin Du */ 48c2e04fdaSChangbin Du static const u8 pci_cfg_space_rw_bmp[PCI_INTERRUPT_LINE + 4] = { 49c2e04fdaSChangbin Du [PCI_COMMAND] = 0xff, 0x07, 50c2e04fdaSChangbin Du [PCI_STATUS] = 0x00, 0xf9, /* the only one RW1C byte */ 51c2e04fdaSChangbin Du [PCI_CACHE_LINE_SIZE] = 0xff, 52c2e04fdaSChangbin Du [PCI_BASE_ADDRESS_0 ... PCI_CARDBUS_CIS - 1] = 0xff, 53c2e04fdaSChangbin Du [PCI_ROM_ADDRESS] = 0x01, 0xf8, 0xff, 0xff, 54c2e04fdaSChangbin Du [PCI_INTERRUPT_LINE] = 0xff, 55c2e04fdaSChangbin Du }; 56c2e04fdaSChangbin Du 57c2e04fdaSChangbin Du /** 58c2e04fdaSChangbin Du * vgpu_pci_cfg_mem_write - write virtual cfg space memory 59a752b070SZhenyu Wang * @vgpu: target vgpu 60a752b070SZhenyu Wang * @off: offset 61a752b070SZhenyu Wang * @src: src ptr to write 62a752b070SZhenyu Wang * @bytes: number of bytes 63c2e04fdaSChangbin Du * 64c2e04fdaSChangbin Du * Use this function to write virtual cfg space memory. 65c2e04fdaSChangbin Du * For standard cfg space, only RW bits can be changed, 66c2e04fdaSChangbin Du * and we emulates the RW1C behavior of PCI_STATUS register. 67c2e04fdaSChangbin Du */ 68c2e04fdaSChangbin Du static void vgpu_pci_cfg_mem_write(struct intel_vgpu *vgpu, unsigned int off, 69c2e04fdaSChangbin Du u8 *src, unsigned int bytes) 70c2e04fdaSChangbin Du { 71c2e04fdaSChangbin Du u8 *cfg_base = vgpu_cfg_space(vgpu); 72c2e04fdaSChangbin Du u8 mask, new, old; 73ba25d977SColin Xu pci_power_t pwr; 74c2e04fdaSChangbin Du int i = 0; 75c2e04fdaSChangbin Du 76c2e04fdaSChangbin Du for (; i < bytes && (off + i < sizeof(pci_cfg_space_rw_bmp)); i++) { 77c2e04fdaSChangbin Du mask = pci_cfg_space_rw_bmp[off + i]; 78c2e04fdaSChangbin Du old = cfg_base[off + i]; 79c2e04fdaSChangbin Du new = src[i] & mask; 80c2e04fdaSChangbin Du 81c2e04fdaSChangbin Du /** 82c2e04fdaSChangbin Du * The PCI_STATUS high byte has RW1C bits, here 83c2e04fdaSChangbin Du * emulates clear by writing 1 for these bits. 84c2e04fdaSChangbin Du * Writing a 0b to RW1C bits has no effect. 85c2e04fdaSChangbin Du */ 86c2e04fdaSChangbin Du if (off + i == PCI_STATUS + 1) 87c2e04fdaSChangbin Du new = (~new & old) & mask; 88c2e04fdaSChangbin Du 89c2e04fdaSChangbin Du cfg_base[off + i] = (old & ~mask) | new; 90c2e04fdaSChangbin Du } 91c2e04fdaSChangbin Du 92c2e04fdaSChangbin Du /* For other configuration space directly copy as it is. */ 93c2e04fdaSChangbin Du if (i < bytes) 94c2e04fdaSChangbin Du memcpy(cfg_base + off + i, src + i, bytes - i); 95ba25d977SColin Xu 96ba25d977SColin Xu if (off == vgpu->cfg_space.pmcsr_off && vgpu->cfg_space.pmcsr_off) { 97ba25d977SColin Xu pwr = (pci_power_t __force)(*(u16*)(&vgpu_cfg_space(vgpu)[off]) 98ba25d977SColin Xu & PCI_PM_CTRL_STATE_MASK); 99ba25d977SColin Xu if (pwr == PCI_D3hot) 100ba25d977SColin Xu vgpu->d3_entered = true; 101ba25d977SColin Xu gvt_dbg_core("vgpu-%d power status changed to %d\n", 102ba25d977SColin Xu vgpu->id, pwr); 103ba25d977SColin Xu } 104c2e04fdaSChangbin Du } 105c2e04fdaSChangbin Du 1064d60c5fdSZhi Wang /** 1074d60c5fdSZhi Wang * intel_vgpu_emulate_cfg_read - emulate vGPU configuration space read 108a752b070SZhenyu Wang * @vgpu: target vgpu 109a752b070SZhenyu Wang * @offset: offset 110a752b070SZhenyu Wang * @p_data: return data ptr 111a752b070SZhenyu Wang * @bytes: number of bytes to read 1124d60c5fdSZhi Wang * 1134d60c5fdSZhi Wang * Returns: 1144d60c5fdSZhi Wang * Zero on success, negative error code if failed. 1154d60c5fdSZhi Wang */ 1169ec1e66bSJike Song int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset, 1174d60c5fdSZhi Wang void *p_data, unsigned int bytes) 1184d60c5fdSZhi Wang { 119a61ac1e7SChris Wilson struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 12012d58619SPankaj Bharadiya 12112d58619SPankaj Bharadiya if (drm_WARN_ON(&i915->drm, bytes > 4)) 1224d60c5fdSZhi Wang return -EINVAL; 1234d60c5fdSZhi Wang 12412d58619SPankaj Bharadiya if (drm_WARN_ON(&i915->drm, 12512d58619SPankaj Bharadiya offset + bytes > vgpu->gvt->device_info.cfg_space_size)) 1264d60c5fdSZhi Wang return -EINVAL; 1274d60c5fdSZhi Wang 1284d60c5fdSZhi Wang memcpy(p_data, vgpu_cfg_space(vgpu) + offset, bytes); 1294d60c5fdSZhi Wang return 0; 1304d60c5fdSZhi Wang } 1314d60c5fdSZhi Wang 132*c977092aSChristoph Hellwig static void map_aperture(struct intel_vgpu *vgpu, bool map) 1334d60c5fdSZhi Wang { 134*c977092aSChristoph Hellwig if (map != vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].tracked) 1354d60c5fdSZhi Wang vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].tracked = map; 1364d60c5fdSZhi Wang } 1374d60c5fdSZhi Wang 138*c977092aSChristoph Hellwig static void trap_gttmmio(struct intel_vgpu *vgpu, bool trap) 1394d60c5fdSZhi Wang { 140*c977092aSChristoph Hellwig if (trap != vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].tracked) 1414d60c5fdSZhi Wang vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].tracked = trap; 1424d60c5fdSZhi Wang } 1434d60c5fdSZhi Wang 1444d60c5fdSZhi Wang static int emulate_pci_command_write(struct intel_vgpu *vgpu, 1454d60c5fdSZhi Wang unsigned int offset, void *p_data, unsigned int bytes) 1464d60c5fdSZhi Wang { 1474d60c5fdSZhi Wang u8 old = vgpu_cfg_space(vgpu)[offset]; 1484d60c5fdSZhi Wang u8 new = *(u8 *)p_data; 1494d60c5fdSZhi Wang u8 changed = old ^ new; 1504d60c5fdSZhi Wang 151c2e04fdaSChangbin Du vgpu_pci_cfg_mem_write(vgpu, offset, p_data, bytes); 1524d60c5fdSZhi Wang if (!(changed & PCI_COMMAND_MEMORY)) 1534d60c5fdSZhi Wang return 0; 1544d60c5fdSZhi Wang 1554d60c5fdSZhi Wang if (old & PCI_COMMAND_MEMORY) { 156*c977092aSChristoph Hellwig trap_gttmmio(vgpu, false); 157*c977092aSChristoph Hellwig map_aperture(vgpu, false); 1584d60c5fdSZhi Wang } else { 159*c977092aSChristoph Hellwig trap_gttmmio(vgpu, true); 160*c977092aSChristoph Hellwig map_aperture(vgpu, true); 1614d60c5fdSZhi Wang } 1624d60c5fdSZhi Wang 1634d60c5fdSZhi Wang return 0; 1644d60c5fdSZhi Wang } 1654d60c5fdSZhi Wang 166c4270d12SChangbin Du static int emulate_pci_rom_bar_write(struct intel_vgpu *vgpu, 167c4270d12SChangbin Du unsigned int offset, void *p_data, unsigned int bytes) 168c4270d12SChangbin Du { 169c4270d12SChangbin Du u32 *pval = (u32 *)(vgpu_cfg_space(vgpu) + offset); 170c4270d12SChangbin Du u32 new = *(u32 *)(p_data); 171c4270d12SChangbin Du 172c4270d12SChangbin Du if ((new & PCI_ROM_ADDRESS_MASK) == PCI_ROM_ADDRESS_MASK) 173c4270d12SChangbin Du /* We don't have rom, return size of 0. */ 174c4270d12SChangbin Du *pval = 0; 175c4270d12SChangbin Du else 176c4270d12SChangbin Du vgpu_pci_cfg_mem_write(vgpu, offset, p_data, bytes); 177c4270d12SChangbin Du return 0; 178c4270d12SChangbin Du } 179c4270d12SChangbin Du 180*c977092aSChristoph Hellwig static void emulate_pci_bar_write(struct intel_vgpu *vgpu, unsigned int offset, 1814d60c5fdSZhi Wang void *p_data, unsigned int bytes) 1824d60c5fdSZhi Wang { 1834d60c5fdSZhi Wang u32 new = *(u32 *)(p_data); 1844d60c5fdSZhi Wang bool lo = IS_ALIGNED(offset, 8); 1854d60c5fdSZhi Wang u64 size; 1864d60c5fdSZhi Wang bool mmio_enabled = 1874d60c5fdSZhi Wang vgpu_cfg_space(vgpu)[PCI_COMMAND] & PCI_COMMAND_MEMORY; 188f1751362SChangbin Du struct intel_vgpu_pci_bar *bars = vgpu->cfg_space.bar; 1894d60c5fdSZhi Wang 1904d60c5fdSZhi Wang /* 1914d60c5fdSZhi Wang * Power-up software can determine how much address 1924d60c5fdSZhi Wang * space the device requires by writing a value of 1934d60c5fdSZhi Wang * all 1's to the register and then reading the value 1944d60c5fdSZhi Wang * back. The device will return 0's in all don't-care 1954d60c5fdSZhi Wang * address bits. 1964d60c5fdSZhi Wang */ 197f1751362SChangbin Du if (new == 0xffffffff) { 198f1751362SChangbin Du switch (offset) { 199f1751362SChangbin Du case PCI_BASE_ADDRESS_0: 200f1751362SChangbin Du case PCI_BASE_ADDRESS_1: 201f1751362SChangbin Du size = ~(bars[INTEL_GVT_PCI_BAR_GTTMMIO].size -1); 202f1751362SChangbin Du intel_vgpu_write_pci_bar(vgpu, offset, 203f1751362SChangbin Du size >> (lo ? 0 : 32), lo); 2044d60c5fdSZhi Wang /* 205f1751362SChangbin Du * Untrap the BAR, since guest hasn't configured a 2064d60c5fdSZhi Wang * valid GPA 2074d60c5fdSZhi Wang */ 208*c977092aSChristoph Hellwig trap_gttmmio(vgpu, false); 2094d60c5fdSZhi Wang break; 210f1751362SChangbin Du case PCI_BASE_ADDRESS_2: 211f1751362SChangbin Du case PCI_BASE_ADDRESS_3: 212f1751362SChangbin Du size = ~(bars[INTEL_GVT_PCI_BAR_APERTURE].size -1); 213f1751362SChangbin Du intel_vgpu_write_pci_bar(vgpu, offset, 214f1751362SChangbin Du size >> (lo ? 0 : 32), lo); 215*c977092aSChristoph Hellwig map_aperture(vgpu, false); 2164d60c5fdSZhi Wang break; 217f1751362SChangbin Du default: 218f1751362SChangbin Du /* Unimplemented BARs */ 219f1751362SChangbin Du intel_vgpu_write_pci_bar(vgpu, offset, 0x0, false); 2204d60c5fdSZhi Wang } 2214d60c5fdSZhi Wang } else { 222f1751362SChangbin Du switch (offset) { 223f1751362SChangbin Du case PCI_BASE_ADDRESS_0: 224f1751362SChangbin Du case PCI_BASE_ADDRESS_1: 2254d60c5fdSZhi Wang /* 226f1751362SChangbin Du * Untrap the old BAR first, since guest has 2274d60c5fdSZhi Wang * re-configured the BAR 2284d60c5fdSZhi Wang */ 229f1751362SChangbin Du trap_gttmmio(vgpu, false); 2304d60c5fdSZhi Wang intel_vgpu_write_pci_bar(vgpu, offset, new, lo); 231*c977092aSChristoph Hellwig trap_gttmmio(vgpu, mmio_enabled); 2324d60c5fdSZhi Wang break; 233f1751362SChangbin Du case PCI_BASE_ADDRESS_2: 234f1751362SChangbin Du case PCI_BASE_ADDRESS_3: 235f1751362SChangbin Du map_aperture(vgpu, false); 236f1751362SChangbin Du intel_vgpu_write_pci_bar(vgpu, offset, new, lo); 237*c977092aSChristoph Hellwig map_aperture(vgpu, mmio_enabled); 2384d60c5fdSZhi Wang break; 239f1751362SChangbin Du default: 240f1751362SChangbin Du intel_vgpu_write_pci_bar(vgpu, offset, new, lo); 2414d60c5fdSZhi Wang } 2424d60c5fdSZhi Wang } 2434d60c5fdSZhi Wang } 2444d60c5fdSZhi Wang 2454d60c5fdSZhi Wang /** 2464d60c5fdSZhi Wang * intel_vgpu_emulate_cfg_read - emulate vGPU configuration space write 247a752b070SZhenyu Wang * @vgpu: target vgpu 248a752b070SZhenyu Wang * @offset: offset 249a752b070SZhenyu Wang * @p_data: write data ptr 250a752b070SZhenyu Wang * @bytes: number of bytes to write 2514d60c5fdSZhi Wang * 2524d60c5fdSZhi Wang * Returns: 2534d60c5fdSZhi Wang * Zero on success, negative error code if failed. 2544d60c5fdSZhi Wang */ 2559ec1e66bSJike Song int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset, 2564d60c5fdSZhi Wang void *p_data, unsigned int bytes) 2574d60c5fdSZhi Wang { 258a61ac1e7SChris Wilson struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 2594d60c5fdSZhi Wang int ret; 2604d60c5fdSZhi Wang 26112d58619SPankaj Bharadiya if (drm_WARN_ON(&i915->drm, bytes > 4)) 2624d60c5fdSZhi Wang return -EINVAL; 2634d60c5fdSZhi Wang 26412d58619SPankaj Bharadiya if (drm_WARN_ON(&i915->drm, 26512d58619SPankaj Bharadiya offset + bytes > vgpu->gvt->device_info.cfg_space_size)) 2664d60c5fdSZhi Wang return -EINVAL; 2674d60c5fdSZhi Wang 2684d60c5fdSZhi Wang /* First check if it's PCI_COMMAND */ 2694d60c5fdSZhi Wang if (IS_ALIGNED(offset, 2) && offset == PCI_COMMAND) { 27012d58619SPankaj Bharadiya if (drm_WARN_ON(&i915->drm, bytes > 2)) 2714d60c5fdSZhi Wang return -EINVAL; 2724d60c5fdSZhi Wang return emulate_pci_command_write(vgpu, offset, p_data, bytes); 2734d60c5fdSZhi Wang } 2744d60c5fdSZhi Wang 2754d60c5fdSZhi Wang switch (rounddown(offset, 4)) { 276c4270d12SChangbin Du case PCI_ROM_ADDRESS: 27712d58619SPankaj Bharadiya if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4))) 278c4270d12SChangbin Du return -EINVAL; 279c4270d12SChangbin Du return emulate_pci_rom_bar_write(vgpu, offset, p_data, bytes); 280c4270d12SChangbin Du 281f1751362SChangbin Du case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_5: 28212d58619SPankaj Bharadiya if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4))) 2834d60c5fdSZhi Wang return -EINVAL; 284*c977092aSChristoph Hellwig emulate_pci_bar_write(vgpu, offset, p_data, bytes); 285*c977092aSChristoph Hellwig break; 2864d60c5fdSZhi Wang case INTEL_GVT_PCI_SWSCI: 28712d58619SPankaj Bharadiya if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4))) 2884d60c5fdSZhi Wang return -EINVAL; 2894d60c5fdSZhi Wang ret = intel_vgpu_emulate_opregion_request(vgpu, *(u32 *)p_data); 2904d60c5fdSZhi Wang if (ret) 2914d60c5fdSZhi Wang return ret; 2924d60c5fdSZhi Wang break; 2934d60c5fdSZhi Wang 2944d60c5fdSZhi Wang case INTEL_GVT_PCI_OPREGION: 29512d58619SPankaj Bharadiya if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4))) 2964d60c5fdSZhi Wang return -EINVAL; 2974dff110bSXiong Zhang ret = intel_vgpu_opregion_base_write_handler(vgpu, 2984dff110bSXiong Zhang *(u32 *)p_data); 2994d60c5fdSZhi Wang if (ret) 3004d60c5fdSZhi Wang return ret; 3014d60c5fdSZhi Wang 302c2e04fdaSChangbin Du vgpu_pci_cfg_mem_write(vgpu, offset, p_data, bytes); 3034d60c5fdSZhi Wang break; 3044d60c5fdSZhi Wang default: 305c2e04fdaSChangbin Du vgpu_pci_cfg_mem_write(vgpu, offset, p_data, bytes); 3064d60c5fdSZhi Wang break; 3074d60c5fdSZhi Wang } 3084d60c5fdSZhi Wang return 0; 3094d60c5fdSZhi Wang } 310536fc234SChangbin Du 311536fc234SChangbin Du /** 312536fc234SChangbin Du * intel_vgpu_init_cfg_space - init vGPU configuration space when create vGPU 313536fc234SChangbin Du * 314536fc234SChangbin Du * @vgpu: a vGPU 315536fc234SChangbin Du * @primary: is the vGPU presented as primary 316536fc234SChangbin Du * 317536fc234SChangbin Du */ 318536fc234SChangbin Du void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu, 319536fc234SChangbin Du bool primary) 320536fc234SChangbin Du { 321536fc234SChangbin Du struct intel_gvt *gvt = vgpu->gvt; 3229ff06c38SThomas Zimmermann struct pci_dev *pdev = to_pci_dev(gvt->gt->i915->drm.dev); 323536fc234SChangbin Du const struct intel_gvt_device_info *info = &gvt->device_info; 324536fc234SChangbin Du u16 *gmch_ctl; 325ba25d977SColin Xu u8 next; 326536fc234SChangbin Du 327536fc234SChangbin Du memcpy(vgpu_cfg_space(vgpu), gvt->firmware.cfg_space, 328536fc234SChangbin Du info->cfg_space_size); 329536fc234SChangbin Du 330536fc234SChangbin Du if (!primary) { 331536fc234SChangbin Du vgpu_cfg_space(vgpu)[PCI_CLASS_DEVICE] = 332536fc234SChangbin Du INTEL_GVT_PCI_CLASS_VGA_OTHER; 333536fc234SChangbin Du vgpu_cfg_space(vgpu)[PCI_CLASS_PROG] = 334536fc234SChangbin Du INTEL_GVT_PCI_CLASS_VGA_OTHER; 335536fc234SChangbin Du } 336536fc234SChangbin Du 337536fc234SChangbin Du /* Show guest that there isn't any stolen memory.*/ 338536fc234SChangbin Du gmch_ctl = (u16 *)(vgpu_cfg_space(vgpu) + INTEL_GVT_PCI_GMCH_CONTROL); 339536fc234SChangbin Du *gmch_ctl &= ~(BDW_GMCH_GMS_MASK << BDW_GMCH_GMS_SHIFT); 340536fc234SChangbin Du 341536fc234SChangbin Du intel_vgpu_write_pci_bar(vgpu, PCI_BASE_ADDRESS_2, 342536fc234SChangbin Du gvt_aperture_pa_base(gvt), true); 343536fc234SChangbin Du 344536fc234SChangbin Du vgpu_cfg_space(vgpu)[PCI_COMMAND] &= ~(PCI_COMMAND_IO 345536fc234SChangbin Du | PCI_COMMAND_MEMORY 346536fc234SChangbin Du | PCI_COMMAND_MASTER); 347536fc234SChangbin Du /* 348536fc234SChangbin Du * Clear the bar upper 32bit and let guest to assign the new value 349536fc234SChangbin Du */ 350536fc234SChangbin Du memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_1, 0, 4); 351536fc234SChangbin Du memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_3, 0, 4); 352f1751362SChangbin Du memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_4, 0, 8); 353536fc234SChangbin Du memset(vgpu_cfg_space(vgpu) + INTEL_GVT_PCI_OPREGION, 0, 4); 354536fc234SChangbin Du 355f1751362SChangbin Du vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].size = 3569ff06c38SThomas Zimmermann pci_resource_len(pdev, 0); 357f1751362SChangbin Du vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].size = 3589ff06c38SThomas Zimmermann pci_resource_len(pdev, 2); 359c4270d12SChangbin Du 360c4270d12SChangbin Du memset(vgpu_cfg_space(vgpu) + PCI_ROM_ADDRESS, 0, 4); 361ba25d977SColin Xu 362ba25d977SColin Xu /* PM Support */ 363ba25d977SColin Xu vgpu->cfg_space.pmcsr_off = 0; 364ba25d977SColin Xu if (vgpu_cfg_space(vgpu)[PCI_STATUS] & PCI_STATUS_CAP_LIST) { 365ba25d977SColin Xu next = vgpu_cfg_space(vgpu)[PCI_CAPABILITY_LIST]; 366ba25d977SColin Xu do { 367ba25d977SColin Xu if (vgpu_cfg_space(vgpu)[next + PCI_CAP_LIST_ID] == PCI_CAP_ID_PM) { 368ba25d977SColin Xu vgpu->cfg_space.pmcsr_off = next + PCI_PM_CTRL; 369ba25d977SColin Xu break; 370ba25d977SColin Xu } 371ba25d977SColin Xu next = vgpu_cfg_space(vgpu)[next + PCI_CAP_LIST_NEXT]; 372ba25d977SColin Xu } while (next); 373ba25d977SColin Xu } 374536fc234SChangbin Du } 375c64ff6c7SChangbin Du 376c64ff6c7SChangbin Du /** 377c64ff6c7SChangbin Du * intel_vgpu_reset_cfg_space - reset vGPU configuration space 378c64ff6c7SChangbin Du * 379c64ff6c7SChangbin Du * @vgpu: a vGPU 380c64ff6c7SChangbin Du * 381c64ff6c7SChangbin Du */ 382c64ff6c7SChangbin Du void intel_vgpu_reset_cfg_space(struct intel_vgpu *vgpu) 383c64ff6c7SChangbin Du { 384c64ff6c7SChangbin Du u8 cmd = vgpu_cfg_space(vgpu)[PCI_COMMAND]; 385c64ff6c7SChangbin Du bool primary = vgpu_cfg_space(vgpu)[PCI_CLASS_DEVICE] != 386c64ff6c7SChangbin Du INTEL_GVT_PCI_CLASS_VGA_OTHER; 387c64ff6c7SChangbin Du 388c64ff6c7SChangbin Du if (cmd & PCI_COMMAND_MEMORY) { 389c64ff6c7SChangbin Du trap_gttmmio(vgpu, false); 390c64ff6c7SChangbin Du map_aperture(vgpu, false); 391c64ff6c7SChangbin Du } 392c64ff6c7SChangbin Du 393c64ff6c7SChangbin Du /** 394c64ff6c7SChangbin Du * Currently we only do such reset when vGPU is not 395c64ff6c7SChangbin Du * owned by any VM, so we simply restore entire cfg 396c64ff6c7SChangbin Du * space to default value. 397c64ff6c7SChangbin Du */ 398c64ff6c7SChangbin Du intel_vgpu_init_cfg_space(vgpu, primary); 399c64ff6c7SChangbin Du } 400