14d60c5fdSZhi Wang /* 24d60c5fdSZhi Wang * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 34d60c5fdSZhi Wang * 44d60c5fdSZhi Wang * Permission is hereby granted, free of charge, to any person obtaining a 54d60c5fdSZhi Wang * copy of this software and associated documentation files (the "Software"), 64d60c5fdSZhi Wang * to deal in the Software without restriction, including without limitation 74d60c5fdSZhi Wang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 84d60c5fdSZhi Wang * and/or sell copies of the Software, and to permit persons to whom the 94d60c5fdSZhi Wang * Software is furnished to do so, subject to the following conditions: 104d60c5fdSZhi Wang * 114d60c5fdSZhi Wang * The above copyright notice and this permission notice (including the next 124d60c5fdSZhi Wang * paragraph) shall be included in all copies or substantial portions of the 134d60c5fdSZhi Wang * Software. 144d60c5fdSZhi Wang * 154d60c5fdSZhi Wang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 164d60c5fdSZhi Wang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 174d60c5fdSZhi Wang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 184d60c5fdSZhi Wang * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 194d60c5fdSZhi Wang * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 204d60c5fdSZhi Wang * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 214d60c5fdSZhi Wang * SOFTWARE. 224d60c5fdSZhi Wang * 234d60c5fdSZhi Wang * Authors: 244d60c5fdSZhi Wang * Eddie Dong <eddie.dong@intel.com> 254d60c5fdSZhi Wang * Jike Song <jike.song@intel.com> 264d60c5fdSZhi Wang * 274d60c5fdSZhi Wang * Contributors: 284d60c5fdSZhi Wang * Zhi Wang <zhi.a.wang@intel.com> 294d60c5fdSZhi Wang * Min He <min.he@intel.com> 304d60c5fdSZhi Wang * Bing Niu <bing.niu@intel.com> 314d60c5fdSZhi Wang * 324d60c5fdSZhi Wang */ 334d60c5fdSZhi Wang 344d60c5fdSZhi Wang #include "i915_drv.h" 35feddf6e8SZhenyu Wang #include "gvt.h" 364d60c5fdSZhi Wang 374d60c5fdSZhi Wang enum { 384d60c5fdSZhi Wang INTEL_GVT_PCI_BAR_GTTMMIO = 0, 394d60c5fdSZhi Wang INTEL_GVT_PCI_BAR_APERTURE, 404d60c5fdSZhi Wang INTEL_GVT_PCI_BAR_PIO, 414d60c5fdSZhi Wang INTEL_GVT_PCI_BAR_MAX, 424d60c5fdSZhi Wang }; 434d60c5fdSZhi Wang 44c2e04fdaSChangbin Du /* bitmap for writable bits (RW or RW1C bits, but cannot co-exist in one 45c2e04fdaSChangbin Du * byte) byte by byte in standard pci configuration space. (not the full 46c2e04fdaSChangbin Du * 256 bytes.) 47c2e04fdaSChangbin Du */ 48c2e04fdaSChangbin Du static const u8 pci_cfg_space_rw_bmp[PCI_INTERRUPT_LINE + 4] = { 49c2e04fdaSChangbin Du [PCI_COMMAND] = 0xff, 0x07, 50c2e04fdaSChangbin Du [PCI_STATUS] = 0x00, 0xf9, /* the only one RW1C byte */ 51c2e04fdaSChangbin Du [PCI_CACHE_LINE_SIZE] = 0xff, 52c2e04fdaSChangbin Du [PCI_BASE_ADDRESS_0 ... PCI_CARDBUS_CIS - 1] = 0xff, 53c2e04fdaSChangbin Du [PCI_ROM_ADDRESS] = 0x01, 0xf8, 0xff, 0xff, 54c2e04fdaSChangbin Du [PCI_INTERRUPT_LINE] = 0xff, 55c2e04fdaSChangbin Du }; 56c2e04fdaSChangbin Du 57c2e04fdaSChangbin Du /** 58c2e04fdaSChangbin Du * vgpu_pci_cfg_mem_write - write virtual cfg space memory 59c2e04fdaSChangbin Du * 60c2e04fdaSChangbin Du * Use this function to write virtual cfg space memory. 61c2e04fdaSChangbin Du * For standard cfg space, only RW bits can be changed, 62c2e04fdaSChangbin Du * and we emulates the RW1C behavior of PCI_STATUS register. 63c2e04fdaSChangbin Du */ 64c2e04fdaSChangbin Du static void vgpu_pci_cfg_mem_write(struct intel_vgpu *vgpu, unsigned int off, 65c2e04fdaSChangbin Du u8 *src, unsigned int bytes) 66c2e04fdaSChangbin Du { 67c2e04fdaSChangbin Du u8 *cfg_base = vgpu_cfg_space(vgpu); 68c2e04fdaSChangbin Du u8 mask, new, old; 69c2e04fdaSChangbin Du int i = 0; 70c2e04fdaSChangbin Du 71c2e04fdaSChangbin Du for (; i < bytes && (off + i < sizeof(pci_cfg_space_rw_bmp)); i++) { 72c2e04fdaSChangbin Du mask = pci_cfg_space_rw_bmp[off + i]; 73c2e04fdaSChangbin Du old = cfg_base[off + i]; 74c2e04fdaSChangbin Du new = src[i] & mask; 75c2e04fdaSChangbin Du 76c2e04fdaSChangbin Du /** 77c2e04fdaSChangbin Du * The PCI_STATUS high byte has RW1C bits, here 78c2e04fdaSChangbin Du * emulates clear by writing 1 for these bits. 79c2e04fdaSChangbin Du * Writing a 0b to RW1C bits has no effect. 80c2e04fdaSChangbin Du */ 81c2e04fdaSChangbin Du if (off + i == PCI_STATUS + 1) 82c2e04fdaSChangbin Du new = (~new & old) & mask; 83c2e04fdaSChangbin Du 84c2e04fdaSChangbin Du cfg_base[off + i] = (old & ~mask) | new; 85c2e04fdaSChangbin Du } 86c2e04fdaSChangbin Du 87c2e04fdaSChangbin Du /* For other configuration space directly copy as it is. */ 88c2e04fdaSChangbin Du if (i < bytes) 89c2e04fdaSChangbin Du memcpy(cfg_base + off + i, src + i, bytes - i); 90c2e04fdaSChangbin Du } 91c2e04fdaSChangbin Du 924d60c5fdSZhi Wang /** 934d60c5fdSZhi Wang * intel_vgpu_emulate_cfg_read - emulate vGPU configuration space read 944d60c5fdSZhi Wang * 954d60c5fdSZhi Wang * Returns: 964d60c5fdSZhi Wang * Zero on success, negative error code if failed. 974d60c5fdSZhi Wang */ 989ec1e66bSJike Song int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset, 994d60c5fdSZhi Wang void *p_data, unsigned int bytes) 1004d60c5fdSZhi Wang { 1014d60c5fdSZhi Wang if (WARN_ON(bytes > 4)) 1024d60c5fdSZhi Wang return -EINVAL; 1034d60c5fdSZhi Wang 10402d578e5SChangbin Du if (WARN_ON(offset + bytes > vgpu->gvt->device_info.cfg_space_size)) 1054d60c5fdSZhi Wang return -EINVAL; 1064d60c5fdSZhi Wang 1074d60c5fdSZhi Wang memcpy(p_data, vgpu_cfg_space(vgpu) + offset, bytes); 1084d60c5fdSZhi Wang return 0; 1094d60c5fdSZhi Wang } 1104d60c5fdSZhi Wang 1114d60c5fdSZhi Wang static int map_aperture(struct intel_vgpu *vgpu, bool map) 1124d60c5fdSZhi Wang { 113f090a00dSChangbin Du phys_addr_t aperture_pa = vgpu_aperture_pa_base(vgpu); 114f090a00dSChangbin Du unsigned long aperture_sz = vgpu_aperture_sz(vgpu); 115f090a00dSChangbin Du u64 first_gfn; 1164d60c5fdSZhi Wang u64 val; 1174d60c5fdSZhi Wang int ret; 1184d60c5fdSZhi Wang 1194d60c5fdSZhi Wang if (map == vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].tracked) 1204d60c5fdSZhi Wang return 0; 1214d60c5fdSZhi Wang 122f090a00dSChangbin Du if (map) { 123f090a00dSChangbin Du vgpu->gm.aperture_va = memremap(aperture_pa, aperture_sz, 124f090a00dSChangbin Du MEMREMAP_WC); 125f090a00dSChangbin Du if (!vgpu->gm.aperture_va) 126f090a00dSChangbin Du return -ENOMEM; 127f090a00dSChangbin Du } else { 128f090a00dSChangbin Du memunmap(vgpu->gm.aperture_va); 129f090a00dSChangbin Du vgpu->gm.aperture_va = NULL; 130f090a00dSChangbin Du } 131f090a00dSChangbin Du 1324d60c5fdSZhi Wang val = vgpu_cfg_space(vgpu)[PCI_BASE_ADDRESS_2]; 1334d60c5fdSZhi Wang if (val & PCI_BASE_ADDRESS_MEM_TYPE_64) 1344d60c5fdSZhi Wang val = *(u64 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_2); 1354d60c5fdSZhi Wang else 1364d60c5fdSZhi Wang val = *(u32 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_2); 1374d60c5fdSZhi Wang 1384d60c5fdSZhi Wang first_gfn = (val + vgpu_aperture_offset(vgpu)) >> PAGE_SHIFT; 1394d60c5fdSZhi Wang 1404d60c5fdSZhi Wang ret = intel_gvt_hypervisor_map_gfn_to_mfn(vgpu, first_gfn, 141f090a00dSChangbin Du aperture_pa >> PAGE_SHIFT, 142f090a00dSChangbin Du aperture_sz >> PAGE_SHIFT, 143f090a00dSChangbin Du map); 144f090a00dSChangbin Du if (ret) { 145f090a00dSChangbin Du memunmap(vgpu->gm.aperture_va); 146f090a00dSChangbin Du vgpu->gm.aperture_va = NULL; 1474d60c5fdSZhi Wang return ret; 148f090a00dSChangbin Du } 1494d60c5fdSZhi Wang 1504d60c5fdSZhi Wang vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].tracked = map; 1514d60c5fdSZhi Wang return 0; 1524d60c5fdSZhi Wang } 1534d60c5fdSZhi Wang 1544d60c5fdSZhi Wang static int trap_gttmmio(struct intel_vgpu *vgpu, bool trap) 1554d60c5fdSZhi Wang { 1564d60c5fdSZhi Wang u64 start, end; 1574d60c5fdSZhi Wang u64 val; 1584d60c5fdSZhi Wang int ret; 1594d60c5fdSZhi Wang 1604d60c5fdSZhi Wang if (trap == vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].tracked) 1614d60c5fdSZhi Wang return 0; 1624d60c5fdSZhi Wang 1634d60c5fdSZhi Wang val = vgpu_cfg_space(vgpu)[PCI_BASE_ADDRESS_0]; 1644d60c5fdSZhi Wang if (val & PCI_BASE_ADDRESS_MEM_TYPE_64) 1654d60c5fdSZhi Wang start = *(u64 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_0); 1664d60c5fdSZhi Wang else 1674d60c5fdSZhi Wang start = *(u32 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_0); 1684d60c5fdSZhi Wang 1694d60c5fdSZhi Wang start &= ~GENMASK(3, 0); 1704d60c5fdSZhi Wang end = start + vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].size - 1; 1714d60c5fdSZhi Wang 1724d60c5fdSZhi Wang ret = intel_gvt_hypervisor_set_trap_area(vgpu, start, end, trap); 1734d60c5fdSZhi Wang if (ret) 1744d60c5fdSZhi Wang return ret; 1754d60c5fdSZhi Wang 1764d60c5fdSZhi Wang vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].tracked = trap; 1774d60c5fdSZhi Wang return 0; 1784d60c5fdSZhi Wang } 1794d60c5fdSZhi Wang 1804d60c5fdSZhi Wang static int emulate_pci_command_write(struct intel_vgpu *vgpu, 1814d60c5fdSZhi Wang unsigned int offset, void *p_data, unsigned int bytes) 1824d60c5fdSZhi Wang { 1834d60c5fdSZhi Wang u8 old = vgpu_cfg_space(vgpu)[offset]; 1844d60c5fdSZhi Wang u8 new = *(u8 *)p_data; 1854d60c5fdSZhi Wang u8 changed = old ^ new; 1864d60c5fdSZhi Wang int ret; 1874d60c5fdSZhi Wang 188c2e04fdaSChangbin Du vgpu_pci_cfg_mem_write(vgpu, offset, p_data, bytes); 1894d60c5fdSZhi Wang if (!(changed & PCI_COMMAND_MEMORY)) 1904d60c5fdSZhi Wang return 0; 1914d60c5fdSZhi Wang 1924d60c5fdSZhi Wang if (old & PCI_COMMAND_MEMORY) { 1934d60c5fdSZhi Wang ret = trap_gttmmio(vgpu, false); 1944d60c5fdSZhi Wang if (ret) 1954d60c5fdSZhi Wang return ret; 1964d60c5fdSZhi Wang ret = map_aperture(vgpu, false); 1974d60c5fdSZhi Wang if (ret) 1984d60c5fdSZhi Wang return ret; 1994d60c5fdSZhi Wang } else { 2004d60c5fdSZhi Wang ret = trap_gttmmio(vgpu, true); 2014d60c5fdSZhi Wang if (ret) 2024d60c5fdSZhi Wang return ret; 2034d60c5fdSZhi Wang ret = map_aperture(vgpu, true); 2044d60c5fdSZhi Wang if (ret) 2054d60c5fdSZhi Wang return ret; 2064d60c5fdSZhi Wang } 2074d60c5fdSZhi Wang 2084d60c5fdSZhi Wang return 0; 2094d60c5fdSZhi Wang } 2104d60c5fdSZhi Wang 211c4270d12SChangbin Du static int emulate_pci_rom_bar_write(struct intel_vgpu *vgpu, 212c4270d12SChangbin Du unsigned int offset, void *p_data, unsigned int bytes) 213c4270d12SChangbin Du { 214c4270d12SChangbin Du u32 *pval = (u32 *)(vgpu_cfg_space(vgpu) + offset); 215c4270d12SChangbin Du u32 new = *(u32 *)(p_data); 216c4270d12SChangbin Du 217c4270d12SChangbin Du if ((new & PCI_ROM_ADDRESS_MASK) == PCI_ROM_ADDRESS_MASK) 218c4270d12SChangbin Du /* We don't have rom, return size of 0. */ 219c4270d12SChangbin Du *pval = 0; 220c4270d12SChangbin Du else 221c4270d12SChangbin Du vgpu_pci_cfg_mem_write(vgpu, offset, p_data, bytes); 222c4270d12SChangbin Du return 0; 223c4270d12SChangbin Du } 224c4270d12SChangbin Du 2254d60c5fdSZhi Wang static int emulate_pci_bar_write(struct intel_vgpu *vgpu, unsigned int offset, 2264d60c5fdSZhi Wang void *p_data, unsigned int bytes) 2274d60c5fdSZhi Wang { 2284d60c5fdSZhi Wang u32 new = *(u32 *)(p_data); 2294d60c5fdSZhi Wang bool lo = IS_ALIGNED(offset, 8); 2304d60c5fdSZhi Wang u64 size; 2314d60c5fdSZhi Wang int ret = 0; 2324d60c5fdSZhi Wang bool mmio_enabled = 2334d60c5fdSZhi Wang vgpu_cfg_space(vgpu)[PCI_COMMAND] & PCI_COMMAND_MEMORY; 234f1751362SChangbin Du struct intel_vgpu_pci_bar *bars = vgpu->cfg_space.bar; 2354d60c5fdSZhi Wang 2364d60c5fdSZhi Wang /* 2374d60c5fdSZhi Wang * Power-up software can determine how much address 2384d60c5fdSZhi Wang * space the device requires by writing a value of 2394d60c5fdSZhi Wang * all 1's to the register and then reading the value 2404d60c5fdSZhi Wang * back. The device will return 0's in all don't-care 2414d60c5fdSZhi Wang * address bits. 2424d60c5fdSZhi Wang */ 243f1751362SChangbin Du if (new == 0xffffffff) { 244f1751362SChangbin Du switch (offset) { 245f1751362SChangbin Du case PCI_BASE_ADDRESS_0: 246f1751362SChangbin Du case PCI_BASE_ADDRESS_1: 247f1751362SChangbin Du size = ~(bars[INTEL_GVT_PCI_BAR_GTTMMIO].size -1); 248f1751362SChangbin Du intel_vgpu_write_pci_bar(vgpu, offset, 249f1751362SChangbin Du size >> (lo ? 0 : 32), lo); 2504d60c5fdSZhi Wang /* 251f1751362SChangbin Du * Untrap the BAR, since guest hasn't configured a 2524d60c5fdSZhi Wang * valid GPA 2534d60c5fdSZhi Wang */ 2544d60c5fdSZhi Wang ret = trap_gttmmio(vgpu, false); 2554d60c5fdSZhi Wang break; 256f1751362SChangbin Du case PCI_BASE_ADDRESS_2: 257f1751362SChangbin Du case PCI_BASE_ADDRESS_3: 258f1751362SChangbin Du size = ~(bars[INTEL_GVT_PCI_BAR_APERTURE].size -1); 259f1751362SChangbin Du intel_vgpu_write_pci_bar(vgpu, offset, 260f1751362SChangbin Du size >> (lo ? 0 : 32), lo); 2614d60c5fdSZhi Wang ret = map_aperture(vgpu, false); 2624d60c5fdSZhi Wang break; 263f1751362SChangbin Du default: 264f1751362SChangbin Du /* Unimplemented BARs */ 265f1751362SChangbin Du intel_vgpu_write_pci_bar(vgpu, offset, 0x0, false); 2664d60c5fdSZhi Wang } 2674d60c5fdSZhi Wang } else { 268f1751362SChangbin Du switch (offset) { 269f1751362SChangbin Du case PCI_BASE_ADDRESS_0: 270f1751362SChangbin Du case PCI_BASE_ADDRESS_1: 2714d60c5fdSZhi Wang /* 272f1751362SChangbin Du * Untrap the old BAR first, since guest has 2734d60c5fdSZhi Wang * re-configured the BAR 2744d60c5fdSZhi Wang */ 275f1751362SChangbin Du trap_gttmmio(vgpu, false); 2764d60c5fdSZhi Wang intel_vgpu_write_pci_bar(vgpu, offset, new, lo); 277f1751362SChangbin Du ret = trap_gttmmio(vgpu, mmio_enabled); 2784d60c5fdSZhi Wang break; 279f1751362SChangbin Du case PCI_BASE_ADDRESS_2: 280f1751362SChangbin Du case PCI_BASE_ADDRESS_3: 281f1751362SChangbin Du map_aperture(vgpu, false); 282f1751362SChangbin Du intel_vgpu_write_pci_bar(vgpu, offset, new, lo); 283f1751362SChangbin Du ret = map_aperture(vgpu, mmio_enabled); 2844d60c5fdSZhi Wang break; 285f1751362SChangbin Du default: 286f1751362SChangbin Du intel_vgpu_write_pci_bar(vgpu, offset, new, lo); 2874d60c5fdSZhi Wang } 2884d60c5fdSZhi Wang } 2894d60c5fdSZhi Wang return ret; 2904d60c5fdSZhi Wang } 2914d60c5fdSZhi Wang 2924d60c5fdSZhi Wang /** 2934d60c5fdSZhi Wang * intel_vgpu_emulate_cfg_read - emulate vGPU configuration space write 2944d60c5fdSZhi Wang * 2954d60c5fdSZhi Wang * Returns: 2964d60c5fdSZhi Wang * Zero on success, negative error code if failed. 2974d60c5fdSZhi Wang */ 2989ec1e66bSJike Song int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset, 2994d60c5fdSZhi Wang void *p_data, unsigned int bytes) 3004d60c5fdSZhi Wang { 3014d60c5fdSZhi Wang int ret; 3024d60c5fdSZhi Wang 3034d60c5fdSZhi Wang if (WARN_ON(bytes > 4)) 3044d60c5fdSZhi Wang return -EINVAL; 3054d60c5fdSZhi Wang 30602d578e5SChangbin Du if (WARN_ON(offset + bytes > vgpu->gvt->device_info.cfg_space_size)) 3074d60c5fdSZhi Wang return -EINVAL; 3084d60c5fdSZhi Wang 3094d60c5fdSZhi Wang /* First check if it's PCI_COMMAND */ 3104d60c5fdSZhi Wang if (IS_ALIGNED(offset, 2) && offset == PCI_COMMAND) { 3114d60c5fdSZhi Wang if (WARN_ON(bytes > 2)) 3124d60c5fdSZhi Wang return -EINVAL; 3134d60c5fdSZhi Wang return emulate_pci_command_write(vgpu, offset, p_data, bytes); 3144d60c5fdSZhi Wang } 3154d60c5fdSZhi Wang 3164d60c5fdSZhi Wang switch (rounddown(offset, 4)) { 317c4270d12SChangbin Du case PCI_ROM_ADDRESS: 318c4270d12SChangbin Du if (WARN_ON(!IS_ALIGNED(offset, 4))) 319c4270d12SChangbin Du return -EINVAL; 320c4270d12SChangbin Du return emulate_pci_rom_bar_write(vgpu, offset, p_data, bytes); 321c4270d12SChangbin Du 322f1751362SChangbin Du case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_5: 3234d60c5fdSZhi Wang if (WARN_ON(!IS_ALIGNED(offset, 4))) 3244d60c5fdSZhi Wang return -EINVAL; 3254d60c5fdSZhi Wang return emulate_pci_bar_write(vgpu, offset, p_data, bytes); 3264d60c5fdSZhi Wang 3274d60c5fdSZhi Wang case INTEL_GVT_PCI_SWSCI: 3284d60c5fdSZhi Wang if (WARN_ON(!IS_ALIGNED(offset, 4))) 3294d60c5fdSZhi Wang return -EINVAL; 3304d60c5fdSZhi Wang ret = intel_vgpu_emulate_opregion_request(vgpu, *(u32 *)p_data); 3314d60c5fdSZhi Wang if (ret) 3324d60c5fdSZhi Wang return ret; 3334d60c5fdSZhi Wang break; 3344d60c5fdSZhi Wang 3354d60c5fdSZhi Wang case INTEL_GVT_PCI_OPREGION: 3364d60c5fdSZhi Wang if (WARN_ON(!IS_ALIGNED(offset, 4))) 3374d60c5fdSZhi Wang return -EINVAL; 3384dff110bSXiong Zhang ret = intel_vgpu_opregion_base_write_handler(vgpu, 3394dff110bSXiong Zhang *(u32 *)p_data); 3404d60c5fdSZhi Wang if (ret) 3414d60c5fdSZhi Wang return ret; 3424d60c5fdSZhi Wang 343c2e04fdaSChangbin Du vgpu_pci_cfg_mem_write(vgpu, offset, p_data, bytes); 3444d60c5fdSZhi Wang break; 3454d60c5fdSZhi Wang default: 346c2e04fdaSChangbin Du vgpu_pci_cfg_mem_write(vgpu, offset, p_data, bytes); 3474d60c5fdSZhi Wang break; 3484d60c5fdSZhi Wang } 3494d60c5fdSZhi Wang return 0; 3504d60c5fdSZhi Wang } 351536fc234SChangbin Du 352536fc234SChangbin Du /** 353536fc234SChangbin Du * intel_vgpu_init_cfg_space - init vGPU configuration space when create vGPU 354536fc234SChangbin Du * 355536fc234SChangbin Du * @vgpu: a vGPU 356536fc234SChangbin Du * @primary: is the vGPU presented as primary 357536fc234SChangbin Du * 358536fc234SChangbin Du */ 359536fc234SChangbin Du void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu, 360536fc234SChangbin Du bool primary) 361536fc234SChangbin Du { 362536fc234SChangbin Du struct intel_gvt *gvt = vgpu->gvt; 363536fc234SChangbin Du const struct intel_gvt_device_info *info = &gvt->device_info; 364536fc234SChangbin Du u16 *gmch_ctl; 365536fc234SChangbin Du 366536fc234SChangbin Du memcpy(vgpu_cfg_space(vgpu), gvt->firmware.cfg_space, 367536fc234SChangbin Du info->cfg_space_size); 368536fc234SChangbin Du 369536fc234SChangbin Du if (!primary) { 370536fc234SChangbin Du vgpu_cfg_space(vgpu)[PCI_CLASS_DEVICE] = 371536fc234SChangbin Du INTEL_GVT_PCI_CLASS_VGA_OTHER; 372536fc234SChangbin Du vgpu_cfg_space(vgpu)[PCI_CLASS_PROG] = 373536fc234SChangbin Du INTEL_GVT_PCI_CLASS_VGA_OTHER; 374536fc234SChangbin Du } 375536fc234SChangbin Du 376536fc234SChangbin Du /* Show guest that there isn't any stolen memory.*/ 377536fc234SChangbin Du gmch_ctl = (u16 *)(vgpu_cfg_space(vgpu) + INTEL_GVT_PCI_GMCH_CONTROL); 378536fc234SChangbin Du *gmch_ctl &= ~(BDW_GMCH_GMS_MASK << BDW_GMCH_GMS_SHIFT); 379536fc234SChangbin Du 380536fc234SChangbin Du intel_vgpu_write_pci_bar(vgpu, PCI_BASE_ADDRESS_2, 381536fc234SChangbin Du gvt_aperture_pa_base(gvt), true); 382536fc234SChangbin Du 383536fc234SChangbin Du vgpu_cfg_space(vgpu)[PCI_COMMAND] &= ~(PCI_COMMAND_IO 384536fc234SChangbin Du | PCI_COMMAND_MEMORY 385536fc234SChangbin Du | PCI_COMMAND_MASTER); 386536fc234SChangbin Du /* 387536fc234SChangbin Du * Clear the bar upper 32bit and let guest to assign the new value 388536fc234SChangbin Du */ 389536fc234SChangbin Du memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_1, 0, 4); 390536fc234SChangbin Du memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_3, 0, 4); 391f1751362SChangbin Du memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_4, 0, 8); 392536fc234SChangbin Du memset(vgpu_cfg_space(vgpu) + INTEL_GVT_PCI_OPREGION, 0, 4); 393536fc234SChangbin Du 394f1751362SChangbin Du vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].size = 395f1751362SChangbin Du pci_resource_len(gvt->dev_priv->drm.pdev, 0); 396f1751362SChangbin Du vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].size = 397f1751362SChangbin Du pci_resource_len(gvt->dev_priv->drm.pdev, 2); 398c4270d12SChangbin Du 399c4270d12SChangbin Du memset(vgpu_cfg_space(vgpu) + PCI_ROM_ADDRESS, 0, 4); 400536fc234SChangbin Du } 401c64ff6c7SChangbin Du 402c64ff6c7SChangbin Du /** 403c64ff6c7SChangbin Du * intel_vgpu_reset_cfg_space - reset vGPU configuration space 404c64ff6c7SChangbin Du * 405c64ff6c7SChangbin Du * @vgpu: a vGPU 406c64ff6c7SChangbin Du * 407c64ff6c7SChangbin Du */ 408c64ff6c7SChangbin Du void intel_vgpu_reset_cfg_space(struct intel_vgpu *vgpu) 409c64ff6c7SChangbin Du { 410c64ff6c7SChangbin Du u8 cmd = vgpu_cfg_space(vgpu)[PCI_COMMAND]; 411c64ff6c7SChangbin Du bool primary = vgpu_cfg_space(vgpu)[PCI_CLASS_DEVICE] != 412c64ff6c7SChangbin Du INTEL_GVT_PCI_CLASS_VGA_OTHER; 413c64ff6c7SChangbin Du 414c64ff6c7SChangbin Du if (cmd & PCI_COMMAND_MEMORY) { 415c64ff6c7SChangbin Du trap_gttmmio(vgpu, false); 416c64ff6c7SChangbin Du map_aperture(vgpu, false); 417c64ff6c7SChangbin Du } 418c64ff6c7SChangbin Du 419c64ff6c7SChangbin Du /** 420c64ff6c7SChangbin Du * Currently we only do such reset when vGPU is not 421c64ff6c7SChangbin Du * owned by any VM, so we simply restore entire cfg 422c64ff6c7SChangbin Du * space to default value. 423c64ff6c7SChangbin Du */ 424c64ff6c7SChangbin Du intel_vgpu_init_cfg_space(vgpu, primary); 425c64ff6c7SChangbin Du } 426