14d60c5fdSZhi Wang /*
24d60c5fdSZhi Wang * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
34d60c5fdSZhi Wang *
44d60c5fdSZhi Wang * Permission is hereby granted, free of charge, to any person obtaining a
54d60c5fdSZhi Wang * copy of this software and associated documentation files (the "Software"),
64d60c5fdSZhi Wang * to deal in the Software without restriction, including without limitation
74d60c5fdSZhi Wang * the rights to use, copy, modify, merge, publish, distribute, sublicense,
84d60c5fdSZhi Wang * and/or sell copies of the Software, and to permit persons to whom the
94d60c5fdSZhi Wang * Software is furnished to do so, subject to the following conditions:
104d60c5fdSZhi Wang *
114d60c5fdSZhi Wang * The above copyright notice and this permission notice (including the next
124d60c5fdSZhi Wang * paragraph) shall be included in all copies or substantial portions of the
134d60c5fdSZhi Wang * Software.
144d60c5fdSZhi Wang *
154d60c5fdSZhi Wang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
164d60c5fdSZhi Wang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
174d60c5fdSZhi Wang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
184d60c5fdSZhi Wang * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
194d60c5fdSZhi Wang * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
204d60c5fdSZhi Wang * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
214d60c5fdSZhi Wang * SOFTWARE.
224d60c5fdSZhi Wang *
234d60c5fdSZhi Wang * Authors:
244d60c5fdSZhi Wang * Eddie Dong <eddie.dong@intel.com>
254d60c5fdSZhi Wang * Jike Song <jike.song@intel.com>
264d60c5fdSZhi Wang *
274d60c5fdSZhi Wang * Contributors:
284d60c5fdSZhi Wang * Zhi Wang <zhi.a.wang@intel.com>
294d60c5fdSZhi Wang * Min He <min.he@intel.com>
304d60c5fdSZhi Wang * Bing Niu <bing.niu@intel.com>
314d60c5fdSZhi Wang *
324d60c5fdSZhi Wang */
334d60c5fdSZhi Wang
344d60c5fdSZhi Wang #include "i915_drv.h"
35feddf6e8SZhenyu Wang #include "gvt.h"
366bba2b30SPiotr Piórkowski #include "intel_pci_config.h"
374d60c5fdSZhi Wang
384d60c5fdSZhi Wang enum {
394d60c5fdSZhi Wang INTEL_GVT_PCI_BAR_GTTMMIO = 0,
404d60c5fdSZhi Wang INTEL_GVT_PCI_BAR_APERTURE,
414d60c5fdSZhi Wang INTEL_GVT_PCI_BAR_PIO,
424d60c5fdSZhi Wang INTEL_GVT_PCI_BAR_MAX,
434d60c5fdSZhi Wang };
444d60c5fdSZhi Wang
45c2e04fdaSChangbin Du /* bitmap for writable bits (RW or RW1C bits, but cannot co-exist in one
46c2e04fdaSChangbin Du * byte) byte by byte in standard pci configuration space. (not the full
47c2e04fdaSChangbin Du * 256 bytes.)
48c2e04fdaSChangbin Du */
49c2e04fdaSChangbin Du static const u8 pci_cfg_space_rw_bmp[PCI_INTERRUPT_LINE + 4] = {
50c2e04fdaSChangbin Du [PCI_COMMAND] = 0xff, 0x07,
51c2e04fdaSChangbin Du [PCI_STATUS] = 0x00, 0xf9, /* the only one RW1C byte */
52c2e04fdaSChangbin Du [PCI_CACHE_LINE_SIZE] = 0xff,
53c2e04fdaSChangbin Du [PCI_BASE_ADDRESS_0 ... PCI_CARDBUS_CIS - 1] = 0xff,
54c2e04fdaSChangbin Du [PCI_ROM_ADDRESS] = 0x01, 0xf8, 0xff, 0xff,
55c2e04fdaSChangbin Du [PCI_INTERRUPT_LINE] = 0xff,
56c2e04fdaSChangbin Du };
57c2e04fdaSChangbin Du
58c2e04fdaSChangbin Du /**
59c2e04fdaSChangbin Du * vgpu_pci_cfg_mem_write - write virtual cfg space memory
60a752b070SZhenyu Wang * @vgpu: target vgpu
61a752b070SZhenyu Wang * @off: offset
62a752b070SZhenyu Wang * @src: src ptr to write
63a752b070SZhenyu Wang * @bytes: number of bytes
64c2e04fdaSChangbin Du *
65c2e04fdaSChangbin Du * Use this function to write virtual cfg space memory.
66c2e04fdaSChangbin Du * For standard cfg space, only RW bits can be changed,
67c2e04fdaSChangbin Du * and we emulates the RW1C behavior of PCI_STATUS register.
68c2e04fdaSChangbin Du */
vgpu_pci_cfg_mem_write(struct intel_vgpu * vgpu,unsigned int off,u8 * src,unsigned int bytes)69c2e04fdaSChangbin Du static void vgpu_pci_cfg_mem_write(struct intel_vgpu *vgpu, unsigned int off,
70c2e04fdaSChangbin Du u8 *src, unsigned int bytes)
71c2e04fdaSChangbin Du {
72c2e04fdaSChangbin Du u8 *cfg_base = vgpu_cfg_space(vgpu);
73c2e04fdaSChangbin Du u8 mask, new, old;
74ba25d977SColin Xu pci_power_t pwr;
75c2e04fdaSChangbin Du int i = 0;
76c2e04fdaSChangbin Du
77c2e04fdaSChangbin Du for (; i < bytes && (off + i < sizeof(pci_cfg_space_rw_bmp)); i++) {
78c2e04fdaSChangbin Du mask = pci_cfg_space_rw_bmp[off + i];
79c2e04fdaSChangbin Du old = cfg_base[off + i];
80c2e04fdaSChangbin Du new = src[i] & mask;
81c2e04fdaSChangbin Du
82c2e04fdaSChangbin Du /**
83c2e04fdaSChangbin Du * The PCI_STATUS high byte has RW1C bits, here
84c2e04fdaSChangbin Du * emulates clear by writing 1 for these bits.
85c2e04fdaSChangbin Du * Writing a 0b to RW1C bits has no effect.
86c2e04fdaSChangbin Du */
87c2e04fdaSChangbin Du if (off + i == PCI_STATUS + 1)
88c2e04fdaSChangbin Du new = (~new & old) & mask;
89c2e04fdaSChangbin Du
90c2e04fdaSChangbin Du cfg_base[off + i] = (old & ~mask) | new;
91c2e04fdaSChangbin Du }
92c2e04fdaSChangbin Du
93c2e04fdaSChangbin Du /* For other configuration space directly copy as it is. */
94c2e04fdaSChangbin Du if (i < bytes)
95c2e04fdaSChangbin Du memcpy(cfg_base + off + i, src + i, bytes - i);
96ba25d977SColin Xu
97ba25d977SColin Xu if (off == vgpu->cfg_space.pmcsr_off && vgpu->cfg_space.pmcsr_off) {
98ba25d977SColin Xu pwr = (pci_power_t __force)(*(u16*)(&vgpu_cfg_space(vgpu)[off])
99ba25d977SColin Xu & PCI_PM_CTRL_STATE_MASK);
100ba25d977SColin Xu if (pwr == PCI_D3hot)
101ba25d977SColin Xu vgpu->d3_entered = true;
102ba25d977SColin Xu gvt_dbg_core("vgpu-%d power status changed to %d\n",
103ba25d977SColin Xu vgpu->id, pwr);
104ba25d977SColin Xu }
105c2e04fdaSChangbin Du }
106c2e04fdaSChangbin Du
1074d60c5fdSZhi Wang /**
1084d60c5fdSZhi Wang * intel_vgpu_emulate_cfg_read - emulate vGPU configuration space read
109a752b070SZhenyu Wang * @vgpu: target vgpu
110a752b070SZhenyu Wang * @offset: offset
111a752b070SZhenyu Wang * @p_data: return data ptr
112a752b070SZhenyu Wang * @bytes: number of bytes to read
1134d60c5fdSZhi Wang *
1144d60c5fdSZhi Wang * Returns:
1154d60c5fdSZhi Wang * Zero on success, negative error code if failed.
1164d60c5fdSZhi Wang */
intel_vgpu_emulate_cfg_read(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1179ec1e66bSJike Song int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset,
1184d60c5fdSZhi Wang void *p_data, unsigned int bytes)
1194d60c5fdSZhi Wang {
120a61ac1e7SChris Wilson struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
12112d58619SPankaj Bharadiya
12212d58619SPankaj Bharadiya if (drm_WARN_ON(&i915->drm, bytes > 4))
1234d60c5fdSZhi Wang return -EINVAL;
1244d60c5fdSZhi Wang
12512d58619SPankaj Bharadiya if (drm_WARN_ON(&i915->drm,
12612d58619SPankaj Bharadiya offset + bytes > vgpu->gvt->device_info.cfg_space_size))
1274d60c5fdSZhi Wang return -EINVAL;
1284d60c5fdSZhi Wang
1294d60c5fdSZhi Wang memcpy(p_data, vgpu_cfg_space(vgpu) + offset, bytes);
1304d60c5fdSZhi Wang return 0;
1314d60c5fdSZhi Wang }
1324d60c5fdSZhi Wang
map_aperture(struct intel_vgpu * vgpu,bool map)133c977092aSChristoph Hellwig static void map_aperture(struct intel_vgpu *vgpu, bool map)
1344d60c5fdSZhi Wang {
135c977092aSChristoph Hellwig if (map != vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].tracked)
1364d60c5fdSZhi Wang vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].tracked = map;
1374d60c5fdSZhi Wang }
1384d60c5fdSZhi Wang
trap_gttmmio(struct intel_vgpu * vgpu,bool trap)139c977092aSChristoph Hellwig static void trap_gttmmio(struct intel_vgpu *vgpu, bool trap)
1404d60c5fdSZhi Wang {
141c977092aSChristoph Hellwig if (trap != vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].tracked)
1424d60c5fdSZhi Wang vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].tracked = trap;
1434d60c5fdSZhi Wang }
1444d60c5fdSZhi Wang
emulate_pci_command_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1454d60c5fdSZhi Wang static int emulate_pci_command_write(struct intel_vgpu *vgpu,
1464d60c5fdSZhi Wang unsigned int offset, void *p_data, unsigned int bytes)
1474d60c5fdSZhi Wang {
1484d60c5fdSZhi Wang u8 old = vgpu_cfg_space(vgpu)[offset];
1494d60c5fdSZhi Wang u8 new = *(u8 *)p_data;
1504d60c5fdSZhi Wang u8 changed = old ^ new;
1514d60c5fdSZhi Wang
152c2e04fdaSChangbin Du vgpu_pci_cfg_mem_write(vgpu, offset, p_data, bytes);
1534d60c5fdSZhi Wang if (!(changed & PCI_COMMAND_MEMORY))
1544d60c5fdSZhi Wang return 0;
1554d60c5fdSZhi Wang
1564d60c5fdSZhi Wang if (old & PCI_COMMAND_MEMORY) {
157c977092aSChristoph Hellwig trap_gttmmio(vgpu, false);
158c977092aSChristoph Hellwig map_aperture(vgpu, false);
1594d60c5fdSZhi Wang } else {
160c977092aSChristoph Hellwig trap_gttmmio(vgpu, true);
161c977092aSChristoph Hellwig map_aperture(vgpu, true);
1624d60c5fdSZhi Wang }
1634d60c5fdSZhi Wang
1644d60c5fdSZhi Wang return 0;
1654d60c5fdSZhi Wang }
1664d60c5fdSZhi Wang
emulate_pci_rom_bar_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)167c4270d12SChangbin Du static int emulate_pci_rom_bar_write(struct intel_vgpu *vgpu,
168c4270d12SChangbin Du unsigned int offset, void *p_data, unsigned int bytes)
169c4270d12SChangbin Du {
170c4270d12SChangbin Du u32 *pval = (u32 *)(vgpu_cfg_space(vgpu) + offset);
171c4270d12SChangbin Du u32 new = *(u32 *)(p_data);
172c4270d12SChangbin Du
173c4270d12SChangbin Du if ((new & PCI_ROM_ADDRESS_MASK) == PCI_ROM_ADDRESS_MASK)
174c4270d12SChangbin Du /* We don't have rom, return size of 0. */
175c4270d12SChangbin Du *pval = 0;
176c4270d12SChangbin Du else
177c4270d12SChangbin Du vgpu_pci_cfg_mem_write(vgpu, offset, p_data, bytes);
178c4270d12SChangbin Du return 0;
179c4270d12SChangbin Du }
180c4270d12SChangbin Du
emulate_pci_bar_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)181c977092aSChristoph Hellwig static void emulate_pci_bar_write(struct intel_vgpu *vgpu, unsigned int offset,
1824d60c5fdSZhi Wang void *p_data, unsigned int bytes)
1834d60c5fdSZhi Wang {
1844d60c5fdSZhi Wang u32 new = *(u32 *)(p_data);
1854d60c5fdSZhi Wang bool lo = IS_ALIGNED(offset, 8);
1864d60c5fdSZhi Wang u64 size;
1874d60c5fdSZhi Wang bool mmio_enabled =
1884d60c5fdSZhi Wang vgpu_cfg_space(vgpu)[PCI_COMMAND] & PCI_COMMAND_MEMORY;
189f1751362SChangbin Du struct intel_vgpu_pci_bar *bars = vgpu->cfg_space.bar;
1904d60c5fdSZhi Wang
1914d60c5fdSZhi Wang /*
1924d60c5fdSZhi Wang * Power-up software can determine how much address
1934d60c5fdSZhi Wang * space the device requires by writing a value of
1944d60c5fdSZhi Wang * all 1's to the register and then reading the value
1954d60c5fdSZhi Wang * back. The device will return 0's in all don't-care
1964d60c5fdSZhi Wang * address bits.
1974d60c5fdSZhi Wang */
198f1751362SChangbin Du if (new == 0xffffffff) {
199f1751362SChangbin Du switch (offset) {
200f1751362SChangbin Du case PCI_BASE_ADDRESS_0:
201f1751362SChangbin Du case PCI_BASE_ADDRESS_1:
202f1751362SChangbin Du size = ~(bars[INTEL_GVT_PCI_BAR_GTTMMIO].size -1);
203f1751362SChangbin Du intel_vgpu_write_pci_bar(vgpu, offset,
204f1751362SChangbin Du size >> (lo ? 0 : 32), lo);
2054d60c5fdSZhi Wang /*
206f1751362SChangbin Du * Untrap the BAR, since guest hasn't configured a
2074d60c5fdSZhi Wang * valid GPA
2084d60c5fdSZhi Wang */
209c977092aSChristoph Hellwig trap_gttmmio(vgpu, false);
2104d60c5fdSZhi Wang break;
211f1751362SChangbin Du case PCI_BASE_ADDRESS_2:
212f1751362SChangbin Du case PCI_BASE_ADDRESS_3:
213f1751362SChangbin Du size = ~(bars[INTEL_GVT_PCI_BAR_APERTURE].size -1);
214f1751362SChangbin Du intel_vgpu_write_pci_bar(vgpu, offset,
215f1751362SChangbin Du size >> (lo ? 0 : 32), lo);
216c977092aSChristoph Hellwig map_aperture(vgpu, false);
2174d60c5fdSZhi Wang break;
218f1751362SChangbin Du default:
219f1751362SChangbin Du /* Unimplemented BARs */
220f1751362SChangbin Du intel_vgpu_write_pci_bar(vgpu, offset, 0x0, false);
2214d60c5fdSZhi Wang }
2224d60c5fdSZhi Wang } else {
223f1751362SChangbin Du switch (offset) {
224f1751362SChangbin Du case PCI_BASE_ADDRESS_0:
225f1751362SChangbin Du case PCI_BASE_ADDRESS_1:
2264d60c5fdSZhi Wang /*
227f1751362SChangbin Du * Untrap the old BAR first, since guest has
2284d60c5fdSZhi Wang * re-configured the BAR
2294d60c5fdSZhi Wang */
230f1751362SChangbin Du trap_gttmmio(vgpu, false);
2314d60c5fdSZhi Wang intel_vgpu_write_pci_bar(vgpu, offset, new, lo);
232c977092aSChristoph Hellwig trap_gttmmio(vgpu, mmio_enabled);
2334d60c5fdSZhi Wang break;
234f1751362SChangbin Du case PCI_BASE_ADDRESS_2:
235f1751362SChangbin Du case PCI_BASE_ADDRESS_3:
236f1751362SChangbin Du map_aperture(vgpu, false);
237f1751362SChangbin Du intel_vgpu_write_pci_bar(vgpu, offset, new, lo);
238c977092aSChristoph Hellwig map_aperture(vgpu, mmio_enabled);
2394d60c5fdSZhi Wang break;
240f1751362SChangbin Du default:
241f1751362SChangbin Du intel_vgpu_write_pci_bar(vgpu, offset, new, lo);
2424d60c5fdSZhi Wang }
2434d60c5fdSZhi Wang }
2444d60c5fdSZhi Wang }
2454d60c5fdSZhi Wang
2464d60c5fdSZhi Wang /**
247*df947eb6SMauro Carvalho Chehab * intel_vgpu_emulate_cfg_write - emulate vGPU configuration space write
248a752b070SZhenyu Wang * @vgpu: target vgpu
249a752b070SZhenyu Wang * @offset: offset
250a752b070SZhenyu Wang * @p_data: write data ptr
251a752b070SZhenyu Wang * @bytes: number of bytes to write
2524d60c5fdSZhi Wang *
2534d60c5fdSZhi Wang * Returns:
2544d60c5fdSZhi Wang * Zero on success, negative error code if failed.
2554d60c5fdSZhi Wang */
intel_vgpu_emulate_cfg_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)2569ec1e66bSJike Song int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset,
2574d60c5fdSZhi Wang void *p_data, unsigned int bytes)
2584d60c5fdSZhi Wang {
259a61ac1e7SChris Wilson struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
2604d60c5fdSZhi Wang int ret;
2614d60c5fdSZhi Wang
26212d58619SPankaj Bharadiya if (drm_WARN_ON(&i915->drm, bytes > 4))
2634d60c5fdSZhi Wang return -EINVAL;
2644d60c5fdSZhi Wang
26512d58619SPankaj Bharadiya if (drm_WARN_ON(&i915->drm,
26612d58619SPankaj Bharadiya offset + bytes > vgpu->gvt->device_info.cfg_space_size))
2674d60c5fdSZhi Wang return -EINVAL;
2684d60c5fdSZhi Wang
2694d60c5fdSZhi Wang /* First check if it's PCI_COMMAND */
2704d60c5fdSZhi Wang if (IS_ALIGNED(offset, 2) && offset == PCI_COMMAND) {
27112d58619SPankaj Bharadiya if (drm_WARN_ON(&i915->drm, bytes > 2))
2724d60c5fdSZhi Wang return -EINVAL;
2734d60c5fdSZhi Wang return emulate_pci_command_write(vgpu, offset, p_data, bytes);
2744d60c5fdSZhi Wang }
2754d60c5fdSZhi Wang
2764d60c5fdSZhi Wang switch (rounddown(offset, 4)) {
277c4270d12SChangbin Du case PCI_ROM_ADDRESS:
27812d58619SPankaj Bharadiya if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4)))
279c4270d12SChangbin Du return -EINVAL;
280c4270d12SChangbin Du return emulate_pci_rom_bar_write(vgpu, offset, p_data, bytes);
281c4270d12SChangbin Du
282f1751362SChangbin Du case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_5:
28312d58619SPankaj Bharadiya if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4)))
2844d60c5fdSZhi Wang return -EINVAL;
285c977092aSChristoph Hellwig emulate_pci_bar_write(vgpu, offset, p_data, bytes);
286c977092aSChristoph Hellwig break;
2874d60c5fdSZhi Wang case INTEL_GVT_PCI_SWSCI:
28812d58619SPankaj Bharadiya if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4)))
2894d60c5fdSZhi Wang return -EINVAL;
2904d60c5fdSZhi Wang ret = intel_vgpu_emulate_opregion_request(vgpu, *(u32 *)p_data);
2914d60c5fdSZhi Wang if (ret)
2924d60c5fdSZhi Wang return ret;
2934d60c5fdSZhi Wang break;
2944d60c5fdSZhi Wang
2954d60c5fdSZhi Wang case INTEL_GVT_PCI_OPREGION:
29612d58619SPankaj Bharadiya if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4)))
2974d60c5fdSZhi Wang return -EINVAL;
2984dff110bSXiong Zhang ret = intel_vgpu_opregion_base_write_handler(vgpu,
2994dff110bSXiong Zhang *(u32 *)p_data);
3004d60c5fdSZhi Wang if (ret)
3014d60c5fdSZhi Wang return ret;
3024d60c5fdSZhi Wang
303c2e04fdaSChangbin Du vgpu_pci_cfg_mem_write(vgpu, offset, p_data, bytes);
3044d60c5fdSZhi Wang break;
3054d60c5fdSZhi Wang default:
306c2e04fdaSChangbin Du vgpu_pci_cfg_mem_write(vgpu, offset, p_data, bytes);
3074d60c5fdSZhi Wang break;
3084d60c5fdSZhi Wang }
3094d60c5fdSZhi Wang return 0;
3104d60c5fdSZhi Wang }
311536fc234SChangbin Du
312536fc234SChangbin Du /**
313536fc234SChangbin Du * intel_vgpu_init_cfg_space - init vGPU configuration space when create vGPU
314536fc234SChangbin Du *
315536fc234SChangbin Du * @vgpu: a vGPU
316536fc234SChangbin Du * @primary: is the vGPU presented as primary
317536fc234SChangbin Du *
318536fc234SChangbin Du */
intel_vgpu_init_cfg_space(struct intel_vgpu * vgpu,bool primary)319536fc234SChangbin Du void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu,
320536fc234SChangbin Du bool primary)
321536fc234SChangbin Du {
322536fc234SChangbin Du struct intel_gvt *gvt = vgpu->gvt;
3239ff06c38SThomas Zimmermann struct pci_dev *pdev = to_pci_dev(gvt->gt->i915->drm.dev);
324536fc234SChangbin Du const struct intel_gvt_device_info *info = &gvt->device_info;
325536fc234SChangbin Du u16 *gmch_ctl;
326ba25d977SColin Xu u8 next;
327536fc234SChangbin Du
328536fc234SChangbin Du memcpy(vgpu_cfg_space(vgpu), gvt->firmware.cfg_space,
329536fc234SChangbin Du info->cfg_space_size);
330536fc234SChangbin Du
331536fc234SChangbin Du if (!primary) {
332536fc234SChangbin Du vgpu_cfg_space(vgpu)[PCI_CLASS_DEVICE] =
333536fc234SChangbin Du INTEL_GVT_PCI_CLASS_VGA_OTHER;
334536fc234SChangbin Du vgpu_cfg_space(vgpu)[PCI_CLASS_PROG] =
335536fc234SChangbin Du INTEL_GVT_PCI_CLASS_VGA_OTHER;
336536fc234SChangbin Du }
337536fc234SChangbin Du
338536fc234SChangbin Du /* Show guest that there isn't any stolen memory.*/
339536fc234SChangbin Du gmch_ctl = (u16 *)(vgpu_cfg_space(vgpu) + INTEL_GVT_PCI_GMCH_CONTROL);
340536fc234SChangbin Du *gmch_ctl &= ~(BDW_GMCH_GMS_MASK << BDW_GMCH_GMS_SHIFT);
341536fc234SChangbin Du
342536fc234SChangbin Du intel_vgpu_write_pci_bar(vgpu, PCI_BASE_ADDRESS_2,
343536fc234SChangbin Du gvt_aperture_pa_base(gvt), true);
344536fc234SChangbin Du
345536fc234SChangbin Du vgpu_cfg_space(vgpu)[PCI_COMMAND] &= ~(PCI_COMMAND_IO
346536fc234SChangbin Du | PCI_COMMAND_MEMORY
347536fc234SChangbin Du | PCI_COMMAND_MASTER);
348536fc234SChangbin Du /*
349536fc234SChangbin Du * Clear the bar upper 32bit and let guest to assign the new value
350536fc234SChangbin Du */
351536fc234SChangbin Du memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_1, 0, 4);
352536fc234SChangbin Du memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_3, 0, 4);
353f1751362SChangbin Du memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_4, 0, 8);
354536fc234SChangbin Du memset(vgpu_cfg_space(vgpu) + INTEL_GVT_PCI_OPREGION, 0, 4);
355536fc234SChangbin Du
356f1751362SChangbin Du vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].size =
3576bba2b30SPiotr Piórkowski pci_resource_len(pdev, GEN4_GTTMMADR_BAR);
358f1751362SChangbin Du vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].size =
3596bba2b30SPiotr Piórkowski pci_resource_len(pdev, GEN4_GMADR_BAR);
360c4270d12SChangbin Du
361c4270d12SChangbin Du memset(vgpu_cfg_space(vgpu) + PCI_ROM_ADDRESS, 0, 4);
362ba25d977SColin Xu
363ba25d977SColin Xu /* PM Support */
364ba25d977SColin Xu vgpu->cfg_space.pmcsr_off = 0;
365ba25d977SColin Xu if (vgpu_cfg_space(vgpu)[PCI_STATUS] & PCI_STATUS_CAP_LIST) {
366ba25d977SColin Xu next = vgpu_cfg_space(vgpu)[PCI_CAPABILITY_LIST];
367ba25d977SColin Xu do {
368ba25d977SColin Xu if (vgpu_cfg_space(vgpu)[next + PCI_CAP_LIST_ID] == PCI_CAP_ID_PM) {
369ba25d977SColin Xu vgpu->cfg_space.pmcsr_off = next + PCI_PM_CTRL;
370ba25d977SColin Xu break;
371ba25d977SColin Xu }
372ba25d977SColin Xu next = vgpu_cfg_space(vgpu)[next + PCI_CAP_LIST_NEXT];
373ba25d977SColin Xu } while (next);
374ba25d977SColin Xu }
375536fc234SChangbin Du }
376c64ff6c7SChangbin Du
377c64ff6c7SChangbin Du /**
378c64ff6c7SChangbin Du * intel_vgpu_reset_cfg_space - reset vGPU configuration space
379c64ff6c7SChangbin Du *
380c64ff6c7SChangbin Du * @vgpu: a vGPU
381c64ff6c7SChangbin Du *
382c64ff6c7SChangbin Du */
intel_vgpu_reset_cfg_space(struct intel_vgpu * vgpu)383c64ff6c7SChangbin Du void intel_vgpu_reset_cfg_space(struct intel_vgpu *vgpu)
384c64ff6c7SChangbin Du {
385c64ff6c7SChangbin Du u8 cmd = vgpu_cfg_space(vgpu)[PCI_COMMAND];
386c64ff6c7SChangbin Du bool primary = vgpu_cfg_space(vgpu)[PCI_CLASS_DEVICE] !=
387c64ff6c7SChangbin Du INTEL_GVT_PCI_CLASS_VGA_OTHER;
388c64ff6c7SChangbin Du
389c64ff6c7SChangbin Du if (cmd & PCI_COMMAND_MEMORY) {
390c64ff6c7SChangbin Du trap_gttmmio(vgpu, false);
391c64ff6c7SChangbin Du map_aperture(vgpu, false);
392c64ff6c7SChangbin Du }
393c64ff6c7SChangbin Du
394c64ff6c7SChangbin Du /**
395c64ff6c7SChangbin Du * Currently we only do such reset when vGPU is not
396c64ff6c7SChangbin Du * owned by any VM, so we simply restore entire cfg
397c64ff6c7SChangbin Du * space to default value.
398c64ff6c7SChangbin Du */
399c64ff6c7SChangbin Du intel_vgpu_init_cfg_space(vgpu, primary);
400c64ff6c7SChangbin Du }
401