1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Kevin Tian <kevin.tian@intel.com> 25 * Dexuan Cui 26 * 27 * Contributors: 28 * Pei Zhang <pei.zhang@intel.com> 29 * Min He <min.he@intel.com> 30 * Niu Bing <bing.niu@intel.com> 31 * Yulei Zhang <yulei.zhang@intel.com> 32 * Zhenyu Wang <zhenyuw@linux.intel.com> 33 * Zhi Wang <zhi.a.wang@intel.com> 34 * 35 */ 36 37 #include "i915_drv.h" 38 #include "gvt.h" 39 40 #define MB_TO_BYTES(mb) ((mb) << 20ULL) 41 #define BYTES_TO_MB(b) ((b) >> 20ULL) 42 43 #define HOST_LOW_GM_SIZE MB_TO_BYTES(128) 44 #define HOST_HIGH_GM_SIZE MB_TO_BYTES(384) 45 #define HOST_FENCE 4 46 47 static int alloc_gm(struct intel_vgpu *vgpu, bool high_gm) 48 { 49 struct intel_gvt *gvt = vgpu->gvt; 50 struct drm_i915_private *dev_priv = gvt->dev_priv; 51 u32 alloc_flag, search_flag; 52 u64 start, end, size; 53 struct drm_mm_node *node; 54 int retried = 0; 55 int ret; 56 57 if (high_gm) { 58 search_flag = DRM_MM_SEARCH_BELOW; 59 alloc_flag = DRM_MM_CREATE_TOP; 60 node = &vgpu->gm.high_gm_node; 61 size = vgpu_hidden_sz(vgpu); 62 start = gvt_hidden_gmadr_base(gvt); 63 end = gvt_hidden_gmadr_end(gvt); 64 } else { 65 search_flag = DRM_MM_SEARCH_DEFAULT; 66 alloc_flag = DRM_MM_CREATE_DEFAULT; 67 node = &vgpu->gm.low_gm_node; 68 size = vgpu_aperture_sz(vgpu); 69 start = gvt_aperture_gmadr_base(gvt); 70 end = gvt_aperture_gmadr_end(gvt); 71 } 72 73 mutex_lock(&dev_priv->drm.struct_mutex); 74 search_again: 75 ret = drm_mm_insert_node_in_range_generic(&dev_priv->ggtt.base.mm, 76 node, size, 4096, 0, 77 start, end, search_flag, 78 alloc_flag); 79 if (ret) { 80 ret = i915_gem_evict_something(&dev_priv->ggtt.base, 81 size, 4096, 0, start, end, 0); 82 if (ret == 0 && ++retried < 3) 83 goto search_again; 84 85 gvt_err("fail to alloc %s gm space from host, retried %d\n", 86 high_gm ? "high" : "low", retried); 87 } 88 mutex_unlock(&dev_priv->drm.struct_mutex); 89 return ret; 90 } 91 92 static int alloc_vgpu_gm(struct intel_vgpu *vgpu) 93 { 94 struct intel_gvt *gvt = vgpu->gvt; 95 struct drm_i915_private *dev_priv = gvt->dev_priv; 96 int ret; 97 98 ret = alloc_gm(vgpu, false); 99 if (ret) 100 return ret; 101 102 ret = alloc_gm(vgpu, true); 103 if (ret) 104 goto out_free_aperture; 105 106 gvt_dbg_core("vgpu%d: alloc low GM start %llx size %llx\n", vgpu->id, 107 vgpu_aperture_offset(vgpu), vgpu_aperture_sz(vgpu)); 108 109 gvt_dbg_core("vgpu%d: alloc high GM start %llx size %llx\n", vgpu->id, 110 vgpu_hidden_offset(vgpu), vgpu_hidden_sz(vgpu)); 111 112 return 0; 113 out_free_aperture: 114 mutex_lock(&dev_priv->drm.struct_mutex); 115 drm_mm_remove_node(&vgpu->gm.low_gm_node); 116 mutex_unlock(&dev_priv->drm.struct_mutex); 117 return ret; 118 } 119 120 static void free_vgpu_gm(struct intel_vgpu *vgpu) 121 { 122 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 123 124 mutex_lock(&dev_priv->drm.struct_mutex); 125 drm_mm_remove_node(&vgpu->gm.low_gm_node); 126 drm_mm_remove_node(&vgpu->gm.high_gm_node); 127 mutex_unlock(&dev_priv->drm.struct_mutex); 128 } 129 130 /** 131 * intel_vgpu_write_fence - write fence registers owned by a vGPU 132 * @vgpu: vGPU instance 133 * @fence: vGPU fence register number 134 * @value: Fence register value to be written 135 * 136 * This function is used to write fence registers owned by a vGPU. The vGPU 137 * fence register number will be translated into HW fence register number. 138 * 139 */ 140 void intel_vgpu_write_fence(struct intel_vgpu *vgpu, 141 u32 fence, u64 value) 142 { 143 struct intel_gvt *gvt = vgpu->gvt; 144 struct drm_i915_private *dev_priv = gvt->dev_priv; 145 struct drm_i915_fence_reg *reg; 146 i915_reg_t fence_reg_lo, fence_reg_hi; 147 148 assert_rpm_wakelock_held(dev_priv); 149 150 if (WARN_ON(fence > vgpu_fence_sz(vgpu))) 151 return; 152 153 reg = vgpu->fence.regs[fence]; 154 if (WARN_ON(!reg)) 155 return; 156 157 fence_reg_lo = FENCE_REG_GEN6_LO(reg->id); 158 fence_reg_hi = FENCE_REG_GEN6_HI(reg->id); 159 160 I915_WRITE(fence_reg_lo, 0); 161 POSTING_READ(fence_reg_lo); 162 163 I915_WRITE(fence_reg_hi, upper_32_bits(value)); 164 I915_WRITE(fence_reg_lo, lower_32_bits(value)); 165 POSTING_READ(fence_reg_lo); 166 } 167 168 static void free_vgpu_fence(struct intel_vgpu *vgpu) 169 { 170 struct intel_gvt *gvt = vgpu->gvt; 171 struct drm_i915_private *dev_priv = gvt->dev_priv; 172 struct drm_i915_fence_reg *reg; 173 u32 i; 174 175 if (WARN_ON(!vgpu_fence_sz(vgpu))) 176 return; 177 178 intel_runtime_pm_get(dev_priv); 179 180 mutex_lock(&dev_priv->drm.struct_mutex); 181 for (i = 0; i < vgpu_fence_sz(vgpu); i++) { 182 reg = vgpu->fence.regs[i]; 183 intel_vgpu_write_fence(vgpu, i, 0); 184 list_add_tail(®->link, 185 &dev_priv->mm.fence_list); 186 } 187 mutex_unlock(&dev_priv->drm.struct_mutex); 188 189 intel_runtime_pm_put(dev_priv); 190 } 191 192 static int alloc_vgpu_fence(struct intel_vgpu *vgpu) 193 { 194 struct intel_gvt *gvt = vgpu->gvt; 195 struct drm_i915_private *dev_priv = gvt->dev_priv; 196 struct drm_i915_fence_reg *reg; 197 int i; 198 struct list_head *pos, *q; 199 200 intel_runtime_pm_get(dev_priv); 201 202 /* Request fences from host */ 203 mutex_lock(&dev_priv->drm.struct_mutex); 204 i = 0; 205 list_for_each_safe(pos, q, &dev_priv->mm.fence_list) { 206 reg = list_entry(pos, struct drm_i915_fence_reg, link); 207 if (reg->pin_count || reg->vma) 208 continue; 209 list_del(pos); 210 vgpu->fence.regs[i] = reg; 211 intel_vgpu_write_fence(vgpu, i, 0); 212 if (++i == vgpu_fence_sz(vgpu)) 213 break; 214 } 215 if (i != vgpu_fence_sz(vgpu)) 216 goto out_free_fence; 217 218 mutex_unlock(&dev_priv->drm.struct_mutex); 219 intel_runtime_pm_put(dev_priv); 220 return 0; 221 out_free_fence: 222 /* Return fences to host, if fail */ 223 for (i = 0; i < vgpu_fence_sz(vgpu); i++) { 224 reg = vgpu->fence.regs[i]; 225 if (!reg) 226 continue; 227 list_add_tail(®->link, 228 &dev_priv->mm.fence_list); 229 } 230 mutex_unlock(&dev_priv->drm.struct_mutex); 231 intel_runtime_pm_put(dev_priv); 232 return -ENOSPC; 233 } 234 235 static void free_resource(struct intel_vgpu *vgpu) 236 { 237 struct intel_gvt *gvt = vgpu->gvt; 238 239 gvt->gm.vgpu_allocated_low_gm_size -= vgpu_aperture_sz(vgpu); 240 gvt->gm.vgpu_allocated_high_gm_size -= vgpu_hidden_sz(vgpu); 241 gvt->fence.vgpu_allocated_fence_num -= vgpu_fence_sz(vgpu); 242 } 243 244 static int alloc_resource(struct intel_vgpu *vgpu, 245 struct intel_vgpu_creation_params *param) 246 { 247 struct intel_gvt *gvt = vgpu->gvt; 248 unsigned long request, avail, max, taken; 249 const char *item; 250 251 if (!param->low_gm_sz || !param->high_gm_sz || !param->fence_sz) { 252 gvt_err("Invalid vGPU creation params\n"); 253 return -EINVAL; 254 } 255 256 item = "low GM space"; 257 max = gvt_aperture_sz(gvt) - HOST_LOW_GM_SIZE; 258 taken = gvt->gm.vgpu_allocated_low_gm_size; 259 avail = max - taken; 260 request = MB_TO_BYTES(param->low_gm_sz); 261 262 if (request > avail) 263 goto no_enough_resource; 264 265 vgpu_aperture_sz(vgpu) = request; 266 267 item = "high GM space"; 268 max = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE; 269 taken = gvt->gm.vgpu_allocated_high_gm_size; 270 avail = max - taken; 271 request = MB_TO_BYTES(param->high_gm_sz); 272 273 if (request > avail) 274 goto no_enough_resource; 275 276 vgpu_hidden_sz(vgpu) = request; 277 278 item = "fence"; 279 max = gvt_fence_sz(gvt) - HOST_FENCE; 280 taken = gvt->fence.vgpu_allocated_fence_num; 281 avail = max - taken; 282 request = param->fence_sz; 283 284 if (request > avail) 285 goto no_enough_resource; 286 287 vgpu_fence_sz(vgpu) = request; 288 289 gvt->gm.vgpu_allocated_low_gm_size += MB_TO_BYTES(param->low_gm_sz); 290 gvt->gm.vgpu_allocated_high_gm_size += MB_TO_BYTES(param->high_gm_sz); 291 gvt->fence.vgpu_allocated_fence_num += param->fence_sz; 292 return 0; 293 294 no_enough_resource: 295 gvt_err("vgpu%d: fail to allocate resource %s\n", vgpu->id, item); 296 gvt_err("vgpu%d: request %luMB avail %luMB max %luMB taken %luMB\n", 297 vgpu->id, BYTES_TO_MB(request), BYTES_TO_MB(avail), 298 BYTES_TO_MB(max), BYTES_TO_MB(taken)); 299 return -ENOSPC; 300 } 301 302 /** 303 * inte_gvt_free_vgpu_resource - free HW resource owned by a vGPU 304 * @vgpu: a vGPU 305 * 306 * This function is used to free the HW resource owned by a vGPU. 307 * 308 */ 309 void intel_vgpu_free_resource(struct intel_vgpu *vgpu) 310 { 311 free_vgpu_gm(vgpu); 312 free_vgpu_fence(vgpu); 313 free_resource(vgpu); 314 } 315 316 /** 317 * intel_alloc_vgpu_resource - allocate HW resource for a vGPU 318 * @vgpu: vGPU 319 * @param: vGPU creation params 320 * 321 * This function is used to allocate HW resource for a vGPU. User specifies 322 * the resource configuration through the creation params. 323 * 324 * Returns: 325 * zero on success, negative error code if failed. 326 * 327 */ 328 int intel_vgpu_alloc_resource(struct intel_vgpu *vgpu, 329 struct intel_vgpu_creation_params *param) 330 { 331 int ret; 332 333 ret = alloc_resource(vgpu, param); 334 if (ret) 335 return ret; 336 337 ret = alloc_vgpu_gm(vgpu); 338 if (ret) 339 goto out_free_resource; 340 341 ret = alloc_vgpu_fence(vgpu); 342 if (ret) 343 goto out_free_vgpu_gm; 344 345 return 0; 346 347 out_free_vgpu_gm: 348 free_vgpu_gm(vgpu); 349 out_free_resource: 350 free_resource(vgpu); 351 return ret; 352 } 353