128a60deeSZhi Wang /*
228a60deeSZhi Wang * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
328a60deeSZhi Wang *
428a60deeSZhi Wang * Permission is hereby granted, free of charge, to any person obtaining a
528a60deeSZhi Wang * copy of this software and associated documentation files (the "Software"),
628a60deeSZhi Wang * to deal in the Software without restriction, including without limitation
728a60deeSZhi Wang * the rights to use, copy, modify, merge, publish, distribute, sublicense,
828a60deeSZhi Wang * and/or sell copies of the Software, and to permit persons to whom the
928a60deeSZhi Wang * Software is furnished to do so, subject to the following conditions:
1028a60deeSZhi Wang *
1128a60deeSZhi Wang * The above copyright notice and this permission notice (including the next
1228a60deeSZhi Wang * paragraph) shall be included in all copies or substantial portions of the
1328a60deeSZhi Wang * Software.
1428a60deeSZhi Wang *
1528a60deeSZhi Wang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
1628a60deeSZhi Wang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
1728a60deeSZhi Wang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
1828a60deeSZhi Wang * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
1928a60deeSZhi Wang * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
2028a60deeSZhi Wang * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
2128a60deeSZhi Wang * SOFTWARE.
2228a60deeSZhi Wang *
2328a60deeSZhi Wang * Authors:
2428a60deeSZhi Wang * Kevin Tian <kevin.tian@intel.com>
2528a60deeSZhi Wang * Dexuan Cui
2628a60deeSZhi Wang *
2728a60deeSZhi Wang * Contributors:
2828a60deeSZhi Wang * Pei Zhang <pei.zhang@intel.com>
2928a60deeSZhi Wang * Min He <min.he@intel.com>
3028a60deeSZhi Wang * Niu Bing <bing.niu@intel.com>
3128a60deeSZhi Wang * Yulei Zhang <yulei.zhang@intel.com>
3228a60deeSZhi Wang * Zhenyu Wang <zhenyuw@linux.intel.com>
3328a60deeSZhi Wang * Zhi Wang <zhi.a.wang@intel.com>
3428a60deeSZhi Wang *
3528a60deeSZhi Wang */
3628a60deeSZhi Wang
3728a60deeSZhi Wang #include "i915_drv.h"
38ce2fce25SMatt Roper #include "i915_reg.h"
39f899f786SChris Wilson #include "gt/intel_ggtt_fencing.h"
40feddf6e8SZhenyu Wang #include "gvt.h"
4128a60deeSZhi Wang
alloc_gm(struct intel_vgpu * vgpu,bool high_gm)4228a60deeSZhi Wang static int alloc_gm(struct intel_vgpu *vgpu, bool high_gm)
4328a60deeSZhi Wang {
4428a60deeSZhi Wang struct intel_gvt *gvt = vgpu->gvt;
45a61ac1e7SChris Wilson struct intel_gt *gt = gvt->gt;
46e007b19dSChris Wilson unsigned int flags;
4728a60deeSZhi Wang u64 start, end, size;
4828a60deeSZhi Wang struct drm_mm_node *node;
4928a60deeSZhi Wang int ret;
5028a60deeSZhi Wang
5128a60deeSZhi Wang if (high_gm) {
5228a60deeSZhi Wang node = &vgpu->gm.high_gm_node;
5328a60deeSZhi Wang size = vgpu_hidden_sz(vgpu);
545b3cac19SZhenyu Wang start = ALIGN(gvt_hidden_gmadr_base(gvt), I915_GTT_PAGE_SIZE);
555b3cac19SZhenyu Wang end = ALIGN(gvt_hidden_gmadr_end(gvt), I915_GTT_PAGE_SIZE);
56e007b19dSChris Wilson flags = PIN_HIGH;
5728a60deeSZhi Wang } else {
5828a60deeSZhi Wang node = &vgpu->gm.low_gm_node;
5928a60deeSZhi Wang size = vgpu_aperture_sz(vgpu);
605b3cac19SZhenyu Wang start = ALIGN(gvt_aperture_gmadr_base(gvt), I915_GTT_PAGE_SIZE);
615b3cac19SZhenyu Wang end = ALIGN(gvt_aperture_gmadr_end(gvt), I915_GTT_PAGE_SIZE);
62e007b19dSChris Wilson flags = PIN_MAPPABLE;
6328a60deeSZhi Wang }
6428a60deeSZhi Wang
65a61ac1e7SChris Wilson mutex_lock(>->ggtt->vm.mutex);
66a61ac1e7SChris Wilson mmio_hw_access_pre(gt);
677e00897bSMaarten Lankhorst ret = i915_gem_gtt_insert(>->ggtt->vm, NULL, node,
685b3cac19SZhenyu Wang size, I915_GTT_PAGE_SIZE,
695b3cac19SZhenyu Wang I915_COLOR_UNEVICTABLE,
70e007b19dSChris Wilson start, end, flags);
71a61ac1e7SChris Wilson mmio_hw_access_post(gt);
72a61ac1e7SChris Wilson mutex_unlock(>->ggtt->vm.mutex);
73e007b19dSChris Wilson if (ret)
74e007b19dSChris Wilson gvt_err("fail to alloc %s gm space from host\n",
75e007b19dSChris Wilson high_gm ? "high" : "low");
76e007b19dSChris Wilson
7728a60deeSZhi Wang return ret;
7828a60deeSZhi Wang }
7928a60deeSZhi Wang
alloc_vgpu_gm(struct intel_vgpu * vgpu)8028a60deeSZhi Wang static int alloc_vgpu_gm(struct intel_vgpu *vgpu)
8128a60deeSZhi Wang {
8228a60deeSZhi Wang struct intel_gvt *gvt = vgpu->gvt;
83a61ac1e7SChris Wilson struct intel_gt *gt = gvt->gt;
8428a60deeSZhi Wang int ret;
8528a60deeSZhi Wang
8628a60deeSZhi Wang ret = alloc_gm(vgpu, false);
8728a60deeSZhi Wang if (ret)
8828a60deeSZhi Wang return ret;
8928a60deeSZhi Wang
9028a60deeSZhi Wang ret = alloc_gm(vgpu, true);
9128a60deeSZhi Wang if (ret)
9228a60deeSZhi Wang goto out_free_aperture;
9328a60deeSZhi Wang
9428a60deeSZhi Wang gvt_dbg_core("vgpu%d: alloc low GM start %llx size %llx\n", vgpu->id,
9528a60deeSZhi Wang vgpu_aperture_offset(vgpu), vgpu_aperture_sz(vgpu));
9628a60deeSZhi Wang
9728a60deeSZhi Wang gvt_dbg_core("vgpu%d: alloc high GM start %llx size %llx\n", vgpu->id,
9828a60deeSZhi Wang vgpu_hidden_offset(vgpu), vgpu_hidden_sz(vgpu));
9928a60deeSZhi Wang
10028a60deeSZhi Wang return 0;
10128a60deeSZhi Wang out_free_aperture:
102a61ac1e7SChris Wilson mutex_lock(>->ggtt->vm.mutex);
10328a60deeSZhi Wang drm_mm_remove_node(&vgpu->gm.low_gm_node);
104a61ac1e7SChris Wilson mutex_unlock(>->ggtt->vm.mutex);
10528a60deeSZhi Wang return ret;
10628a60deeSZhi Wang }
10728a60deeSZhi Wang
free_vgpu_gm(struct intel_vgpu * vgpu)10828a60deeSZhi Wang static void free_vgpu_gm(struct intel_vgpu *vgpu)
10928a60deeSZhi Wang {
110a61ac1e7SChris Wilson struct intel_gvt *gvt = vgpu->gvt;
111a61ac1e7SChris Wilson struct intel_gt *gt = gvt->gt;
11228a60deeSZhi Wang
113a61ac1e7SChris Wilson mutex_lock(>->ggtt->vm.mutex);
11428a60deeSZhi Wang drm_mm_remove_node(&vgpu->gm.low_gm_node);
11528a60deeSZhi Wang drm_mm_remove_node(&vgpu->gm.high_gm_node);
116a61ac1e7SChris Wilson mutex_unlock(>->ggtt->vm.mutex);
11728a60deeSZhi Wang }
11828a60deeSZhi Wang
11928a60deeSZhi Wang /**
12028a60deeSZhi Wang * intel_vgpu_write_fence - write fence registers owned by a vGPU
12128a60deeSZhi Wang * @vgpu: vGPU instance
12228a60deeSZhi Wang * @fence: vGPU fence register number
12328a60deeSZhi Wang * @value: Fence register value to be written
12428a60deeSZhi Wang *
12528a60deeSZhi Wang * This function is used to write fence registers owned by a vGPU. The vGPU
12628a60deeSZhi Wang * fence register number will be translated into HW fence register number.
12728a60deeSZhi Wang *
12828a60deeSZhi Wang */
intel_vgpu_write_fence(struct intel_vgpu * vgpu,u32 fence,u64 value)12928a60deeSZhi Wang void intel_vgpu_write_fence(struct intel_vgpu *vgpu,
13028a60deeSZhi Wang u32 fence, u64 value)
13128a60deeSZhi Wang {
13228a60deeSZhi Wang struct intel_gvt *gvt = vgpu->gvt;
133a61ac1e7SChris Wilson struct drm_i915_private *i915 = gvt->gt->i915;
134a61ac1e7SChris Wilson struct intel_uncore *uncore = gvt->gt->uncore;
1350cf289bdSChris Wilson struct i915_fence_reg *reg;
13628a60deeSZhi Wang i915_reg_t fence_reg_lo, fence_reg_hi;
13728a60deeSZhi Wang
138a61ac1e7SChris Wilson assert_rpm_wakelock_held(uncore->rpm);
13975ea10daSChris Wilson
140a61ac1e7SChris Wilson if (drm_WARN_ON(&i915->drm, fence >= vgpu_fence_sz(vgpu)))
14128a60deeSZhi Wang return;
14228a60deeSZhi Wang
14328a60deeSZhi Wang reg = vgpu->fence.regs[fence];
144a61ac1e7SChris Wilson if (drm_WARN_ON(&i915->drm, !reg))
14528a60deeSZhi Wang return;
14628a60deeSZhi Wang
14728a60deeSZhi Wang fence_reg_lo = FENCE_REG_GEN6_LO(reg->id);
14828a60deeSZhi Wang fence_reg_hi = FENCE_REG_GEN6_HI(reg->id);
14928a60deeSZhi Wang
150a61ac1e7SChris Wilson intel_uncore_write(uncore, fence_reg_lo, 0);
151a61ac1e7SChris Wilson intel_uncore_posting_read(uncore, fence_reg_lo);
15228a60deeSZhi Wang
153a61ac1e7SChris Wilson intel_uncore_write(uncore, fence_reg_hi, upper_32_bits(value));
154a61ac1e7SChris Wilson intel_uncore_write(uncore, fence_reg_lo, lower_32_bits(value));
155a61ac1e7SChris Wilson intel_uncore_posting_read(uncore, fence_reg_lo);
15628a60deeSZhi Wang }
15728a60deeSZhi Wang
_clear_vgpu_fence(struct intel_vgpu * vgpu)158d22a48bfSChangbin Du static void _clear_vgpu_fence(struct intel_vgpu *vgpu)
159d22a48bfSChangbin Du {
160d22a48bfSChangbin Du int i;
161d22a48bfSChangbin Du
162d22a48bfSChangbin Du for (i = 0; i < vgpu_fence_sz(vgpu); i++)
163d22a48bfSChangbin Du intel_vgpu_write_fence(vgpu, i, 0);
164d22a48bfSChangbin Du }
165d22a48bfSChangbin Du
free_vgpu_fence(struct intel_vgpu * vgpu)16628a60deeSZhi Wang static void free_vgpu_fence(struct intel_vgpu *vgpu)
16728a60deeSZhi Wang {
16828a60deeSZhi Wang struct intel_gvt *gvt = vgpu->gvt;
169a61ac1e7SChris Wilson struct intel_uncore *uncore = gvt->gt->uncore;
1700cf289bdSChris Wilson struct i915_fence_reg *reg;
171a61ac1e7SChris Wilson intel_wakeref_t wakeref;
17228a60deeSZhi Wang u32 i;
17328a60deeSZhi Wang
174a61ac1e7SChris Wilson if (drm_WARN_ON(&gvt->gt->i915->drm, !vgpu_fence_sz(vgpu)))
17528a60deeSZhi Wang return;
17628a60deeSZhi Wang
177a61ac1e7SChris Wilson wakeref = intel_runtime_pm_get(uncore->rpm);
17875ea10daSChris Wilson
179a61ac1e7SChris Wilson mutex_lock(&gvt->gt->ggtt->vm.mutex);
180d22a48bfSChangbin Du _clear_vgpu_fence(vgpu);
18128a60deeSZhi Wang for (i = 0; i < vgpu_fence_sz(vgpu); i++) {
18228a60deeSZhi Wang reg = vgpu->fence.regs[i];
183969b0950SChangbin Du i915_unreserve_fence(reg);
184969b0950SChangbin Du vgpu->fence.regs[i] = NULL;
18528a60deeSZhi Wang }
186a61ac1e7SChris Wilson mutex_unlock(&gvt->gt->ggtt->vm.mutex);
18775ea10daSChris Wilson
188a61ac1e7SChris Wilson intel_runtime_pm_put(uncore->rpm, wakeref);
18928a60deeSZhi Wang }
19028a60deeSZhi Wang
alloc_vgpu_fence(struct intel_vgpu * vgpu)19128a60deeSZhi Wang static int alloc_vgpu_fence(struct intel_vgpu *vgpu)
19228a60deeSZhi Wang {
19328a60deeSZhi Wang struct intel_gvt *gvt = vgpu->gvt;
194a61ac1e7SChris Wilson struct intel_uncore *uncore = gvt->gt->uncore;
1950cf289bdSChris Wilson struct i915_fence_reg *reg;
196a61ac1e7SChris Wilson intel_wakeref_t wakeref;
19728a60deeSZhi Wang int i;
19828a60deeSZhi Wang
199a61ac1e7SChris Wilson wakeref = intel_runtime_pm_get(uncore->rpm);
20075ea10daSChris Wilson
20128a60deeSZhi Wang /* Request fences from host */
202a61ac1e7SChris Wilson mutex_lock(&gvt->gt->ggtt->vm.mutex);
203969b0950SChangbin Du
204969b0950SChangbin Du for (i = 0; i < vgpu_fence_sz(vgpu); i++) {
205a61ac1e7SChris Wilson reg = i915_reserve_fence(gvt->gt->ggtt);
206969b0950SChangbin Du if (IS_ERR(reg))
20728a60deeSZhi Wang goto out_free_fence;
20828a60deeSZhi Wang
209969b0950SChangbin Du vgpu->fence.regs[i] = reg;
210969b0950SChangbin Du }
211969b0950SChangbin Du
212d22a48bfSChangbin Du _clear_vgpu_fence(vgpu);
213d22a48bfSChangbin Du
214a61ac1e7SChris Wilson mutex_unlock(&gvt->gt->ggtt->vm.mutex);
215a61ac1e7SChris Wilson intel_runtime_pm_put(uncore->rpm, wakeref);
21628a60deeSZhi Wang return 0;
217a61ac1e7SChris Wilson
21828a60deeSZhi Wang out_free_fence:
219969b0950SChangbin Du gvt_vgpu_err("Failed to alloc fences\n");
22028a60deeSZhi Wang /* Return fences to host, if fail */
22128a60deeSZhi Wang for (i = 0; i < vgpu_fence_sz(vgpu); i++) {
22228a60deeSZhi Wang reg = vgpu->fence.regs[i];
22328a60deeSZhi Wang if (!reg)
22428a60deeSZhi Wang continue;
225969b0950SChangbin Du i915_unreserve_fence(reg);
226969b0950SChangbin Du vgpu->fence.regs[i] = NULL;
22728a60deeSZhi Wang }
228a61ac1e7SChris Wilson mutex_unlock(&gvt->gt->ggtt->vm.mutex);
229a61ac1e7SChris Wilson intel_runtime_pm_put_unchecked(uncore->rpm);
23028a60deeSZhi Wang return -ENOSPC;
23128a60deeSZhi Wang }
23228a60deeSZhi Wang
free_resource(struct intel_vgpu * vgpu)23328a60deeSZhi Wang static void free_resource(struct intel_vgpu *vgpu)
23428a60deeSZhi Wang {
23528a60deeSZhi Wang struct intel_gvt *gvt = vgpu->gvt;
23628a60deeSZhi Wang
23728a60deeSZhi Wang gvt->gm.vgpu_allocated_low_gm_size -= vgpu_aperture_sz(vgpu);
23828a60deeSZhi Wang gvt->gm.vgpu_allocated_high_gm_size -= vgpu_hidden_sz(vgpu);
23928a60deeSZhi Wang gvt->fence.vgpu_allocated_fence_num -= vgpu_fence_sz(vgpu);
24028a60deeSZhi Wang }
24128a60deeSZhi Wang
alloc_resource(struct intel_vgpu * vgpu,const struct intel_vgpu_config * conf)24228a60deeSZhi Wang static int alloc_resource(struct intel_vgpu *vgpu,
2431aa3834fSChristoph Hellwig const struct intel_vgpu_config *conf)
24428a60deeSZhi Wang {
24528a60deeSZhi Wang struct intel_gvt *gvt = vgpu->gvt;
24628a60deeSZhi Wang unsigned long request, avail, max, taken;
24728a60deeSZhi Wang const char *item;
24828a60deeSZhi Wang
2491aa3834fSChristoph Hellwig if (!conf->low_mm || !conf->high_mm || !conf->fence) {
250695fbc08STina Zhang gvt_vgpu_err("Invalid vGPU creation params\n");
25128a60deeSZhi Wang return -EINVAL;
25228a60deeSZhi Wang }
25328a60deeSZhi Wang
25428a60deeSZhi Wang item = "low GM space";
25528a60deeSZhi Wang max = gvt_aperture_sz(gvt) - HOST_LOW_GM_SIZE;
25628a60deeSZhi Wang taken = gvt->gm.vgpu_allocated_low_gm_size;
25728a60deeSZhi Wang avail = max - taken;
2581aa3834fSChristoph Hellwig request = conf->low_mm;
25928a60deeSZhi Wang
26028a60deeSZhi Wang if (request > avail)
26128a60deeSZhi Wang goto no_enough_resource;
26228a60deeSZhi Wang
2635b3cac19SZhenyu Wang vgpu_aperture_sz(vgpu) = ALIGN(request, I915_GTT_PAGE_SIZE);
26428a60deeSZhi Wang
26528a60deeSZhi Wang item = "high GM space";
26628a60deeSZhi Wang max = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE;
26728a60deeSZhi Wang taken = gvt->gm.vgpu_allocated_high_gm_size;
26828a60deeSZhi Wang avail = max - taken;
2691aa3834fSChristoph Hellwig request = conf->high_mm;
27028a60deeSZhi Wang
27128a60deeSZhi Wang if (request > avail)
27228a60deeSZhi Wang goto no_enough_resource;
27328a60deeSZhi Wang
2745b3cac19SZhenyu Wang vgpu_hidden_sz(vgpu) = ALIGN(request, I915_GTT_PAGE_SIZE);
27528a60deeSZhi Wang
27628a60deeSZhi Wang item = "fence";
27728a60deeSZhi Wang max = gvt_fence_sz(gvt) - HOST_FENCE;
27828a60deeSZhi Wang taken = gvt->fence.vgpu_allocated_fence_num;
27928a60deeSZhi Wang avail = max - taken;
2801aa3834fSChristoph Hellwig request = conf->fence;
28128a60deeSZhi Wang
28228a60deeSZhi Wang if (request > avail)
28328a60deeSZhi Wang goto no_enough_resource;
28428a60deeSZhi Wang
28528a60deeSZhi Wang vgpu_fence_sz(vgpu) = request;
28628a60deeSZhi Wang
2871aa3834fSChristoph Hellwig gvt->gm.vgpu_allocated_low_gm_size += conf->low_mm;
2881aa3834fSChristoph Hellwig gvt->gm.vgpu_allocated_high_gm_size += conf->high_mm;
2891aa3834fSChristoph Hellwig gvt->fence.vgpu_allocated_fence_num += conf->fence;
29028a60deeSZhi Wang return 0;
29128a60deeSZhi Wang
29228a60deeSZhi Wang no_enough_resource:
2934cf196ebSChuanxiao Dong gvt_err("fail to allocate resource %s\n", item);
2944cf196ebSChuanxiao Dong gvt_err("request %luMB avail %luMB max %luMB taken %luMB\n",
295695fbc08STina Zhang BYTES_TO_MB(request), BYTES_TO_MB(avail),
29628a60deeSZhi Wang BYTES_TO_MB(max), BYTES_TO_MB(taken));
29728a60deeSZhi Wang return -ENOSPC;
29828a60deeSZhi Wang }
29928a60deeSZhi Wang
30028a60deeSZhi Wang /**
3010f761f57SJiapeng Chong * intel_vgpu_free_resource() - free HW resource owned by a vGPU
30228a60deeSZhi Wang * @vgpu: a vGPU
30328a60deeSZhi Wang *
30428a60deeSZhi Wang * This function is used to free the HW resource owned by a vGPU.
30528a60deeSZhi Wang *
30628a60deeSZhi Wang */
intel_vgpu_free_resource(struct intel_vgpu * vgpu)30728a60deeSZhi Wang void intel_vgpu_free_resource(struct intel_vgpu *vgpu)
30828a60deeSZhi Wang {
30928a60deeSZhi Wang free_vgpu_gm(vgpu);
31028a60deeSZhi Wang free_vgpu_fence(vgpu);
31128a60deeSZhi Wang free_resource(vgpu);
31228a60deeSZhi Wang }
31328a60deeSZhi Wang
31428a60deeSZhi Wang /**
315d22a48bfSChangbin Du * intel_vgpu_reset_resource - reset resource state owned by a vGPU
316d22a48bfSChangbin Du * @vgpu: a vGPU
317d22a48bfSChangbin Du *
318d22a48bfSChangbin Du * This function is used to reset resource state owned by a vGPU.
319d22a48bfSChangbin Du *
320d22a48bfSChangbin Du */
intel_vgpu_reset_resource(struct intel_vgpu * vgpu)321d22a48bfSChangbin Du void intel_vgpu_reset_resource(struct intel_vgpu *vgpu)
322d22a48bfSChangbin Du {
323a61ac1e7SChris Wilson struct intel_gvt *gvt = vgpu->gvt;
324a61ac1e7SChris Wilson intel_wakeref_t wakeref;
325d22a48bfSChangbin Du
326a61ac1e7SChris Wilson with_intel_runtime_pm(gvt->gt->uncore->rpm, wakeref)
327d22a48bfSChangbin Du _clear_vgpu_fence(vgpu);
328d22a48bfSChangbin Du }
329d22a48bfSChangbin Du
330d22a48bfSChangbin Du /**
3310f761f57SJiapeng Chong * intel_vgpu_alloc_resource() - allocate HW resource for a vGPU
33228a60deeSZhi Wang * @vgpu: vGPU
333*67f2dd9fSJani Nikula * @conf: vGPU creation params
33428a60deeSZhi Wang *
33528a60deeSZhi Wang * This function is used to allocate HW resource for a vGPU. User specifies
33628a60deeSZhi Wang * the resource configuration through the creation params.
33728a60deeSZhi Wang *
33828a60deeSZhi Wang * Returns:
33928a60deeSZhi Wang * zero on success, negative error code if failed.
34028a60deeSZhi Wang *
34128a60deeSZhi Wang */
intel_vgpu_alloc_resource(struct intel_vgpu * vgpu,const struct intel_vgpu_config * conf)34228a60deeSZhi Wang int intel_vgpu_alloc_resource(struct intel_vgpu *vgpu,
3431aa3834fSChristoph Hellwig const struct intel_vgpu_config *conf)
34428a60deeSZhi Wang {
34528a60deeSZhi Wang int ret;
34628a60deeSZhi Wang
3471aa3834fSChristoph Hellwig ret = alloc_resource(vgpu, conf);
34828a60deeSZhi Wang if (ret)
34928a60deeSZhi Wang return ret;
35028a60deeSZhi Wang
35128a60deeSZhi Wang ret = alloc_vgpu_gm(vgpu);
35228a60deeSZhi Wang if (ret)
35328a60deeSZhi Wang goto out_free_resource;
35428a60deeSZhi Wang
35528a60deeSZhi Wang ret = alloc_vgpu_fence(vgpu);
35628a60deeSZhi Wang if (ret)
35728a60deeSZhi Wang goto out_free_vgpu_gm;
35828a60deeSZhi Wang
35928a60deeSZhi Wang return 0;
36028a60deeSZhi Wang
36128a60deeSZhi Wang out_free_vgpu_gm:
36228a60deeSZhi Wang free_vgpu_gm(vgpu);
36328a60deeSZhi Wang out_free_resource:
36428a60deeSZhi Wang free_resource(vgpu);
36528a60deeSZhi Wang return ret;
36628a60deeSZhi Wang }
367