1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2016-2019 Intel Corporation 4 */ 5 6 #include <linux/bitfield.h> 7 #include <linux/firmware.h> 8 #include <drm/drm_print.h> 9 10 #include "intel_uc_fw.h" 11 #include "intel_uc_fw_abi.h" 12 #include "i915_drv.h" 13 14 static inline struct intel_gt * 15 ____uc_fw_to_gt(struct intel_uc_fw *uc_fw, enum intel_uc_fw_type type) 16 { 17 if (type == INTEL_UC_FW_TYPE_GUC) 18 return container_of(uc_fw, struct intel_gt, uc.guc.fw); 19 20 GEM_BUG_ON(type != INTEL_UC_FW_TYPE_HUC); 21 return container_of(uc_fw, struct intel_gt, uc.huc.fw); 22 } 23 24 static inline struct intel_gt *__uc_fw_to_gt(struct intel_uc_fw *uc_fw) 25 { 26 GEM_BUG_ON(uc_fw->status == INTEL_UC_FIRMWARE_UNINITIALIZED); 27 return ____uc_fw_to_gt(uc_fw, uc_fw->type); 28 } 29 30 #ifdef CONFIG_DRM_I915_DEBUG_GUC 31 void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw, 32 enum intel_uc_fw_status status) 33 { 34 uc_fw->__status = status; 35 drm_dbg(&__uc_fw_to_gt(uc_fw)->i915->drm, 36 "%s firmware -> %s\n", 37 intel_uc_fw_type_repr(uc_fw->type), 38 status == INTEL_UC_FIRMWARE_SELECTED ? 39 uc_fw->path : intel_uc_fw_status_repr(status)); 40 } 41 #endif 42 43 /* 44 * List of required GuC and HuC binaries per-platform. 45 * Must be ordered based on platform + revid, from newer to older. 46 * 47 * TGL 35.2 is interface-compatible with 33.0 for previous Gens. The deltas 48 * between 33.0 and 35.2 are only related to new additions to support new Gen12 49 * features. 50 * 51 * Note that RKL uses the same firmware as TGL. 52 */ 53 #define INTEL_UC_FIRMWARE_DEFS(fw_def, guc_def, huc_def) \ 54 fw_def(ROCKETLAKE, 0, guc_def(tgl, 35, 2, 0), huc_def(tgl, 7, 5, 0)) \ 55 fw_def(TIGERLAKE, 0, guc_def(tgl, 35, 2, 0), huc_def(tgl, 7, 5, 0)) \ 56 fw_def(ELKHARTLAKE, 0, guc_def(ehl, 33, 0, 4), huc_def(ehl, 9, 0, 0)) \ 57 fw_def(ICELAKE, 0, guc_def(icl, 33, 0, 0), huc_def(icl, 9, 0, 0)) \ 58 fw_def(COMETLAKE, 5, guc_def(cml, 33, 0, 0), huc_def(cml, 4, 0, 0)) \ 59 fw_def(COFFEELAKE, 0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 4, 0, 0)) \ 60 fw_def(GEMINILAKE, 0, guc_def(glk, 33, 0, 0), huc_def(glk, 4, 0, 0)) \ 61 fw_def(KABYLAKE, 0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 4, 0, 0)) \ 62 fw_def(BROXTON, 0, guc_def(bxt, 33, 0, 0), huc_def(bxt, 2, 0, 0)) \ 63 fw_def(SKYLAKE, 0, guc_def(skl, 33, 0, 0), huc_def(skl, 2, 0, 0)) 64 65 #define __MAKE_UC_FW_PATH(prefix_, name_, major_, minor_, patch_) \ 66 "i915/" \ 67 __stringify(prefix_) name_ \ 68 __stringify(major_) "." \ 69 __stringify(minor_) "." \ 70 __stringify(patch_) ".bin" 71 72 #define MAKE_GUC_FW_PATH(prefix_, major_, minor_, patch_) \ 73 __MAKE_UC_FW_PATH(prefix_, "_guc_", major_, minor_, patch_) 74 75 #define MAKE_HUC_FW_PATH(prefix_, major_, minor_, bld_num_) \ 76 __MAKE_UC_FW_PATH(prefix_, "_huc_", major_, minor_, bld_num_) 77 78 /* All blobs need to be declared via MODULE_FIRMWARE() */ 79 #define INTEL_UC_MODULE_FW(platform_, revid_, guc_, huc_) \ 80 MODULE_FIRMWARE(guc_); \ 81 MODULE_FIRMWARE(huc_); 82 83 INTEL_UC_FIRMWARE_DEFS(INTEL_UC_MODULE_FW, MAKE_GUC_FW_PATH, MAKE_HUC_FW_PATH) 84 85 /* The below structs and macros are used to iterate across the list of blobs */ 86 struct __packed uc_fw_blob { 87 u8 major; 88 u8 minor; 89 const char *path; 90 }; 91 92 #define UC_FW_BLOB(major_, minor_, path_) \ 93 { .major = major_, .minor = minor_, .path = path_ } 94 95 #define GUC_FW_BLOB(prefix_, major_, minor_, patch_) \ 96 UC_FW_BLOB(major_, minor_, \ 97 MAKE_GUC_FW_PATH(prefix_, major_, minor_, patch_)) 98 99 #define HUC_FW_BLOB(prefix_, major_, minor_, bld_num_) \ 100 UC_FW_BLOB(major_, minor_, \ 101 MAKE_HUC_FW_PATH(prefix_, major_, minor_, bld_num_)) 102 103 struct __packed uc_fw_platform_requirement { 104 enum intel_platform p; 105 u8 rev; /* first platform rev using this FW */ 106 const struct uc_fw_blob blobs[INTEL_UC_FW_NUM_TYPES]; 107 }; 108 109 #define MAKE_FW_LIST(platform_, revid_, guc_, huc_) \ 110 { \ 111 .p = INTEL_##platform_, \ 112 .rev = revid_, \ 113 .blobs[INTEL_UC_FW_TYPE_GUC] = guc_, \ 114 .blobs[INTEL_UC_FW_TYPE_HUC] = huc_, \ 115 }, 116 117 static void 118 __uc_fw_auto_select(struct drm_i915_private *i915, struct intel_uc_fw *uc_fw) 119 { 120 static const struct uc_fw_platform_requirement fw_blobs[] = { 121 INTEL_UC_FIRMWARE_DEFS(MAKE_FW_LIST, GUC_FW_BLOB, HUC_FW_BLOB) 122 }; 123 enum intel_platform p = INTEL_INFO(i915)->platform; 124 u8 rev = INTEL_REVID(i915); 125 int i; 126 127 for (i = 0; i < ARRAY_SIZE(fw_blobs) && p <= fw_blobs[i].p; i++) { 128 if (p == fw_blobs[i].p && rev >= fw_blobs[i].rev) { 129 const struct uc_fw_blob *blob = 130 &fw_blobs[i].blobs[uc_fw->type]; 131 uc_fw->path = blob->path; 132 uc_fw->major_ver_wanted = blob->major; 133 uc_fw->minor_ver_wanted = blob->minor; 134 break; 135 } 136 } 137 138 /* make sure the list is ordered as expected */ 139 if (IS_ENABLED(CONFIG_DRM_I915_SELFTEST)) { 140 for (i = 1; i < ARRAY_SIZE(fw_blobs); i++) { 141 if (fw_blobs[i].p < fw_blobs[i - 1].p) 142 continue; 143 144 if (fw_blobs[i].p == fw_blobs[i - 1].p && 145 fw_blobs[i].rev < fw_blobs[i - 1].rev) 146 continue; 147 148 pr_err("invalid FW blob order: %s r%u comes before %s r%u\n", 149 intel_platform_name(fw_blobs[i - 1].p), 150 fw_blobs[i - 1].rev, 151 intel_platform_name(fw_blobs[i].p), 152 fw_blobs[i].rev); 153 154 uc_fw->path = NULL; 155 } 156 } 157 158 /* We don't want to enable GuC/HuC on pre-Gen11 by default */ 159 if (i915->params.enable_guc == -1 && p < INTEL_ICELAKE) 160 uc_fw->path = NULL; 161 } 162 163 static const char *__override_guc_firmware_path(struct drm_i915_private *i915) 164 { 165 if (i915->params.enable_guc & (ENABLE_GUC_SUBMISSION | 166 ENABLE_GUC_LOAD_HUC)) 167 return i915->params.guc_firmware_path; 168 return ""; 169 } 170 171 static const char *__override_huc_firmware_path(struct drm_i915_private *i915) 172 { 173 if (i915->params.enable_guc & ENABLE_GUC_LOAD_HUC) 174 return i915->params.huc_firmware_path; 175 return ""; 176 } 177 178 static void __uc_fw_user_override(struct drm_i915_private *i915, struct intel_uc_fw *uc_fw) 179 { 180 const char *path = NULL; 181 182 switch (uc_fw->type) { 183 case INTEL_UC_FW_TYPE_GUC: 184 path = __override_guc_firmware_path(i915); 185 break; 186 case INTEL_UC_FW_TYPE_HUC: 187 path = __override_huc_firmware_path(i915); 188 break; 189 } 190 191 if (unlikely(path)) { 192 uc_fw->path = path; 193 uc_fw->user_overridden = true; 194 } 195 } 196 197 /** 198 * intel_uc_fw_init_early - initialize the uC object and select the firmware 199 * @uc_fw: uC firmware 200 * @type: type of uC 201 * 202 * Initialize the state of our uC object and relevant tracking and select the 203 * firmware to fetch and load. 204 */ 205 void intel_uc_fw_init_early(struct intel_uc_fw *uc_fw, 206 enum intel_uc_fw_type type) 207 { 208 struct drm_i915_private *i915 = ____uc_fw_to_gt(uc_fw, type)->i915; 209 210 /* 211 * we use FIRMWARE_UNINITIALIZED to detect checks against uc_fw->status 212 * before we're looked at the HW caps to see if we have uc support 213 */ 214 BUILD_BUG_ON(INTEL_UC_FIRMWARE_UNINITIALIZED); 215 GEM_BUG_ON(uc_fw->status); 216 GEM_BUG_ON(uc_fw->path); 217 218 uc_fw->type = type; 219 220 if (HAS_GT_UC(i915)) { 221 __uc_fw_auto_select(i915, uc_fw); 222 __uc_fw_user_override(i915, uc_fw); 223 } 224 225 intel_uc_fw_change_status(uc_fw, uc_fw->path ? *uc_fw->path ? 226 INTEL_UC_FIRMWARE_SELECTED : 227 INTEL_UC_FIRMWARE_DISABLED : 228 INTEL_UC_FIRMWARE_NOT_SUPPORTED); 229 } 230 231 static void __force_fw_fetch_failures(struct intel_uc_fw *uc_fw, int e) 232 { 233 struct drm_i915_private *i915 = __uc_fw_to_gt(uc_fw)->i915; 234 bool user = e == -EINVAL; 235 236 if (i915_inject_probe_error(i915, e)) { 237 /* non-existing blob */ 238 uc_fw->path = "<invalid>"; 239 uc_fw->user_overridden = user; 240 } else if (i915_inject_probe_error(i915, e)) { 241 /* require next major version */ 242 uc_fw->major_ver_wanted += 1; 243 uc_fw->minor_ver_wanted = 0; 244 uc_fw->user_overridden = user; 245 } else if (i915_inject_probe_error(i915, e)) { 246 /* require next minor version */ 247 uc_fw->minor_ver_wanted += 1; 248 uc_fw->user_overridden = user; 249 } else if (uc_fw->major_ver_wanted && 250 i915_inject_probe_error(i915, e)) { 251 /* require prev major version */ 252 uc_fw->major_ver_wanted -= 1; 253 uc_fw->minor_ver_wanted = 0; 254 uc_fw->user_overridden = user; 255 } else if (uc_fw->minor_ver_wanted && 256 i915_inject_probe_error(i915, e)) { 257 /* require prev minor version - hey, this should work! */ 258 uc_fw->minor_ver_wanted -= 1; 259 uc_fw->user_overridden = user; 260 } else if (user && i915_inject_probe_error(i915, e)) { 261 /* officially unsupported platform */ 262 uc_fw->major_ver_wanted = 0; 263 uc_fw->minor_ver_wanted = 0; 264 uc_fw->user_overridden = true; 265 } 266 } 267 268 /** 269 * intel_uc_fw_fetch - fetch uC firmware 270 * @uc_fw: uC firmware 271 * 272 * Fetch uC firmware into GEM obj. 273 * 274 * Return: 0 on success, a negative errno code on failure. 275 */ 276 int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw) 277 { 278 struct drm_i915_private *i915 = __uc_fw_to_gt(uc_fw)->i915; 279 struct device *dev = i915->drm.dev; 280 struct drm_i915_gem_object *obj; 281 const struct firmware *fw = NULL; 282 struct uc_css_header *css; 283 size_t size; 284 int err; 285 286 GEM_BUG_ON(!i915->wopcm.size); 287 GEM_BUG_ON(!intel_uc_fw_is_enabled(uc_fw)); 288 289 err = i915_inject_probe_error(i915, -ENXIO); 290 if (err) 291 goto fail; 292 293 __force_fw_fetch_failures(uc_fw, -EINVAL); 294 __force_fw_fetch_failures(uc_fw, -ESTALE); 295 296 err = request_firmware(&fw, uc_fw->path, dev); 297 if (err) 298 goto fail; 299 300 /* Check the size of the blob before examining buffer contents */ 301 if (unlikely(fw->size < sizeof(struct uc_css_header))) { 302 drm_warn(&i915->drm, "%s firmware %s: invalid size: %zu < %zu\n", 303 intel_uc_fw_type_repr(uc_fw->type), uc_fw->path, 304 fw->size, sizeof(struct uc_css_header)); 305 err = -ENODATA; 306 goto fail; 307 } 308 309 css = (struct uc_css_header *)fw->data; 310 311 /* Check integrity of size values inside CSS header */ 312 size = (css->header_size_dw - css->key_size_dw - css->modulus_size_dw - 313 css->exponent_size_dw) * sizeof(u32); 314 if (unlikely(size != sizeof(struct uc_css_header))) { 315 drm_warn(&i915->drm, 316 "%s firmware %s: unexpected header size: %zu != %zu\n", 317 intel_uc_fw_type_repr(uc_fw->type), uc_fw->path, 318 fw->size, sizeof(struct uc_css_header)); 319 err = -EPROTO; 320 goto fail; 321 } 322 323 /* uCode size must calculated from other sizes */ 324 uc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32); 325 326 /* now RSA */ 327 if (unlikely(css->key_size_dw != UOS_RSA_SCRATCH_COUNT)) { 328 drm_warn(&i915->drm, "%s firmware %s: unexpected key size: %u != %u\n", 329 intel_uc_fw_type_repr(uc_fw->type), uc_fw->path, 330 css->key_size_dw, UOS_RSA_SCRATCH_COUNT); 331 err = -EPROTO; 332 goto fail; 333 } 334 uc_fw->rsa_size = css->key_size_dw * sizeof(u32); 335 336 /* At least, it should have header, uCode and RSA. Size of all three. */ 337 size = sizeof(struct uc_css_header) + uc_fw->ucode_size + uc_fw->rsa_size; 338 if (unlikely(fw->size < size)) { 339 drm_warn(&i915->drm, "%s firmware %s: invalid size: %zu < %zu\n", 340 intel_uc_fw_type_repr(uc_fw->type), uc_fw->path, 341 fw->size, size); 342 err = -ENOEXEC; 343 goto fail; 344 } 345 346 /* Sanity check whether this fw is not larger than whole WOPCM memory */ 347 size = __intel_uc_fw_get_upload_size(uc_fw); 348 if (unlikely(size >= i915->wopcm.size)) { 349 drm_warn(&i915->drm, "%s firmware %s: invalid size: %zu > %zu\n", 350 intel_uc_fw_type_repr(uc_fw->type), uc_fw->path, 351 size, (size_t)i915->wopcm.size); 352 err = -E2BIG; 353 goto fail; 354 } 355 356 /* Get version numbers from the CSS header */ 357 uc_fw->major_ver_found = FIELD_GET(CSS_SW_VERSION_UC_MAJOR, 358 css->sw_version); 359 uc_fw->minor_ver_found = FIELD_GET(CSS_SW_VERSION_UC_MINOR, 360 css->sw_version); 361 362 if (uc_fw->major_ver_found != uc_fw->major_ver_wanted || 363 uc_fw->minor_ver_found < uc_fw->minor_ver_wanted) { 364 drm_notice(&i915->drm, "%s firmware %s: unexpected version: %u.%u != %u.%u\n", 365 intel_uc_fw_type_repr(uc_fw->type), uc_fw->path, 366 uc_fw->major_ver_found, uc_fw->minor_ver_found, 367 uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted); 368 if (!intel_uc_fw_is_overridden(uc_fw)) { 369 err = -ENOEXEC; 370 goto fail; 371 } 372 } 373 374 obj = i915_gem_object_create_shmem_from_data(i915, fw->data, fw->size); 375 if (IS_ERR(obj)) { 376 err = PTR_ERR(obj); 377 goto fail; 378 } 379 380 uc_fw->obj = obj; 381 uc_fw->size = fw->size; 382 intel_uc_fw_change_status(uc_fw, INTEL_UC_FIRMWARE_AVAILABLE); 383 384 release_firmware(fw); 385 return 0; 386 387 fail: 388 intel_uc_fw_change_status(uc_fw, err == -ENOENT ? 389 INTEL_UC_FIRMWARE_MISSING : 390 INTEL_UC_FIRMWARE_ERROR); 391 392 drm_notice(&i915->drm, "%s firmware %s: fetch failed with error %d\n", 393 intel_uc_fw_type_repr(uc_fw->type), uc_fw->path, err); 394 drm_info(&i915->drm, "%s firmware(s) can be downloaded from %s\n", 395 intel_uc_fw_type_repr(uc_fw->type), INTEL_UC_FIRMWARE_URL); 396 397 release_firmware(fw); /* OK even if fw is NULL */ 398 return err; 399 } 400 401 static u32 uc_fw_ggtt_offset(struct intel_uc_fw *uc_fw) 402 { 403 struct i915_ggtt *ggtt = __uc_fw_to_gt(uc_fw)->ggtt; 404 struct drm_mm_node *node = &ggtt->uc_fw; 405 406 GEM_BUG_ON(!drm_mm_node_allocated(node)); 407 GEM_BUG_ON(upper_32_bits(node->start)); 408 GEM_BUG_ON(upper_32_bits(node->start + node->size - 1)); 409 410 return lower_32_bits(node->start); 411 } 412 413 static void uc_fw_bind_ggtt(struct intel_uc_fw *uc_fw) 414 { 415 struct drm_i915_gem_object *obj = uc_fw->obj; 416 struct i915_ggtt *ggtt = __uc_fw_to_gt(uc_fw)->ggtt; 417 struct i915_vma dummy = { 418 .node.start = uc_fw_ggtt_offset(uc_fw), 419 .node.size = obj->base.size, 420 .pages = obj->mm.pages, 421 .vm = &ggtt->vm, 422 }; 423 424 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj)); 425 GEM_BUG_ON(dummy.node.size > ggtt->uc_fw.size); 426 427 /* uc_fw->obj cache domains were not controlled across suspend */ 428 drm_clflush_sg(dummy.pages); 429 430 ggtt->vm.insert_entries(&ggtt->vm, &dummy, I915_CACHE_NONE, 0); 431 } 432 433 static void uc_fw_unbind_ggtt(struct intel_uc_fw *uc_fw) 434 { 435 struct drm_i915_gem_object *obj = uc_fw->obj; 436 struct i915_ggtt *ggtt = __uc_fw_to_gt(uc_fw)->ggtt; 437 u64 start = uc_fw_ggtt_offset(uc_fw); 438 439 ggtt->vm.clear_range(&ggtt->vm, start, obj->base.size); 440 } 441 442 static int uc_fw_xfer(struct intel_uc_fw *uc_fw, u32 dst_offset, u32 dma_flags) 443 { 444 struct intel_gt *gt = __uc_fw_to_gt(uc_fw); 445 struct intel_uncore *uncore = gt->uncore; 446 u64 offset; 447 int ret; 448 449 ret = i915_inject_probe_error(gt->i915, -ETIMEDOUT); 450 if (ret) 451 return ret; 452 453 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); 454 455 /* Set the source address for the uCode */ 456 offset = uc_fw_ggtt_offset(uc_fw); 457 GEM_BUG_ON(upper_32_bits(offset) & 0xFFFF0000); 458 intel_uncore_write_fw(uncore, DMA_ADDR_0_LOW, lower_32_bits(offset)); 459 intel_uncore_write_fw(uncore, DMA_ADDR_0_HIGH, upper_32_bits(offset)); 460 461 /* Set the DMA destination */ 462 intel_uncore_write_fw(uncore, DMA_ADDR_1_LOW, dst_offset); 463 intel_uncore_write_fw(uncore, DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM); 464 465 /* 466 * Set the transfer size. The header plus uCode will be copied to WOPCM 467 * via DMA, excluding any other components 468 */ 469 intel_uncore_write_fw(uncore, DMA_COPY_SIZE, 470 sizeof(struct uc_css_header) + uc_fw->ucode_size); 471 472 /* Start the DMA */ 473 intel_uncore_write_fw(uncore, DMA_CTRL, 474 _MASKED_BIT_ENABLE(dma_flags | START_DMA)); 475 476 /* Wait for DMA to finish */ 477 ret = intel_wait_for_register_fw(uncore, DMA_CTRL, START_DMA, 0, 100); 478 if (ret) 479 drm_err(>->i915->drm, "DMA for %s fw failed, DMA_CTRL=%u\n", 480 intel_uc_fw_type_repr(uc_fw->type), 481 intel_uncore_read_fw(uncore, DMA_CTRL)); 482 483 /* Disable the bits once DMA is over */ 484 intel_uncore_write_fw(uncore, DMA_CTRL, _MASKED_BIT_DISABLE(dma_flags)); 485 486 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL); 487 488 return ret; 489 } 490 491 /** 492 * intel_uc_fw_upload - load uC firmware using custom loader 493 * @uc_fw: uC firmware 494 * @dst_offset: destination offset 495 * @dma_flags: flags for flags for dma ctrl 496 * 497 * Loads uC firmware and updates internal flags. 498 * 499 * Return: 0 on success, non-zero on failure. 500 */ 501 int intel_uc_fw_upload(struct intel_uc_fw *uc_fw, u32 dst_offset, u32 dma_flags) 502 { 503 struct intel_gt *gt = __uc_fw_to_gt(uc_fw); 504 int err; 505 506 /* make sure the status was cleared the last time we reset the uc */ 507 GEM_BUG_ON(intel_uc_fw_is_loaded(uc_fw)); 508 509 err = i915_inject_probe_error(gt->i915, -ENOEXEC); 510 if (err) 511 return err; 512 513 if (!intel_uc_fw_is_loadable(uc_fw)) 514 return -ENOEXEC; 515 516 /* Call custom loader */ 517 uc_fw_bind_ggtt(uc_fw); 518 err = uc_fw_xfer(uc_fw, dst_offset, dma_flags); 519 uc_fw_unbind_ggtt(uc_fw); 520 if (err) 521 goto fail; 522 523 intel_uc_fw_change_status(uc_fw, INTEL_UC_FIRMWARE_TRANSFERRED); 524 return 0; 525 526 fail: 527 i915_probe_error(gt->i915, "Failed to load %s firmware %s (%d)\n", 528 intel_uc_fw_type_repr(uc_fw->type), uc_fw->path, 529 err); 530 intel_uc_fw_change_status(uc_fw, INTEL_UC_FIRMWARE_FAIL); 531 return err; 532 } 533 534 int intel_uc_fw_init(struct intel_uc_fw *uc_fw) 535 { 536 int err; 537 538 /* this should happen before the load! */ 539 GEM_BUG_ON(intel_uc_fw_is_loaded(uc_fw)); 540 541 if (!intel_uc_fw_is_available(uc_fw)) 542 return -ENOEXEC; 543 544 err = i915_gem_object_pin_pages(uc_fw->obj); 545 if (err) { 546 DRM_DEBUG_DRIVER("%s fw pin-pages err=%d\n", 547 intel_uc_fw_type_repr(uc_fw->type), err); 548 intel_uc_fw_change_status(uc_fw, INTEL_UC_FIRMWARE_FAIL); 549 } 550 551 return err; 552 } 553 554 void intel_uc_fw_fini(struct intel_uc_fw *uc_fw) 555 { 556 if (i915_gem_object_has_pinned_pages(uc_fw->obj)) 557 i915_gem_object_unpin_pages(uc_fw->obj); 558 559 intel_uc_fw_change_status(uc_fw, INTEL_UC_FIRMWARE_AVAILABLE); 560 } 561 562 /** 563 * intel_uc_fw_cleanup_fetch - cleanup uC firmware 564 * @uc_fw: uC firmware 565 * 566 * Cleans up uC firmware by releasing the firmware GEM obj. 567 */ 568 void intel_uc_fw_cleanup_fetch(struct intel_uc_fw *uc_fw) 569 { 570 if (!intel_uc_fw_is_available(uc_fw)) 571 return; 572 573 i915_gem_object_put(fetch_and_zero(&uc_fw->obj)); 574 575 intel_uc_fw_change_status(uc_fw, INTEL_UC_FIRMWARE_SELECTED); 576 } 577 578 /** 579 * intel_uc_fw_copy_rsa - copy fw RSA to buffer 580 * 581 * @uc_fw: uC firmware 582 * @dst: dst buffer 583 * @max_len: max number of bytes to copy 584 * 585 * Return: number of copied bytes. 586 */ 587 size_t intel_uc_fw_copy_rsa(struct intel_uc_fw *uc_fw, void *dst, u32 max_len) 588 { 589 struct sg_table *pages = uc_fw->obj->mm.pages; 590 u32 size = min_t(u32, uc_fw->rsa_size, max_len); 591 u32 offset = sizeof(struct uc_css_header) + uc_fw->ucode_size; 592 593 GEM_BUG_ON(!intel_uc_fw_is_available(uc_fw)); 594 595 return sg_pcopy_to_buffer(pages->sgl, pages->nents, dst, size, offset); 596 } 597 598 /** 599 * intel_uc_fw_dump - dump information about uC firmware 600 * @uc_fw: uC firmware 601 * @p: the &drm_printer 602 * 603 * Pretty printer for uC firmware. 604 */ 605 void intel_uc_fw_dump(const struct intel_uc_fw *uc_fw, struct drm_printer *p) 606 { 607 drm_printf(p, "%s firmware: %s\n", 608 intel_uc_fw_type_repr(uc_fw->type), uc_fw->path); 609 drm_printf(p, "\tstatus: %s\n", 610 intel_uc_fw_status_repr(uc_fw->status)); 611 drm_printf(p, "\tversion: wanted %u.%u, found %u.%u\n", 612 uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted, 613 uc_fw->major_ver_found, uc_fw->minor_ver_found); 614 drm_printf(p, "\tuCode: %u bytes\n", uc_fw->ucode_size); 615 drm_printf(p, "\tRSA: %u bytes\n", uc_fw->rsa_size); 616 } 617