xref: /openbmc/linux/drivers/gpu/drm/i915/gt/uc/intel_uc.c (revision f5ad1c74)
1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright © 2016-2019 Intel Corporation
4  */
5 
6 #include "gt/intel_gt.h"
7 #include "gt/intel_reset.h"
8 #include "intel_guc.h"
9 #include "intel_guc_ads.h"
10 #include "intel_guc_submission.h"
11 #include "intel_uc.h"
12 
13 #include "i915_drv.h"
14 
15 static const struct intel_uc_ops uc_ops_off;
16 static const struct intel_uc_ops uc_ops_on;
17 
18 /* Reset GuC providing us with fresh state for both GuC and HuC.
19  */
20 static int __intel_uc_reset_hw(struct intel_uc *uc)
21 {
22 	struct intel_gt *gt = uc_to_gt(uc);
23 	int ret;
24 	u32 guc_status;
25 
26 	ret = i915_inject_probe_error(gt->i915, -ENXIO);
27 	if (ret)
28 		return ret;
29 
30 	ret = intel_reset_guc(gt);
31 	if (ret) {
32 		DRM_ERROR("Failed to reset GuC, ret = %d\n", ret);
33 		return ret;
34 	}
35 
36 	guc_status = intel_uncore_read(gt->uncore, GUC_STATUS);
37 	WARN(!(guc_status & GS_MIA_IN_RESET),
38 	     "GuC status: 0x%x, MIA core expected to be in reset\n",
39 	     guc_status);
40 
41 	return ret;
42 }
43 
44 static void __confirm_options(struct intel_uc *uc)
45 {
46 	struct drm_i915_private *i915 = uc_to_gt(uc)->i915;
47 
48 	drm_dbg(&i915->drm,
49 		"enable_guc=%d (guc:%s submission:%s huc:%s)\n",
50 		i915->params.enable_guc,
51 		yesno(intel_uc_wants_guc(uc)),
52 		yesno(intel_uc_wants_guc_submission(uc)),
53 		yesno(intel_uc_wants_huc(uc)));
54 
55 	if (i915->params.enable_guc == -1)
56 		return;
57 
58 	if (i915->params.enable_guc == 0) {
59 		GEM_BUG_ON(intel_uc_wants_guc(uc));
60 		GEM_BUG_ON(intel_uc_wants_guc_submission(uc));
61 		GEM_BUG_ON(intel_uc_wants_huc(uc));
62 		return;
63 	}
64 
65 	if (!intel_uc_supports_guc(uc))
66 		drm_info(&i915->drm,
67 			 "Incompatible option enable_guc=%d - %s\n",
68 			 i915->params.enable_guc, "GuC is not supported!");
69 
70 	if (i915->params.enable_guc & ENABLE_GUC_LOAD_HUC &&
71 	    !intel_uc_supports_huc(uc))
72 		drm_info(&i915->drm,
73 			 "Incompatible option enable_guc=%d - %s\n",
74 			 i915->params.enable_guc, "HuC is not supported!");
75 
76 	if (i915->params.enable_guc & ENABLE_GUC_SUBMISSION &&
77 	    !intel_uc_supports_guc_submission(uc))
78 		drm_info(&i915->drm,
79 			 "Incompatible option enable_guc=%d - %s\n",
80 			 i915->params.enable_guc, "GuC submission is N/A");
81 
82 	if (i915->params.enable_guc & ~(ENABLE_GUC_SUBMISSION |
83 					  ENABLE_GUC_LOAD_HUC))
84 		drm_info(&i915->drm,
85 			 "Incompatible option enable_guc=%d - %s\n",
86 			 i915->params.enable_guc, "undocumented flag");
87 }
88 
89 void intel_uc_init_early(struct intel_uc *uc)
90 {
91 	intel_guc_init_early(&uc->guc);
92 	intel_huc_init_early(&uc->huc);
93 
94 	__confirm_options(uc);
95 
96 	if (intel_uc_wants_guc(uc))
97 		uc->ops = &uc_ops_on;
98 	else
99 		uc->ops = &uc_ops_off;
100 }
101 
102 void intel_uc_driver_late_release(struct intel_uc *uc)
103 {
104 }
105 
106 /**
107  * intel_uc_init_mmio - setup uC MMIO access
108  * @uc: the intel_uc structure
109  *
110  * Setup minimal state necessary for MMIO accesses later in the
111  * initialization sequence.
112  */
113 void intel_uc_init_mmio(struct intel_uc *uc)
114 {
115 	intel_guc_init_send_regs(&uc->guc);
116 }
117 
118 static void __uc_capture_load_err_log(struct intel_uc *uc)
119 {
120 	struct intel_guc *guc = &uc->guc;
121 
122 	if (guc->log.vma && !uc->load_err_log)
123 		uc->load_err_log = i915_gem_object_get(guc->log.vma->obj);
124 }
125 
126 static void __uc_free_load_err_log(struct intel_uc *uc)
127 {
128 	struct drm_i915_gem_object *log = fetch_and_zero(&uc->load_err_log);
129 
130 	if (log)
131 		i915_gem_object_put(log);
132 }
133 
134 void intel_uc_driver_remove(struct intel_uc *uc)
135 {
136 	intel_uc_fini_hw(uc);
137 	intel_uc_fini(uc);
138 	__uc_free_load_err_log(uc);
139 }
140 
141 static inline bool guc_communication_enabled(struct intel_guc *guc)
142 {
143 	return intel_guc_ct_enabled(&guc->ct);
144 }
145 
146 /*
147  * Events triggered while CT buffers are disabled are logged in the SCRATCH_15
148  * register using the same bits used in the CT message payload. Since our
149  * communication channel with guc is turned off at this point, we can save the
150  * message and handle it after we turn it back on.
151  */
152 static void guc_clear_mmio_msg(struct intel_guc *guc)
153 {
154 	intel_uncore_write(guc_to_gt(guc)->uncore, SOFT_SCRATCH(15), 0);
155 }
156 
157 static void guc_get_mmio_msg(struct intel_guc *guc)
158 {
159 	u32 val;
160 
161 	spin_lock_irq(&guc->irq_lock);
162 
163 	val = intel_uncore_read(guc_to_gt(guc)->uncore, SOFT_SCRATCH(15));
164 	guc->mmio_msg |= val & guc->msg_enabled_mask;
165 
166 	/*
167 	 * clear all events, including the ones we're not currently servicing,
168 	 * to make sure we don't try to process a stale message if we enable
169 	 * handling of more events later.
170 	 */
171 	guc_clear_mmio_msg(guc);
172 
173 	spin_unlock_irq(&guc->irq_lock);
174 }
175 
176 static void guc_handle_mmio_msg(struct intel_guc *guc)
177 {
178 	struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
179 
180 	/* we need communication to be enabled to reply to GuC */
181 	GEM_BUG_ON(!guc_communication_enabled(guc));
182 
183 	if (!guc->mmio_msg)
184 		return;
185 
186 	spin_lock_irq(&i915->irq_lock);
187 	intel_guc_to_host_process_recv_msg(guc, &guc->mmio_msg, 1);
188 	spin_unlock_irq(&i915->irq_lock);
189 
190 	guc->mmio_msg = 0;
191 }
192 
193 static void guc_reset_interrupts(struct intel_guc *guc)
194 {
195 	guc->interrupts.reset(guc);
196 }
197 
198 static void guc_enable_interrupts(struct intel_guc *guc)
199 {
200 	guc->interrupts.enable(guc);
201 }
202 
203 static void guc_disable_interrupts(struct intel_guc *guc)
204 {
205 	guc->interrupts.disable(guc);
206 }
207 
208 static int guc_enable_communication(struct intel_guc *guc)
209 {
210 	struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
211 	int ret;
212 
213 	GEM_BUG_ON(guc_communication_enabled(guc));
214 
215 	ret = i915_inject_probe_error(i915, -ENXIO);
216 	if (ret)
217 		return ret;
218 
219 	ret = intel_guc_ct_enable(&guc->ct);
220 	if (ret)
221 		return ret;
222 
223 	/* check for mmio messages received before/during the CT enable */
224 	guc_get_mmio_msg(guc);
225 	guc_handle_mmio_msg(guc);
226 
227 	guc_enable_interrupts(guc);
228 
229 	/* check for CT messages received before we enabled interrupts */
230 	spin_lock_irq(&i915->irq_lock);
231 	intel_guc_ct_event_handler(&guc->ct);
232 	spin_unlock_irq(&i915->irq_lock);
233 
234 	drm_dbg(&i915->drm, "GuC communication enabled\n");
235 
236 	return 0;
237 }
238 
239 static void guc_disable_communication(struct intel_guc *guc)
240 {
241 	struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
242 
243 	/*
244 	 * Events generated during or after CT disable are logged by guc in
245 	 * via mmio. Make sure the register is clear before disabling CT since
246 	 * all events we cared about have already been processed via CT.
247 	 */
248 	guc_clear_mmio_msg(guc);
249 
250 	guc_disable_interrupts(guc);
251 
252 	intel_guc_ct_disable(&guc->ct);
253 
254 	/*
255 	 * Check for messages received during/after the CT disable. We do not
256 	 * expect any messages to have arrived via CT between the interrupt
257 	 * disable and the CT disable because GuC should've been idle until we
258 	 * triggered the CT disable protocol.
259 	 */
260 	guc_get_mmio_msg(guc);
261 
262 	drm_dbg(&i915->drm, "GuC communication disabled\n");
263 }
264 
265 static void __uc_fetch_firmwares(struct intel_uc *uc)
266 {
267 	int err;
268 
269 	GEM_BUG_ON(!intel_uc_wants_guc(uc));
270 
271 	err = intel_uc_fw_fetch(&uc->guc.fw);
272 	if (err) {
273 		/* Make sure we transition out of transient "SELECTED" state */
274 		if (intel_uc_wants_huc(uc)) {
275 			drm_dbg(&uc_to_gt(uc)->i915->drm,
276 				"Failed to fetch GuC: %d disabling HuC\n", err);
277 			intel_uc_fw_change_status(&uc->huc.fw,
278 						  INTEL_UC_FIRMWARE_ERROR);
279 		}
280 
281 		return;
282 	}
283 
284 	if (intel_uc_wants_huc(uc))
285 		intel_uc_fw_fetch(&uc->huc.fw);
286 }
287 
288 static void __uc_cleanup_firmwares(struct intel_uc *uc)
289 {
290 	intel_uc_fw_cleanup_fetch(&uc->huc.fw);
291 	intel_uc_fw_cleanup_fetch(&uc->guc.fw);
292 }
293 
294 static int __uc_init(struct intel_uc *uc)
295 {
296 	struct intel_guc *guc = &uc->guc;
297 	struct intel_huc *huc = &uc->huc;
298 	int ret;
299 
300 	GEM_BUG_ON(!intel_uc_wants_guc(uc));
301 
302 	if (!intel_uc_uses_guc(uc))
303 		return 0;
304 
305 	if (i915_inject_probe_failure(uc_to_gt(uc)->i915))
306 		return -ENOMEM;
307 
308 	/* XXX: GuC submission is unavailable for now */
309 	GEM_BUG_ON(intel_uc_uses_guc_submission(uc));
310 
311 	ret = intel_guc_init(guc);
312 	if (ret)
313 		return ret;
314 
315 	if (intel_uc_uses_huc(uc)) {
316 		ret = intel_huc_init(huc);
317 		if (ret)
318 			goto out_guc;
319 	}
320 
321 	return 0;
322 
323 out_guc:
324 	intel_guc_fini(guc);
325 	return ret;
326 }
327 
328 static void __uc_fini(struct intel_uc *uc)
329 {
330 	intel_huc_fini(&uc->huc);
331 	intel_guc_fini(&uc->guc);
332 }
333 
334 static int __uc_sanitize(struct intel_uc *uc)
335 {
336 	struct intel_guc *guc = &uc->guc;
337 	struct intel_huc *huc = &uc->huc;
338 
339 	GEM_BUG_ON(!intel_uc_supports_guc(uc));
340 
341 	intel_huc_sanitize(huc);
342 	intel_guc_sanitize(guc);
343 
344 	return __intel_uc_reset_hw(uc);
345 }
346 
347 /* Initialize and verify the uC regs related to uC positioning in WOPCM */
348 static int uc_init_wopcm(struct intel_uc *uc)
349 {
350 	struct intel_gt *gt = uc_to_gt(uc);
351 	struct intel_uncore *uncore = gt->uncore;
352 	u32 base = intel_wopcm_guc_base(&gt->i915->wopcm);
353 	u32 size = intel_wopcm_guc_size(&gt->i915->wopcm);
354 	u32 huc_agent = intel_uc_uses_huc(uc) ? HUC_LOADING_AGENT_GUC : 0;
355 	u32 mask;
356 	int err;
357 
358 	if (unlikely(!base || !size)) {
359 		i915_probe_error(gt->i915, "Unsuccessful WOPCM partitioning\n");
360 		return -E2BIG;
361 	}
362 
363 	GEM_BUG_ON(!intel_uc_supports_guc(uc));
364 	GEM_BUG_ON(!(base & GUC_WOPCM_OFFSET_MASK));
365 	GEM_BUG_ON(base & ~GUC_WOPCM_OFFSET_MASK);
366 	GEM_BUG_ON(!(size & GUC_WOPCM_SIZE_MASK));
367 	GEM_BUG_ON(size & ~GUC_WOPCM_SIZE_MASK);
368 
369 	err = i915_inject_probe_error(gt->i915, -ENXIO);
370 	if (err)
371 		return err;
372 
373 	mask = GUC_WOPCM_SIZE_MASK | GUC_WOPCM_SIZE_LOCKED;
374 	err = intel_uncore_write_and_verify(uncore, GUC_WOPCM_SIZE, size, mask,
375 					    size | GUC_WOPCM_SIZE_LOCKED);
376 	if (err)
377 		goto err_out;
378 
379 	mask = GUC_WOPCM_OFFSET_MASK | GUC_WOPCM_OFFSET_VALID | huc_agent;
380 	err = intel_uncore_write_and_verify(uncore, DMA_GUC_WOPCM_OFFSET,
381 					    base | huc_agent, mask,
382 					    base | huc_agent |
383 					    GUC_WOPCM_OFFSET_VALID);
384 	if (err)
385 		goto err_out;
386 
387 	return 0;
388 
389 err_out:
390 	i915_probe_error(gt->i915, "Failed to init uC WOPCM registers!\n");
391 	i915_probe_error(gt->i915, "%s(%#x)=%#x\n", "DMA_GUC_WOPCM_OFFSET",
392 			 i915_mmio_reg_offset(DMA_GUC_WOPCM_OFFSET),
393 			 intel_uncore_read(uncore, DMA_GUC_WOPCM_OFFSET));
394 	i915_probe_error(gt->i915, "%s(%#x)=%#x\n", "GUC_WOPCM_SIZE",
395 			 i915_mmio_reg_offset(GUC_WOPCM_SIZE),
396 			 intel_uncore_read(uncore, GUC_WOPCM_SIZE));
397 
398 	return err;
399 }
400 
401 static bool uc_is_wopcm_locked(struct intel_uc *uc)
402 {
403 	struct intel_gt *gt = uc_to_gt(uc);
404 	struct intel_uncore *uncore = gt->uncore;
405 
406 	return (intel_uncore_read(uncore, GUC_WOPCM_SIZE) & GUC_WOPCM_SIZE_LOCKED) ||
407 	       (intel_uncore_read(uncore, DMA_GUC_WOPCM_OFFSET) & GUC_WOPCM_OFFSET_VALID);
408 }
409 
410 static int __uc_check_hw(struct intel_uc *uc)
411 {
412 	if (!intel_uc_supports_guc(uc))
413 		return 0;
414 
415 	/*
416 	 * We can silently continue without GuC only if it was never enabled
417 	 * before on this system after reboot, otherwise we risk GPU hangs.
418 	 * To check if GuC was loaded before we look at WOPCM registers.
419 	 */
420 	if (uc_is_wopcm_locked(uc))
421 		return -EIO;
422 
423 	return 0;
424 }
425 
426 static int __uc_init_hw(struct intel_uc *uc)
427 {
428 	struct drm_i915_private *i915 = uc_to_gt(uc)->i915;
429 	struct intel_guc *guc = &uc->guc;
430 	struct intel_huc *huc = &uc->huc;
431 	int ret, attempts;
432 
433 	GEM_BUG_ON(!intel_uc_supports_guc(uc));
434 	GEM_BUG_ON(!intel_uc_wants_guc(uc));
435 
436 	if (!intel_uc_fw_is_loadable(&guc->fw)) {
437 		ret = __uc_check_hw(uc) ||
438 		      intel_uc_fw_is_overridden(&guc->fw) ||
439 		      intel_uc_wants_guc_submission(uc) ?
440 		      intel_uc_fw_status_to_error(guc->fw.status) : 0;
441 		goto err_out;
442 	}
443 
444 	ret = uc_init_wopcm(uc);
445 	if (ret)
446 		goto err_out;
447 
448 	guc_reset_interrupts(guc);
449 
450 	/* WaEnableuKernelHeaderValidFix:skl */
451 	/* WaEnableGuCBootHashCheckNotSet:skl,bxt,kbl */
452 	if (IS_GEN(i915, 9))
453 		attempts = 3;
454 	else
455 		attempts = 1;
456 
457 	while (attempts--) {
458 		/*
459 		 * Always reset the GuC just before (re)loading, so
460 		 * that the state and timing are fairly predictable
461 		 */
462 		ret = __uc_sanitize(uc);
463 		if (ret)
464 			goto err_out;
465 
466 		intel_huc_fw_upload(huc);
467 		intel_guc_ads_reset(guc);
468 		intel_guc_write_params(guc);
469 		ret = intel_guc_fw_upload(guc);
470 		if (ret == 0)
471 			break;
472 
473 		DRM_DEBUG_DRIVER("GuC fw load failed: %d; will reset and "
474 				 "retry %d more time(s)\n", ret, attempts);
475 	}
476 
477 	/* Did we succeded or run out of retries? */
478 	if (ret)
479 		goto err_log_capture;
480 
481 	ret = guc_enable_communication(guc);
482 	if (ret)
483 		goto err_log_capture;
484 
485 	intel_huc_auth(huc);
486 
487 	ret = intel_guc_sample_forcewake(guc);
488 	if (ret)
489 		goto err_communication;
490 
491 	if (intel_uc_uses_guc_submission(uc))
492 		intel_guc_submission_enable(guc);
493 
494 	drm_info(&i915->drm, "%s firmware %s version %u.%u %s:%s\n",
495 		 intel_uc_fw_type_repr(INTEL_UC_FW_TYPE_GUC), guc->fw.path,
496 		 guc->fw.major_ver_found, guc->fw.minor_ver_found,
497 		 "submission",
498 		 enableddisabled(intel_uc_uses_guc_submission(uc)));
499 
500 	if (intel_uc_uses_huc(uc)) {
501 		drm_info(&i915->drm, "%s firmware %s version %u.%u %s:%s\n",
502 			 intel_uc_fw_type_repr(INTEL_UC_FW_TYPE_HUC),
503 			 huc->fw.path,
504 			 huc->fw.major_ver_found, huc->fw.minor_ver_found,
505 			 "authenticated",
506 			 yesno(intel_huc_is_authenticated(huc)));
507 	}
508 
509 	return 0;
510 
511 	/*
512 	 * We've failed to load the firmware :(
513 	 */
514 err_communication:
515 	guc_disable_communication(guc);
516 err_log_capture:
517 	__uc_capture_load_err_log(uc);
518 err_out:
519 	__uc_sanitize(uc);
520 
521 	if (!ret) {
522 		drm_notice(&i915->drm, "GuC is uninitialized\n");
523 		/* We want to run without GuC submission */
524 		return 0;
525 	}
526 
527 	i915_probe_error(i915, "GuC initialization failed %d\n", ret);
528 
529 	/* We want to keep KMS alive */
530 	return -EIO;
531 }
532 
533 static void __uc_fini_hw(struct intel_uc *uc)
534 {
535 	struct intel_guc *guc = &uc->guc;
536 
537 	if (!intel_guc_is_fw_running(guc))
538 		return;
539 
540 	if (intel_uc_uses_guc_submission(uc))
541 		intel_guc_submission_disable(guc);
542 
543 	if (guc_communication_enabled(guc))
544 		guc_disable_communication(guc);
545 
546 	__uc_sanitize(uc);
547 }
548 
549 /**
550  * intel_uc_reset_prepare - Prepare for reset
551  * @uc: the intel_uc structure
552  *
553  * Preparing for full gpu reset.
554  */
555 void intel_uc_reset_prepare(struct intel_uc *uc)
556 {
557 	struct intel_guc *guc = &uc->guc;
558 
559 	if (!intel_guc_is_ready(guc))
560 		return;
561 
562 	guc_disable_communication(guc);
563 	__uc_sanitize(uc);
564 }
565 
566 void intel_uc_runtime_suspend(struct intel_uc *uc)
567 {
568 	struct intel_guc *guc = &uc->guc;
569 	int err;
570 
571 	if (!intel_guc_is_ready(guc))
572 		return;
573 
574 	err = intel_guc_suspend(guc);
575 	if (err)
576 		DRM_DEBUG_DRIVER("Failed to suspend GuC, err=%d", err);
577 
578 	guc_disable_communication(guc);
579 }
580 
581 void intel_uc_suspend(struct intel_uc *uc)
582 {
583 	struct intel_guc *guc = &uc->guc;
584 	intel_wakeref_t wakeref;
585 
586 	if (!intel_guc_is_ready(guc))
587 		return;
588 
589 	with_intel_runtime_pm(uc_to_gt(uc)->uncore->rpm, wakeref)
590 		intel_uc_runtime_suspend(uc);
591 }
592 
593 static int __uc_resume(struct intel_uc *uc, bool enable_communication)
594 {
595 	struct intel_guc *guc = &uc->guc;
596 	int err;
597 
598 	if (!intel_guc_is_fw_running(guc))
599 		return 0;
600 
601 	/* Make sure we enable communication if and only if it's disabled */
602 	GEM_BUG_ON(enable_communication == guc_communication_enabled(guc));
603 
604 	if (enable_communication)
605 		guc_enable_communication(guc);
606 
607 	err = intel_guc_resume(guc);
608 	if (err) {
609 		DRM_DEBUG_DRIVER("Failed to resume GuC, err=%d", err);
610 		return err;
611 	}
612 
613 	return 0;
614 }
615 
616 int intel_uc_resume(struct intel_uc *uc)
617 {
618 	/*
619 	 * When coming out of S3/S4 we sanitize and re-init the HW, so
620 	 * communication is already re-enabled at this point.
621 	 */
622 	return __uc_resume(uc, false);
623 }
624 
625 int intel_uc_runtime_resume(struct intel_uc *uc)
626 {
627 	/*
628 	 * During runtime resume we don't sanitize, so we need to re-init
629 	 * communication as well.
630 	 */
631 	return __uc_resume(uc, true);
632 }
633 
634 static const struct intel_uc_ops uc_ops_off = {
635 	.init_hw = __uc_check_hw,
636 };
637 
638 static const struct intel_uc_ops uc_ops_on = {
639 	.sanitize = __uc_sanitize,
640 
641 	.init_fw = __uc_fetch_firmwares,
642 	.fini_fw = __uc_cleanup_firmwares,
643 
644 	.init = __uc_init,
645 	.fini = __uc_fini,
646 
647 	.init_hw = __uc_init_hw,
648 	.fini_hw = __uc_fini_hw,
649 };
650