1 /* 2 * Copyright © 2016-2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/types.h> 26 27 #include "gt/intel_gt.h" 28 #include "intel_huc.h" 29 #include "i915_drv.h" 30 31 void intel_huc_init_early(struct intel_huc *huc) 32 { 33 struct drm_i915_private *i915 = huc_to_gt(huc)->i915; 34 35 intel_huc_fw_init_early(huc); 36 37 if (INTEL_GEN(i915) >= 11) { 38 huc->status.reg = GEN11_HUC_KERNEL_LOAD_INFO; 39 huc->status.mask = HUC_LOAD_SUCCESSFUL; 40 huc->status.value = HUC_LOAD_SUCCESSFUL; 41 } else { 42 huc->status.reg = HUC_STATUS2; 43 huc->status.mask = HUC_FW_VERIFIED; 44 huc->status.value = HUC_FW_VERIFIED; 45 } 46 } 47 48 static int intel_huc_rsa_data_create(struct intel_huc *huc) 49 { 50 struct intel_gt *gt = huc_to_gt(huc); 51 struct intel_guc *guc = >->uc.guc; 52 struct i915_vma *vma; 53 size_t copied; 54 void *vaddr; 55 56 /* 57 * HuC firmware will sit above GUC_GGTT_TOP and will not map 58 * through GTT. Unfortunately, this means GuC cannot perform 59 * the HuC auth. as the rsa offset now falls within the GuC 60 * inaccessible range. We resort to perma-pinning an additional 61 * vma within the accessible range that only contains the rsa 62 * signature. The GuC can use this extra pinning to perform 63 * the authentication since its GGTT offset will be GuC 64 * accessible. 65 */ 66 GEM_BUG_ON(huc->fw.rsa_size > PAGE_SIZE); 67 vma = intel_guc_allocate_vma(guc, PAGE_SIZE); 68 if (IS_ERR(vma)) 69 return PTR_ERR(vma); 70 71 vaddr = i915_gem_object_pin_map(vma->obj, I915_MAP_WB); 72 if (IS_ERR(vaddr)) { 73 i915_vma_unpin_and_release(&vma, 0); 74 return PTR_ERR(vaddr); 75 } 76 77 copied = intel_uc_fw_copy_rsa(&huc->fw, vaddr, vma->size); 78 GEM_BUG_ON(copied < huc->fw.rsa_size); 79 80 i915_gem_object_unpin_map(vma->obj); 81 82 huc->rsa_data = vma; 83 84 return 0; 85 } 86 87 static void intel_huc_rsa_data_destroy(struct intel_huc *huc) 88 { 89 i915_vma_unpin_and_release(&huc->rsa_data, 0); 90 } 91 92 int intel_huc_init(struct intel_huc *huc) 93 { 94 int err; 95 96 err = intel_uc_fw_init(&huc->fw); 97 if (err) 98 return err; 99 100 /* 101 * HuC firmware image is outside GuC accessible range. 102 * Copy the RSA signature out of the image into 103 * a perma-pinned region set aside for it 104 */ 105 err = intel_huc_rsa_data_create(huc); 106 if (err) 107 goto out_fini; 108 109 return 0; 110 111 out_fini: 112 intel_uc_fw_fini(&huc->fw); 113 return err; 114 } 115 116 void intel_huc_fini(struct intel_huc *huc) 117 { 118 intel_uc_fw_fini(&huc->fw); 119 intel_huc_rsa_data_destroy(huc); 120 } 121 122 /** 123 * intel_huc_auth() - Authenticate HuC uCode 124 * @huc: intel_huc structure 125 * 126 * Called after HuC and GuC firmware loading during intel_uc_init_hw(). 127 * 128 * This function pins HuC firmware image object into GGTT. 129 * Then it invokes GuC action to authenticate passing the offset to RSA 130 * signature through intel_guc_auth_huc(). It then waits for 50ms for 131 * firmware verification ACK and unpins the object. 132 */ 133 int intel_huc_auth(struct intel_huc *huc) 134 { 135 struct intel_gt *gt = huc_to_gt(huc); 136 struct intel_guc *guc = >->uc.guc; 137 int ret; 138 139 GEM_BUG_ON(!intel_uc_fw_is_loaded(&huc->fw)); 140 GEM_BUG_ON(intel_huc_is_authenticated(huc)); 141 142 ret = intel_guc_auth_huc(guc, 143 intel_guc_ggtt_offset(guc, huc->rsa_data)); 144 if (ret) { 145 DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret); 146 goto fail; 147 } 148 149 /* Check authentication status, it should be done by now */ 150 ret = __intel_wait_for_register(gt->uncore, 151 huc->status.reg, 152 huc->status.mask, 153 huc->status.value, 154 2, 50, NULL); 155 if (ret) { 156 DRM_ERROR("HuC: Firmware not verified %d\n", ret); 157 goto fail; 158 } 159 160 huc->fw.status = INTEL_UC_FIRMWARE_RUNNING; 161 162 return 0; 163 164 fail: 165 huc->fw.status = INTEL_UC_FIRMWARE_FAIL; 166 167 DRM_ERROR("HuC: Authentication failed %d\n", ret); 168 return ret; 169 } 170 171 /** 172 * intel_huc_check_status() - check HuC status 173 * @huc: intel_huc structure 174 * 175 * This function reads status register to verify if HuC 176 * firmware was successfully loaded. 177 * 178 * Returns: 1 if HuC firmware is loaded and verified, 179 * 0 if HuC firmware is not loaded and -ENODEV if HuC 180 * is not present on this platform. 181 */ 182 int intel_huc_check_status(struct intel_huc *huc) 183 { 184 struct intel_gt *gt = huc_to_gt(huc); 185 intel_wakeref_t wakeref; 186 u32 status = 0; 187 188 if (!intel_uc_is_using_huc(>->uc)) 189 return -ENODEV; 190 191 with_intel_runtime_pm(>->i915->runtime_pm, wakeref) 192 status = intel_uncore_read(gt->uncore, huc->status.reg); 193 194 return (status & huc->status.mask) == huc->status.value; 195 } 196