1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2016-2019 Intel Corporation 4 */ 5 6 #include <linux/types.h> 7 8 #include "gt/intel_gt.h" 9 #include "intel_huc.h" 10 #include "i915_drv.h" 11 12 /** 13 * DOC: HuC 14 * 15 * The HuC is a dedicated microcontroller for usage in media HEVC (High 16 * Efficiency Video Coding) operations. Userspace can directly use the firmware 17 * capabilities by adding HuC specific commands to batch buffers. 18 * 19 * The kernel driver is only responsible for loading the HuC firmware and 20 * triggering its security authentication, which is performed by the GuC. For 21 * The GuC to correctly perform the authentication, the HuC binary must be 22 * loaded before the GuC one. Loading the HuC is optional; however, not using 23 * the HuC might negatively impact power usage and/or performance of media 24 * workloads, depending on the use-cases. 25 * 26 * See https://github.com/intel/media-driver for the latest details on HuC 27 * functionality. 28 */ 29 30 /** 31 * DOC: HuC Memory Management 32 * 33 * Similarly to the GuC, the HuC can't do any memory allocations on its own, 34 * with the difference being that the allocations for HuC usage are handled by 35 * the userspace driver instead of the kernel one. The HuC accesses the memory 36 * via the PPGTT belonging to the context loaded on the VCS executing the 37 * HuC-specific commands. 38 */ 39 40 void intel_huc_init_early(struct intel_huc *huc) 41 { 42 struct drm_i915_private *i915 = huc_to_gt(huc)->i915; 43 44 intel_uc_fw_init_early(&huc->fw, INTEL_UC_FW_TYPE_HUC); 45 46 if (INTEL_GEN(i915) >= 11) { 47 huc->status.reg = GEN11_HUC_KERNEL_LOAD_INFO; 48 huc->status.mask = HUC_LOAD_SUCCESSFUL; 49 huc->status.value = HUC_LOAD_SUCCESSFUL; 50 } else { 51 huc->status.reg = HUC_STATUS2; 52 huc->status.mask = HUC_FW_VERIFIED; 53 huc->status.value = HUC_FW_VERIFIED; 54 } 55 } 56 57 static int intel_huc_rsa_data_create(struct intel_huc *huc) 58 { 59 struct intel_gt *gt = huc_to_gt(huc); 60 struct intel_guc *guc = >->uc.guc; 61 struct i915_vma *vma; 62 size_t copied; 63 void *vaddr; 64 int err; 65 66 err = i915_inject_probe_error(gt->i915, -ENXIO); 67 if (err) 68 return err; 69 70 /* 71 * HuC firmware will sit above GUC_GGTT_TOP and will not map 72 * through GTT. Unfortunately, this means GuC cannot perform 73 * the HuC auth. as the rsa offset now falls within the GuC 74 * inaccessible range. We resort to perma-pinning an additional 75 * vma within the accessible range that only contains the rsa 76 * signature. The GuC can use this extra pinning to perform 77 * the authentication since its GGTT offset will be GuC 78 * accessible. 79 */ 80 GEM_BUG_ON(huc->fw.rsa_size > PAGE_SIZE); 81 vma = intel_guc_allocate_vma(guc, PAGE_SIZE); 82 if (IS_ERR(vma)) 83 return PTR_ERR(vma); 84 85 vaddr = i915_gem_object_pin_map_unlocked(vma->obj, I915_MAP_WB); 86 if (IS_ERR(vaddr)) { 87 i915_vma_unpin_and_release(&vma, 0); 88 return PTR_ERR(vaddr); 89 } 90 91 copied = intel_uc_fw_copy_rsa(&huc->fw, vaddr, vma->size); 92 GEM_BUG_ON(copied < huc->fw.rsa_size); 93 94 i915_gem_object_unpin_map(vma->obj); 95 96 huc->rsa_data = vma; 97 98 return 0; 99 } 100 101 static void intel_huc_rsa_data_destroy(struct intel_huc *huc) 102 { 103 i915_vma_unpin_and_release(&huc->rsa_data, 0); 104 } 105 106 int intel_huc_init(struct intel_huc *huc) 107 { 108 struct drm_i915_private *i915 = huc_to_gt(huc)->i915; 109 int err; 110 111 err = intel_uc_fw_init(&huc->fw); 112 if (err) 113 goto out; 114 115 /* 116 * HuC firmware image is outside GuC accessible range. 117 * Copy the RSA signature out of the image into 118 * a perma-pinned region set aside for it 119 */ 120 err = intel_huc_rsa_data_create(huc); 121 if (err) 122 goto out_fini; 123 124 intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_LOADABLE); 125 126 return 0; 127 128 out_fini: 129 intel_uc_fw_fini(&huc->fw); 130 out: 131 i915_probe_error(i915, "failed with %d\n", err); 132 return err; 133 } 134 135 void intel_huc_fini(struct intel_huc *huc) 136 { 137 if (!intel_uc_fw_is_loadable(&huc->fw)) 138 return; 139 140 intel_huc_rsa_data_destroy(huc); 141 intel_uc_fw_fini(&huc->fw); 142 } 143 144 /** 145 * intel_huc_auth() - Authenticate HuC uCode 146 * @huc: intel_huc structure 147 * 148 * Called after HuC and GuC firmware loading during intel_uc_init_hw(). 149 * 150 * This function invokes the GuC action to authenticate the HuC firmware, 151 * passing the offset of the RSA signature to intel_guc_auth_huc(). It then 152 * waits for up to 50ms for firmware verification ACK. 153 */ 154 int intel_huc_auth(struct intel_huc *huc) 155 { 156 struct intel_gt *gt = huc_to_gt(huc); 157 struct intel_guc *guc = >->uc.guc; 158 int ret; 159 160 GEM_BUG_ON(intel_huc_is_authenticated(huc)); 161 162 if (!intel_uc_fw_is_loaded(&huc->fw)) 163 return -ENOEXEC; 164 165 ret = i915_inject_probe_error(gt->i915, -ENXIO); 166 if (ret) 167 goto fail; 168 169 ret = intel_guc_auth_huc(guc, 170 intel_guc_ggtt_offset(guc, huc->rsa_data)); 171 if (ret) { 172 DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret); 173 goto fail; 174 } 175 176 /* Check authentication status, it should be done by now */ 177 ret = __intel_wait_for_register(gt->uncore, 178 huc->status.reg, 179 huc->status.mask, 180 huc->status.value, 181 2, 50, NULL); 182 if (ret) { 183 DRM_ERROR("HuC: Firmware not verified %d\n", ret); 184 goto fail; 185 } 186 187 intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_RUNNING); 188 return 0; 189 190 fail: 191 i915_probe_error(gt->i915, "HuC: Authentication failed %d\n", ret); 192 intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_FAIL); 193 return ret; 194 } 195 196 /** 197 * intel_huc_check_status() - check HuC status 198 * @huc: intel_huc structure 199 * 200 * This function reads status register to verify if HuC 201 * firmware was successfully loaded. 202 * 203 * Returns: 204 * * -ENODEV if HuC is not present on this platform, 205 * * -EOPNOTSUPP if HuC firmware is disabled, 206 * * -ENOPKG if HuC firmware was not installed, 207 * * -ENOEXEC if HuC firmware is invalid or mismatched, 208 * * 0 if HuC firmware is not running, 209 * * 1 if HuC firmware is authenticated and running. 210 */ 211 int intel_huc_check_status(struct intel_huc *huc) 212 { 213 struct intel_gt *gt = huc_to_gt(huc); 214 intel_wakeref_t wakeref; 215 u32 status = 0; 216 217 switch (__intel_uc_fw_status(&huc->fw)) { 218 case INTEL_UC_FIRMWARE_NOT_SUPPORTED: 219 return -ENODEV; 220 case INTEL_UC_FIRMWARE_DISABLED: 221 return -EOPNOTSUPP; 222 case INTEL_UC_FIRMWARE_MISSING: 223 return -ENOPKG; 224 case INTEL_UC_FIRMWARE_ERROR: 225 return -ENOEXEC; 226 default: 227 break; 228 } 229 230 with_intel_runtime_pm(gt->uncore->rpm, wakeref) 231 status = intel_uncore_read(gt->uncore, huc->status.reg); 232 233 return (status & huc->status.mask) == huc->status.value; 234 } 235 236 /** 237 * intel_huc_load_status - dump information about HuC load status 238 * @huc: the HuC 239 * @p: the &drm_printer 240 * 241 * Pretty printer for HuC load status. 242 */ 243 void intel_huc_load_status(struct intel_huc *huc, struct drm_printer *p) 244 { 245 struct intel_gt *gt = huc_to_gt(huc); 246 intel_wakeref_t wakeref; 247 248 if (!intel_huc_is_supported(huc)) { 249 drm_printf(p, "HuC not supported\n"); 250 return; 251 } 252 253 if (!intel_huc_is_wanted(huc)) { 254 drm_printf(p, "HuC disabled\n"); 255 return; 256 } 257 258 intel_uc_fw_dump(&huc->fw, p); 259 260 with_intel_runtime_pm(gt->uncore->rpm, wakeref) 261 drm_printf(p, "HuC status: 0x%08x\n", 262 intel_uncore_read(gt->uncore, huc->status.reg)); 263 } 264