xref: /openbmc/linux/drivers/gpu/drm/i915/gt/uc/intel_huc.c (revision 1f012283)
1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright © 2016-2019 Intel Corporation
4  */
5 
6 #include <linux/types.h>
7 
8 #include "gt/intel_gt.h"
9 #include "intel_huc.h"
10 #include "i915_drv.h"
11 
12 /**
13  * DOC: HuC
14  *
15  * The HuC is a dedicated microcontroller for usage in media HEVC (High
16  * Efficiency Video Coding) operations. Userspace can directly use the firmware
17  * capabilities by adding HuC specific commands to batch buffers.
18  *
19  * The kernel driver is only responsible for loading the HuC firmware and
20  * triggering its security authentication, which is performed by the GuC. For
21  * The GuC to correctly perform the authentication, the HuC binary must be
22  * loaded before the GuC one. Loading the HuC is optional; however, not using
23  * the HuC might negatively impact power usage and/or performance of media
24  * workloads, depending on the use-cases.
25  *
26  * See https://github.com/intel/media-driver for the latest details on HuC
27  * functionality.
28  */
29 
30 /**
31  * DOC: HuC Memory Management
32  *
33  * Similarly to the GuC, the HuC can't do any memory allocations on its own,
34  * with the difference being that the allocations for HuC usage are handled by
35  * the userspace driver instead of the kernel one. The HuC accesses the memory
36  * via the PPGTT belonging to the context loaded on the VCS executing the
37  * HuC-specific commands.
38  */
39 
40 void intel_huc_init_early(struct intel_huc *huc)
41 {
42 	struct drm_i915_private *i915 = huc_to_gt(huc)->i915;
43 
44 	intel_uc_fw_init_early(&huc->fw, INTEL_UC_FW_TYPE_HUC);
45 
46 	if (GRAPHICS_VER(i915) >= 11) {
47 		huc->status.reg = GEN11_HUC_KERNEL_LOAD_INFO;
48 		huc->status.mask = HUC_LOAD_SUCCESSFUL;
49 		huc->status.value = HUC_LOAD_SUCCESSFUL;
50 	} else {
51 		huc->status.reg = HUC_STATUS2;
52 		huc->status.mask = HUC_FW_VERIFIED;
53 		huc->status.value = HUC_FW_VERIFIED;
54 	}
55 }
56 
57 static int intel_huc_rsa_data_create(struct intel_huc *huc)
58 {
59 	struct intel_gt *gt = huc_to_gt(huc);
60 	struct intel_guc *guc = &gt->uc.guc;
61 	struct i915_vma *vma;
62 	size_t copied;
63 	void *vaddr;
64 	int err;
65 
66 	err = i915_inject_probe_error(gt->i915, -ENXIO);
67 	if (err)
68 		return err;
69 
70 	/*
71 	 * HuC firmware will sit above GUC_GGTT_TOP and will not map
72 	 * through GTT. Unfortunately, this means GuC cannot perform
73 	 * the HuC auth. as the rsa offset now falls within the GuC
74 	 * inaccessible range. We resort to perma-pinning an additional
75 	 * vma within the accessible range that only contains the rsa
76 	 * signature. The GuC can use this extra pinning to perform
77 	 * the authentication since its GGTT offset will be GuC
78 	 * accessible.
79 	 */
80 	GEM_BUG_ON(huc->fw.rsa_size > PAGE_SIZE);
81 	vma = intel_guc_allocate_vma(guc, PAGE_SIZE);
82 	if (IS_ERR(vma))
83 		return PTR_ERR(vma);
84 
85 	vaddr = i915_gem_object_pin_map_unlocked(vma->obj,
86 						 i915_coherent_map_type(gt->i915,
87 									vma->obj, true));
88 	if (IS_ERR(vaddr)) {
89 		i915_vma_unpin_and_release(&vma, 0);
90 		err = PTR_ERR(vaddr);
91 		goto unpin_out;
92 	}
93 
94 	copied = intel_uc_fw_copy_rsa(&huc->fw, vaddr, vma->size);
95 	i915_gem_object_unpin_map(vma->obj);
96 
97 	if (copied < huc->fw.rsa_size) {
98 		err = -ENOMEM;
99 		goto unpin_out;
100 	}
101 
102 	huc->rsa_data = vma;
103 
104 	return 0;
105 
106 unpin_out:
107 	i915_vma_unpin_and_release(&vma, 0);
108 	return err;
109 }
110 
111 static void intel_huc_rsa_data_destroy(struct intel_huc *huc)
112 {
113 	i915_vma_unpin_and_release(&huc->rsa_data, 0);
114 }
115 
116 int intel_huc_init(struct intel_huc *huc)
117 {
118 	struct drm_i915_private *i915 = huc_to_gt(huc)->i915;
119 	int err;
120 
121 	err = intel_uc_fw_init(&huc->fw);
122 	if (err)
123 		goto out;
124 
125 	/*
126 	 * HuC firmware image is outside GuC accessible range.
127 	 * Copy the RSA signature out of the image into
128 	 * a perma-pinned region set aside for it
129 	 */
130 	err = intel_huc_rsa_data_create(huc);
131 	if (err)
132 		goto out_fini;
133 
134 	intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_LOADABLE);
135 
136 	return 0;
137 
138 out_fini:
139 	intel_uc_fw_fini(&huc->fw);
140 out:
141 	i915_probe_error(i915, "failed with %d\n", err);
142 	return err;
143 }
144 
145 void intel_huc_fini(struct intel_huc *huc)
146 {
147 	if (!intel_uc_fw_is_loadable(&huc->fw))
148 		return;
149 
150 	intel_huc_rsa_data_destroy(huc);
151 	intel_uc_fw_fini(&huc->fw);
152 }
153 
154 /**
155  * intel_huc_auth() - Authenticate HuC uCode
156  * @huc: intel_huc structure
157  *
158  * Called after HuC and GuC firmware loading during intel_uc_init_hw().
159  *
160  * This function invokes the GuC action to authenticate the HuC firmware,
161  * passing the offset of the RSA signature to intel_guc_auth_huc(). It then
162  * waits for up to 50ms for firmware verification ACK.
163  */
164 int intel_huc_auth(struct intel_huc *huc)
165 {
166 	struct intel_gt *gt = huc_to_gt(huc);
167 	struct intel_guc *guc = &gt->uc.guc;
168 	int ret;
169 
170 	GEM_BUG_ON(intel_huc_is_authenticated(huc));
171 
172 	if (!intel_uc_fw_is_loaded(&huc->fw))
173 		return -ENOEXEC;
174 
175 	ret = i915_inject_probe_error(gt->i915, -ENXIO);
176 	if (ret)
177 		goto fail;
178 
179 	ret = intel_guc_auth_huc(guc,
180 				 intel_guc_ggtt_offset(guc, huc->rsa_data));
181 	if (ret) {
182 		DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret);
183 		goto fail;
184 	}
185 
186 	/* Check authentication status, it should be done by now */
187 	ret = __intel_wait_for_register(gt->uncore,
188 					huc->status.reg,
189 					huc->status.mask,
190 					huc->status.value,
191 					2, 50, NULL);
192 	if (ret) {
193 		DRM_ERROR("HuC: Firmware not verified %d\n", ret);
194 		goto fail;
195 	}
196 
197 	intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_RUNNING);
198 	return 0;
199 
200 fail:
201 	i915_probe_error(gt->i915, "HuC: Authentication failed %d\n", ret);
202 	intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_FAIL);
203 	return ret;
204 }
205 
206 /**
207  * intel_huc_check_status() - check HuC status
208  * @huc: intel_huc structure
209  *
210  * This function reads status register to verify if HuC
211  * firmware was successfully loaded.
212  *
213  * Returns:
214  *  * -ENODEV if HuC is not present on this platform,
215  *  * -EOPNOTSUPP if HuC firmware is disabled,
216  *  * -ENOPKG if HuC firmware was not installed,
217  *  * -ENOEXEC if HuC firmware is invalid or mismatched,
218  *  * 0 if HuC firmware is not running,
219  *  * 1 if HuC firmware is authenticated and running.
220  */
221 int intel_huc_check_status(struct intel_huc *huc)
222 {
223 	struct intel_gt *gt = huc_to_gt(huc);
224 	intel_wakeref_t wakeref;
225 	u32 status = 0;
226 
227 	switch (__intel_uc_fw_status(&huc->fw)) {
228 	case INTEL_UC_FIRMWARE_NOT_SUPPORTED:
229 		return -ENODEV;
230 	case INTEL_UC_FIRMWARE_DISABLED:
231 		return -EOPNOTSUPP;
232 	case INTEL_UC_FIRMWARE_MISSING:
233 		return -ENOPKG;
234 	case INTEL_UC_FIRMWARE_ERROR:
235 		return -ENOEXEC;
236 	default:
237 		break;
238 	}
239 
240 	with_intel_runtime_pm(gt->uncore->rpm, wakeref)
241 		status = intel_uncore_read(gt->uncore, huc->status.reg);
242 
243 	return (status & huc->status.mask) == huc->status.value;
244 }
245 
246 /**
247  * intel_huc_load_status - dump information about HuC load status
248  * @huc: the HuC
249  * @p: the &drm_printer
250  *
251  * Pretty printer for HuC load status.
252  */
253 void intel_huc_load_status(struct intel_huc *huc, struct drm_printer *p)
254 {
255 	struct intel_gt *gt = huc_to_gt(huc);
256 	intel_wakeref_t wakeref;
257 
258 	if (!intel_huc_is_supported(huc)) {
259 		drm_printf(p, "HuC not supported\n");
260 		return;
261 	}
262 
263 	if (!intel_huc_is_wanted(huc)) {
264 		drm_printf(p, "HuC disabled\n");
265 		return;
266 	}
267 
268 	intel_uc_fw_dump(&huc->fw, p);
269 
270 	with_intel_runtime_pm(gt->uncore->rpm, wakeref)
271 		drm_printf(p, "HuC status: 0x%08x\n",
272 			   intel_uncore_read(gt->uncore, huc->status.reg));
273 }
274