1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2016-2019 Intel Corporation 4 */ 5 6 #include <linux/types.h> 7 8 #include "gt/intel_gt.h" 9 #include "intel_huc.h" 10 #include "i915_drv.h" 11 12 /** 13 * DOC: HuC 14 * 15 * The HuC is a dedicated microcontroller for usage in media HEVC (High 16 * Efficiency Video Coding) operations. Userspace can directly use the firmware 17 * capabilities by adding HuC specific commands to batch buffers. 18 * 19 * The kernel driver is only responsible for loading the HuC firmware and 20 * triggering its security authentication, which is performed by the GuC. For 21 * The GuC to correctly perform the authentication, the HuC binary must be 22 * loaded before the GuC one. Loading the HuC is optional; however, not using 23 * the HuC might negatively impact power usage and/or performance of media 24 * workloads, depending on the use-cases. 25 * 26 * See https://github.com/intel/media-driver for the latest details on HuC 27 * functionality. 28 */ 29 30 /** 31 * DOC: HuC Memory Management 32 * 33 * Similarly to the GuC, the HuC can't do any memory allocations on its own, 34 * with the difference being that the allocations for HuC usage are handled by 35 * the userspace driver instead of the kernel one. The HuC accesses the memory 36 * via the PPGTT belonging to the context loaded on the VCS executing the 37 * HuC-specific commands. 38 */ 39 40 void intel_huc_init_early(struct intel_huc *huc) 41 { 42 struct drm_i915_private *i915 = huc_to_gt(huc)->i915; 43 44 intel_uc_fw_init_early(&huc->fw, INTEL_UC_FW_TYPE_HUC); 45 46 if (GRAPHICS_VER(i915) >= 11) { 47 huc->status.reg = GEN11_HUC_KERNEL_LOAD_INFO; 48 huc->status.mask = HUC_LOAD_SUCCESSFUL; 49 huc->status.value = HUC_LOAD_SUCCESSFUL; 50 } else { 51 huc->status.reg = HUC_STATUS2; 52 huc->status.mask = HUC_FW_VERIFIED; 53 huc->status.value = HUC_FW_VERIFIED; 54 } 55 } 56 57 static int intel_huc_rsa_data_create(struct intel_huc *huc) 58 { 59 struct intel_gt *gt = huc_to_gt(huc); 60 struct intel_guc *guc = >->uc.guc; 61 struct i915_vma *vma; 62 size_t copied; 63 void *vaddr; 64 int err; 65 66 err = i915_inject_probe_error(gt->i915, -ENXIO); 67 if (err) 68 return err; 69 70 /* 71 * HuC firmware will sit above GUC_GGTT_TOP and will not map 72 * through GTT. Unfortunately, this means GuC cannot perform 73 * the HuC auth. as the rsa offset now falls within the GuC 74 * inaccessible range. We resort to perma-pinning an additional 75 * vma within the accessible range that only contains the rsa 76 * signature. The GuC can use this extra pinning to perform 77 * the authentication since its GGTT offset will be GuC 78 * accessible. 79 */ 80 GEM_BUG_ON(huc->fw.rsa_size > PAGE_SIZE); 81 vma = intel_guc_allocate_vma(guc, PAGE_SIZE); 82 if (IS_ERR(vma)) 83 return PTR_ERR(vma); 84 85 vaddr = i915_gem_object_pin_map_unlocked(vma->obj, 86 i915_coherent_map_type(gt->i915, 87 vma->obj, true)); 88 if (IS_ERR(vaddr)) { 89 i915_vma_unpin_and_release(&vma, 0); 90 return PTR_ERR(vaddr); 91 } 92 93 copied = intel_uc_fw_copy_rsa(&huc->fw, vaddr, vma->size); 94 GEM_BUG_ON(copied < huc->fw.rsa_size); 95 96 i915_gem_object_unpin_map(vma->obj); 97 98 huc->rsa_data = vma; 99 100 return 0; 101 } 102 103 static void intel_huc_rsa_data_destroy(struct intel_huc *huc) 104 { 105 i915_vma_unpin_and_release(&huc->rsa_data, 0); 106 } 107 108 int intel_huc_init(struct intel_huc *huc) 109 { 110 struct drm_i915_private *i915 = huc_to_gt(huc)->i915; 111 int err; 112 113 err = intel_uc_fw_init(&huc->fw); 114 if (err) 115 goto out; 116 117 /* 118 * HuC firmware image is outside GuC accessible range. 119 * Copy the RSA signature out of the image into 120 * a perma-pinned region set aside for it 121 */ 122 err = intel_huc_rsa_data_create(huc); 123 if (err) 124 goto out_fini; 125 126 intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_LOADABLE); 127 128 return 0; 129 130 out_fini: 131 intel_uc_fw_fini(&huc->fw); 132 out: 133 i915_probe_error(i915, "failed with %d\n", err); 134 return err; 135 } 136 137 void intel_huc_fini(struct intel_huc *huc) 138 { 139 if (!intel_uc_fw_is_loadable(&huc->fw)) 140 return; 141 142 intel_huc_rsa_data_destroy(huc); 143 intel_uc_fw_fini(&huc->fw); 144 } 145 146 /** 147 * intel_huc_auth() - Authenticate HuC uCode 148 * @huc: intel_huc structure 149 * 150 * Called after HuC and GuC firmware loading during intel_uc_init_hw(). 151 * 152 * This function invokes the GuC action to authenticate the HuC firmware, 153 * passing the offset of the RSA signature to intel_guc_auth_huc(). It then 154 * waits for up to 50ms for firmware verification ACK. 155 */ 156 int intel_huc_auth(struct intel_huc *huc) 157 { 158 struct intel_gt *gt = huc_to_gt(huc); 159 struct intel_guc *guc = >->uc.guc; 160 int ret; 161 162 GEM_BUG_ON(intel_huc_is_authenticated(huc)); 163 164 if (!intel_uc_fw_is_loaded(&huc->fw)) 165 return -ENOEXEC; 166 167 ret = i915_inject_probe_error(gt->i915, -ENXIO); 168 if (ret) 169 goto fail; 170 171 ret = intel_guc_auth_huc(guc, 172 intel_guc_ggtt_offset(guc, huc->rsa_data)); 173 if (ret) { 174 DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret); 175 goto fail; 176 } 177 178 /* Check authentication status, it should be done by now */ 179 ret = __intel_wait_for_register(gt->uncore, 180 huc->status.reg, 181 huc->status.mask, 182 huc->status.value, 183 2, 50, NULL); 184 if (ret) { 185 DRM_ERROR("HuC: Firmware not verified %d\n", ret); 186 goto fail; 187 } 188 189 intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_RUNNING); 190 return 0; 191 192 fail: 193 i915_probe_error(gt->i915, "HuC: Authentication failed %d\n", ret); 194 intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_FAIL); 195 return ret; 196 } 197 198 /** 199 * intel_huc_check_status() - check HuC status 200 * @huc: intel_huc structure 201 * 202 * This function reads status register to verify if HuC 203 * firmware was successfully loaded. 204 * 205 * Returns: 206 * * -ENODEV if HuC is not present on this platform, 207 * * -EOPNOTSUPP if HuC firmware is disabled, 208 * * -ENOPKG if HuC firmware was not installed, 209 * * -ENOEXEC if HuC firmware is invalid or mismatched, 210 * * 0 if HuC firmware is not running, 211 * * 1 if HuC firmware is authenticated and running. 212 */ 213 int intel_huc_check_status(struct intel_huc *huc) 214 { 215 struct intel_gt *gt = huc_to_gt(huc); 216 intel_wakeref_t wakeref; 217 u32 status = 0; 218 219 switch (__intel_uc_fw_status(&huc->fw)) { 220 case INTEL_UC_FIRMWARE_NOT_SUPPORTED: 221 return -ENODEV; 222 case INTEL_UC_FIRMWARE_DISABLED: 223 return -EOPNOTSUPP; 224 case INTEL_UC_FIRMWARE_MISSING: 225 return -ENOPKG; 226 case INTEL_UC_FIRMWARE_ERROR: 227 return -ENOEXEC; 228 default: 229 break; 230 } 231 232 with_intel_runtime_pm(gt->uncore->rpm, wakeref) 233 status = intel_uncore_read(gt->uncore, huc->status.reg); 234 235 return (status & huc->status.mask) == huc->status.value; 236 } 237 238 /** 239 * intel_huc_load_status - dump information about HuC load status 240 * @huc: the HuC 241 * @p: the &drm_printer 242 * 243 * Pretty printer for HuC load status. 244 */ 245 void intel_huc_load_status(struct intel_huc *huc, struct drm_printer *p) 246 { 247 struct intel_gt *gt = huc_to_gt(huc); 248 intel_wakeref_t wakeref; 249 250 if (!intel_huc_is_supported(huc)) { 251 drm_printf(p, "HuC not supported\n"); 252 return; 253 } 254 255 if (!intel_huc_is_wanted(huc)) { 256 drm_printf(p, "HuC disabled\n"); 257 return; 258 } 259 260 intel_uc_fw_dump(&huc->fw, p); 261 262 with_intel_runtime_pm(gt->uncore->rpm, wakeref) 263 drm_printf(p, "HuC status: 0x%08x\n", 264 intel_uncore_read(gt->uncore, huc->status.reg)); 265 } 266