1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright © 2014-2019 Intel Corporation
4  */
5 
6 #ifndef _INTEL_GUC_FWIF_H
7 #define _INTEL_GUC_FWIF_H
8 
9 #include <linux/bits.h>
10 #include <linux/compiler.h>
11 #include <linux/types.h>
12 #include "gt/intel_engine_types.h"
13 
14 #include "abi/guc_actions_abi.h"
15 #include "abi/guc_actions_slpc_abi.h"
16 #include "abi/guc_errors_abi.h"
17 #include "abi/guc_communication_mmio_abi.h"
18 #include "abi/guc_communication_ctb_abi.h"
19 #include "abi/guc_klvs_abi.h"
20 #include "abi/guc_messages_abi.h"
21 
22 /* Payload length only i.e. don't include G2H header length */
23 #define G2H_LEN_DW_SCHED_CONTEXT_MODE_SET	2
24 #define G2H_LEN_DW_DEREGISTER_CONTEXT		1
25 
26 #define GUC_CONTEXT_DISABLE		0
27 #define GUC_CONTEXT_ENABLE		1
28 
29 #define GUC_CLIENT_PRIORITY_KMD_HIGH	0
30 #define GUC_CLIENT_PRIORITY_HIGH	1
31 #define GUC_CLIENT_PRIORITY_KMD_NORMAL	2
32 #define GUC_CLIENT_PRIORITY_NORMAL	3
33 #define GUC_CLIENT_PRIORITY_NUM		4
34 
35 #define GUC_MAX_CONTEXT_ID		65535
36 #define	GUC_INVALID_CONTEXT_ID		GUC_MAX_CONTEXT_ID
37 
38 #define GUC_RENDER_ENGINE		0
39 #define GUC_VIDEO_ENGINE		1
40 #define GUC_BLITTER_ENGINE		2
41 #define GUC_VIDEOENHANCE_ENGINE		3
42 #define GUC_VIDEO_ENGINE2		4
43 #define GUC_MAX_ENGINES_NUM		(GUC_VIDEO_ENGINE2 + 1)
44 
45 #define GUC_RENDER_CLASS		0
46 #define GUC_VIDEO_CLASS			1
47 #define GUC_VIDEOENHANCE_CLASS		2
48 #define GUC_BLITTER_CLASS		3
49 #define GUC_COMPUTE_CLASS		4
50 #define GUC_LAST_ENGINE_CLASS		GUC_COMPUTE_CLASS
51 #define GUC_MAX_ENGINE_CLASSES		16
52 #define GUC_MAX_INSTANCES_PER_CLASS	32
53 
54 #define GUC_DOORBELL_INVALID		256
55 
56 /*
57  * Work queue item header definitions
58  *
59  * Work queue is circular buffer used to submit complex (multi-lrc) submissions
60  * to the GuC. A work queue item is an entry in the circular buffer.
61  */
62 #define WQ_STATUS_ACTIVE		1
63 #define WQ_STATUS_SUSPENDED		2
64 #define WQ_STATUS_CMD_ERROR		3
65 #define WQ_STATUS_ENGINE_ID_NOT_USED	4
66 #define WQ_STATUS_SUSPENDED_FROM_RESET	5
67 #define WQ_TYPE_BATCH_BUF		0x1
68 #define WQ_TYPE_PSEUDO			0x2
69 #define WQ_TYPE_INORDER			0x3
70 #define WQ_TYPE_NOOP			0x4
71 #define WQ_TYPE_MULTI_LRC		0x5
72 #define WQ_TYPE_MASK			GENMASK(7, 0)
73 #define WQ_LEN_MASK			GENMASK(26, 16)
74 
75 #define WQ_GUC_ID_MASK			GENMASK(15, 0)
76 #define WQ_RING_TAIL_MASK		GENMASK(28, 18)
77 
78 #define GUC_STAGE_DESC_ATTR_ACTIVE	BIT(0)
79 #define GUC_STAGE_DESC_ATTR_PENDING_DB	BIT(1)
80 #define GUC_STAGE_DESC_ATTR_KERNEL	BIT(2)
81 #define GUC_STAGE_DESC_ATTR_PREEMPT	BIT(3)
82 #define GUC_STAGE_DESC_ATTR_RESET	BIT(4)
83 #define GUC_STAGE_DESC_ATTR_WQLOCKED	BIT(5)
84 #define GUC_STAGE_DESC_ATTR_PCH		BIT(6)
85 #define GUC_STAGE_DESC_ATTR_TERMINATED	BIT(7)
86 
87 #define GUC_CTL_LOG_PARAMS		0
88 #define   GUC_LOG_VALID			BIT(0)
89 #define   GUC_LOG_NOTIFY_ON_HALF_FULL	BIT(1)
90 #define   GUC_LOG_CAPTURE_ALLOC_UNITS	BIT(2)
91 #define   GUC_LOG_LOG_ALLOC_UNITS	BIT(3)
92 #define   GUC_LOG_CRASH_SHIFT		4
93 #define   GUC_LOG_CRASH_MASK		(0x3 << GUC_LOG_CRASH_SHIFT)
94 #define   GUC_LOG_DEBUG_SHIFT		6
95 #define   GUC_LOG_DEBUG_MASK	        (0xF << GUC_LOG_DEBUG_SHIFT)
96 #define   GUC_LOG_CAPTURE_SHIFT		10
97 #define   GUC_LOG_CAPTURE_MASK	        (0x3 << GUC_LOG_CAPTURE_SHIFT)
98 #define   GUC_LOG_BUF_ADDR_SHIFT	12
99 
100 #define GUC_CTL_WA			1
101 #define   GUC_WA_GAM_CREDITS		BIT(10)
102 #define   GUC_WA_DUAL_QUEUE		BIT(11)
103 #define   GUC_WA_RCS_RESET_BEFORE_RC6	BIT(13)
104 #define   GUC_WA_CONTEXT_ISOLATION	BIT(15)
105 #define   GUC_WA_PRE_PARSER		BIT(14)
106 #define   GUC_WA_HOLD_CCS_SWITCHOUT	BIT(17)
107 #define   GUC_WA_POLLCS			BIT(18)
108 
109 #define GUC_CTL_FEATURE			2
110 #define   GUC_CTL_ENABLE_SLPC		BIT(2)
111 #define   GUC_CTL_DISABLE_SCHEDULER	BIT(14)
112 
113 #define GUC_CTL_DEBUG			3
114 #define   GUC_LOG_VERBOSITY_SHIFT	0
115 #define   GUC_LOG_VERBOSITY_LOW		(0 << GUC_LOG_VERBOSITY_SHIFT)
116 #define   GUC_LOG_VERBOSITY_MED		(1 << GUC_LOG_VERBOSITY_SHIFT)
117 #define   GUC_LOG_VERBOSITY_HIGH	(2 << GUC_LOG_VERBOSITY_SHIFT)
118 #define   GUC_LOG_VERBOSITY_ULTRA	(3 << GUC_LOG_VERBOSITY_SHIFT)
119 /* Verbosity range-check limits, without the shift */
120 #define	  GUC_LOG_VERBOSITY_MIN		0
121 #define	  GUC_LOG_VERBOSITY_MAX		3
122 #define	  GUC_LOG_VERBOSITY_MASK	0x0000000f
123 #define	  GUC_LOG_DESTINATION_MASK	(3 << 4)
124 #define   GUC_LOG_DISABLED		(1 << 6)
125 #define   GUC_PROFILE_ENABLED		(1 << 7)
126 
127 #define GUC_CTL_ADS			4
128 #define   GUC_ADS_ADDR_SHIFT		1
129 #define   GUC_ADS_ADDR_MASK		(0xFFFFF << GUC_ADS_ADDR_SHIFT)
130 
131 #define GUC_CTL_DEVID			5
132 
133 #define GUC_CTL_MAX_DWORDS		(SOFT_SCRATCH_COUNT - 2) /* [1..14] */
134 
135 /* Generic GT SysInfo data types */
136 #define GUC_GENERIC_GT_SYSINFO_SLICE_ENABLED		0
137 #define GUC_GENERIC_GT_SYSINFO_VDBOX_SFC_SUPPORT_MASK	1
138 #define GUC_GENERIC_GT_SYSINFO_DOORBELL_COUNT_PER_SQIDI	2
139 #define GUC_GENERIC_GT_SYSINFO_MAX			16
140 
141 /*
142  * The class goes in bits [0..2] of the GuC ID, the instance in bits [3..6].
143  * Bit 7 can be used for operations that apply to all engine classes&instances.
144  */
145 #define GUC_ENGINE_CLASS_SHIFT		0
146 #define GUC_ENGINE_CLASS_MASK		(0x7 << GUC_ENGINE_CLASS_SHIFT)
147 #define GUC_ENGINE_INSTANCE_SHIFT	3
148 #define GUC_ENGINE_INSTANCE_MASK	(0xf << GUC_ENGINE_INSTANCE_SHIFT)
149 #define GUC_ENGINE_ALL_INSTANCES	BIT(7)
150 
151 #define MAKE_GUC_ID(class, instance) \
152 	(((class) << GUC_ENGINE_CLASS_SHIFT) | \
153 	 ((instance) << GUC_ENGINE_INSTANCE_SHIFT))
154 
155 #define GUC_ID_TO_ENGINE_CLASS(guc_id) \
156 	(((guc_id) & GUC_ENGINE_CLASS_MASK) >> GUC_ENGINE_CLASS_SHIFT)
157 #define GUC_ID_TO_ENGINE_INSTANCE(guc_id) \
158 	(((guc_id) & GUC_ENGINE_INSTANCE_MASK) >> GUC_ENGINE_INSTANCE_SHIFT)
159 
160 #define SLPC_EVENT(id, c) (\
161 FIELD_PREP(HOST2GUC_PC_SLPC_REQUEST_MSG_1_EVENT_ID, id) | \
162 FIELD_PREP(HOST2GUC_PC_SLPC_REQUEST_MSG_1_EVENT_ARGC, c) \
163 )
164 
165 /* the GuC arrays don't include OTHER_CLASS */
166 static u8 engine_class_guc_class_map[] = {
167 	[RENDER_CLASS]            = GUC_RENDER_CLASS,
168 	[COPY_ENGINE_CLASS]       = GUC_BLITTER_CLASS,
169 	[VIDEO_DECODE_CLASS]      = GUC_VIDEO_CLASS,
170 	[VIDEO_ENHANCEMENT_CLASS] = GUC_VIDEOENHANCE_CLASS,
171 	[COMPUTE_CLASS]           = GUC_COMPUTE_CLASS,
172 };
173 
174 static u8 guc_class_engine_class_map[] = {
175 	[GUC_RENDER_CLASS]       = RENDER_CLASS,
176 	[GUC_BLITTER_CLASS]      = COPY_ENGINE_CLASS,
177 	[GUC_VIDEO_CLASS]        = VIDEO_DECODE_CLASS,
178 	[GUC_VIDEOENHANCE_CLASS] = VIDEO_ENHANCEMENT_CLASS,
179 	[GUC_COMPUTE_CLASS]      = COMPUTE_CLASS,
180 };
181 
182 static inline u8 engine_class_to_guc_class(u8 class)
183 {
184 	BUILD_BUG_ON(ARRAY_SIZE(engine_class_guc_class_map) != MAX_ENGINE_CLASS + 1);
185 	GEM_BUG_ON(class > MAX_ENGINE_CLASS || class == OTHER_CLASS);
186 
187 	return engine_class_guc_class_map[class];
188 }
189 
190 static inline u8 guc_class_to_engine_class(u8 guc_class)
191 {
192 	BUILD_BUG_ON(ARRAY_SIZE(guc_class_engine_class_map) != GUC_LAST_ENGINE_CLASS + 1);
193 	GEM_BUG_ON(guc_class > GUC_LAST_ENGINE_CLASS);
194 
195 	return guc_class_engine_class_map[guc_class];
196 }
197 
198 /* Work item for submitting workloads into work queue of GuC. */
199 struct guc_wq_item {
200 	u32 header;
201 	u32 context_desc;
202 	u32 submit_element_info;
203 	u32 fence_id;
204 } __packed;
205 
206 struct guc_sched_wq_desc {
207 	u32 head;
208 	u32 tail;
209 	u32 error_offset;
210 	u32 wq_status;
211 	u32 reserved[28];
212 } __packed;
213 
214 /* Helper for context registration H2G */
215 struct guc_ctxt_registration_info {
216 	u32 flags;
217 	u32 context_idx;
218 	u32 engine_class;
219 	u32 engine_submit_mask;
220 	u32 wq_desc_lo;
221 	u32 wq_desc_hi;
222 	u32 wq_base_lo;
223 	u32 wq_base_hi;
224 	u32 wq_size;
225 	u32 hwlrca_lo;
226 	u32 hwlrca_hi;
227 };
228 #define CONTEXT_REGISTRATION_FLAG_KMD	BIT(0)
229 
230 /* 32-bit KLV structure as used by policy updates and others */
231 struct guc_klv_generic_dw_t {
232 	u32 kl;
233 	u32 value;
234 } __packed;
235 
236 /* Format of the UPDATE_CONTEXT_POLICIES H2G data packet */
237 struct guc_update_context_policy_header {
238 	u32 action;
239 	u32 ctx_id;
240 } __packed;
241 
242 struct guc_update_context_policy {
243 	struct guc_update_context_policy_header header;
244 	struct guc_klv_generic_dw_t klv[GUC_CONTEXT_POLICIES_KLV_NUM_IDS];
245 } __packed;
246 
247 #define GUC_POWER_UNSPECIFIED	0
248 #define GUC_POWER_D0		1
249 #define GUC_POWER_D1		2
250 #define GUC_POWER_D2		3
251 #define GUC_POWER_D3		4
252 
253 /* Scheduling policy settings */
254 
255 #define GLOBAL_POLICY_MAX_NUM_WI 15
256 
257 /* Don't reset an engine upon preemption failure */
258 #define GLOBAL_POLICY_DISABLE_ENGINE_RESET				BIT(0)
259 
260 #define GLOBAL_POLICY_DEFAULT_DPC_PROMOTE_TIME_US 500000
261 
262 struct guc_policies {
263 	u32 submission_queue_depth[GUC_MAX_ENGINE_CLASSES];
264 	/* In micro seconds. How much time to allow before DPC processing is
265 	 * called back via interrupt (to prevent DPC queue drain starving).
266 	 * Typically 1000s of micro seconds (example only, not granularity). */
267 	u32 dpc_promote_time;
268 
269 	/* Must be set to take these new values. */
270 	u32 is_valid;
271 
272 	/* Max number of WIs to process per call. A large value may keep CS
273 	 * idle. */
274 	u32 max_num_work_items;
275 
276 	u32 global_flags;
277 	u32 reserved[4];
278 } __packed;
279 
280 /* GuC MMIO reg state struct */
281 struct guc_mmio_reg {
282 	u32 offset;
283 	u32 value;
284 	u32 flags;
285 #define GUC_REGSET_MASKED		BIT(0)
286 #define GUC_REGSET_NEEDS_STEERING	BIT(1)
287 #define GUC_REGSET_MASKED_WITH_VALUE	BIT(2)
288 #define GUC_REGSET_RESTORE_ONLY		BIT(3)
289 #define GUC_REGSET_STEERING_GROUP       GENMASK(15, 12)
290 #define GUC_REGSET_STEERING_INSTANCE    GENMASK(23, 20)
291 	u32 mask;
292 } __packed;
293 
294 /* GuC register sets */
295 struct guc_mmio_reg_set {
296 	u32 address;
297 	u16 count;
298 	u16 reserved;
299 } __packed;
300 
301 /* HW info */
302 struct guc_gt_system_info {
303 	u8 mapping_table[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
304 	u32 engine_enabled_masks[GUC_MAX_ENGINE_CLASSES];
305 	u32 generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_MAX];
306 } __packed;
307 
308 enum {
309 	GUC_CAPTURE_LIST_INDEX_PF = 0,
310 	GUC_CAPTURE_LIST_INDEX_VF = 1,
311 	GUC_CAPTURE_LIST_INDEX_MAX = 2,
312 };
313 
314 /*Register-types of GuC capture register lists */
315 enum guc_capture_type {
316 	GUC_CAPTURE_LIST_TYPE_GLOBAL = 0,
317 	GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS,
318 	GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE,
319 	GUC_CAPTURE_LIST_TYPE_MAX,
320 };
321 
322 /* GuC Additional Data Struct */
323 struct guc_ads {
324 	struct guc_mmio_reg_set reg_state_list[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
325 	u32 reserved0;
326 	u32 scheduler_policies;
327 	u32 gt_system_info;
328 	u32 reserved1;
329 	u32 control_data;
330 	u32 golden_context_lrca[GUC_MAX_ENGINE_CLASSES];
331 	u32 eng_state_size[GUC_MAX_ENGINE_CLASSES];
332 	u32 private_data;
333 	u32 reserved2;
334 	u32 capture_instance[GUC_CAPTURE_LIST_INDEX_MAX][GUC_MAX_ENGINE_CLASSES];
335 	u32 capture_class[GUC_CAPTURE_LIST_INDEX_MAX][GUC_MAX_ENGINE_CLASSES];
336 	u32 capture_global[GUC_CAPTURE_LIST_INDEX_MAX];
337 	u32 reserved[14];
338 } __packed;
339 
340 /* Engine usage stats */
341 struct guc_engine_usage_record {
342 	u32 current_context_index;
343 	u32 last_switch_in_stamp;
344 	u32 reserved0;
345 	u32 total_runtime;
346 	u32 reserved1[4];
347 } __packed;
348 
349 struct guc_engine_usage {
350 	struct guc_engine_usage_record engines[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
351 } __packed;
352 
353 /* GuC logging structures */
354 
355 enum guc_log_buffer_type {
356 	GUC_DEBUG_LOG_BUFFER,
357 	GUC_CRASH_DUMP_LOG_BUFFER,
358 	GUC_CAPTURE_LOG_BUFFER,
359 	GUC_MAX_LOG_BUFFER
360 };
361 
362 /**
363  * struct guc_log_buffer_state - GuC log buffer state
364  *
365  * Below state structure is used for coordination of retrieval of GuC firmware
366  * logs. Separate state is maintained for each log buffer type.
367  * read_ptr points to the location where i915 read last in log buffer and
368  * is read only for GuC firmware. write_ptr is incremented by GuC with number
369  * of bytes written for each log entry and is read only for i915.
370  * When any type of log buffer becomes half full, GuC sends a flush interrupt.
371  * GuC firmware expects that while it is writing to 2nd half of the buffer,
372  * first half would get consumed by Host and then get a flush completed
373  * acknowledgment from Host, so that it does not end up doing any overwrite
374  * causing loss of logs. So when buffer gets half filled & i915 has requested
375  * for interrupt, GuC will set flush_to_file field, set the sampled_write_ptr
376  * to the value of write_ptr and raise the interrupt.
377  * On receiving the interrupt i915 should read the buffer, clear flush_to_file
378  * field and also update read_ptr with the value of sample_write_ptr, before
379  * sending an acknowledgment to GuC. marker & version fields are for internal
380  * usage of GuC and opaque to i915. buffer_full_cnt field is incremented every
381  * time GuC detects the log buffer overflow.
382  */
383 struct guc_log_buffer_state {
384 	u32 marker[2];
385 	u32 read_ptr;
386 	u32 write_ptr;
387 	u32 size;
388 	u32 sampled_write_ptr;
389 	u32 wrap_offset;
390 	union {
391 		struct {
392 			u32 flush_to_file:1;
393 			u32 buffer_full_cnt:4;
394 			u32 reserved:27;
395 		};
396 		u32 flags;
397 	};
398 	u32 version;
399 } __packed;
400 
401 struct guc_ctx_report {
402 	u32 report_return_status;
403 	u32 reserved1[64];
404 	u32 affected_count;
405 	u32 reserved2[2];
406 } __packed;
407 
408 /* GuC Shared Context Data Struct */
409 struct guc_shared_ctx_data {
410 	u32 addr_of_last_preempted_data_low;
411 	u32 addr_of_last_preempted_data_high;
412 	u32 addr_of_last_preempted_data_high_tmp;
413 	u32 padding;
414 	u32 is_mapped_to_proxy;
415 	u32 proxy_ctx_id;
416 	u32 engine_reset_ctx_id;
417 	u32 media_reset_count;
418 	u32 reserved1[8];
419 	u32 uk_last_ctx_switch_reason;
420 	u32 was_reset;
421 	u32 lrca_gpu_addr;
422 	u64 execlist_ctx;
423 	u32 reserved2[66];
424 	struct guc_ctx_report preempt_ctx_report[GUC_MAX_ENGINES_NUM];
425 } __packed;
426 
427 /* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */
428 enum intel_guc_recv_message {
429 	INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1),
430 	INTEL_GUC_RECV_MSG_EXCEPTION = BIT(30),
431 };
432 
433 #endif
434