1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 #ifndef _INTEL_GUC_FWIF_H 24 #define _INTEL_GUC_FWIF_H 25 26 #include <linux/bits.h> 27 #include <linux/compiler.h> 28 #include <linux/types.h> 29 30 #define GUC_CLIENT_PRIORITY_KMD_HIGH 0 31 #define GUC_CLIENT_PRIORITY_HIGH 1 32 #define GUC_CLIENT_PRIORITY_KMD_NORMAL 2 33 #define GUC_CLIENT_PRIORITY_NORMAL 3 34 #define GUC_CLIENT_PRIORITY_NUM 4 35 36 #define GUC_MAX_STAGE_DESCRIPTORS 1024 37 #define GUC_INVALID_STAGE_ID GUC_MAX_STAGE_DESCRIPTORS 38 39 #define GUC_RENDER_ENGINE 0 40 #define GUC_VIDEO_ENGINE 1 41 #define GUC_BLITTER_ENGINE 2 42 #define GUC_VIDEOENHANCE_ENGINE 3 43 #define GUC_VIDEO_ENGINE2 4 44 #define GUC_MAX_ENGINES_NUM (GUC_VIDEO_ENGINE2 + 1) 45 46 #define GUC_MAX_ENGINE_CLASSES 5 47 #define GUC_MAX_INSTANCES_PER_CLASS 16 48 49 #define GUC_DOORBELL_INVALID 256 50 51 #define GUC_DB_SIZE (PAGE_SIZE) 52 #define GUC_WQ_SIZE (PAGE_SIZE * 2) 53 54 /* Work queue item header definitions */ 55 #define WQ_STATUS_ACTIVE 1 56 #define WQ_STATUS_SUSPENDED 2 57 #define WQ_STATUS_CMD_ERROR 3 58 #define WQ_STATUS_ENGINE_ID_NOT_USED 4 59 #define WQ_STATUS_SUSPENDED_FROM_RESET 5 60 #define WQ_TYPE_SHIFT 0 61 #define WQ_TYPE_BATCH_BUF (0x1 << WQ_TYPE_SHIFT) 62 #define WQ_TYPE_PSEUDO (0x2 << WQ_TYPE_SHIFT) 63 #define WQ_TYPE_INORDER (0x3 << WQ_TYPE_SHIFT) 64 #define WQ_TYPE_NOOP (0x4 << WQ_TYPE_SHIFT) 65 #define WQ_TARGET_SHIFT 10 66 #define WQ_LEN_SHIFT 16 67 #define WQ_NO_WCFLUSH_WAIT (1 << 27) 68 #define WQ_PRESENT_WORKLOAD (1 << 28) 69 70 #define WQ_RING_TAIL_SHIFT 20 71 #define WQ_RING_TAIL_MAX 0x7FF /* 2^11 QWords */ 72 #define WQ_RING_TAIL_MASK (WQ_RING_TAIL_MAX << WQ_RING_TAIL_SHIFT) 73 74 #define GUC_STAGE_DESC_ATTR_ACTIVE BIT(0) 75 #define GUC_STAGE_DESC_ATTR_PENDING_DB BIT(1) 76 #define GUC_STAGE_DESC_ATTR_KERNEL BIT(2) 77 #define GUC_STAGE_DESC_ATTR_PREEMPT BIT(3) 78 #define GUC_STAGE_DESC_ATTR_RESET BIT(4) 79 #define GUC_STAGE_DESC_ATTR_WQLOCKED BIT(5) 80 #define GUC_STAGE_DESC_ATTR_PCH BIT(6) 81 #define GUC_STAGE_DESC_ATTR_TERMINATED BIT(7) 82 83 /* New GuC control data */ 84 #define GUC_CTL_CTXINFO 0 85 #define GUC_CTL_CTXNUM_IN16_SHIFT 0 86 #define GUC_CTL_BASE_ADDR_SHIFT 12 87 88 #define GUC_CTL_LOG_PARAMS 1 89 #define GUC_LOG_VALID (1 << 0) 90 #define GUC_LOG_NOTIFY_ON_HALF_FULL (1 << 1) 91 #define GUC_LOG_ALLOC_IN_MEGABYTE (1 << 3) 92 #define GUC_LOG_CRASH_SHIFT 4 93 #define GUC_LOG_CRASH_MASK (0x3 << GUC_LOG_CRASH_SHIFT) 94 #define GUC_LOG_DPC_SHIFT 6 95 #define GUC_LOG_DPC_MASK (0x7 << GUC_LOG_DPC_SHIFT) 96 #define GUC_LOG_ISR_SHIFT 9 97 #define GUC_LOG_ISR_MASK (0x7 << GUC_LOG_ISR_SHIFT) 98 #define GUC_LOG_BUF_ADDR_SHIFT 12 99 100 #define GUC_CTL_WA 2 101 #define GUC_CTL_FEATURE 3 102 #define GUC_CTL_DISABLE_SCHEDULER (1 << 14) 103 104 #define GUC_CTL_DEBUG 4 105 #define GUC_LOG_VERBOSITY_SHIFT 0 106 #define GUC_LOG_VERBOSITY_LOW (0 << GUC_LOG_VERBOSITY_SHIFT) 107 #define GUC_LOG_VERBOSITY_MED (1 << GUC_LOG_VERBOSITY_SHIFT) 108 #define GUC_LOG_VERBOSITY_HIGH (2 << GUC_LOG_VERBOSITY_SHIFT) 109 #define GUC_LOG_VERBOSITY_ULTRA (3 << GUC_LOG_VERBOSITY_SHIFT) 110 /* Verbosity range-check limits, without the shift */ 111 #define GUC_LOG_VERBOSITY_MIN 0 112 #define GUC_LOG_VERBOSITY_MAX 3 113 #define GUC_LOG_VERBOSITY_MASK 0x0000000f 114 #define GUC_LOG_DESTINATION_MASK (3 << 4) 115 #define GUC_LOG_DISABLED (1 << 6) 116 #define GUC_PROFILE_ENABLED (1 << 7) 117 118 #define GUC_CTL_ADS 5 119 #define GUC_ADS_ADDR_SHIFT 1 120 #define GUC_ADS_ADDR_MASK (0xFFFFF << GUC_ADS_ADDR_SHIFT) 121 122 #define GUC_CTL_MAX_DWORDS (SOFT_SCRATCH_COUNT - 2) /* [1..14] */ 123 124 /* Work item for submitting workloads into work queue of GuC. */ 125 struct guc_wq_item { 126 u32 header; 127 u32 context_desc; 128 u32 submit_element_info; 129 u32 fence_id; 130 } __packed; 131 132 struct guc_process_desc { 133 u32 stage_id; 134 u64 db_base_addr; 135 u32 head; 136 u32 tail; 137 u32 error_offset; 138 u64 wq_base_addr; 139 u32 wq_size_bytes; 140 u32 wq_status; 141 u32 engine_presence; 142 u32 priority; 143 u32 reserved[30]; 144 } __packed; 145 146 /* engine id and context id is packed into guc_execlist_context.context_id*/ 147 #define GUC_ELC_CTXID_OFFSET 0 148 #define GUC_ELC_ENGINE_OFFSET 29 149 150 /* The execlist context including software and HW information */ 151 struct guc_execlist_context { 152 u32 context_desc; 153 u32 context_id; 154 u32 ring_status; 155 u32 ring_lrca; 156 u32 ring_begin; 157 u32 ring_end; 158 u32 ring_next_free_location; 159 u32 ring_current_tail_pointer_value; 160 u8 engine_state_submit_value; 161 u8 engine_state_wait_value; 162 u16 pagefault_count; 163 u16 engine_submit_queue_count; 164 } __packed; 165 166 /* 167 * This structure describes a stage set arranged for a particular communication 168 * between uKernel (GuC) and Driver (KMD). Technically, this is known as a 169 * "GuC Context descriptor" in the specs, but we use the term "stage descriptor" 170 * to avoid confusion with all the other things already named "context" in the 171 * driver. A static pool of these descriptors are stored inside a GEM object 172 * (stage_desc_pool) which is held for the entire lifetime of our interaction 173 * with the GuC, being allocated before the GuC is loaded with its firmware. 174 */ 175 struct guc_stage_desc { 176 u32 sched_common_area; 177 u32 stage_id; 178 u32 pas_id; 179 u8 engines_used; 180 u64 db_trigger_cpu; 181 u32 db_trigger_uk; 182 u64 db_trigger_phy; 183 u16 db_id; 184 185 struct guc_execlist_context lrc[GUC_MAX_ENGINES_NUM]; 186 187 u8 attribute; 188 189 u32 priority; 190 191 u32 wq_sampled_tail_offset; 192 u32 wq_total_submit_enqueues; 193 194 u32 process_desc; 195 u32 wq_addr; 196 u32 wq_size; 197 198 u32 engine_presence; 199 200 u8 engine_suspended; 201 202 u8 reserved0[3]; 203 u64 reserved1[1]; 204 205 u64 desc_private; 206 } __packed; 207 208 /** 209 * DOC: CTB based communication 210 * 211 * The CTB (command transport buffer) communication between Host and GuC 212 * is based on u32 data stream written to the shared buffer. One buffer can 213 * be used to transmit data only in one direction (one-directional channel). 214 * 215 * Current status of the each buffer is stored in the buffer descriptor. 216 * Buffer descriptor holds tail and head fields that represents active data 217 * stream. The tail field is updated by the data producer (sender), and head 218 * field is updated by the data consumer (receiver):: 219 * 220 * +------------+ 221 * | DESCRIPTOR | +=================+============+========+ 222 * +============+ | | MESSAGE(s) | | 223 * | address |--------->+=================+============+========+ 224 * +------------+ 225 * | head | ^-----head--------^ 226 * +------------+ 227 * | tail | ^---------tail-----------------^ 228 * +------------+ 229 * | size | ^---------------size--------------------^ 230 * +------------+ 231 * 232 * Each message in data stream starts with the single u32 treated as a header, 233 * followed by optional set of u32 data that makes message specific payload:: 234 * 235 * +------------+---------+---------+---------+ 236 * | MESSAGE | 237 * +------------+---------+---------+---------+ 238 * | msg[0] | [1] | ... | [n-1] | 239 * +------------+---------+---------+---------+ 240 * | MESSAGE | MESSAGE PAYLOAD | 241 * + HEADER +---------+---------+---------+ 242 * | | 0 | ... | n | 243 * +======+=====+=========+=========+=========+ 244 * | 31:16| code| | | | 245 * +------+-----+ | | | 246 * | 15:5|flags| | | | 247 * +------+-----+ | | | 248 * | 4:0| len| | | | 249 * +------+-----+---------+---------+---------+ 250 * 251 * ^-------------len-------------^ 252 * 253 * The message header consists of: 254 * 255 * - **len**, indicates length of the message payload (in u32) 256 * - **code**, indicates message code 257 * - **flags**, holds various bits to control message handling 258 */ 259 260 /* 261 * Describes single command transport buffer. 262 * Used by both guc-master and clients. 263 */ 264 struct guc_ct_buffer_desc { 265 u32 addr; /* gfx address */ 266 u64 host_private; /* host private data */ 267 u32 size; /* size in bytes */ 268 u32 head; /* offset updated by GuC*/ 269 u32 tail; /* offset updated by owner */ 270 u32 is_in_error; /* error indicator */ 271 u32 fence; /* fence updated by GuC */ 272 u32 status; /* status updated by GuC */ 273 u32 owner; /* id of the channel owner */ 274 u32 owner_sub_id; /* owner-defined field for extra tracking */ 275 u32 reserved[5]; 276 } __packed; 277 278 /* Type of command transport buffer */ 279 #define INTEL_GUC_CT_BUFFER_TYPE_SEND 0x0u 280 #define INTEL_GUC_CT_BUFFER_TYPE_RECV 0x1u 281 282 /* 283 * Definition of the command transport message header (DW0) 284 * 285 * bit[4..0] message len (in dwords) 286 * bit[7..5] reserved 287 * bit[8] response (G2H only) 288 * bit[8] write fence to desc (H2G only) 289 * bit[9] write status to H2G buff (H2G only) 290 * bit[10] send status back via G2H (H2G only) 291 * bit[15..11] reserved 292 * bit[31..16] action code 293 */ 294 #define GUC_CT_MSG_LEN_SHIFT 0 295 #define GUC_CT_MSG_LEN_MASK 0x1F 296 #define GUC_CT_MSG_IS_RESPONSE (1 << 8) 297 #define GUC_CT_MSG_WRITE_FENCE_TO_DESC (1 << 8) 298 #define GUC_CT_MSG_WRITE_STATUS_TO_BUFF (1 << 9) 299 #define GUC_CT_MSG_SEND_STATUS (1 << 10) 300 #define GUC_CT_MSG_ACTION_SHIFT 16 301 #define GUC_CT_MSG_ACTION_MASK 0xFFFF 302 303 #define GUC_FORCEWAKE_RENDER (1 << 0) 304 #define GUC_FORCEWAKE_MEDIA (1 << 1) 305 306 #define GUC_POWER_UNSPECIFIED 0 307 #define GUC_POWER_D0 1 308 #define GUC_POWER_D1 2 309 #define GUC_POWER_D2 3 310 #define GUC_POWER_D3 4 311 312 /* Scheduling policy settings */ 313 314 /* Reset engine upon preempt failure */ 315 #define POLICY_RESET_ENGINE (1<<0) 316 /* Preempt to idle on quantum expiry */ 317 #define POLICY_PREEMPT_TO_IDLE (1<<1) 318 319 #define POLICY_MAX_NUM_WI 15 320 #define POLICY_DEFAULT_DPC_PROMOTE_TIME_US 500000 321 #define POLICY_DEFAULT_EXECUTION_QUANTUM_US 1000000 322 #define POLICY_DEFAULT_PREEMPTION_TIME_US 500000 323 #define POLICY_DEFAULT_FAULT_TIME_US 250000 324 325 struct guc_policy { 326 /* Time for one workload to execute. (in micro seconds) */ 327 u32 execution_quantum; 328 /* Time to wait for a preemption request to completed before issuing a 329 * reset. (in micro seconds). */ 330 u32 preemption_time; 331 /* How much time to allow to run after the first fault is observed. 332 * Then preempt afterwards. (in micro seconds) */ 333 u32 fault_time; 334 u32 policy_flags; 335 u32 reserved[8]; 336 } __packed; 337 338 struct guc_policies { 339 struct guc_policy policy[GUC_CLIENT_PRIORITY_NUM][GUC_MAX_ENGINE_CLASSES]; 340 u32 submission_queue_depth[GUC_MAX_ENGINE_CLASSES]; 341 /* In micro seconds. How much time to allow before DPC processing is 342 * called back via interrupt (to prevent DPC queue drain starving). 343 * Typically 1000s of micro seconds (example only, not granularity). */ 344 u32 dpc_promote_time; 345 346 /* Must be set to take these new values. */ 347 u32 is_valid; 348 349 /* Max number of WIs to process per call. A large value may keep CS 350 * idle. */ 351 u32 max_num_work_items; 352 353 u32 reserved[4]; 354 } __packed; 355 356 /* GuC MMIO reg state struct */ 357 358 359 #define GUC_REGSET_MAX_REGISTERS 64 360 #define GUC_S3_SAVE_SPACE_PAGES 10 361 362 struct guc_mmio_reg { 363 u32 offset; 364 u32 value; 365 u32 flags; 366 #define GUC_REGSET_MASKED (1 << 0) 367 } __packed; 368 369 struct guc_mmio_regset { 370 struct guc_mmio_reg registers[GUC_REGSET_MAX_REGISTERS]; 371 u32 values_valid; 372 u32 number_of_registers; 373 } __packed; 374 375 /* GuC register sets */ 376 struct guc_mmio_reg_state { 377 struct guc_mmio_regset engine_reg[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS]; 378 u32 reserved[98]; 379 } __packed; 380 381 /* HW info */ 382 struct guc_gt_system_info { 383 u32 slice_enabled; 384 u32 rcs_enabled; 385 u32 reserved0; 386 u32 bcs_enabled; 387 u32 vdbox_enable_mask; 388 u32 vdbox_sfc_support_mask; 389 u32 vebox_enable_mask; 390 u32 reserved[9]; 391 } __packed; 392 393 /* Clients info */ 394 struct guc_ct_pool_entry { 395 struct guc_ct_buffer_desc desc; 396 u32 reserved[7]; 397 } __packed; 398 399 #define GUC_CT_POOL_SIZE 2 400 401 struct guc_clients_info { 402 u32 clients_num; 403 u32 reserved0[13]; 404 u32 ct_pool_addr; 405 u32 ct_pool_count; 406 u32 reserved[4]; 407 } __packed; 408 409 /* GuC Additional Data Struct */ 410 struct guc_ads { 411 u32 reg_state_addr; 412 u32 reg_state_buffer; 413 u32 scheduler_policies; 414 u32 gt_system_info; 415 u32 clients_info; 416 u32 control_data; 417 u32 golden_context_lrca[GUC_MAX_ENGINE_CLASSES]; 418 u32 eng_state_size[GUC_MAX_ENGINE_CLASSES]; 419 u32 reserved[16]; 420 } __packed; 421 422 /* GuC logging structures */ 423 424 enum guc_log_buffer_type { 425 GUC_ISR_LOG_BUFFER, 426 GUC_DPC_LOG_BUFFER, 427 GUC_CRASH_DUMP_LOG_BUFFER, 428 GUC_MAX_LOG_BUFFER 429 }; 430 431 /** 432 * struct guc_log_buffer_state - GuC log buffer state 433 * 434 * Below state structure is used for coordination of retrieval of GuC firmware 435 * logs. Separate state is maintained for each log buffer type. 436 * read_ptr points to the location where i915 read last in log buffer and 437 * is read only for GuC firmware. write_ptr is incremented by GuC with number 438 * of bytes written for each log entry and is read only for i915. 439 * When any type of log buffer becomes half full, GuC sends a flush interrupt. 440 * GuC firmware expects that while it is writing to 2nd half of the buffer, 441 * first half would get consumed by Host and then get a flush completed 442 * acknowledgment from Host, so that it does not end up doing any overwrite 443 * causing loss of logs. So when buffer gets half filled & i915 has requested 444 * for interrupt, GuC will set flush_to_file field, set the sampled_write_ptr 445 * to the value of write_ptr and raise the interrupt. 446 * On receiving the interrupt i915 should read the buffer, clear flush_to_file 447 * field and also update read_ptr with the value of sample_write_ptr, before 448 * sending an acknowledgment to GuC. marker & version fields are for internal 449 * usage of GuC and opaque to i915. buffer_full_cnt field is incremented every 450 * time GuC detects the log buffer overflow. 451 */ 452 struct guc_log_buffer_state { 453 u32 marker[2]; 454 u32 read_ptr; 455 u32 write_ptr; 456 u32 size; 457 u32 sampled_write_ptr; 458 union { 459 struct { 460 u32 flush_to_file:1; 461 u32 buffer_full_cnt:4; 462 u32 reserved:27; 463 }; 464 u32 flags; 465 }; 466 u32 version; 467 } __packed; 468 469 struct guc_ctx_report { 470 u32 report_return_status; 471 u32 reserved1[64]; 472 u32 affected_count; 473 u32 reserved2[2]; 474 } __packed; 475 476 /* GuC Shared Context Data Struct */ 477 struct guc_shared_ctx_data { 478 u32 addr_of_last_preempted_data_low; 479 u32 addr_of_last_preempted_data_high; 480 u32 addr_of_last_preempted_data_high_tmp; 481 u32 padding; 482 u32 is_mapped_to_proxy; 483 u32 proxy_ctx_id; 484 u32 engine_reset_ctx_id; 485 u32 media_reset_count; 486 u32 reserved1[8]; 487 u32 uk_last_ctx_switch_reason; 488 u32 was_reset; 489 u32 lrca_gpu_addr; 490 u64 execlist_ctx; 491 u32 reserved2[66]; 492 struct guc_ctx_report preempt_ctx_report[GUC_MAX_ENGINES_NUM]; 493 } __packed; 494 495 /** 496 * DOC: MMIO based communication 497 * 498 * The MMIO based communication between Host and GuC uses software scratch 499 * registers, where first register holds data treated as message header, 500 * and other registers are used to hold message payload. 501 * 502 * For Gen9+, GuC uses software scratch registers 0xC180-0xC1B8, 503 * but no H2G command takes more than 8 parameters and the GuC FW 504 * itself uses an 8-element array to store the H2G message. 505 * 506 * +-----------+---------+---------+---------+ 507 * | MMIO[0] | MMIO[1] | ... | MMIO[n] | 508 * +-----------+---------+---------+---------+ 509 * | header | optional payload | 510 * +======+====+=========+=========+=========+ 511 * | 31:28|type| | | | 512 * +------+----+ | | | 513 * | 27:16|data| | | | 514 * +------+----+ | | | 515 * | 15:0|code| | | | 516 * +------+----+---------+---------+---------+ 517 * 518 * The message header consists of: 519 * 520 * - **type**, indicates message type 521 * - **code**, indicates message code, is specific for **type** 522 * - **data**, indicates message data, optional, depends on **code** 523 * 524 * The following message **types** are supported: 525 * 526 * - **REQUEST**, indicates Host-to-GuC request, requested GuC action code 527 * must be priovided in **code** field. Optional action specific parameters 528 * can be provided in remaining payload registers or **data** field. 529 * 530 * - **RESPONSE**, indicates GuC-to-Host response from earlier GuC request, 531 * action response status will be provided in **code** field. Optional 532 * response data can be returned in remaining payload registers or **data** 533 * field. 534 */ 535 536 #define GUC_MAX_MMIO_MSG_LEN 8 537 538 #define INTEL_GUC_MSG_TYPE_SHIFT 28 539 #define INTEL_GUC_MSG_TYPE_MASK (0xF << INTEL_GUC_MSG_TYPE_SHIFT) 540 #define INTEL_GUC_MSG_DATA_SHIFT 16 541 #define INTEL_GUC_MSG_DATA_MASK (0xFFF << INTEL_GUC_MSG_DATA_SHIFT) 542 #define INTEL_GUC_MSG_CODE_SHIFT 0 543 #define INTEL_GUC_MSG_CODE_MASK (0xFFFF << INTEL_GUC_MSG_CODE_SHIFT) 544 545 #define __INTEL_GUC_MSG_GET(T, m) \ 546 (((m) & INTEL_GUC_MSG_ ## T ## _MASK) >> INTEL_GUC_MSG_ ## T ## _SHIFT) 547 #define INTEL_GUC_MSG_TO_TYPE(m) __INTEL_GUC_MSG_GET(TYPE, m) 548 #define INTEL_GUC_MSG_TO_DATA(m) __INTEL_GUC_MSG_GET(DATA, m) 549 #define INTEL_GUC_MSG_TO_CODE(m) __INTEL_GUC_MSG_GET(CODE, m) 550 551 enum intel_guc_msg_type { 552 INTEL_GUC_MSG_TYPE_REQUEST = 0x0, 553 INTEL_GUC_MSG_TYPE_RESPONSE = 0xF, 554 }; 555 556 #define __INTEL_GUC_MSG_TYPE_IS(T, m) \ 557 (INTEL_GUC_MSG_TO_TYPE(m) == INTEL_GUC_MSG_TYPE_ ## T) 558 #define INTEL_GUC_MSG_IS_REQUEST(m) __INTEL_GUC_MSG_TYPE_IS(REQUEST, m) 559 #define INTEL_GUC_MSG_IS_RESPONSE(m) __INTEL_GUC_MSG_TYPE_IS(RESPONSE, m) 560 561 enum intel_guc_action { 562 INTEL_GUC_ACTION_DEFAULT = 0x0, 563 INTEL_GUC_ACTION_REQUEST_PREEMPTION = 0x2, 564 INTEL_GUC_ACTION_REQUEST_ENGINE_RESET = 0x3, 565 INTEL_GUC_ACTION_ALLOCATE_DOORBELL = 0x10, 566 INTEL_GUC_ACTION_DEALLOCATE_DOORBELL = 0x20, 567 INTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE = 0x30, 568 INTEL_GUC_ACTION_FORCE_LOG_BUFFER_FLUSH = 0x302, 569 INTEL_GUC_ACTION_ENTER_S_STATE = 0x501, 570 INTEL_GUC_ACTION_EXIT_S_STATE = 0x502, 571 INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003, 572 INTEL_GUC_ACTION_SAMPLE_FORCEWAKE = 0x3005, 573 INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000, 574 INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER = 0x4505, 575 INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER = 0x4506, 576 INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000, 577 INTEL_GUC_ACTION_LIMIT 578 }; 579 580 enum intel_guc_preempt_options { 581 INTEL_GUC_PREEMPT_OPTION_DROP_WORK_Q = 0x4, 582 INTEL_GUC_PREEMPT_OPTION_DROP_SUBMIT_Q = 0x8, 583 }; 584 585 enum intel_guc_report_status { 586 INTEL_GUC_REPORT_STATUS_UNKNOWN = 0x0, 587 INTEL_GUC_REPORT_STATUS_ACKED = 0x1, 588 INTEL_GUC_REPORT_STATUS_ERROR = 0x2, 589 INTEL_GUC_REPORT_STATUS_COMPLETE = 0x4, 590 }; 591 592 enum intel_guc_sleep_state_status { 593 INTEL_GUC_SLEEP_STATE_SUCCESS = 0x1, 594 INTEL_GUC_SLEEP_STATE_PREEMPT_TO_IDLE_FAILED = 0x2, 595 INTEL_GUC_SLEEP_STATE_ENGINE_RESET_FAILED = 0x3 596 #define INTEL_GUC_SLEEP_STATE_INVALID_MASK 0x80000000 597 }; 598 599 #define GUC_LOG_CONTROL_LOGGING_ENABLED (1 << 0) 600 #define GUC_LOG_CONTROL_VERBOSITY_SHIFT 4 601 #define GUC_LOG_CONTROL_VERBOSITY_MASK (0xF << GUC_LOG_CONTROL_VERBOSITY_SHIFT) 602 #define GUC_LOG_CONTROL_DEFAULT_LOGGING (1 << 8) 603 604 enum intel_guc_response_status { 605 INTEL_GUC_RESPONSE_STATUS_SUCCESS = 0x0, 606 INTEL_GUC_RESPONSE_STATUS_GENERIC_FAIL = 0xF000, 607 }; 608 609 #define INTEL_GUC_MSG_IS_RESPONSE_SUCCESS(m) \ 610 (typecheck(u32, (m)) && \ 611 ((m) & (INTEL_GUC_MSG_TYPE_MASK | INTEL_GUC_MSG_CODE_MASK)) == \ 612 ((INTEL_GUC_MSG_TYPE_RESPONSE << INTEL_GUC_MSG_TYPE_SHIFT) | \ 613 (INTEL_GUC_RESPONSE_STATUS_SUCCESS << INTEL_GUC_MSG_CODE_SHIFT))) 614 615 /* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */ 616 enum intel_guc_recv_message { 617 INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1), 618 INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER = BIT(3) 619 }; 620 621 #endif 622