1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2014-2019 Intel Corporation 4 */ 5 6 #ifndef _INTEL_GUC_FWIF_H 7 #define _INTEL_GUC_FWIF_H 8 9 #include <linux/bits.h> 10 #include <linux/compiler.h> 11 #include <linux/types.h> 12 #include "gt/intel_engine_types.h" 13 14 #include "abi/guc_actions_abi.h" 15 #include "abi/guc_actions_slpc_abi.h" 16 #include "abi/guc_errors_abi.h" 17 #include "abi/guc_communication_mmio_abi.h" 18 #include "abi/guc_communication_ctb_abi.h" 19 #include "abi/guc_klvs_abi.h" 20 #include "abi/guc_messages_abi.h" 21 22 /* Payload length only i.e. don't include G2H header length */ 23 #define G2H_LEN_DW_SCHED_CONTEXT_MODE_SET 2 24 #define G2H_LEN_DW_DEREGISTER_CONTEXT 1 25 26 #define GUC_CONTEXT_DISABLE 0 27 #define GUC_CONTEXT_ENABLE 1 28 29 #define GUC_CLIENT_PRIORITY_KMD_HIGH 0 30 #define GUC_CLIENT_PRIORITY_HIGH 1 31 #define GUC_CLIENT_PRIORITY_KMD_NORMAL 2 32 #define GUC_CLIENT_PRIORITY_NORMAL 3 33 #define GUC_CLIENT_PRIORITY_NUM 4 34 35 #define GUC_MAX_LRC_DESCRIPTORS 65535 36 #define GUC_INVALID_LRC_ID GUC_MAX_LRC_DESCRIPTORS 37 38 #define GUC_RENDER_ENGINE 0 39 #define GUC_VIDEO_ENGINE 1 40 #define GUC_BLITTER_ENGINE 2 41 #define GUC_VIDEOENHANCE_ENGINE 3 42 #define GUC_VIDEO_ENGINE2 4 43 #define GUC_MAX_ENGINES_NUM (GUC_VIDEO_ENGINE2 + 1) 44 45 #define GUC_RENDER_CLASS 0 46 #define GUC_VIDEO_CLASS 1 47 #define GUC_VIDEOENHANCE_CLASS 2 48 #define GUC_BLITTER_CLASS 3 49 #define GUC_RESERVED_CLASS 4 50 #define GUC_LAST_ENGINE_CLASS GUC_RESERVED_CLASS 51 #define GUC_MAX_ENGINE_CLASSES 16 52 #define GUC_MAX_INSTANCES_PER_CLASS 32 53 54 #define GUC_DOORBELL_INVALID 256 55 56 /* 57 * Work queue item header definitions 58 * 59 * Work queue is circular buffer used to submit complex (multi-lrc) submissions 60 * to the GuC. A work queue item is an entry in the circular buffer. 61 */ 62 #define WQ_STATUS_ACTIVE 1 63 #define WQ_STATUS_SUSPENDED 2 64 #define WQ_STATUS_CMD_ERROR 3 65 #define WQ_STATUS_ENGINE_ID_NOT_USED 4 66 #define WQ_STATUS_SUSPENDED_FROM_RESET 5 67 #define WQ_TYPE_BATCH_BUF 0x1 68 #define WQ_TYPE_PSEUDO 0x2 69 #define WQ_TYPE_INORDER 0x3 70 #define WQ_TYPE_NOOP 0x4 71 #define WQ_TYPE_MULTI_LRC 0x5 72 #define WQ_TYPE_MASK GENMASK(7, 0) 73 #define WQ_LEN_MASK GENMASK(26, 16) 74 75 #define WQ_GUC_ID_MASK GENMASK(15, 0) 76 #define WQ_RING_TAIL_MASK GENMASK(28, 18) 77 78 #define GUC_STAGE_DESC_ATTR_ACTIVE BIT(0) 79 #define GUC_STAGE_DESC_ATTR_PENDING_DB BIT(1) 80 #define GUC_STAGE_DESC_ATTR_KERNEL BIT(2) 81 #define GUC_STAGE_DESC_ATTR_PREEMPT BIT(3) 82 #define GUC_STAGE_DESC_ATTR_RESET BIT(4) 83 #define GUC_STAGE_DESC_ATTR_WQLOCKED BIT(5) 84 #define GUC_STAGE_DESC_ATTR_PCH BIT(6) 85 #define GUC_STAGE_DESC_ATTR_TERMINATED BIT(7) 86 87 #define GUC_CTL_LOG_PARAMS 0 88 #define GUC_LOG_VALID BIT(0) 89 #define GUC_LOG_NOTIFY_ON_HALF_FULL BIT(1) 90 #define GUC_LOG_CAPTURE_ALLOC_UNITS BIT(2) 91 #define GUC_LOG_LOG_ALLOC_UNITS BIT(3) 92 #define GUC_LOG_CRASH_SHIFT 4 93 #define GUC_LOG_CRASH_MASK (0x3 << GUC_LOG_CRASH_SHIFT) 94 #define GUC_LOG_DEBUG_SHIFT 6 95 #define GUC_LOG_DEBUG_MASK (0xF << GUC_LOG_DEBUG_SHIFT) 96 #define GUC_LOG_CAPTURE_SHIFT 10 97 #define GUC_LOG_CAPTURE_MASK (0x3 << GUC_LOG_CAPTURE_SHIFT) 98 #define GUC_LOG_BUF_ADDR_SHIFT 12 99 100 #define GUC_CTL_WA 1 101 #define GUC_WA_POLLCS BIT(18) 102 103 #define GUC_CTL_FEATURE 2 104 #define GUC_CTL_ENABLE_SLPC BIT(2) 105 #define GUC_CTL_DISABLE_SCHEDULER BIT(14) 106 107 #define GUC_CTL_DEBUG 3 108 #define GUC_LOG_VERBOSITY_SHIFT 0 109 #define GUC_LOG_VERBOSITY_LOW (0 << GUC_LOG_VERBOSITY_SHIFT) 110 #define GUC_LOG_VERBOSITY_MED (1 << GUC_LOG_VERBOSITY_SHIFT) 111 #define GUC_LOG_VERBOSITY_HIGH (2 << GUC_LOG_VERBOSITY_SHIFT) 112 #define GUC_LOG_VERBOSITY_ULTRA (3 << GUC_LOG_VERBOSITY_SHIFT) 113 /* Verbosity range-check limits, without the shift */ 114 #define GUC_LOG_VERBOSITY_MIN 0 115 #define GUC_LOG_VERBOSITY_MAX 3 116 #define GUC_LOG_VERBOSITY_MASK 0x0000000f 117 #define GUC_LOG_DESTINATION_MASK (3 << 4) 118 #define GUC_LOG_DISABLED (1 << 6) 119 #define GUC_PROFILE_ENABLED (1 << 7) 120 121 #define GUC_CTL_ADS 4 122 #define GUC_ADS_ADDR_SHIFT 1 123 #define GUC_ADS_ADDR_MASK (0xFFFFF << GUC_ADS_ADDR_SHIFT) 124 125 #define GUC_CTL_DEVID 5 126 127 #define GUC_CTL_MAX_DWORDS (SOFT_SCRATCH_COUNT - 2) /* [1..14] */ 128 129 /* Generic GT SysInfo data types */ 130 #define GUC_GENERIC_GT_SYSINFO_SLICE_ENABLED 0 131 #define GUC_GENERIC_GT_SYSINFO_VDBOX_SFC_SUPPORT_MASK 1 132 #define GUC_GENERIC_GT_SYSINFO_DOORBELL_COUNT_PER_SQIDI 2 133 #define GUC_GENERIC_GT_SYSINFO_MAX 16 134 135 /* 136 * The class goes in bits [0..2] of the GuC ID, the instance in bits [3..6]. 137 * Bit 7 can be used for operations that apply to all engine classes&instances. 138 */ 139 #define GUC_ENGINE_CLASS_SHIFT 0 140 #define GUC_ENGINE_CLASS_MASK (0x7 << GUC_ENGINE_CLASS_SHIFT) 141 #define GUC_ENGINE_INSTANCE_SHIFT 3 142 #define GUC_ENGINE_INSTANCE_MASK (0xf << GUC_ENGINE_INSTANCE_SHIFT) 143 #define GUC_ENGINE_ALL_INSTANCES BIT(7) 144 145 #define MAKE_GUC_ID(class, instance) \ 146 (((class) << GUC_ENGINE_CLASS_SHIFT) | \ 147 ((instance) << GUC_ENGINE_INSTANCE_SHIFT)) 148 149 #define GUC_ID_TO_ENGINE_CLASS(guc_id) \ 150 (((guc_id) & GUC_ENGINE_CLASS_MASK) >> GUC_ENGINE_CLASS_SHIFT) 151 #define GUC_ID_TO_ENGINE_INSTANCE(guc_id) \ 152 (((guc_id) & GUC_ENGINE_INSTANCE_MASK) >> GUC_ENGINE_INSTANCE_SHIFT) 153 154 #define SLPC_EVENT(id, c) (\ 155 FIELD_PREP(HOST2GUC_PC_SLPC_REQUEST_MSG_1_EVENT_ID, id) | \ 156 FIELD_PREP(HOST2GUC_PC_SLPC_REQUEST_MSG_1_EVENT_ARGC, c) \ 157 ) 158 159 static inline u8 engine_class_to_guc_class(u8 class) 160 { 161 BUILD_BUG_ON(GUC_RENDER_CLASS != RENDER_CLASS); 162 BUILD_BUG_ON(GUC_BLITTER_CLASS != COPY_ENGINE_CLASS); 163 BUILD_BUG_ON(GUC_VIDEO_CLASS != VIDEO_DECODE_CLASS); 164 BUILD_BUG_ON(GUC_VIDEOENHANCE_CLASS != VIDEO_ENHANCEMENT_CLASS); 165 GEM_BUG_ON(class > MAX_ENGINE_CLASS || class == OTHER_CLASS); 166 167 return class; 168 } 169 170 static inline u8 guc_class_to_engine_class(u8 guc_class) 171 { 172 GEM_BUG_ON(guc_class > GUC_LAST_ENGINE_CLASS); 173 GEM_BUG_ON(guc_class == GUC_RESERVED_CLASS); 174 175 return guc_class; 176 } 177 178 /* Work item for submitting workloads into work queue of GuC. */ 179 struct guc_wq_item { 180 u32 header; 181 u32 context_desc; 182 u32 submit_element_info; 183 u32 fence_id; 184 } __packed; 185 186 struct guc_process_desc { 187 u32 stage_id; 188 u64 db_base_addr; 189 u32 head; 190 u32 tail; 191 u32 error_offset; 192 u64 wq_base_addr; 193 u32 wq_size_bytes; 194 u32 wq_status; 195 u32 engine_presence; 196 u32 priority; 197 u32 reserved[36]; 198 } __packed; 199 200 #define CONTEXT_REGISTRATION_FLAG_KMD BIT(0) 201 202 #define CONTEXT_POLICY_DEFAULT_EXECUTION_QUANTUM_US 1000000 203 #define CONTEXT_POLICY_DEFAULT_PREEMPTION_TIME_US 500000 204 205 /* Preempt to idle on quantum expiry */ 206 #define CONTEXT_POLICY_FLAG_PREEMPT_TO_IDLE BIT(0) 207 208 /* 209 * GuC Context registration descriptor. 210 * FIXME: This is only required to exist during context registration. 211 * The current 1:1 between guc_lrc_desc and LRCs for the lifetime of the LRC 212 * is not required. 213 */ 214 struct guc_lrc_desc { 215 u32 hw_context_desc; 216 u32 slpm_perf_mode_hint; /* SPLC v1 only */ 217 u32 slpm_freq_hint; 218 u32 engine_submit_mask; /* In logical space */ 219 u8 engine_class; 220 u8 reserved0[3]; 221 u32 priority; 222 u32 process_desc; 223 u32 wq_addr; 224 u32 wq_size; 225 u32 context_flags; /* CONTEXT_REGISTRATION_* */ 226 /* Time for one workload to execute. (in micro seconds) */ 227 u32 execution_quantum; 228 /* Time to wait for a preemption request to complete before issuing a 229 * reset. (in micro seconds). 230 */ 231 u32 preemption_timeout; 232 u32 policy_flags; /* CONTEXT_POLICY_* */ 233 u32 reserved1[19]; 234 } __packed; 235 236 #define GUC_POWER_UNSPECIFIED 0 237 #define GUC_POWER_D0 1 238 #define GUC_POWER_D1 2 239 #define GUC_POWER_D2 3 240 #define GUC_POWER_D3 4 241 242 /* Scheduling policy settings */ 243 244 #define GLOBAL_POLICY_MAX_NUM_WI 15 245 246 /* Don't reset an engine upon preemption failure */ 247 #define GLOBAL_POLICY_DISABLE_ENGINE_RESET BIT(0) 248 249 #define GLOBAL_POLICY_DEFAULT_DPC_PROMOTE_TIME_US 500000 250 251 struct guc_policies { 252 u32 submission_queue_depth[GUC_MAX_ENGINE_CLASSES]; 253 /* In micro seconds. How much time to allow before DPC processing is 254 * called back via interrupt (to prevent DPC queue drain starving). 255 * Typically 1000s of micro seconds (example only, not granularity). */ 256 u32 dpc_promote_time; 257 258 /* Must be set to take these new values. */ 259 u32 is_valid; 260 261 /* Max number of WIs to process per call. A large value may keep CS 262 * idle. */ 263 u32 max_num_work_items; 264 265 u32 global_flags; 266 u32 reserved[4]; 267 } __packed; 268 269 /* GuC MMIO reg state struct */ 270 struct guc_mmio_reg { 271 u32 offset; 272 u32 value; 273 u32 flags; 274 u32 mask; 275 #define GUC_REGSET_MASKED BIT(0) 276 #define GUC_REGSET_MASKED_WITH_VALUE BIT(2) 277 #define GUC_REGSET_RESTORE_ONLY BIT(3) 278 } __packed; 279 280 /* GuC register sets */ 281 struct guc_mmio_reg_set { 282 u32 address; 283 u16 count; 284 u16 reserved; 285 } __packed; 286 287 /* HW info */ 288 struct guc_gt_system_info { 289 u8 mapping_table[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS]; 290 u32 engine_enabled_masks[GUC_MAX_ENGINE_CLASSES]; 291 u32 generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_MAX]; 292 } __packed; 293 294 enum { 295 GUC_CAPTURE_LIST_INDEX_PF = 0, 296 GUC_CAPTURE_LIST_INDEX_VF = 1, 297 GUC_CAPTURE_LIST_INDEX_MAX = 2, 298 }; 299 300 /* GuC Additional Data Struct */ 301 struct guc_ads { 302 struct guc_mmio_reg_set reg_state_list[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS]; 303 u32 reserved0; 304 u32 scheduler_policies; 305 u32 gt_system_info; 306 u32 reserved1; 307 u32 control_data; 308 u32 golden_context_lrca[GUC_MAX_ENGINE_CLASSES]; 309 u32 eng_state_size[GUC_MAX_ENGINE_CLASSES]; 310 u32 private_data; 311 u32 reserved2; 312 u32 capture_instance[GUC_CAPTURE_LIST_INDEX_MAX][GUC_MAX_ENGINE_CLASSES]; 313 u32 capture_class[GUC_CAPTURE_LIST_INDEX_MAX][GUC_MAX_ENGINE_CLASSES]; 314 u32 capture_global[GUC_CAPTURE_LIST_INDEX_MAX]; 315 u32 reserved[14]; 316 } __packed; 317 318 /* Engine usage stats */ 319 struct guc_engine_usage_record { 320 u32 current_context_index; 321 u32 last_switch_in_stamp; 322 u32 reserved0; 323 u32 total_runtime; 324 u32 reserved1[4]; 325 } __packed; 326 327 struct guc_engine_usage { 328 struct guc_engine_usage_record engines[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS]; 329 } __packed; 330 331 /* GuC logging structures */ 332 333 enum guc_log_buffer_type { 334 GUC_DEBUG_LOG_BUFFER, 335 GUC_CRASH_DUMP_LOG_BUFFER, 336 GUC_CAPTURE_LOG_BUFFER, 337 GUC_MAX_LOG_BUFFER 338 }; 339 340 /** 341 * struct guc_log_buffer_state - GuC log buffer state 342 * 343 * Below state structure is used for coordination of retrieval of GuC firmware 344 * logs. Separate state is maintained for each log buffer type. 345 * read_ptr points to the location where i915 read last in log buffer and 346 * is read only for GuC firmware. write_ptr is incremented by GuC with number 347 * of bytes written for each log entry and is read only for i915. 348 * When any type of log buffer becomes half full, GuC sends a flush interrupt. 349 * GuC firmware expects that while it is writing to 2nd half of the buffer, 350 * first half would get consumed by Host and then get a flush completed 351 * acknowledgment from Host, so that it does not end up doing any overwrite 352 * causing loss of logs. So when buffer gets half filled & i915 has requested 353 * for interrupt, GuC will set flush_to_file field, set the sampled_write_ptr 354 * to the value of write_ptr and raise the interrupt. 355 * On receiving the interrupt i915 should read the buffer, clear flush_to_file 356 * field and also update read_ptr with the value of sample_write_ptr, before 357 * sending an acknowledgment to GuC. marker & version fields are for internal 358 * usage of GuC and opaque to i915. buffer_full_cnt field is incremented every 359 * time GuC detects the log buffer overflow. 360 */ 361 struct guc_log_buffer_state { 362 u32 marker[2]; 363 u32 read_ptr; 364 u32 write_ptr; 365 u32 size; 366 u32 sampled_write_ptr; 367 u32 wrap_offset; 368 union { 369 struct { 370 u32 flush_to_file:1; 371 u32 buffer_full_cnt:4; 372 u32 reserved:27; 373 }; 374 u32 flags; 375 }; 376 u32 version; 377 } __packed; 378 379 struct guc_ctx_report { 380 u32 report_return_status; 381 u32 reserved1[64]; 382 u32 affected_count; 383 u32 reserved2[2]; 384 } __packed; 385 386 /* GuC Shared Context Data Struct */ 387 struct guc_shared_ctx_data { 388 u32 addr_of_last_preempted_data_low; 389 u32 addr_of_last_preempted_data_high; 390 u32 addr_of_last_preempted_data_high_tmp; 391 u32 padding; 392 u32 is_mapped_to_proxy; 393 u32 proxy_ctx_id; 394 u32 engine_reset_ctx_id; 395 u32 media_reset_count; 396 u32 reserved1[8]; 397 u32 uk_last_ctx_switch_reason; 398 u32 was_reset; 399 u32 lrca_gpu_addr; 400 u64 execlist_ctx; 401 u32 reserved2[66]; 402 struct guc_ctx_report preempt_ctx_report[GUC_MAX_ENGINES_NUM]; 403 } __packed; 404 405 /* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */ 406 enum intel_guc_recv_message { 407 INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1), 408 INTEL_GUC_RECV_MSG_EXCEPTION = BIT(30), 409 }; 410 411 #endif 412